[AArch64][SVE] Fix ICE extracting fixedvec from scalable load

[peterwaller-arm]

Summary

f526c600c043 had a concern raised because of an invalid typesize request
on a scalable vector, which this patch addresses.

Prevent shouldReduceLoadWidth from attempting to query the bit size, and
add a regression test in sve-extract-fixed-vector.ll.

[MattDevereau]

llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll

410–426

Consider adding a short comment explaining whats going on like the other tests in this file. It's a bit hard (at least for me) to tell exactly what regression is being asserted from the test name alone

[peterwaller-arm]

• Review comment: add test comment.

[paulwalker-arm]

I've added a comment regarding what I believe is a better fix. The problem is, following this advice may well trigger different code paths for other targets and so I'm happy to accept this more minimal fix. I'll leave it up to you which way to go.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

11803

I think the real problem is here where the code is not vector ware. For SVE at least, the index loads are based on the scalar element type and so my feeling is that the real intent here is best followed if getSizeInBits becomes getScalarSizeInBits.

So today this function likely incorrectly always returns false for fixed length vectors, which is not great but better than the crash triggered by scalable vectors.

[peterwaller-arm]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

11803

As discussed offline, we're concerned about the potential performance impact on other targets that we aren't able to test. So for now we're going to apply the band-aid we have.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

bool AArch64TargetLowering::shouldReduceLoadWidth(SDNode *Load,
   // the offset.
   MemSDNode *Mem = dyn_cast<MemSDNode>(Load);
   assert(Mem);
   const SDValue &Base = Mem->getBasePtr();
   if (Base.getOpcode() == ISD::ADD &&
       Base.getOperand(1).getOpcode() == ISD::SHL &&
       Base.getOperand(1).hasOneUse() &&
       Base.getOperand(1).getOperand(1).getOpcode() == ISD::Constant) {
+    // It's unknown whether a scalable vector has a power-of-2 bitwidth.
+    if (Mem->getMemoryVT().isScalableVector())
+      return false;
     // The shift can be combined if it matches the size of the value being
     // loaded (and so reducing the width would make it not match).
     uint64_t ShiftAmount = Base.getOperand(1).getConstantOperandVal(1);
     uint64_t LoadBytes = Mem->getMemoryVT().getSizeInBits()/8;
     if (ShiftAmount == Log2_32(LoadBytes))
       return false;
   }
   // We have no reason to disallow reducing the load width, so allow it.
   return true;
 }
 
 // Truncations from 64-bit GPR to 32-bit GPR is free.

llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll

 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x10, x9, lsl #3]
 ; CHECK-NEXT:    st1d { z0.d }, p0, [x8]
 ; CHECK-NEXT:    addvl sp, sp, #1
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %retval = call <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> %vec, i64 4)
   ret <4 x i64> %retval
 }
 
+; Check that extract from load via bitcast-gep-of-scalar-ptr does not crash.
+define <4 x i32> @typesize_regression_test_v4i32(i32* %addr, i64 %idx) {
+; CHECK-LABEL: typesize_regression_test_v4i32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0, x1, lsl #2]
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ret
+entry:
+  %ptr = getelementptr inbounds i32, i32* %addr, i64 %idx
+  %bc = bitcast i32* %ptr to <vscale x 4 x i32>*
+  %ld = load <vscale x 4 x i32>, <vscale x 4 x i32>* %bc, align 16
+  %out = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %ld, i64 0)
+  ret <4 x i32> %out
+}
+
 attributes #0 = { vscale_range(2,2) }
 attributes #1 = { vscale_range(8,8) }
 
 declare <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64>, i64)
 
 declare <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32>, i64)
 declare <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv2i32(<vscale x 2 x i32>, i64)