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[HIP] Add atomic load, atomic store and atomic cmpxchng_weak builtin support in HIP-clang
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Authored by gandhi21299 on Nov 24 2021, 11:18 AM.

Details

Summary

Introduce __hip_atomic_load, __hip_atomic_store and __hip_atomic_compare_exchange_weak
builtins in HIP.

Diff Detail

Event Timeline

gandhi21299 requested review of this revision.Nov 24 2021, 11:18 AM
gandhi21299 created this revision.
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removed changes in atomic-ops.cl, CUDA test may be sufficient.

gandhi21299 edited the summary of this revision. (Show Details)Nov 24 2021, 12:06 PM

we also need a sema test like clang/test/SemaOpenCL/atomic-ops.cl

clang/test/CodeGenCUDA/atomic-ops.cu
29–31

all three builtins need to accept memory order parameter. check clang/test/CodeGenOpenCL/atomic-ops.cl for reference

  • added order argument in the builtins and changed the tests accordingly
  • adding Sema test
  • applied clang-format

Passed internal CI

Harbormaster completed remote builds in B136094: Diff 389833.
yaxunl added inline comments.Nov 26 2021, 7:52 AM
clang/test/CodeGenCUDA/atomic-ops.cu
14

should have atomic, syncscope and monotonic. same as below

31

the signature of __hip_atomic_compare_exchange_weak is the same as __hip_atomic_compare_exchange_strong and should be called with the same arguments. It should end up with one atomic cmpxchg instruction in IR. same as below

clang/test/SemaCUDA/atomic-ops.cu
11

should use predefined macros for memory order, e.g. __ATOMIC_RELAXED. same as below

68

signature is wrong. see above comments.

gandhi21299 marked an inline comment as done.Nov 26 2021, 8:47 AM
gandhi21299 marked 3 inline comments as done.Nov 26 2021, 10:22 AM
gandhi21299 marked an inline comment as done.

addressed feedback including

  • correction of function signatures
  • checking for order combinations
  • correcting expected store atomic instruction
  • using predefined macros for memory order

applied clang-format

yaxunl added inline comments.Nov 29 2021, 7:28 AM
clang/test/SemaCUDA/atomic-ops.cu
70–75

pls use pre-defined macros for memory order

  • replaced integers with memory order macros in SemaCUDA/atomic-ops.cu
yaxunl accepted this revision.Nov 29 2021, 10:19 AM

LGTM. Thanks.

This revision is now accepted and ready to land.Nov 29 2021, 10:19 AM

Thanks for the review, I will merge this patch in.