[RISCV] Teach VSETVLI insertion to handle mask instruction which has avl from a PHI node.

[jacquesguan]

Summary

Use hasCompatibleVTYPE instead of hasSameVTYPE in needVSETVLIPHI, in order to avoid insert a vsetvli for mask instruction.

[craig.topper]

I already posted a patch for this https://reviews.llvm.org/D113204

[jacquesguan]

In D113649#3123821, @craig.topper wrote:

I already posted a patch for this https://reviews.llvm.org/D113204

OK, I will close this.

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
 
   for (unsigned PHIOp = 1, NumOps = PHI->getNumOperands(); PHIOp != NumOps;
        PHIOp += 2) {
     Register InReg = PHI->getOperand(PHIOp).getReg();
     MachineBasicBlock *PBB = PHI->getOperand(PHIOp + 1).getMBB();
     const BlockData &PBBInfo = BlockInfo[PBB->getNumber()];
     // If the exit from the predecessor has the VTYPE we are looking for
     // we might be able to avoid a VSETVLI.
-    if (PBBInfo.Exit.isUnknown() || !PBBInfo.Exit.hasSameVTYPE(Require))
+    if (PBBInfo.Exit.isUnknown() ||
+        !PBBInfo.Exit.hasCompatibleVTYPE(Require, false))
       return true;
 
     // We need the PHI input to the be the output of a VSET(I)VLI.
     MachineInstr *DefMI = MRI->getVRegDef(InReg);
     if (!DefMI || (DefMI->getOpcode() != RISCV::PseudoVSETVLI &&
                    DefMI->getOpcode() != RISCV::PseudoVSETVLIX0 &&
                    DefMI->getOpcode() != RISCV::PseudoVSETIVLI))
       return true;

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

 }
 declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64)
 declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64)
 
 ; FIXME: There shouldn't be a vsetvli before the vmor.
 define void @test6(i32* nocapture readonly %A, i32* nocapture %B, i64 %n) {
 ; CHECK-LABEL: test6:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a3, a2, e32, m1, ta, mu
-; CHECK-NEXT:    beqz a3, .LBB5_3
+; CHECK-NEXT:    vsetvli a6, a2, e32, m1, ta, mu
+; CHECK-NEXT:    beqz a6, .LBB5_3
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    mv a4, zero
 ; CHECK-NEXT:  .LBB5_2: # %for.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    slli a6, a4, 2
-; CHECK-NEXT:    add a5, a0, a6
-; CHECK-NEXT:    vle32.v v8, (a5)
+; CHECK-NEXT:    slli a5, a4, 2
+; CHECK-NEXT:    add a3, a0, a5
+; CHECK-NEXT:    vle32.v v8, (a3)
 ; CHECK-NEXT:    vmsle.vi v9, v8, -3
 ; CHECK-NEXT:    vmsgt.vi v10, v8, 2
-; CHECK-NEXT:    vsetvli zero, a3, e8, mf4, ta, mu
 ; CHECK-NEXT:    vmor.mm v0, v9, v10
-; CHECK-NEXT:    add a5, a1, a6
-; CHECK-NEXT:    vse32.v v8, (a5), v0.t
-; CHECK-NEXT:    add a4, a4, a3
-; CHECK-NEXT:    vsetvli a3, a2, e32, m1, ta, mu
-; CHECK-NEXT:    bnez a3, .LBB5_2
+; CHECK-NEXT:    add a3, a1, a5
+; CHECK-NEXT:    vse32.v v8, (a3), v0.t
+; CHECK-NEXT:    add a4, a4, a6
+; CHECK-NEXT:    vsetvli a6, a2, e32, m1, ta, mu
+; CHECK-NEXT:    bnez a6, .LBB5_2
 ; CHECK-NEXT:  .LBB5_3: # %for.cond.cleanup
 ; CHECK-NEXT:    ret
 entry:
   %0 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %n, i64 2, i64 0)
   %cmp.not11 = icmp eq i64 %0, 0
   br i1 %cmp.not11, label %for.cond.cleanup, label %for.body
 
 for.cond.cleanup:                                 ; preds = %for.body, %entry