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Differential D113302

[X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC
ClosedPublic

Authored by RKSimon on Nov 5 2021, 11:37 AM.

Details

Reviewers
craig.topper
pengfei
Commits
rGd391e4fe841d: [X86] Update RET/LRET instruction to use the same naming convention as IRET…
Summary

Be more consistent in the naming convention for the various RET instructions to help prevent future scheduler model mismatches like those that were only addressed in D44687.

Diff Detail

Event Timeline

RKSimon created this revision.Nov 5 2021, 11:37 AM
Herald added a subscriber: hiraditya. · View Herald TranscriptNov 5 2021, 11:37 AM
RKSimon requested review of this revision.Nov 5 2021, 11:37 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 5 2021, 11:37 AM
Harbormaster completed remote builds in B132737: Diff 385138.Nov 5 2021, 12:30 PM
pengfei added a comment.Nov 5 2021, 11:36 PM

Not sure if I understand it correct or not. I used to take the number as system mode. E.g., CALL16m, POP32r etc. And W/L/Q as the size of memory operand. Maybe we should change RETL etc. to RET32 instead?

RKSimon planned changes to this revision.Nov 6 2021, 1:21 AM
In D113302#3113304, @pengfei wrote:

Not sure if I understand it correct or not. I used to take the number as system mode. E.g., CALL16m, POP32r etc. And W/L/Q as the size of memory operand. Maybe we should change RETL etc. to RET32 instead?

Sure, that makes sense as well

RKSimon updated this revision to Diff 385266.Nov 6 2021, 5:50 AM
RKSimon retitled this revision from [X86] Update IRET instruction to use the same naming convention as RET/LRET (PR36876). NFC to [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC.
RKSimon updated this revision to Diff 385268.Nov 6 2021, 6:17 AM

update tests

Herald added subscribers: qcolombet, MatzeB. · View Herald TranscriptNov 6 2021, 6:17 AM
RKSimon planned changes to this revision.Nov 6 2021, 6:30 AM

more tests needs updating...

Harbormaster completed remote builds in B132838: Diff 385268.Nov 6 2021, 7:20 AM
RKSimon updated this revision to Diff 385335.Nov 7 2021, 4:12 AM

update tests

Herald added subscribers: wenlei, arphaman. · View Herald TranscriptNov 7 2021, 4:12 AM
Harbormaster completed remote builds in B132897: Diff 385335.Nov 7 2021, 5:10 AM
pengfei accepted this revision.Nov 7 2021, 5:40 AM

Wow, I haven't thought we have so many use of the MI opcodes. Maybe I shouldn't have suggested this way :)

This revision is now accepted and ready to land.Nov 7 2021, 5:40 AM
RKSimon added a comment.Nov 7 2021, 5:59 AM
In D113302#3114128, @pengfei wrote:

Wow, I haven't thought we have so many use of the MI opcodes. Maybe I shouldn't have suggested this way :)

Cheers - I agree - I didn't expect the patch to be so bulky, but still I think it makes sense to get this done once and for all!

This revision was landed with ongoing or failed builds.Nov 7 2021, 7:09 AM
Closed by commit rGd391e4fe841d: [X86] Update RET/LRET instruction to use the same naming convention as IRET… (authored by RKSimon). · Explain Why
This revision was automatically updated to reflect the committed changes.
RKSimon added a commit: rGd391e4fe841d: [X86] Update RET/LRET instruction to use the same naming convention as IRET….

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Diff 385335

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

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/// - https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection /// - https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection
/// ///
/// Returns `true` if a mitigation was applied or warning was emitted. /// Returns `true` if a mitigation was applied or warning was emitted.
void X86AsmParser::applyLVICFIMitigation(MCInst &Inst, MCStreamer &Out) { void X86AsmParser::applyLVICFIMitigation(MCInst &Inst, MCStreamer &Out) {
// Information on control-flow instructions that require manual mitigation can // Information on control-flow instructions that require manual mitigation can
// be found here: // be found here:
// https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions // https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case X86::RETW: case X86::RET16:
case X86::RETL: case X86::RET32:
case X86::RETQ: case X86::RET64:
case X86::RETIL: case X86::RETI16:
case X86::RETIQ: case X86::RETI32:
case X86::RETIW: { case X86::RETI64: {
MCInst ShlInst, FenceInst; MCInst ShlInst, FenceInst;
bool Parse32 = is32BitMode() || Code16GCC; bool Parse32 = is32BitMode() || Code16GCC;
unsigned Basereg = unsigned Basereg =
is64BitMode() ? X86::RSP : (Parse32 ? X86::ESP : X86::SP); is64BitMode() ? X86::RSP : (Parse32 ? X86::ESP : X86::SP);
const MCExpr *Disp = MCConstantExpr::create(0, getContext()); const MCExpr *Disp = MCConstantExpr::create(0, getContext());
auto ShlMemOp = X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp, auto ShlMemOp = X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
/*BaseReg=*/Basereg, /*IndexReg=*/0, /*BaseReg=*/Basereg, /*IndexReg=*/0,
/*Scale=*/1, SMLoc{}, SMLoc{}, 0); /*Scale=*/1, SMLoc{}, SMLoc{}, 0);
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llvm/lib/Target/X86/X86ExpandPseudo.cpp

Show First 20 Lines • Show All 388 Lines • ▼ Show 20 Lines case X86::IRET: {
return true; return true;
} }
case X86::RET: { case X86::RET: {
// Adjust stack to erase error code // Adjust stack to erase error code
int64_t StackAdj = MBBI->getOperand(0).getImm(); int64_t StackAdj = MBBI->getOperand(0).getImm();
MachineInstrBuilder MIB; MachineInstrBuilder MIB;
if (StackAdj == 0) { if (StackAdj == 0) {
MIB = BuildMI(MBB, MBBI, DL, MIB = BuildMI(MBB, MBBI, DL,
TII->get(STI->is64Bit() ? X86::RETQ : X86::RETL)); TII->get(STI->is64Bit() ? X86::RET64 : X86::RET32));
} else if (isUInt<16>(StackAdj)) { } else if (isUInt<16>(StackAdj)) {
MIB = BuildMI(MBB, MBBI, DL, MIB = BuildMI(MBB, MBBI, DL,
TII->get(STI->is64Bit() ? X86::RETIQ : X86::RETIL)) TII->get(STI->is64Bit() ? X86::RETI64 : X86::RETI32))
.addImm(StackAdj); .addImm(StackAdj);
} else { } else {
assert(!STI->is64Bit() && assert(!STI->is64Bit() &&
"shouldn't need to do this for x86_64 targets!"); "shouldn't need to do this for x86_64 targets!");
// A ret can only handle immediates as big as 2**16-1. If we need to pop // A ret can only handle immediates as big as 2**16-1. If we need to pop
// off bytes before the return address, we must do it manually. // off bytes before the return address, we must do it manually.
BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r)).addReg(X86::ECX, RegState::Define); BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r)).addReg(X86::ECX, RegState::Define);
X86FL->emitSPUpdate(MBB, MBBI, DL, StackAdj, /*InEpilogue=*/true); X86FL->emitSPUpdate(MBB, MBBI, DL, StackAdj, /*InEpilogue=*/true);
BuildMI(MBB, MBBI, DL, TII->get(X86::PUSH32r)).addReg(X86::ECX); BuildMI(MBB, MBBI, DL, TII->get(X86::PUSH32r)).addReg(X86::ECX);
MIB = BuildMI(MBB, MBBI, DL, TII->get(X86::RETL)); MIB = BuildMI(MBB, MBBI, DL, TII->get(X86::RET32));
} }
for (unsigned I = 1, E = MBBI->getNumOperands(); I != E; ++I) for (unsigned I = 1, E = MBBI->getNumOperands(); I != E; ++I)
MIB.add(MBBI->getOperand(I)); MIB.add(MBBI->getOperand(I));
MBB.erase(MBBI); MBB.erase(MBBI);
return true; return true;
} }
case X86::LCMPXCHG16B_SAVE_RBX: { case X86::LCMPXCHG16B_SAVE_RBX: {
// Perform the following transformation. // Perform the following transformation.
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llvm/lib/Target/X86/X86FastISel.cpp

Show First 20 Lines • Show All 1,298 Lines • ▼ Show 20 Lines BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::COPY), RetReg).addReg(Reg); TII.get(TargetOpcode::COPY), RetReg).addReg(Reg);
RetRegs.push_back(RetReg); RetRegs.push_back(RetReg);
} }
// Now emit the RET. // Now emit the RET.
MachineInstrBuilder MIB; MachineInstrBuilder MIB;
if (X86MFInfo->getBytesToPopOnReturn()) { if (X86MFInfo->getBytesToPopOnReturn()) {
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Subtarget->is64Bit() ? X86::RETIQ : X86::RETIL)) TII.get(Subtarget->is64Bit() ? X86::RETI64 : X86::RETI32))
.addImm(X86MFInfo->getBytesToPopOnReturn()); .addImm(X86MFInfo->getBytesToPopOnReturn());
} else { } else {
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Subtarget->is64Bit() ? X86::RETQ : X86::RETL)); TII.get(Subtarget->is64Bit() ? X86::RET64 : X86::RET32));
} }
for (unsigned i = 0, e = RetRegs.size(); i != e; ++i) for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
MIB.addReg(RetRegs[i], RegState::Implicit); MIB.addReg(RetRegs[i], RegState::Implicit);
return true; return true;
} }
/// X86SelectLoad - Select and emit code to implement load instructions. /// X86SelectLoad - Select and emit code to implement load instructions.
/// ///
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llvm/lib/Target/X86/X86IndirectThunks.cpp

Show First 20 Lines • Show All 206 Lines • ▼ Show 20 Lines MachineBasicBlock *CaptureSpec =
MF.CreateMachineBasicBlock(Entry->getBasicBlock()); MF.CreateMachineBasicBlock(Entry->getBasicBlock());
MachineBasicBlock *CallTarget = MachineBasicBlock *CallTarget =
MF.CreateMachineBasicBlock(Entry->getBasicBlock()); MF.CreateMachineBasicBlock(Entry->getBasicBlock());
MCSymbol *TargetSym = MF.getContext().createTempSymbol(); MCSymbol *TargetSym = MF.getContext().createTempSymbol();
MF.push_back(CaptureSpec); MF.push_back(CaptureSpec);
MF.push_back(CallTarget); MF.push_back(CallTarget);
const unsigned CallOpc = Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32; const unsigned CallOpc = Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32;
const unsigned RetOpc = Is64Bit ? X86::RETQ : X86::RETL; const unsigned RetOpc = Is64Bit ? X86::RET64 : X86::RET32;
Entry->addLiveIn(ThunkReg); Entry->addLiveIn(ThunkReg);
BuildMI(Entry, DebugLoc(), TII->get(CallOpc)).addSym(TargetSym); BuildMI(Entry, DebugLoc(), TII->get(CallOpc)).addSym(TargetSym);
// The MIR verifier thinks that the CALL in the entry block will fall through // The MIR verifier thinks that the CALL in the entry block will fall through
// to CaptureSpec, so mark it as the successor. Technically, CaptureTarget is // to CaptureSpec, so mark it as the successor. Technically, CaptureTarget is
// the successor, but the MIR verifier doesn't know how to cope with that. // the successor, but the MIR verifier doesn't know how to cope with that.
Entry->addSuccessor(CaptureSpec); Entry->addSuccessor(CaptureSpec);
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llvm/lib/Target/X86/X86InstrControl.td

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// //
// Return instructions. // Return instructions.
// //
// The X86retflag return instructions are variadic because we may add ST0 and // The X86retflag return instructions are variadic because we may add ST0 and
// ST1 arguments when returning values on the x87 stack. // ST1 arguments when returning values on the x87 stack.
let isTerminator = 1, isReturn = 1, isBarrier = 1, let isTerminator = 1, isReturn = 1, isBarrier = 1,
hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in { hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops), def RET32 : I <0xC3, RawFrm, (outs), (ins variable_ops),
"ret{l}", []>, OpSize32, Requires<[Not64BitMode]>; "ret{l}", []>, OpSize32, Requires<[Not64BitMode]>;
def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops), def RET64 : I <0xC3, RawFrm, (outs), (ins variable_ops),
"ret{q}", []>, OpSize32, Requires<[In64BitMode]>; "ret{q}", []>, OpSize32, Requires<[In64BitMode]>;
def RETW : I <0xC3, RawFrm, (outs), (ins), def RET16 : I <0xC3, RawFrm, (outs), (ins),
"ret{w}", []>, OpSize16; "ret{w}", []>, OpSize16;
def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), def RETI32 : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
"ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>; "ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>;
def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), def RETI64 : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
"ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>; "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>;
def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), def RETI16 : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
"ret{w}\t$amt", []>, OpSize16; "ret{w}\t$amt", []>, OpSize16;
def LRETL : I <0xCB, RawFrm, (outs), (ins), def LRET32 : I <0xCB, RawFrm, (outs), (ins),
"{l}ret{l|f}", []>, OpSize32; "{l}ret{l|f}", []>, OpSize32;
def LRETQ : RI <0xCB, RawFrm, (outs), (ins), def LRET64 : RI <0xCB, RawFrm, (outs), (ins),
"{l}ret{|f}q", []>, Requires<[In64BitMode]>; "{l}ret{|f}q", []>, Requires<[In64BitMode]>;
def LRETW : I <0xCB, RawFrm, (outs), (ins), def LRET16 : I <0xCB, RawFrm, (outs), (ins),
"{l}ret{w|f}", []>, OpSize16; "{l}ret{w|f}", []>, OpSize16;
def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), def LRETI32 : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
"{l}ret{l|f}\t$amt", []>, OpSize32; "{l}ret{l|f}\t$amt", []>, OpSize32;
def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt), def LRETI64 : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
"{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>; "{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>;
def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), def LRETI16 : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
"{l}ret{w|f}\t$amt", []>, OpSize16; "{l}ret{w|f}\t$amt", []>, OpSize16;
// The machine return from interrupt instruction, but sometimes we need to // The machine return from interrupt instruction, but sometimes we need to
// perform a post-epilogue stack adjustment. Codegen emits the pseudo form // perform a post-epilogue stack adjustment. Codegen emits the pseudo form
// which expands to include an SP adjustment if necessary. // which expands to include an SP adjustment if necessary.
def IRET16 : I <0xcf, RawFrm, (outs), (ins), "iret{w}", []>, def IRET16 : I <0xcf, RawFrm, (outs), (ins), "iret{w}", []>,
OpSize16; OpSize16;
def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32; def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32;
def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>; def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>;
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llvm/lib/Target/X86/X86InstrInfo.cpp

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// Pin the vtable to this file. // Pin the vtable to this file.
void X86InstrInfo::anchor() {} void X86InstrInfo::anchor() {}
X86InstrInfo::X86InstrInfo(X86Subtarget &STI) X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
: X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
: X86::ADJCALLSTACKDOWN32), : X86::ADJCALLSTACKDOWN32),
(STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
: X86::ADJCALLSTACKUP32), : X86::ADJCALLSTACKUP32),
X86::CATCHRET, X86::CATCHRET,
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-                      X86::CATCHRET,
-                      (STI.is64Bit() ? X86::RET64 : X86::RET32)),
-      Subtarget(STI), RI(STI.getTargetTriple()) {
-}
+                      X86::CATCHRET, (STI.is64Bit() ? X86::RET64 : X86::RET32)),
+      Subtarget(STI), RI(STI.getTargetTriple()) {}
Lint: Pre-merge checks: clang-format: please reformat the code ``` - X86::CATCHRET…
(STI.is64Bit() ? X86::RETQ : X86::RETL)), (STI.is64Bit() ? X86::RET64 : X86::RET32)),
Subtarget(STI), RI(STI.getTargetTriple()) { Subtarget(STI), RI(STI.getTargetTriple()) {
} }
bool bool
X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
Register &SrcReg, Register &DstReg, Register &SrcReg, Register &DstReg,
unsigned &SubIdx) const { unsigned &SubIdx) const {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
▲ Show 20 Lines • Show All 9,264 Lines • ▼ Show 20 Linesvoid X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB,
const outliner::OutlinedFunction &OF) const outliner::OutlinedFunction &OF)
const { const {
// If we're a tail call, we already have a return, so don't do anything. // If we're a tail call, we already have a return, so don't do anything.
if (OF.FrameConstructionID == MachineOutlinerTailCall) if (OF.FrameConstructionID == MachineOutlinerTailCall)
return; return;
// We're a normal call, so our sequence doesn't have a return instruction. // We're a normal call, so our sequence doesn't have a return instruction.
// Add it in. // Add it in.
MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ)); MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RET64));
MBB.insert(MBB.end(), retq); MBB.insert(MBB.end(), retq);
} }
MachineBasicBlock::iterator MachineBasicBlock::iterator
X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB, X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
MachineBasicBlock::iterator &It, MachineBasicBlock::iterator &It,
MachineFunction &MF, MachineFunction &MF,
const outliner::Candidate &C) const { const outliner::Candidate &C) const {
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llvm/lib/Target/X86/X86LoadValueInjectionRetHardening.cpp

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Linesbool X86LoadValueInjectionRetHardeningPass::runOnMachineFunction(
++NumFunctionsConsidered; ++NumFunctionsConsidered;
const X86RegisterInfo *TRI = Subtarget->getRegisterInfo(); const X86RegisterInfo *TRI = Subtarget->getRegisterInfo();
const X86InstrInfo *TII = Subtarget->getInstrInfo(); const X86InstrInfo *TII = Subtarget->getInstrInfo();
bool Modified = false; bool Modified = false;
for (auto &MBB : MF) { for (auto &MBB : MF) {
for (auto MBBI = MBB.begin(); MBBI != MBB.end(); ++MBBI) { for (auto MBBI = MBB.begin(); MBBI != MBB.end(); ++MBBI) {
if (MBBI->getOpcode() != X86::RETQ) if (MBBI->getOpcode() != X86::RET64)
continue; continue;
unsigned ClobberReg = TRI->findDeadCallerSavedReg(MBB, MBBI); unsigned ClobberReg = TRI->findDeadCallerSavedReg(MBB, MBBI);
if (ClobberReg != X86::NoRegister) { if (ClobberReg != X86::NoRegister) {
BuildMI(MBB, MBBI, DebugLoc(), TII->get(X86::POP64r)) BuildMI(MBB, MBBI, DebugLoc(), TII->get(X86::POP64r))
.addReg(ClobberReg, RegState::Define) .addReg(ClobberReg, RegState::Define)
.setMIFlag(MachineInstr::FrameDestroy); .setMIFlag(MachineInstr::FrameDestroy);
BuildMI(MBB, MBBI, DebugLoc(), TII->get(X86::LFENCE)); BuildMI(MBB, MBBI, DebugLoc(), TII->get(X86::LFENCE));
Show All 33 Lines

llvm/lib/Target/X86/X86MCInstLower.cpp

Show First 20 Lines • Show All 415 Lines • ▼ Show 20 Linesstatic void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg); MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
Inst = MCInst(); Inst = MCInst();
Inst.setOpcode(Opcode); Inst.setOpcode(Opcode);
Inst.addOperand(Saved); Inst.addOperand(Saved);
Inst.addOperand(Seg); Inst.addOperand(Seg);
} }
static unsigned getRetOpcode(const X86Subtarget &Subtarget) { static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
return Subtarget.is64Bit() ? X86::RETQ : X86::RETL; return Subtarget.is64Bit() ? X86::RET64 : X86::RET32;
} }
Optional<MCOperand> Optional<MCOperand>
X86MCInstLower::LowerMachineOperand(const MachineInstr *MI, X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
const MachineOperand &MO) const { const MachineOperand &MO) const {
switch (MO.getType()) { switch (MO.getType()) {
default: default:
MI->print(errs()); MI->print(errs());
▲ Show 20 Lines • Show All 2,443 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86RegisterInfo.cpp

Show First 20 Lines • Show All 810 Lines • ▼ Show 20 Linesunsigned X86RegisterInfo::findDeadCallerSavedReg(
if (MBBI == MBB.end()) if (MBBI == MBB.end())
return 0; return 0;
switch (MBBI->getOpcode()) { switch (MBBI->getOpcode()) {
default: default:
return 0; return 0;
case TargetOpcode::PATCHABLE_RET: case TargetOpcode::PATCHABLE_RET:
case X86::RET: case X86::RET:
case X86::RETL: case X86::RET32:
case X86::RETQ: case X86::RET64:
case X86::RETIL: case X86::RETI32:
case X86::RETIQ: case X86::RETI64:
case X86::TCRETURNdi: case X86::TCRETURNdi:
case X86::TCRETURNri: case X86::TCRETURNri:
case X86::TCRETURNmi: case X86::TCRETURNmi:
case X86::TCRETURNdi64: case X86::TCRETURNdi64:
case X86::TCRETURNri64: case X86::TCRETURNri64:
case X86::TCRETURNmi64: case X86::TCRETURNmi64:
case X86::EH_RETURN: case X86::EH_RETURN:
case X86::EH_RETURN64: { case X86::EH_RETURN64: {
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llvm/lib/Target/X86/X86SchedBroadwell.td

Show First 20 Lines • Show All 1,104 Lines • ▼ Show 20 Lines
} }
def: InstRW<[BWWriteResGroup82], (instrs FLDCW16m)>; def: InstRW<[BWWriteResGroup82], (instrs FLDCW16m)>;
def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
let Latency = 7; let Latency = 7;
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [1,1,1]; let ResourceCycles = [1,1,1];
} }
def: InstRW<[BWWriteResGroup84], (instrs LRETQ, RETQ)>; def: InstRW<[BWWriteResGroup84], (instrs LRET64, RET64)>;
def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> { def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
let Latency = 7; let Latency = 7;
let NumMicroOps = 5; let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2]; let ResourceCycles = [1,1,1,2];
} }
def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m(1|i)", def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m(1|i)",
"ROR(8|16|32|64)m(1|i)")>; "ROR(8|16|32|64)m(1|i)")>;
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llvm/lib/Target/X86/X86SchedHaswell.td

Show First 20 Lines • Show All 704 Lines • ▼ Show 20 Lines
//-- Control transfer instructions --// //-- Control transfer instructions --//
// CALL. // CALL.
// i. // i.
def HWWriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> { def HWWriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> {
let NumMicroOps = 4; let NumMicroOps = 4;
let ResourceCycles = [1, 2, 1]; let ResourceCycles = [1, 2, 1];
} }
def : InstRW<[HWWriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>; def : InstRW<[HWWriteRETI], (instregex "RETI(16|32|64)", "LRETI(16|32|64)")>;
// BOUND. // BOUND.
// r,m. // r,m.
def HWWriteBOUND : SchedWriteRes<[]> { def HWWriteBOUND : SchedWriteRes<[]> {
let NumMicroOps = 15; let NumMicroOps = 15;
} }
def : InstRW<[HWWriteBOUND], (instregex "BOUNDS(16|32)rm")>; def : InstRW<[HWWriteBOUND], (instregex "BOUNDS(16|32)rm")>;
▲ Show 20 Lines • Show All 461 Lines • ▼ Show 20 Lines
} }
def: InstRW<[HWWriteResGroup39], (instrs FLDCW16m)>; def: InstRW<[HWWriteResGroup39], (instrs FLDCW16m)>;
def HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> { def HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
let Latency = 7; let Latency = 7;
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [1,1,1]; let ResourceCycles = [1,1,1];
} }
def: InstRW<[HWWriteResGroup41], (instrs LRETQ, RETL, RETQ)>; def: InstRW<[HWWriteResGroup41], (instrs LRET64, RET32, RET64)>;
def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> { def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> {
let Latency = 3; let Latency = 3;
let NumMicroOps = 4; let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1]; let ResourceCycles = [1,1,1,1];
} }
def: InstRW<[HWWriteResGroup44], (instregex "CALL(16|32|64)r")>; def: InstRW<[HWWriteResGroup44], (instregex "CALL(16|32|64)r")>;
▲ Show 20 Lines • Show All 834 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86SchedIceLake.td

Show First 20 Lines • Show All 1,438 Lines • ▼ Show 20 Lines
} }
def: InstRW<[ICXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>; def: InstRW<[ICXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>;
def ICXWriteResGroup104 : SchedWriteRes<[ICXPort6,ICXPort23,ICXPort0156]> { def ICXWriteResGroup104 : SchedWriteRes<[ICXPort6,ICXPort23,ICXPort0156]> {
let Latency = 7; let Latency = 7;
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [1,1,1]; let ResourceCycles = [1,1,1];
} }
def: InstRW<[ICXWriteResGroup104], (instrs LRETQ, RETQ)>; def: InstRW<[ICXWriteResGroup104], (instrs LRET64, RET64)>;
def ICXWriteResGroup106 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort237]> { def ICXWriteResGroup106 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort237]> {
let Latency = 7; let Latency = 7;
let NumMicroOps = 4; let NumMicroOps = 4;
let ResourceCycles = [1,2,1]; let ResourceCycles = [1,2,1];
} }
def: InstRW<[ICXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)", def: InstRW<[ICXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",
"VCOMPRESSPS(Z|Z128|Z256)mr(b?)", "VCOMPRESSPS(Z|Z128|Z256)mr(b?)",
▲ Show 20 Lines • Show All 1,181 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86SchedSandyBridge.td

Show First 20 Lines • Show All 600 Lines • ▼ Show 20 Lines
def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> { def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> {
let Latency = 1; let Latency = 1;
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP, def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP,
LD_Frr, ST_Frr, ST_FPrr)>; LD_Frr, ST_Frr, ST_FPrr)>;
def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>; // FIXME: This seems wrong compared to other Intel CPUs. def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>; // FIXME: This seems wrong compared to other Intel CPUs.
def: InstRW<[SBWriteResGroup2], (instrs RETQ)>; def: InstRW<[SBWriteResGroup2], (instrs RET64)>;
def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> { def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> {
let Latency = 1; let Latency = 1;
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>; def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>;
▲ Show 20 Lines • Show All 616 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86SchedSkylakeClient.td

Show First 20 Lines • Show All 1,169 Lines • ▼ Show 20 Lines
} }
def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>; def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>;
def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> { def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
let Latency = 7; let Latency = 7;
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [1,1,1]; let ResourceCycles = [1,1,1];
} }
def: InstRW<[SKLWriteResGroup98], (instrs LRETQ, RETQ)>; def: InstRW<[SKLWriteResGroup98], (instrs LRET64, RET64)>;
def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
let Latency = 7; let Latency = 7;
let NumMicroOps = 5; let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2]; let ResourceCycles = [1,1,1,2];
} }
def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)", def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)",
"ROR(8|16|32|64)m(1|i)")>; "ROR(8|16|32|64)m(1|i)")>;
▲ Show 20 Lines • Show All 718 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86SchedSkylakeServer.td

Show First 20 Lines • Show All 1,430 Lines • ▼ Show 20 Lines
} }
def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>; def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>;
def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> { def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> {
let Latency = 7; let Latency = 7;
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [1,1,1]; let ResourceCycles = [1,1,1];
} }
def: InstRW<[SKXWriteResGroup104], (instrs LRETQ, RETQ)>; def: InstRW<[SKXWriteResGroup104], (instrs LRET64, RET64)>;
def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
let Latency = 7; let Latency = 7;
let NumMicroOps = 4; let NumMicroOps = 4;
let ResourceCycles = [1,2,1]; let ResourceCycles = [1,2,1];
} }
def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)", def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",
"VCOMPRESSPS(Z|Z128|Z256)mr(b?)", "VCOMPRESSPS(Z|Z128|Z256)mr(b?)",
▲ Show 20 Lines • Show All 1,181 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86ScheduleAtom.td

Show First 20 Lines • Show All 534 Lines • ▼ Show 20 Lines
} }
def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r, def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r,
POP16rmr, POP32rmr, POP64rmr, POP16rmr, POP32rmr, POP64rmr,
PUSH16r, PUSH32r, PUSH64r, PUSH16r, PUSH32r, PUSH64r,
PUSHi16, PUSHi32, PUSHi16, PUSHi32,
PUSH16rmr, PUSH32rmr, PUSH64rmr, PUSH16rmr, PUSH32rmr, PUSH64rmr,
PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32, PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32,
XCH_F)>; XCH_F)>;
def : InstRW<[AtomWrite0_1_1], (instregex "RETI(L|Q|W)$", def : InstRW<[AtomWrite0_1_1], (instregex "RETI(16|32|64)$",
"IRET(16|32|64)?")>; "IRET(16|32|64)?")>;
def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> { def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> {
let Latency = 5; let Latency = 5;
let ResourceCycles = [5, 5]; let ResourceCycles = [5, 5];
} }
def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIirm, MMX_CVTTPS2PIirm)>; def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIirm, MMX_CVTTPS2PIirm)>;
def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>; def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>;
▲ Show 20 Lines • Show All 262 Lines • ▼ Show 20 Linesdef AtomWrite01_78 : SchedWriteRes<[AtomPort01]> {
let ResourceCycles = [78]; let ResourceCycles = [78];
} }
def : InstRW<[AtomWrite01_78], (instrs RDMSR)>; def : InstRW<[AtomWrite01_78], (instrs RDMSR)>;
def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> { def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> {
let Latency = 79; let Latency = 79;
let ResourceCycles = [79]; let ResourceCycles = [79];
} }
def : InstRW<[AtomWrite01_79], (instregex "RET(L|Q|W)?$", def : InstRW<[AtomWrite01_79], (instregex "RET(16|32|64)?$",
"LRETI?(L|Q|W)")>; "LRETI?(16|32|64)")>;
def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> { def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> {
let Latency = 92; let Latency = 92;
let ResourceCycles = [92]; let ResourceCycles = [92];
} }
def : InstRW<[AtomWrite01_92], (instrs IN8ri, IN16ri, IN32ri)>; def : InstRW<[AtomWrite01_92], (instrs IN8ri, IN16ri, IN32ri)>;
def AtomWrite01_94 : SchedWriteRes<[AtomPort01]> { def AtomWrite01_94 : SchedWriteRes<[AtomPort01]> {
▲ Show 20 Lines • Show All 78 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86ScheduleZnver1.td

Show First 20 Lines • Show All 691 Lines • ▼ Show 20 Lines
def : InstRW<[ZnWriteCALLr], (instregex "CALL(16|32)r")>; def : InstRW<[ZnWriteCALLr], (instregex "CALL(16|32)r")>;
def : InstRW<[WriteMicrocoded], (instregex "CALL(16|32)m")>; def : InstRW<[WriteMicrocoded], (instregex "CALL(16|32)m")>;
// RET. // RET.
def ZnWriteRET : SchedWriteRes<[ZnALU03]> { def ZnWriteRET : SchedWriteRes<[ZnALU03]> {
let NumMicroOps = 2; let NumMicroOps = 2;
} }
def : InstRW<[ZnWriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)", def : InstRW<[ZnWriteRET], (instregex "RET(16|32|64)", "LRET(16|32|64)",
"IRET(16|32|64)")>; "IRET(16|32|64)")>;
//-- Logic instructions --// //-- Logic instructions --//
// AND OR XOR. // AND OR XOR.
// m,r/i. // m,r/i.
def : InstRW<[WriteALULd], def : InstRW<[WriteALULd],
(instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)", (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)",
▲ Show 20 Lines • Show All 836 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86ScheduleZnver2.td

Show First 20 Lines • Show All 691 Lines • ▼ Show 20 Lines
def : InstRW<[Zn2WriteCALLr], (instregex "CALL(16|32)r")>; def : InstRW<[Zn2WriteCALLr], (instregex "CALL(16|32)r")>;
def : InstRW<[WriteMicrocoded], (instregex "CALL(16|32)m")>; def : InstRW<[WriteMicrocoded], (instregex "CALL(16|32)m")>;
// RET. // RET.
def Zn2WriteRET : SchedWriteRes<[Zn2ALU03]> { def Zn2WriteRET : SchedWriteRes<[Zn2ALU03]> {
let NumMicroOps = 2; let NumMicroOps = 2;
} }
def : InstRW<[Zn2WriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)", def : InstRW<[Zn2WriteRET], (instregex "RET(16|32|64)", "LRET(16|32|64)",
"IRET(16|32|64)")>; "IRET(16|32|64)")>;
//-- Logic instructions --// //-- Logic instructions --//
// AND OR XOR. // AND OR XOR.
// m,r/i. // m,r/i.
def : InstRW<[WriteALULd], def : InstRW<[WriteALULd],
(instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)", (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)",
▲ Show 20 Lines • Show All 825 Lines • Show Last 20 Lines

llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables.mir

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines bb.0.entry:
; dead-mi-elimination will remove %15:gr32 = ... ; dead-mi-elimination will remove %15:gr32 = ...
%15:gr32 = MOV32rm %stack.0.a.addr, 1, $noreg, 0, $noreg :: (load (s32) from %ir.a.addr) %15:gr32 = MOV32rm %stack.0.a.addr, 1, $noreg, 0, $noreg :: (load (s32) from %ir.a.addr)
MOV32mr %stack.2.c, 1, $noreg, 0, $noreg, killed %13 :: (store (s32) into %ir.c) MOV32mr %stack.2.c, 1, $noreg, 0, $noreg, killed %13 :: (store (s32) into %ir.c)
%9:gr32 = MOV32rm %stack.2.c, 1, $noreg, 0, $noreg :: (load (s32) from %ir.c) %9:gr32 = MOV32rm %stack.2.c, 1, $noreg, 0, $noreg :: (load (s32) from %ir.c)
%8:gr32 = SHL32ri killed %9, 1, implicit-def $eflags %8:gr32 = SHL32ri killed %9, 1, implicit-def $eflags
MOV32mr $noreg, 1, $noreg, @ga, $noreg, killed %8 :: (store (s32) into @ga) MOV32mr $noreg, 1, $noreg, @ga, $noreg, killed %8 :: (store (s32) into @ga)
%5:gr32 = MOV32rm %stack.2.c, 1, $noreg, 0, $noreg :: (load (s32) from %ir.c) %5:gr32 = MOV32rm %stack.2.c, 1, $noreg, 0, $noreg :: (load (s32) from %ir.c)
$eax = COPY %5 $eax = COPY %5
RETQ implicit $eax RET64 implicit $eax
;CHECK: WARNING: Missing line 9 ;CHECK: WARNING: Missing line 9
;CHECK-NEXT: Machine IR debug info check: FAIL ;CHECK-NEXT: Machine IR debug info check: FAIL
;CHECK-PASS: Machine IR debug info check: PASS ;CHECK-PASS: Machine IR debug info check: PASS
... ...

llvm/test/CodeGen/MIR/X86/auto-successor.mir

# RUN: llc -mtriple=x86_64-- -o - %s -run-pass=none -verify-machineinstrs -simplify-mir | FileCheck %s # RUN: llc -mtriple=x86_64-- -o - %s -run-pass=none -verify-machineinstrs -simplify-mir | FileCheck %s
--- ---
# We shouldn't need any explicit successor lists in these examples # We shouldn't need any explicit successor lists in these examples
# CHECK-LABEL: name: func0 # CHECK-LABEL: name: func0
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NOT: successors # CHECK-NOT: successors
# CHECK: JCC_1 %bb.1, 4, implicit undef $eflags # CHECK: JCC_1 %bb.1, 4, implicit undef $eflags
# CHECK: JMP_1 %bb.3 # CHECK: JMP_1 %bb.3
# CHECK: bb.1: # CHECK: bb.1:
# CHECK-NOT: successors # CHECK-NOT: successors
# CHECK: bb.2: # CHECK: bb.2:
# CHECK-NOT: successors # CHECK-NOT: successors
# CHECK: JCC_1 %bb.1, 4, implicit undef $eflags # CHECK: JCC_1 %bb.1, 4, implicit undef $eflags
# CHECK: bb.3: # CHECK: bb.3:
# CHECK: RETQ undef $eax # CHECK: RET64 undef $eax
name: func0 name: func0
body: | body: |
bb.0: bb.0:
JCC_1 %bb.1, 4, implicit undef $eflags JCC_1 %bb.1, 4, implicit undef $eflags
JMP_1 %bb.3 JMP_1 %bb.3
bb.1: bb.1:
bb.2: bb.2:
JCC_1 %bb.1, 4, implicit undef $eflags JCC_1 %bb.1, 4, implicit undef $eflags
bb.3: bb.3:
JCC_1 %bb.4, 4, implicit undef $eflags ; condjump+fallthrough to same block JCC_1 %bb.4, 4, implicit undef $eflags ; condjump+fallthrough to same block
bb.4: bb.4:
RETQ undef $eax RET64 undef $eax
... ...
--- ---
# Some cases that need explicit successors: # Some cases that need explicit successors:
# CHECK-LABEL: name: func1 # CHECK-LABEL: name: func1
name: func1 name: func1
body: | body: |
bb.0: bb.0:
; CHECK: bb.0: ; CHECK: bb.0:
Show All 11 Linesbody: |
bb.2: bb.2:
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: successors: %bb.1(0x60000000), %bb.3(0x20000000) ; CHECK: successors: %bb.1(0x60000000), %bb.3(0x20000000)
successors: %bb.1(3), %bb.3(1) ; branch probabilities not normalized successors: %bb.1(3), %bb.3(1) ; branch probabilities not normalized
JCC_1 %bb.1, 4, implicit undef $eflags JCC_1 %bb.1, 4, implicit undef $eflags
bb.3: bb.3:
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: RETQ undef $eax ; CHECK: RET64 undef $eax
RETQ undef $eax RET64 undef $eax
... ...

llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir

Show All 25 Lines
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: bb.0.body: ; CHECK-LABEL: bb.0.body:
; CHECK-NEXT: liveins: $edi, $esi ; CHECK-NEXT: liveins: $edi, $esi
bb.0.body: bb.0.body:
liveins: $edi, $esi liveins: $edi, $esi
$eax = LEA64_32r killed $rdi, 1, killed $rsi, 0, _ $eax = LEA64_32r killed $rdi, 1, killed $rsi, 0, _
RETQ $eax RET64 $eax
... ...
--- ---
name: test2 name: test2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: test2 ; CHECK-LABEL: name: test2
; Verify that we can have multiple lists of liveins that will be merged into ; Verify that we can have multiple lists of liveins that will be merged into
; one. ; one.
; CHECK: bb.0.body: ; CHECK: bb.0.body:
; CHECK-NEXT: liveins: $edi, $esi ; CHECK-NEXT: liveins: $edi, $esi
bb.0.body: bb.0.body:
liveins: $edi liveins: $edi
liveins: $esi liveins: $esi
$eax = LEA64_32r killed $rdi, 1, killed $rsi, 0, _ $eax = LEA64_32r killed $rdi, 1, killed $rsi, 0, _
RETQ $eax RET64 $eax
... ...
--- ---
name: test3 name: test3
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; Verify that we can have an empty list of liveins. ; Verify that we can have an empty list of liveins.
; CHECK-LABEL: name: test3 ; CHECK-LABEL: name: test3
; CHECK: bb.0.body: ; CHECK: bb.0.body:
; CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags ; CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags
bb.0.body: bb.0.body:
liveins: liveins:
$eax = MOV32r0 implicit-def dead $eflags $eax = MOV32r0 implicit-def dead $eflags
RETQ killed $eax RET64 killed $eax
... ...

llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir

Show All 25 Lines bb.0.entry:
liveins: $edi 44 liveins: $edi 44
CMP32ri8 $edi, 10, implicit-def $eflags CMP32ri8 $edi, 10, implicit-def $eflags
JCC_1 %bb.2.exit, 15, implicit killed $eflags JCC_1 %bb.2.exit, 15, implicit killed $eflags
; CHECK: [[@LINE+1]]:8: basic block definition should be located at the start of the line ; CHECK: [[@LINE+1]]:8: basic block definition should be located at the start of the line
less bb.1: less bb.1:
$eax = MOV32r0 implicit-def dead $eflags $eax = MOV32r0 implicit-def dead $eflags
RETQ killed $eax RET64 killed $eax
bb.2.exit: bb.2.exit:
liveins: $edi liveins: $edi
$eax = COPY killed $edi $eax = COPY killed $edi
RETQ killed $eax RET64 killed $eax
... ...

llvm/test/CodeGen/MIR/X86/block-address-operands.mir

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Linesbody: |
bb.0.entry: bb.0.entry:
successors: %bb.1.block successors: %bb.1.block
; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test, %ir-block.block), $noreg ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test, %ir-block.block), $noreg
$rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block.block), _ $rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block.block), _
MOV64mr $rip, 1, _, @addr, _, killed $rax MOV64mr $rip, 1, _, @addr, _, killed $rax
JMP64m $rip, 1, _, @addr, _ JMP64m $rip, 1, _, @addr, _
bb.1.block (address-taken): bb.1.block (address-taken):
RETQ RET64
... ...
--- ---
name: test2 name: test2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.entry: bb.0.entry:
successors: %bb.1 successors: %bb.1
; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test2, %ir-block."quoted block"), $noreg ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test2, %ir-block."quoted block"), $noreg
$rax = LEA64r $rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _ $rax = LEA64r $rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _
MOV64mr $rip, 1, _, @addr, _, killed $rax MOV64mr $rip, 1, _, @addr, _, killed $rax
JMP64m $rip, 1, _, @addr, _ JMP64m $rip, 1, _, @addr, _
bb.1 (address-taken): bb.1 (address-taken):
RETQ RET64
... ...
--- ---
name: slot_in_other_function name: slot_in_other_function
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK-LABEL: name: slot_in_other_function ; CHECK-LABEL: name: slot_in_other_function
; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test3, %ir-block.0), $noreg ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test3, %ir-block.0), $noreg
$rax = LEA64r $rip, 1, _, blockaddress(@test3, %ir-block.0), _ $rax = LEA64r $rip, 1, _, blockaddress(@test3, %ir-block.0), _
MOV64mr killed $rdi, 1, _, 0, _, killed $rax MOV64mr killed $rdi, 1, _, 0, _, killed $rax
RETQ RET64
... ...
--- ---
name: test3 name: test3
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.entry: bb.0.entry:
successors: %bb.1 successors: %bb.1
; CHECK-LABEL: name: test3 ; CHECK-LABEL: name: test3
; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test3, %ir-block.0), $noreg ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test3, %ir-block.0), $noreg
$rax = LEA64r $rip, 1, _, blockaddress(@test3, %ir-block.0), _ $rax = LEA64r $rip, 1, _, blockaddress(@test3, %ir-block.0), _
MOV64mr $rip, 1, _, @addr, _, killed $rax MOV64mr $rip, 1, _, @addr, _, killed $rax
JMP64m $rip, 1, _, @addr, _ JMP64m $rip, 1, _, @addr, _
bb.1 (address-taken): bb.1 (address-taken):
RETQ RET64
... ...
--- ---
name: test4 name: test4
body: | body: |
bb.0.entry: bb.0.entry:
successors: %bb.1.block successors: %bb.1.block
; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test, %ir-block.block) + 2, $noreg ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test, %ir-block.block) + 2, $noreg
$rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _ $rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _
MOV64mr $rip, 1, _, @addr, _, killed $rax MOV64mr $rip, 1, _, @addr, _, killed $rax
JMP64m $rip, 1, _, @addr, _ JMP64m $rip, 1, _, @addr, _
bb.1.block (address-taken): bb.1.block (address-taken):
RETQ RET64
... ...

llvm/test/CodeGen/MIR/X86/branch-probabilities.mir

# RUN: llc -o - %s -mtriple=x86_64-- -run-pass=none | FileCheck %s # RUN: llc -o - %s -mtriple=x86_64-- -run-pass=none | FileCheck %s
--- ---
# Check that branch probabilities are printed correctly as hex numbers. # Check that branch probabilities are printed correctly as hex numbers.
# CHECK-LABEL: name: test # CHECK-LABEL: name: test
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NEXT: successors: %bb.1(0x66666666), %bb.2(0x1999999a) # CHECK-NEXT: successors: %bb.1(0x66666666), %bb.2(0x1999999a)
name: test name: test
body: | body: |
bb.0: bb.0:
successors: %bb.1(4), %bb.2(1) successors: %bb.1(4), %bb.2(1)
JCC_1 %bb.2, 4, implicit undef $eflags JCC_1 %bb.2, 4, implicit undef $eflags
bb.1: bb.1:
NOOP NOOP
bb.2: bb.2:
RETQ undef $eax RET64 undef $eax
... ...

llvm/test/CodeGen/MIR/X86/callee-saved-info.mir

Show All 33 Lines
--- ---
name: compute name: compute
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.body: bb.0.body:
liveins: $edi liveins: $edi
$eax = COPY killed $edi $eax = COPY killed $edi
RETQ killed $eax RET64 killed $eax
... ...
--- ---
name: func name: func
tracksRegLiveness: true tracksRegLiveness: true
frameInfo: frameInfo:
stackSize: 24 stackSize: 24
maxAlignment: 4 maxAlignment: 4
adjustsStack: true adjustsStack: true
Show All 36 Lines bb.2.loop:
$eax = DEC32r killed $eax, implicit-def dead $eflags $eax = DEC32r killed $eax, implicit-def dead $eflags
MOV32mr $rsp, 1, _, 12, _, killed $eax MOV32mr $rsp, 1, _, 12, _, killed $eax
JMP_1 %bb.1.check JMP_1 %bb.1.check
bb.3.exit: bb.3.exit:
$eax = MOV32r0 implicit-def dead $eflags $eax = MOV32r0 implicit-def dead $eflags
$rsp = ADD64ri8 $rsp, 16, implicit-def dead $eflags $rsp = ADD64ri8 $rsp, 16, implicit-def dead $eflags
$rbx = POP64r implicit-def $rsp, implicit $rsp $rbx = POP64r implicit-def $rsp, implicit $rsp
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir

Show All 18 Lines
stack: stack:
- { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 } - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
$rsp = SUB64ri32 $rsp, 4040, implicit-def dead $eflags $rsp = SUB64ri32 $rsp, 4040, implicit-def dead $eflags
; CHECK: CFI_INSTRUCTION def_cfa_offset 4048 ; CHECK: CFI_INSTRUCTION def_cfa_offset 4048
CFI_INSTRUCTION def_cfa_offset 4048 CFI_INSTRUCTION def_cfa_offset 4048
$rsp = ADD64ri32 $rsp, 4040, implicit-def dead $eflags $rsp = ADD64ri32 $rsp, 4040, implicit-def dead $eflags
RETQ RET64
... ...

llvm/test/CodeGen/MIR/X86/cfi-offset.mir

Show All 36 Lines bb.0.entry:
$ebx = COPY $edi, implicit-def $rbx $ebx = COPY $edi, implicit-def $rbx
$ebx = ADD32rr $ebx, killed $esi, implicit-def dead $eflags $ebx = ADD32rr $ebx, killed $esi, implicit-def dead $eflags
$ebx = ADD32rr $ebx, killed $edx, implicit-def dead $eflags $ebx = ADD32rr $ebx, killed $edx, implicit-def dead $eflags
$ebx = ADD32rr $ebx, killed $ecx, implicit-def dead $eflags $ebx = ADD32rr $ebx, killed $ecx, implicit-def dead $eflags
$edi = COPY $ebx $edi = COPY $ebx
CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp
$eax = LEA64_32r killed $rbx, 1, $rbx, 0, _ $eax = LEA64_32r killed $rbx, 1, $rbx, 0, _
$rbx = POP64r implicit-def $rsp, implicit $rsp $rbx = POP64r implicit-def $rsp, implicit $rsp
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir

Show All 14 Linesconstants:
- id: 0 - id: 0
value: 'double 3.250000e+00' value: 'double 3.250000e+00'
# CHECK: [[@LINE+1]]:18: redefinition of constant pool item '%const.0' # CHECK: [[@LINE+1]]:18: redefinition of constant pool item '%const.0'
- id: 0 - id: 0
value: 'double 3.250000e+00' value: 'double 3.250000e+00'
body: | body: |
bb.0.entry: bb.0.entry:
%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
RETQ %xmm0 RET64 %xmm0
... ...

llvm/test/CodeGen/MIR/X86/constant-pool.mir

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.0, $noreg, implicit $mxcsr ; CHECK: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.0, $noreg, implicit $mxcsr
; CHECK-NEXT: $xmm1 = ADDSSrm killed $xmm1, $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr ; CHECK-NEXT: $xmm1 = ADDSSrm killed $xmm1, $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr
$xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _, implicit $mxcsr $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _, implicit $mxcsr
$xmm1 = ADDSSrm killed $xmm1, $rip, 1, _, %const.1, _, implicit $mxcsr $xmm1 = ADDSSrm killed $xmm1, $rip, 1, _, %const.1, _, implicit $mxcsr
$xmm1 = CVTSS2SDrr killed $xmm1, implicit $mxcsr $xmm1 = CVTSS2SDrr killed $xmm1, implicit $mxcsr
$xmm0 = MULSDrr killed $xmm0, killed $xmm1, implicit $mxcsr $xmm0 = MULSDrr killed $xmm0, killed $xmm1, implicit $mxcsr
RETQ $xmm0 RET64 $xmm0
... ...
--- ---
# Verify that alignment can be inferred: # Verify that alignment can be inferred:
# CHECK: name: test2 # CHECK: name: test2
# CHECK: constants: # CHECK: constants:
# CHECK-NEXT: - id: 0 # CHECK-NEXT: - id: 0
# CHECK-NEXT: value: 'double 3.250000e+00' # CHECK-NEXT: value: 'double 3.250000e+00'
# CHECK-NEXT: alignment: 8 # CHECK-NEXT: alignment: 8
Show All 9 Linesconstants:
- id: 1 - id: 1
value: 'float 6.250000e+00' value: 'float 6.250000e+00'
body: | body: |
bb.0.entry: bb.0.entry:
$xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _, implicit $mxcsr $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _, implicit $mxcsr
$xmm1 = ADDSSrm killed $xmm1, $rip, 1, _, %const.1, _, implicit $mxcsr $xmm1 = ADDSSrm killed $xmm1, $rip, 1, _, %const.1, _, implicit $mxcsr
$xmm1 = CVTSS2SDrr killed $xmm1, implicit $mxcsr $xmm1 = CVTSS2SDrr killed $xmm1, implicit $mxcsr
$xmm0 = MULSDrr killed $xmm0, killed $xmm1, implicit $mxcsr $xmm0 = MULSDrr killed $xmm0, killed $xmm1, implicit $mxcsr
RETQ $xmm0 RET64 $xmm0
... ...
--- ---
# Verify that the non-standard alignments are respected: # Verify that the non-standard alignments are respected:
# CHECK: name: test3 # CHECK: name: test3
# CHECK: constants: # CHECK: constants:
# CHECK-NEXT: - id: 0 # CHECK-NEXT: - id: 0
# CHECK-NEXT: value: 'double 3.250000e+00' # CHECK-NEXT: value: 'double 3.250000e+00'
# CHECK-NEXT: alignment: 128 # CHECK-NEXT: alignment: 128
Show All 13 Lines
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.0, $noreg, implicit $mxcsr ; CHECK: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.0, $noreg, implicit $mxcsr
; CHECK-NEXT: $xmm1 = ADDSSrm killed $xmm1, $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr ; CHECK-NEXT: $xmm1 = ADDSSrm killed $xmm1, $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr
$xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _, implicit $mxcsr $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _, implicit $mxcsr
$xmm1 = ADDSSrm killed $xmm1, $rip, 1, _, %const.1, _, implicit $mxcsr $xmm1 = ADDSSrm killed $xmm1, $rip, 1, _, %const.1, _, implicit $mxcsr
$xmm1 = CVTSS2SDrr killed $xmm1, implicit $mxcsr $xmm1 = CVTSS2SDrr killed $xmm1, implicit $mxcsr
$xmm0 = MULSDrr killed $xmm0, killed $xmm1, implicit $mxcsr $xmm0 = MULSDrr killed $xmm0, killed $xmm1, implicit $mxcsr
RETQ $xmm0 RET64 $xmm0
... ...
--- ---
# CHECK: name: test4 # CHECK: name: test4
name: test4 name: test4
constants: constants:
- id: 0 - id: 0
value: 'double 3.250000e+00' value: 'double 3.250000e+00'
- id: 1 - id: 1
value: 'float 6.250000e+00' value: 'float 6.250000e+00'
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.1 - 12, $noreg, implicit $mxcsr ; CHECK: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.1 - 12, $noreg, implicit $mxcsr
; CHECK-NEXT: $xmm1 = ADDSSrm killed $xmm1, $rip, 1, $noreg, %const.0 + 8, $noreg, implicit $mxcsr ; CHECK-NEXT: $xmm1 = ADDSSrm killed $xmm1, $rip, 1, $noreg, %const.0 + 8, $noreg, implicit $mxcsr
$xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.1 - 12, _, implicit $mxcsr $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.1 - 12, _, implicit $mxcsr
$xmm1 = ADDSSrm killed $xmm1, $rip, 1, _, %const.0 + 8, _, implicit $mxcsr $xmm1 = ADDSSrm killed $xmm1, $rip, 1, _, %const.0 + 8, _, implicit $mxcsr
$xmm1 = CVTSS2SDrr killed $xmm1, implicit $mxcsr $xmm1 = CVTSS2SDrr killed $xmm1, implicit $mxcsr
$xmm0 = MULSDrr killed $xmm0, killed $xmm1, implicit $mxcsr $xmm0 = MULSDrr killed $xmm0, killed $xmm1, implicit $mxcsr
RETQ $xmm0 RET64 $xmm0
... ...

llvm/test/CodeGen/MIR/X86/constant-value-error.mir

Show All 14 Lines
name: test name: test
constants: constants:
- id: 0 - id: 0
# CHECK: [[@LINE+1]]:19: expected type # CHECK: [[@LINE+1]]:19: expected type
value: 'dub 3.250000e+00' value: 'dub 3.250000e+00'
body: | body: |
bb.0.entry: bb.0.entry:
%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
RETQ %xmm0 RET64 %xmm0
... ...

llvm/test/CodeGen/MIR/X86/dbg-value-list.mir

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines bb.0.entry:
DBG_VALUE $edi, $noreg, !12, !DIExpression(), debug-location !15 DBG_VALUE $edi, $noreg, !12, !DIExpression(), debug-location !15
DBG_VALUE $esi, $noreg, !13, !DIExpression(), debug-location !15 DBG_VALUE $esi, $noreg, !13, !DIExpression(), debug-location !15
$eax = MOV32rr $edi $eax = MOV32rr $edi
DBG_VALUE_LIST !14, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_stack_value), $edi, $esi, debug-location !15 DBG_VALUE_LIST !14, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_stack_value), $edi, $esi, debug-location !15
DBG_VALUE $esi, $noreg, !13, !DIExpression(), debug-location !15 DBG_VALUE $esi, $noreg, !13, !DIExpression(), debug-location !15
DBG_VALUE $eax, $noreg, !12, !DIExpression(), debug-location !15 DBG_VALUE $eax, $noreg, !12, !DIExpression(), debug-location !15
renamable $eax = nsw IMUL32rr killed renamable $eax, killed renamable $esi, implicit-def dead $eflags, debug-location !16 renamable $eax = nsw IMUL32rr killed renamable $eax, killed renamable $esi, implicit-def dead $eflags, debug-location !16
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/CodeGen/MIR/X86/dead-register-flag.mir

Show All 14 Lines
... ...
--- ---
name: foo name: foo
body: | body: |
; CHECK: bb.0.body: ; CHECK: bb.0.body:
bb.0.body: bb.0.body:
; CHECK: $eax = IMUL32rri8 $edi, 11, implicit-def dead $eflags ; CHECK: $eax = IMUL32rri8 $edi, 11, implicit-def dead $eflags
$eax = IMUL32rri8 $edi, 11, implicit-def dead $eflags $eax = IMUL32rri8 $edi, 11, implicit-def dead $eflags
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir

Show All 14 Linesliveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: [[@LINE+1]]:83: the tied-def operand #3 is already tied with another register operand ; CHECK: [[@LINE+1]]:83: the tied-def operand #3 is already tied with another register operand
INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(tied-def 3), killed $rdi(tied-def 3) INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(tied-def 3), killed $rdi(tied-def 3)
$rax = COPY killed $rdi $rax = COPY killed $rdi
RETQ killed $rax RET64 killed $rax
... ...

llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir

Show All 17 Linesliveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: [[@LINE+1]]:50: duplicate 'volatile' memory operand flag ; CHECK: [[@LINE+1]]:50: duplicate 'volatile' memory operand flag
$eax = MOV32rm $rdi, 1, _, 0, _ :: (volatile volatile load (s32) from %ir.x) $eax = MOV32rm $rdi, 1, _, 0, _ :: (volatile volatile load (s32) from %ir.x)
$eax = INC32r killed $eax, implicit-def dead $eflags $eax = INC32r killed $eax, implicit-def dead $eflags
MOV32mr killed $rdi, 1, _, 0, _, $eax :: (volatile store (s32) into %ir.x) MOV32mr killed $rdi, 1, _, 0, _, $eax :: (volatile store (s32) into %ir.x)
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir

Show All 21 Lines bb.0.entry:
successors: %bb.1.less, %bb.2.exit successors: %bb.1.less, %bb.2.exit
CMP32ri8 $edi, 10, implicit-def $eflags CMP32ri8 $edi, 10, implicit-def $eflags
; CHECK: [[@LINE+1]]:36: duplicate 'implicit' register flag ; CHECK: [[@LINE+1]]:36: duplicate 'implicit' register flag
JCC_1 %bb.2.exit, 15, implicit implicit $eflags JCC_1 %bb.2.exit, 15, implicit implicit $eflags
bb.1.less: bb.1.less:
$eax = MOV32r0 implicit-def $eflags $eax = MOV32r0 implicit-def $eflags
RETQ $eax RET64 $eax
bb.2.exit: bb.2.exit:
$eax = COPY $edi $eax = COPY $edi
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir

Show All 34 Lines bb.0.entry:
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
$ecx = COPY $edi $ecx = COPY $edi
$ecx = ADD32rr killed $ecx, killed $esi, implicit-def dead $eflags $ecx = ADD32rr killed $ecx, killed $esi, implicit-def dead $eflags
; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $ax, 12 /* clobber */, implicit-def dead early-clobber $di ; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $ax, 12 /* clobber */, implicit-def dead early-clobber $di
INLINEASM &nop, 1, 12, implicit-def dead early-clobber $ax, 12, implicit-def dead early-clobber $di INLINEASM &nop, 1, 12, implicit-def dead early-clobber $ax, 12, implicit-def dead early-clobber $di
$edi = COPY killed $ecx $edi = COPY killed $ecx
CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp
$rax = POP64r implicit-def $rsp, implicit $rsp $rax = POP64r implicit-def $rsp, implicit $rsp
RETQ RET64
... ...

llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir

Show All 20 Lines bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: [[@LINE+1]]:69: expected 'align' ; CHECK: [[@LINE+1]]:69: expected 'align'
$xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load (s128) from %ir.vec, 32) $xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load (s128) from %ir.vec, 32)
$xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load (s128) from %ir.vec + 16, basealign 32) $xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load (s128) from %ir.vec + 16, basealign 32)
$xmm2 = FsFLD0SS $xmm2 = FsFLD0SS
$xmm1 = MOVSSrr killed $xmm1, killed $xmm2 $xmm1 = MOVSSrr killed $xmm1, killed $xmm2
MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store (s128) into %ir.vec, align 32) MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store (s128) into %ir.vec, align 32)
MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store (s128) into %ir.vec + 16, basealign 32) MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store (s128) into %ir.vec + 16, basealign 32)
RETQ RET64
... ...

llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir

Show All 20 Lines bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: [[@LINE+1]]:74: expected an integer literal after 'align' ; CHECK: [[@LINE+1]]:74: expected an integer literal after 'align'
$xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load (s128) from %ir.vec, align) $xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load (s128) from %ir.vec, align)
$xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load (s128) from %ir.vec + 16, basealign 32) $xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load (s128) from %ir.vec + 16, basealign 32)
$xmm2 = FsFLD0SS $xmm2 = FsFLD0SS
$xmm1 = MOVSSrr killed $xmm1, killed $xmm2 $xmm1 = MOVSSrr killed $xmm1, killed $xmm2
MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store (s128) into %ir.vec, align 32) MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store (s128) into %ir.vec, align 32)
MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store (s128) into %ir.vec + 16, basealign 32) MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store (s128) into %ir.vec + 16, basealign 32)
RETQ RET64
... ...

llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir

Show All 24 Linesbody: |
successors: %bb.1.less, %bb.2.exit successors: %bb.1.less, %bb.2.exit
liveins: $edi 44 liveins: $edi 44
CMP32ri8 $edi, 10, implicit-def $eflags CMP32ri8 $edi, 10, implicit-def $eflags
JCC_1 %bb.2.exit, 15, implicit killed $eflags JCC_1 %bb.2.exit, 15, implicit killed $eflags
bb.1.less: bb.1.less:
$eax = MOV32r0 implicit-def dead $eflags $eax = MOV32r0 implicit-def dead $eflags
RETQ killed $eax RET64 killed $eax
bb.2.exit: bb.2.exit:
liveins: $edi liveins: $edi
$eax = COPY killed $edi $eax = COPY killed $edi
RETQ killed $eax RET64 killed $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir

Show All 20 Linesbody: |
bb.0.entry: bb.0.entry:
successors: %bb.1.block successors: %bb.1.block
; CHECK: [[@LINE+1]]:51: expected an IR block reference ; CHECK: [[@LINE+1]]:51: expected an IR block reference
$rax = LEA64r $rip, 1, _, blockaddress(@test, _), _ $rax = LEA64r $rip, 1, _, blockaddress(@test, _), _
MOV64mr $rip, 1, _, @addr, _, killed $rax MOV64mr $rip, 1, _, @addr, _, killed $rax
JMP64m $rip, 1, _, @addr, _ JMP64m $rip, 1, _, @addr, _
bb.1.block (address-taken): bb.1.block (address-taken):
RETQ RET64
... ...

llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir

Show All 32 Lines bb.0.entry:
$ebx = COPY $edi, implicit-def $rbx $ebx = COPY $edi, implicit-def $rbx
$ebx = ADD32rr $ebx, killed $esi, implicit-def dead $eflags $ebx = ADD32rr $ebx, killed $esi, implicit-def dead $eflags
$ebx = ADD32rr $ebx, killed $edx, implicit-def dead $eflags $ebx = ADD32rr $ebx, killed $edx, implicit-def dead $eflags
$ebx = ADD32rr $ebx, killed $ecx, implicit-def dead $eflags $ebx = ADD32rr $ebx, killed $ecx, implicit-def dead $eflags
$edi = COPY $ebx $edi = COPY $ebx
CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp
$eax = LEA64_32r killed $rbx, 1, $rbx, 0, _ $eax = LEA64_32r killed $rbx, 1, $rbx, 0, _
$rbx = POP64r implicit-def $rsp, implicit $rsp $rbx = POP64r implicit-def $rsp, implicit $rsp
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir

Show All 15 Lines
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry2: bb.0.entry2:
liveins: $rdi liveins: $rdi
; CHECK: [[@LINE+1]]:91: expected ',' before the next machine memory operand ; CHECK: [[@LINE+1]]:91: expected ',' before the next machine memory operand
INC32m killed $rdi, 1, _, 0, _, implicit-def dead $eflags :: (store (s32) into %ir.a) (load (s32) from %ir.a) INC32m killed $rdi, 1, _, 0, _, implicit-def dead $eflags :: (store (s32) into %ir.a) (load (s32) from %ir.a)
RETQ RET64
... ...

llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir

Show All 24 Lines bb.0.entry:
CMP32ri8 $eax, 10, implicit-def $eflags CMP32ri8 $eax, 10, implicit-def $eflags
; CHECK: [[@LINE+1]]:40: missing implicit register operand 'implicit $eflags' ; CHECK: [[@LINE+1]]:40: missing implicit register operand 'implicit $eflags'
JCC_1 %bb.2.exit, 15, implicit $eax JCC_1 %bb.2.exit, 15, implicit $eax
bb.1.less: bb.1.less:
$eax = MOV32r0 implicit-def $eflags $eax = MOV32r0 implicit-def $eflags
bb.2.exit: bb.2.exit:
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir

Show All 24 Lines bb.0.entry:
CMP32ri8 $eax, 10, implicit-def $eflags CMP32ri8 $eax, 10, implicit-def $eflags
; CHECK: [[@LINE+1]]:47: missing implicit register operand 'implicit $eflags' ; CHECK: [[@LINE+1]]:47: missing implicit register operand 'implicit $eflags'
JCC_1 %bb.2.exit, 15, implicit-def $eflags JCC_1 %bb.2.exit, 15, implicit-def $eflags
bb.1.less: bb.1.less:
$eax = MOV32r0 implicit-def $eflags $eax = MOV32r0 implicit-def $eflags
bb.2.exit: bb.2.exit:
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir

Show All 20 Linesbody: |
bb.0.entry: bb.0.entry:
successors: %bb.1.block successors: %bb.1.block
; CHECK: [[@LINE+1]]:44: expected an IR function reference ; CHECK: [[@LINE+1]]:44: expected an IR function reference
$rax = LEA64r $rip, 1, _, blockaddress(@addr, %ir-block.block), _ $rax = LEA64r $rip, 1, _, blockaddress(@addr, %ir-block.block), _
MOV64mr $rip, 1, _, @addr, _, killed $rax MOV64mr $rip, 1, _, @addr, _, killed $rax
JMP64m $rip, 1, _, @addr, _ JMP64m $rip, 1, _, @addr, _
bb.1.block (address-taken): bb.1.block (address-taken):
RETQ RET64
... ...

llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir

Show All 20 Linesbody: |
bb.0.entry: bb.0.entry:
successors: %bb.1.block successors: %bb.1.block
; CHECK: [[@LINE+1]]:44: expected a global value ; CHECK: [[@LINE+1]]:44: expected a global value
$rax = LEA64r $rip, 1, _, blockaddress(0, %ir-block.block), _ $rax = LEA64r $rip, 1, _, blockaddress(0, %ir-block.block), _
MOV64mr $rip, 1, _, @addr, _, killed $rax MOV64mr $rip, 1, _, @addr, _, killed $rax
JMP64m $rip, 1, _, @addr, _ JMP64m $rip, 1, _, @addr, _
bb.1.block (address-taken): bb.1.block (address-taken):
RETQ RET64
... ...

llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir

Show All 14 Lines
--- ---
name: inc name: inc
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: [[@LINE+1]]:37: expected an integer literal after '+' ; CHECK: [[@LINE+1]]:37: expected an integer literal after '+'
$rax = MOV64rm $rip, 1, _, @G + , _ $rax = MOV64rm $rip, 1, _, @G + , _
$eax = MOV32rm $rax, 1, _, 0, _ $eax = MOV32rm $rax, 1, _, 0, _
$eax = INC32r $eax, implicit-def $eflags $eax = INC32r $eax, implicit-def $eflags
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir

Show All 14 Linesliveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: [[@LINE+1]]:78: expected tied-def or low-level type after '(' ; CHECK: [[@LINE+1]]:78: expected tied-def or low-level type after '('
INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(tied-def) INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(tied-def)
$rax = COPY killed $rdi $rax = COPY killed $rdi
RETQ killed $rax RET64 killed $rax
... ...

llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir

Show All 22 Lines ; CHECK: [[@LINE+1]]:29: expected an integer literal after '('
successors: %bb.1.less (_), %bb.2.exit(32) successors: %bb.1.less (_), %bb.2.exit(32)
liveins: $edi liveins: $edi
CMP32ri8 $edi, 10, implicit-def $eflags CMP32ri8 $edi, 10, implicit-def $eflags
JCC_1 %bb.2.exit, 15, implicit killed $eflags JCC_1 %bb.2.exit, 15, implicit killed $eflags
bb.1.less: bb.1.less:
$eax = MOV32r0 implicit-def dead $eflags $eax = MOV32r0 implicit-def dead $eflags
RETQ killed $eax RET64 killed $eax
bb.2.exit: bb.2.exit:
liveins: $edi liveins: $edi
$eax = COPY killed $edi $eax = COPY killed $edi
RETQ killed $eax RET64 killed $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir

Show All 13 Lines
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: [[@LINE+1]]:48: expected 'load' or 'store' memory operation ; CHECK: [[@LINE+1]]:48: expected 'load' or 'store' memory operation
$eax = MOV32rm killed $rdi, 1, _, 0, _ :: (4 from %ir.a) $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (4 from %ir.a)
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir

# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- | --- |
define i32 @foo() { define i32 @foo() {
entry: entry:
ret i32 0 ret i32 0
} }
... ...
--- ---
name: foo name: foo
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: [[@LINE+1]]:20: expected a machine operand ; CHECK: [[@LINE+1]]:20: expected a machine operand
$eax = XOR32rr = $eax = XOR32rr =
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Linesstack:
- { id: 0, name: x.addr, size: 4, alignment: 4 } - { id: 0, name: x.addr, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
%0 = COPY $edi %0 = COPY $edi
; CHECK: [[@LINE+1]]:46: expected a metadata node after 'debug-location' ; CHECK: [[@LINE+1]]:46: expected a metadata node after 'debug-location'
DBG_VALUE _, 0, !12, !13, debug-location 14 DBG_VALUE _, 0, !12, !13, debug-location 14
MOV32mr $stack.x.addr, 1, _, 0, _, %0 MOV32mr $stack.x.addr, 1, _, 0, _, %0
$eax = COPY %0 $eax = COPY %0
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Linesstack:
- { id: 0, name: x.addr, size: 4, alignment: 4 } - { id: 0, name: x.addr, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
%0 = COPY $edi %0 = COPY $edi
; CHECK: [[@LINE+1]]:28: expected metadata id after '!' ; CHECK: [[@LINE+1]]:28: expected metadata id after '!'
DBG_VALUE _, 0, !12, ! _ DBG_VALUE _, 0, !12, ! _
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
$eax = COPY %0 $eax = COPY %0
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir

Show All 16 Lines
# CHECK: [[@LINE+1]]:29: expected a metadata node # CHECK: [[@LINE+1]]:29: expected a metadata node
debug-info-variable: '0' } debug-info-variable: '0' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $edi liveins: $edi
MOV32mr $rsp, 1, _, -4, _, $edi :: (store (s32) into %ir.xa) MOV32mr $rsp, 1, _, -4, _, $edi :: (store (s32) into %ir.xa)
$eax = COPY killed $edi $eax = COPY killed $edi
RETQ killed $eax RET64 killed $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir

Show All 20 Lines
body: | body: |
bb.0.body: bb.0.body:
liveins: $edi, $esi liveins: $edi, $esi
%1 = COPY $esi %1 = COPY $esi
%2 = COPY $edi %2 = COPY $edi
%2 = IMUL32rr %2, %1, implicit-def dead $eflags %2 = IMUL32rr %2, %1, implicit-def dead $eflags
$eax = COPY %2 $eax = COPY %2
RETQ killed $eax RET64 killed $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir

Show All 31 Lines
--- ---
name: compute name: compute
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.body: bb.0.body:
liveins: $edi liveins: $edi
$eax = COPY killed $edi $eax = COPY killed $edi
RETQ killed $eax RET64 killed $eax
... ...
--- ---
name: func name: func
tracksRegLiveness: true tracksRegLiveness: true
frameInfo: frameInfo:
stackSize: 24 stackSize: 24
maxAlignment: 4 maxAlignment: 4
adjustsStack: true adjustsStack: true
Show All 30 Lines bb.2.loop:
$eax = DEC32r killed $eax, implicit-def dead $eflags $eax = DEC32r killed $eax, implicit-def dead $eflags
MOV32mr $rsp, 1, _, 12, _, killed $eax MOV32mr $rsp, 1, _, 12, _, killed $eax
JMP_1 %bb.1.check JMP_1 %bb.1.check
bb.3.exit: bb.3.exit:
$eax = MOV32r0 implicit-def dead $eflags $eax = MOV32r0 implicit-def dead $eflags
$rsp = ADD64ri8 $rsp, 16, implicit-def dead $eflags $rsp = ADD64ri8 $rsp, 16, implicit-def dead $eflags
$rbx = POP64r implicit-def $rsp, implicit $rsp $rbx = POP64r implicit-def $rsp, implicit $rsp
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir

Show All 16 Linesliveins:
# CHECK: [[@LINE+1]]:13: expected a named register # CHECK: [[@LINE+1]]:13: expected a named register
- { reg: '%0' } - { reg: '%0' }
body: | body: |
bb.0.body: bb.0.body:
liveins: %edi liveins: %edi
%0 = COPY %edi %0 = COPY %edi
%eax = COPY %0 %eax = COPY %0
RETQ %eax RET64 %eax
... ...

llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir

Show All 10 Lines
--- ---
name: test name: test
body: | body: |
bb.0.body: bb.0.body:
; CHECK: [[@LINE+1]]:14: expected a named register ; CHECK: [[@LINE+1]]:14: expected a named register
liveins: %0 liveins: %0
$eax = COPY $edi $eax = COPY $edi
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir

Show All 25 Linesbody: |
; CHECK: [[@LINE+1]]:19: expected line break at the end of a list ; CHECK: [[@LINE+1]]:19: expected line break at the end of a list
liveins: $edi 44 liveins: $edi 44
CMP32ri8 $edi, 10, implicit-def $eflags CMP32ri8 $edi, 10, implicit-def $eflags
JCC_1 %bb.2.exit, 15, implicit killed $eflags JCC_1 %bb.2.exit, 15, implicit killed $eflags
bb.1.less: bb.1.less:
$eax = MOV32r0 implicit-def dead $eflags $eax = MOV32r0 implicit-def dead $eflags
RETQ killed $eax RET64 killed $eax
bb.2.exit: bb.2.exit:
liveins: $edi liveins: $edi
$eax = COPY killed $edi $eax = COPY killed $edi
RETQ killed $eax RET64 killed $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir

Show All 23 Lines bb.0.entry:
CMP32ri8 $eax, 10, implicit-def $eflags CMP32ri8 $eax, 10, implicit-def $eflags
; CHECK: [[@LINE+1]]:15: expected a number after '%bb.' ; CHECK: [[@LINE+1]]:15: expected a number after '%bb.'
JCC_1 %bb.nah, 15, implicit $eflags JCC_1 %bb.nah, 15, implicit $eflags
bb.1.true: bb.1.true:
$eax = MOV32r0 implicit-def $eflags $eax = MOV32r0 implicit-def $eflags
bb.2.nah: bb.2.nah:
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir

Show All 16 Lines
stack: stack:
- { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 } - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
$rsp = SUB64ri32 $rsp, 4040, implicit-def dead $eflags $rsp = SUB64ri32 $rsp, 4040, implicit-def dead $eflags
; CHECK: [[@LINE+1]]:36: expected a cfi offset ; CHECK: [[@LINE+1]]:36: expected a cfi offset
CFI_INSTRUCTION def_cfa_offset _ CFI_INSTRUCTION def_cfa_offset _
$rsp = ADD64ri32 $rsp, 4040, implicit-def dead $eflags $rsp = ADD64ri32 $rsp, 4040, implicit-def dead $eflags
RETQ RET64
... ...

llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir

Show All 13 Lines
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: [[@LINE+1]]:64: expected a pointer IR value ; CHECK: [[@LINE+1]]:64: expected a pointer IR value
$eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load (s32) from %ir.b) $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load (s32) from %ir.b)
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir

Show All 20 Lines bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: [[@LINE+1]]:75: expected an integer literal after 'align' ; CHECK: [[@LINE+1]]:75: expected an integer literal after 'align'
$xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load (s128) from %ir.vec, align -32) $xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load (s128) from %ir.vec, align -32)
$xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load (s128) from %ir.vec + 16, basealign 32) $xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load (s128) from %ir.vec + 16, basealign 32)
$xmm2 = FsFLD0SS $xmm2 = FsFLD0SS
$xmm1 = MOVSSrr killed $xmm1, killed $xmm2 $xmm1 = MOVSSrr killed $xmm1, killed $xmm2
MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store (s128) into %ir.vec, align 32) MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store (s128) into %ir.vec, align 32)
MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store (s128) into %ir.vec + 16, basealign 32) MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store (s128) into %ir.vec + 16, basealign 32)
RETQ RET64
... ...

llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir

Show All 32 Lines bb.0.entry:
$ebx = COPY $edi, implicit-def $rbx $ebx = COPY $edi, implicit-def $rbx
$ebx = ADD32rr $ebx, killed $esi, implicit-def dead $eflags $ebx = ADD32rr $ebx, killed $esi, implicit-def dead $eflags
$ebx = ADD32rr $ebx, killed $edx, implicit-def dead $eflags $ebx = ADD32rr $ebx, killed $edx, implicit-def dead $eflags
$ebx = ADD32rr $ebx, killed $ecx, implicit-def dead $eflags $ebx = ADD32rr $ebx, killed $ecx, implicit-def dead $eflags
$edi = COPY $ebx $edi = COPY $ebx
CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp
$eax = LEA64_32r killed $rbx, 1, $rbx, 0, _ $eax = LEA64_32r killed $rbx, 1, $rbx, 0, _
$rbx = POP64r implicit-def $rsp, implicit $rsp $rbx = POP64r implicit-def $rsp, implicit $rsp
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir

Show All 10 Lines
... ...
--- ---
name: foo name: foo
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: [[@LINE+1]]:33: expected a register after register flags ; CHECK: [[@LINE+1]]:33: expected a register after register flags
$eax = MOV32r0 implicit-def 2 $eax = MOV32r0 implicit-def 2
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir

Show All 13 Lines
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: [[@LINE+1]]:53: expected an atomic scope, ordering or a size specification ; CHECK: [[@LINE+1]]:53: expected an atomic scope, ordering or a size specification
$eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load from %ir.a) $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load from %ir.a)
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir

Show All 13 Lines
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: [[@LINE+1]]:53: expected memory LLT, the size integer literal or 'unknown-size' after memory operation ; CHECK: [[@LINE+1]]:53: expected memory LLT, the size integer literal or 'unknown-size' after memory operation
$eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load . from %ir.a) $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load . from %ir.a)
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-stack-object.mir

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines bb.0.entry:
$rsi = LEA64r $rsp, 1, _, 19, _ $rsi = LEA64r $rsp, 1, _, 19, _
MOV64mr $rsp, 1, _, 8, _, $rsi MOV64mr $rsp, 1, _, 8, _, $rsi
$rdi = LEA64r $rip, 1, _, @.str, _ $rdi = LEA64r $rip, 1, _, @.str, _
dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $al dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $al
CALL64pcrel32 @printf, csr_64, implicit $rsp, implicit $rdi, implicit $rsi, implicit $al, implicit-def $rsp, implicit-def $eax CALL64pcrel32 @printf, csr_64, implicit $rsp, implicit $rdi, implicit $rsi, implicit $al, implicit-def $rsp, implicit-def $eax
CMP64rm killed $rbx, $rsp, 1, _, 24, _, implicit-def $eflags CMP64rm killed $rbx, $rsp, 1, _, 24, _, implicit-def $eflags
$rsp = ADD64ri8 $rsp, 32, implicit-def dead $eflags $rsp = ADD64ri8 $rsp, 32, implicit-def dead $eflags
$rbx = POP64r implicit-def $rsp, implicit $rsp $rbx = POP64r implicit-def $rsp, implicit $rsp
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir

Show All 16 Linesregisters:
- { id: 2, class: gr8 } - { id: 2, class: gr8 }
body: | body: |
bb.0.entry: bb.0.entry:
%0 = COPY $edi %0 = COPY $edi
; CHECK: [[@LINE+1]]:20: expected a subregister index after '.' ; CHECK: [[@LINE+1]]:20: expected a subregister index after '.'
%1 = COPY %0 . 42 %1 = COPY %0 . 42
%2 = AND8ri %1, 1, implicit-def $eflags %2 = AND8ri %1, 1, implicit-def $eflags
$al = COPY %2 $al = COPY %2
RETQ $al RET64 $al
... ...

llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir

Show All 14 Lines
--- ---
name: inc name: inc
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: [[@LINE+1]]:46: expected the name of the target flag ; CHECK: [[@LINE+1]]:46: expected the name of the target flag
$rax = MOV64rm $rip, 1, _, target-flags( ) @G, _ $rax = MOV64rm $rip, 1, _, target-flags( ) @G, _
$eax = MOV32rm killed $rax, 1, _, 0, _ $eax = MOV32rm killed $rax, 1, _, 0, _
$eax = INC32r killed $eax, implicit-def dead $eflags $eax = INC32r killed $eax, implicit-def dead $eflags
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir

Show All 14 Linesliveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: [[@LINE+1]]:70: expected tied-def or low-level type after '(' ; CHECK: [[@LINE+1]]:70: expected tied-def or low-level type after '('
INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(3) INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(3)
$rax = COPY killed $rdi $rax = COPY killed $rdi
RETQ killed $rax RET64 killed $rax
... ...

llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir

Show All 13 Lines
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: [[@LINE+1]]:64: expected an IR value reference ; CHECK: [[@LINE+1]]:64: expected an IR value reference
$eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load (s32) from a) $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load (s32) from a)
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir

Show All 16 Linesliveins:
# CHECK: [[@LINE+1]]:34: expected a virtual register # CHECK: [[@LINE+1]]:34: expected a virtual register
- { reg: '$edi', virtual-reg: '$edi' } - { reg: '$edi', virtual-reg: '$edi' }
body: | body: |
bb.0.body: bb.0.body:
liveins: $edi liveins: $edi
%0 = COPY $edi %0 = COPY $edi
$eax = COPY %0 $eax = COPY %0
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir

Show All 40 Lines bb.0.entry:
$eax = MOV32rm $rsp, 4, $rax, 0, _ $eax = MOV32rm $rsp, 4, $rax, 0, _
CMP64rm $rcx, $rsp, 1, _, 512, _, implicit-def $eflags CMP64rm $rcx, $rsp, 1, _, 512, _, implicit-def $eflags
JCC_1 %bb.2.entry, 5, implicit $eflags JCC_1 %bb.2.entry, 5, implicit $eflags
bb.1.entry: bb.1.entry:
liveins: $eax liveins: $eax
$rsp = ADD64ri32 $rsp, 520, implicit-def $eflags $rsp = ADD64ri32 $rsp, 520, implicit-def $eflags
RETQ $eax RET64 $eax
bb.2.entry: bb.2.entry:
; CHECK: CALL64pcrel32 &__stack_chk_fail, ; CHECK: CALL64pcrel32 &__stack_chk_fail,
; CHECK-NEXT: CALL64pcrel32 &__stack_chk_fail.09-_, ; CHECK-NEXT: CALL64pcrel32 &__stack_chk_fail.09-_,
; CHECK-NEXT: CALL64pcrel32 &"__stack_chk_fail$", ; CHECK-NEXT: CALL64pcrel32 &"__stack_chk_fail$",
; CHECK-NEXT: CALL64pcrel32 &"$Quoted \09 External symbol \11 ", ; CHECK-NEXT: CALL64pcrel32 &"$Quoted \09 External symbol \11 ",
; CHECK-NEXT: CALL64pcrel32 &__stack_chk_fail + 2, ; CHECK-NEXT: CALL64pcrel32 &__stack_chk_fail + 2,
; CHECK-NEXT: CALL64pcrel32 &" check stack - 20" - 20, ; CHECK-NEXT: CALL64pcrel32 &" check stack - 20" - 20,
CALL64pcrel32 &__stack_chk_fail, csr_64, implicit $rsp, implicit-def $rsp CALL64pcrel32 &__stack_chk_fail, csr_64, implicit $rsp, implicit-def $rsp
CALL64pcrel32 &__stack_chk_fail.09-_, csr_64, implicit $rsp, implicit-def $rsp CALL64pcrel32 &__stack_chk_fail.09-_, csr_64, implicit $rsp, implicit-def $rsp
CALL64pcrel32 &__stack_chk_fail$, csr_64, implicit $rsp, implicit-def $rsp CALL64pcrel32 &__stack_chk_fail$, csr_64, implicit $rsp, implicit-def $rsp
CALL64pcrel32 &"$Quoted \09 External symbol \11 ", csr_64, implicit $rsp, implicit-def $rsp CALL64pcrel32 &"$Quoted \09 External symbol \11 ", csr_64, implicit $rsp, implicit-def $rsp
CALL64pcrel32 &__stack_chk_fail + 2, csr_64, implicit $rsp, implicit-def $rsp CALL64pcrel32 &__stack_chk_fail + 2, csr_64, implicit $rsp, implicit-def $rsp
CALL64pcrel32 &" check stack - 20" - 20, csr_64, implicit $rsp, implicit-def $rsp CALL64pcrel32 &" check stack - 20" - 20, csr_64, implicit $rsp, implicit-def $rsp
... ...

llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir

Show All 29 Linesbody: |
bb.0.entry: bb.0.entry:
frame-setup PUSH32r undef $eax, implicit-def $esp, implicit $esp frame-setup PUSH32r undef $eax, implicit-def $esp, implicit $esp
CFI_INSTRUCTION def_cfa_offset 8 CFI_INSTRUCTION def_cfa_offset 8
; CHECK: name: test ; CHECK: name: test
; CHECK: $eax = MOV32rm $esp, 1, $noreg, 8, $noreg :: (load (s32) from %fixed-stack.0, align 16) ; CHECK: $eax = MOV32rm $esp, 1, $noreg, 8, $noreg :: (load (s32) from %fixed-stack.0, align 16)
$eax = MOV32rm $esp, 1, _, 8, _ :: (load (s32) from %fixed-stack.0, align 16) $eax = MOV32rm $esp, 1, _, 8, _ :: (load (s32) from %fixed-stack.0, align 16)
MOV32mr $esp, 1, _, 0, _, $eax :: (store (s32) into %ir.b) MOV32mr $esp, 1, _, 0, _, $eax :: (store (s32) into %ir.b)
$edx = POP32r implicit-def $esp, implicit $esp $edx = POP32r implicit-def $esp, implicit $esp
RETL $eax RET32 $eax
... ...

llvm/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir

Show All 18 Lines
fixedStack: fixedStack:
- { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
# CHECK: [[@LINE+1]]:11: redefinition of fixed stack object '%fixed-stack.0' # CHECK: [[@LINE+1]]:11: redefinition of fixed stack object '%fixed-stack.0'
- { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
body: | body: |
bb.0.entry: bb.0.entry:
$eax = MOV32rm $esp, 1, _, 4, _ $eax = MOV32rm $esp, 1, _, 4, _
$eax = ADD32rm killed $eax, $esp, 1, _, 8, _, implicit-def dead $eflags $eax = ADD32rm killed $eax, $esp, 1, _, 8, _, implicit-def dead $eflags
RETL $eax RET32 $eax
... ...

llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir

Show All 24 Lines
fixedStack: fixedStack:
- { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false } - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
stack: stack:
- { id: 0, offset: -8, size: 4, alignment: 4 } - { id: 0, offset: -8, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
$eax = MOV32rm $esp, 1, _, 8, _ $eax = MOV32rm $esp, 1, _, 8, _
MOV32mr $esp, 1, _, 0, _, $eax MOV32mr $esp, 1, _, 0, _, $eax
RETL $eax RET32 $eax
... ...

llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines bb.2.true:
$rsi = LEA64r %stack.0.tmp, 1, _, 0, _ $rsi = LEA64r %stack.0.tmp, 1, _, 0, _
$edi = MOV32r0 implicit-def dead $eflags $edi = MOV32r0 implicit-def dead $eflags
CALL64pcrel32 @doSomething, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $rsi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax CALL64pcrel32 @doSomething, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $rsi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $ssp, implicit-def dead $eflags, implicit $rsp, implicit $ssp ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $ssp, implicit-def dead $eflags, implicit $rsp, implicit $ssp
bb.3.false: bb.3.false:
liveins: $eax liveins: $eax
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines bb.0.entry:
CMP64rm killed $rbx, $rsp, 1, _, 24, _, implicit-def $eflags CMP64rm killed $rbx, $rsp, 1, _, 24, _, implicit-def $eflags
JCC_1 %bb.2.entry, 5, implicit $eflags JCC_1 %bb.2.entry, 5, implicit $eflags
bb.1.entry: bb.1.entry:
liveins: $eax liveins: $eax
$rsp = ADD64ri8 $rsp, 32, implicit-def dead $eflags $rsp = ADD64ri8 $rsp, 32, implicit-def dead $eflags
$rbx = POP64r implicit-def $rsp, implicit $rsp $rbx = POP64r implicit-def $rsp, implicit $rsp
RETQ $eax RET64 $eax
bb.2.entry: bb.2.entry:
CALL64pcrel32 &__stack_chk_fail, csr_64, implicit $rsp, implicit-def $rsp CALL64pcrel32 &__stack_chk_fail, csr_64, implicit $rsp, implicit-def $rsp
... ...

llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir

Show All 15 Lines--- |
} }
... ...
--- ---
name: compute name: compute
body: | body: |
bb.0.body: bb.0.body:
$eax = IMUL32rri8 $edi, 11, implicit-def $eflags $eax = IMUL32rri8 $edi, 11, implicit-def $eflags
RETQ $eax RET64 $eax
... ...
--- ---
name: foo name: foo
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: frame-setup PUSH64r $rax ; CHECK: frame-setup PUSH64r $rax
frame-setup PUSH64r $rax, implicit-def $rsp, implicit $rsp frame-setup PUSH64r $rax, implicit-def $rsp, implicit $rsp
CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax
; CHECK: $rdx = frame-destroy POP64r ; CHECK: $rdx = frame-destroy POP64r
$rdx = frame-destroy POP64r implicit-def $rsp, implicit $rsp $rdx = frame-destroy POP64r implicit-def $rsp, implicit $rsp
; CHECK: $rdx = frame-setup frame-destroy POP64r ; CHECK: $rdx = frame-setup frame-destroy POP64r
$rdx = frame-setup frame-destroy POP64r implicit-def $rsp, implicit $rsp $rdx = frame-setup frame-destroy POP64r implicit-def $rsp, implicit $rsp
; CHECK: $rdx = frame-setup frame-destroy POP64r ; CHECK: $rdx = frame-setup frame-destroy POP64r
$rdx = frame-destroy frame-setup POP64r implicit-def $rsp, implicit $rsp $rdx = frame-destroy frame-setup POP64r implicit-def $rsp, implicit $rsp
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/function-liveins.mir

Show All 26 Lines
body: | body: |
bb.0.body: bb.0.body:
liveins: $edi, $esi liveins: $edi, $esi
%1 = COPY $esi %1 = COPY $esi
%0 = COPY $edi %0 = COPY $edi
%2 = ADD32rr %0, %1, implicit-def dead $eflags %2 = ADD32rr %0, %1, implicit-def dead $eflags
$eax = COPY %2 $eax = COPY %2
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/global-value-operands.mir

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
# CHECK: name: inc # CHECK: name: inc
name: inc name: inc
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: $rax = MOV64rm $rip, 1, $noreg, @G, $noreg ; CHECK: $rax = MOV64rm $rip, 1, $noreg, @G, $noreg
$rax = MOV64rm $rip, 1, _, @G, _ $rax = MOV64rm $rip, 1, _, @G, _
$eax = MOV32rm $rax, 1, _, 0, _ $eax = MOV32rm $rax, 1, _, 0, _
$eax = INC32r $eax, implicit-def $eflags $eax = INC32r $eax, implicit-def $eflags
RETQ $eax RET64 $eax
... ...
--- ---
# CHECK: name: inc2 # CHECK: name: inc2
name: inc2 name: inc2
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: $rax = MOV64rm $rip, 1, $noreg, @0, $noreg ; CHECK: $rax = MOV64rm $rip, 1, $noreg, @0, $noreg
$rax = MOV64rm $rip, 1, _, @0, _ $rax = MOV64rm $rip, 1, _, @0, _
$eax = MOV32rm $rax, 1, _, 0, _ $eax = MOV32rm $rax, 1, _, 0, _
$eax = INC32r $eax, implicit-def $eflags $eax = INC32r $eax, implicit-def $eflags
RETQ $eax RET64 $eax
... ...
--- ---
name: test name: test
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: , @".$0", ; CHECK: , @".$0",
; CHECK: , @-_-, ; CHECK: , @-_-,
; CHECK: , @_-_a, ; CHECK: , @_-_a,
; CHECK: , @"$.-B", ; CHECK: , @"$.-B",
$rax = MOV64rm $rip, 1, _, @.$0, _ $rax = MOV64rm $rip, 1, _, @.$0, _
$eax = MOV32rm killed $rax, 1, _, 0, _ $eax = MOV32rm killed $rax, 1, _, 0, _
$rcx = MOV64rm $rip, 1, _, @-_-, _ $rcx = MOV64rm $rip, 1, _, @-_-, _
MOV32mr killed $rcx, 1, _, 0, _, killed $eax MOV32mr killed $rcx, 1, _, 0, _, killed $eax
$rax = MOV64rm $rip, 1, _, @_-_a, _ $rax = MOV64rm $rip, 1, _, @_-_a, _
$eax = MOV32rm killed $rax, 1, _, 0, _ $eax = MOV32rm killed $rax, 1, _, 0, _
$rcx = MOV64rm $rip, 1, _, @$.-B, _ $rcx = MOV64rm $rip, 1, _, @$.-B, _
MOV32mr killed $rcx, 1, _, 0, _, $eax MOV32mr killed $rcx, 1, _, 0, _, $eax
RETQ $eax RET64 $eax
... ...
--- ---
name: test2 name: test2
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: , @"\01Hello@$%09 \\ World,", ; CHECK: , @"\01Hello@$%09 \\ World,",
$rax = MOV64rm $rip, 1, _, @"\01Hello@$%09 \\ World,", _ $rax = MOV64rm $rip, 1, _, @"\01Hello@$%09 \\ World,", _
$eax = MOV32rm killed $rax, 1, _, 0, _ $eax = MOV32rm killed $rax, 1, _, 0, _
RETQ $eax RET64 $eax
... ...
--- ---
# CHECK: name: test3 # CHECK: name: test3
name: test3 name: test3
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: , @".$0", ; CHECK: , @".$0",
; CHECK: , @-_-, ; CHECK: , @-_-,
; CHECK: , @_-_a + 4, ; CHECK: , @_-_a + 4,
; CHECK: , @"$.-B" - 8, ; CHECK: , @"$.-B" - 8,
$rax = MOV64rm $rip, 1, _, @.$0 + 0, _ $rax = MOV64rm $rip, 1, _, @.$0 + 0, _
$eax = MOV32rm killed $rax, 1, _, 0, _ $eax = MOV32rm killed $rax, 1, _, 0, _
$rcx = MOV64rm $rip, 1, _, @-_- - 0, _ $rcx = MOV64rm $rip, 1, _, @-_- - 0, _
MOV32mr killed $rcx, 1, _, 0, _, killed $eax MOV32mr killed $rcx, 1, _, 0, _, killed $eax
$rax = MOV64rm $rip, 1, _, @_-_a + 4, _ $rax = MOV64rm $rip, 1, _, @_-_a + 4, _
$eax = MOV32rm killed $rax, 1, _, 0, _ $eax = MOV32rm killed $rax, 1, _, 0, _
$rcx = MOV64rm $rip, 1, _, @$.-B - 8, _ $rcx = MOV64rm $rip, 1, _, @$.-B - 8, _
MOV32mr killed $rcx, 1, _, 0, _, $eax MOV32mr killed $rcx, 1, _, 0, _, $eax
RETQ $eax RET64 $eax
... ...
--- ---
# CHECK: name: tf # CHECK: name: tf
name: tf name: tf
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: $rax = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @G, $noreg ; CHECK: $rax = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @G, $noreg
$rax = MOV64rm $rip, 1, _, target-flags(x86-gotpcrel) @G, _ $rax = MOV64rm $rip, 1, _, target-flags(x86-gotpcrel) @G, _
$eax = MOV32rm $rax, 1, _, 0, _ $eax = MOV32rm $rax, 1, _, 0, _
$eax = INC32r $eax, implicit-def $eflags $eax = INC32r $eax, implicit-def $eflags
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/immediate-operands.mir

Show All 14 Lines
... ...
--- ---
# CHECK: name: foo # CHECK: name: foo
name: foo name: foo
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: $eax = MOV32ri 42 ; CHECK: $eax = MOV32ri 42
; CHECK-NEXT: RETQ $eax ; CHECK-NEXT: RET64 $eax
$eax = MOV32ri 42 $eax = MOV32ri 42
RETQ $eax RET64 $eax
... ...
--- ---
# CHECK: name: bar # CHECK: name: bar
name: bar name: bar
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: $eax = MOV32ri -11 ; CHECK: $eax = MOV32ri -11
; CHECK-NEXT: RETQ $eax ; CHECK-NEXT: RET64 $eax
$eax = MOV32ri -11 $eax = MOV32ri -11
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir

Show All 34 Lines bb.0.entry:
; CHECK: CMP32ri8 $edi, 10, implicit-def $eflags ; CHECK: CMP32ri8 $edi, 10, implicit-def $eflags
; CHECK-NEXT: JCC_1 %bb.2, 15, implicit $eflags ; CHECK-NEXT: JCC_1 %bb.2, 15, implicit $eflags
CMP32ri8 $edi, 10, implicit-def $eflags CMP32ri8 $edi, 10, implicit-def $eflags
JCC_1 %bb.2, 15, implicit $eflags JCC_1 %bb.2, 15, implicit $eflags
bb.1.less: bb.1.less:
; CHECK: $eax = MOV32r0 implicit-def $eflags ; CHECK: $eax = MOV32r0 implicit-def $eflags
$eax = MOV32r0 implicit-def $eflags $eax = MOV32r0 implicit-def $eflags
RETQ $eax RET64 $eax
bb.2.exit: bb.2.exit:
$eax = COPY $edi $eax = COPY $edi
RETQ $eax RET64 $eax
... ...
--- ---
name: implicit_subregister1 name: implicit_subregister1
body: | body: |
bb.0.entry: bb.0.entry:
; Verify that the implicit register verifier won't report an error on implicit ; Verify that the implicit register verifier won't report an error on implicit
; subregisters. ; subregisters.
; CHECK-LABEL: name: implicit_subregister1 ; CHECK-LABEL: name: implicit_subregister1
; CHECK: dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al ; CHECK: dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al
dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al
RETQ killed $al RET64 killed $al
... ...
--- ---
name: implicit_subregister2 name: implicit_subregister2
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: implicit_subregister2 ; CHECK-LABEL: name: implicit_subregister2
; CHECK: dead $r15 = XOR64rr undef $r15, undef $r15, implicit-def dead $eflags, implicit-def $r15w ; CHECK: dead $r15 = XOR64rr undef $r15, undef $r15, implicit-def dead $eflags, implicit-def $r15w
dead $r15 = XOR64rr undef $r15, undef $r15, implicit-def dead $eflags, implicit-def $r15w dead $r15 = XOR64rr undef $r15, undef $r15, implicit-def dead $eflags, implicit-def $r15w
RETQ killed $r15w RET64 killed $r15w
... ...

llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir

Show All 25 Lines
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi, $rsi liveins: $rdi, $rsi
; CHECK-LABEL: name: test ; CHECK-LABEL: name: test
; CHECK: INLINEASM &foo, 0 /* attdialect */, 4390922 /* regdef:GR64 */, def $rsi, 4390922 /* regdef:GR64 */, def dead $rdi, ; CHECK: INLINEASM &foo, 0 /* attdialect */, 4390922 /* regdef:GR64 */, def $rsi, 4390922 /* regdef:GR64 */, def dead $rdi,
INLINEASM &foo, 0, 4390922, def $rsi, 4390922, def dead $rdi, 2147549193, killed $rdi, 2147483657, killed $rsi, 12, implicit-def dead early-clobber $eflags INLINEASM &foo, 0, 4390922, def $rsi, 4390922, def dead $rdi, 2147549193, killed $rdi, 2147483657, killed $rsi, 12, implicit-def dead early-clobber $eflags
$rax = MOV64rr killed $rsi $rax = MOV64rr killed $rsi
RETQ killed $rax RET64 killed $rax
... ...
--- ---
name: test2 name: test2
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
- { reg: '$rsi' } - { reg: '$rsi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi, $rsi liveins: $rdi, $rsi
; Verify that the register ties are preserved. ; Verify that the register ties are preserved.
; CHECK-LABEL: name: test2 ; CHECK-LABEL: name: test2
; CHECK: INLINEASM &foo, 0 /* attdialect */, 4390922 /* regdef:GR64 */, def $rsi, 4390922 /* regdef:GR64 */, def dead $rdi, 2147549193 /* reguse tiedto:$1 */, killed $rdi(tied-def 5), 2147483657 /* reguse tiedto:$0 */, killed $rsi(tied-def 3), 12 /* clobber */, implicit-def dead early-clobber $eflags ; CHECK: INLINEASM &foo, 0 /* attdialect */, 4390922 /* regdef:GR64 */, def $rsi, 4390922 /* regdef:GR64 */, def dead $rdi, 2147549193 /* reguse tiedto:$1 */, killed $rdi(tied-def 5), 2147483657 /* reguse tiedto:$0 */, killed $rsi(tied-def 3), 12 /* clobber */, implicit-def dead early-clobber $eflags
INLINEASM &foo, 0, 4390922, def $rsi, 4390922, def dead $rdi, 2147549193, killed $rdi(tied-def 5), 2147483657, killed $rsi(tied-def 3), 12, implicit-def dead early-clobber $eflags INLINEASM &foo, 0, 4390922, def $rsi, 4390922, def dead $rdi, 2147549193, killed $rdi(tied-def 5), 2147483657, killed $rsi(tied-def 3), 12, implicit-def dead early-clobber $eflags
$rax = MOV64rr killed $rsi $rax = MOV64rr killed $rsi
RETQ killed $rax RET64 killed $rax
... ...

llvm/test/CodeGen/MIR/X86/instr-symbols-and-mcsymbol-operands.mir

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Linesbody: |
; CHECK: %3:gr64 = MOV64ri32 <mcsymbol .Lpost_f> ; CHECK: %3:gr64 = MOV64ri32 <mcsymbol .Lpost_f>
; CHECK: %4:gr64 = MOV64ri32 <mcsymbol .Lpre_g> ; CHECK: %4:gr64 = MOV64ri32 <mcsymbol .Lpre_g>
; CHECK: %5:gr64 = MOV64ri32 <mcsymbol .Lpost_h> ; CHECK: %5:gr64 = MOV64ri32 <mcsymbol .Lpost_h>
%6:gr64 = ADD64rr killed %2, killed %3, implicit-def $eflags %6:gr64 = ADD64rr killed %2, killed %3, implicit-def $eflags
%7:gr64 = ADD64rr killed %4, killed %5, implicit-def $eflags %7:gr64 = ADD64rr killed %4, killed %5, implicit-def $eflags
%8:gr64 = ADD64rr killed %6, killed %7, implicit-def $eflags %8:gr64 = ADD64rr killed %6, killed %7, implicit-def $eflags
$rax = COPY %8 $rax = COPY %8
RETQ implicit $rax RET64 implicit $rax
... ...

llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
stack: stack:
- { id: 0, name: x.addr, size: 4, alignment: 4 } - { id: 0, name: x.addr, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $edi liveins: $edi
; CHECK: DBG_VALUE $noreg, 0, !11, !DIExpression(), debug-location !12 ; CHECK: DBG_VALUE $noreg, 0, !11, !DIExpression(), debug-location !12
; CHECK: DBG_VALUE $noreg, 0, !11, !DIExpression(), debug-location !12 ; CHECK: DBG_VALUE $noreg, 0, !11, !DIExpression(), debug-location !12
; CHECK: $eax = COPY %0, debug-location !13 ; CHECK: $eax = COPY %0, debug-location !13
; CHECK: RETQ $eax, debug-location !13 ; CHECK: RET64 $eax, debug-location !13
%0 = COPY $edi %0 = COPY $edi
DBG_VALUE _, 0, !12, !DIExpression(), debug-location !13 DBG_VALUE _, 0, !12, !DIExpression(), debug-location !13
; Test whether debug-use is still recognized for compatibility with old ; Test whether debug-use is still recognized for compatibility with old
; files. ; files.
DBG_VALUE debug-use _, 0, !12, !DIExpression(), debug-location !13 DBG_VALUE debug-use _, 0, !12, !DIExpression(), debug-location !13
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
$eax = COPY %0, debug-location !14 $eax = COPY %0, debug-location !14
RETQ $eax, debug-location !14 RET64 $eax, debug-location !14
... ...
--- ---
name: test_typed_immediates name: test_typed_immediates
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gr32 } - { id: 0, class: gr32 }
frameInfo: frameInfo:
maxAlignment: 4 maxAlignment: 4
stack: stack:
- { id: 0, name: x.addr, size: 4, alignment: 4 } - { id: 0, name: x.addr, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $edi liveins: $edi
%0 = COPY $edi %0 = COPY $edi
; CHECK: DBG_VALUE $noreg, i32 0, !11, !DIExpression() ; CHECK: DBG_VALUE $noreg, i32 0, !11, !DIExpression()
; CHECK-NEXT: DBG_VALUE $noreg, i64 -22, !11, !DIExpression() ; CHECK-NEXT: DBG_VALUE $noreg, i64 -22, !11, !DIExpression()
; CHECK-NEXT: DBG_VALUE $noreg, i128 123492148938512984928424384934328985928, !11, !DIExpression() ; CHECK-NEXT: DBG_VALUE $noreg, i128 123492148938512984928424384934328985928, !11, !DIExpression()
DBG_VALUE _, i32 0, !12, !DIExpression(), debug-location !13 DBG_VALUE _, i32 0, !12, !DIExpression(), debug-location !13
DBG_VALUE _, i64 -22, !12, !DIExpression(), debug-location !13 DBG_VALUE _, i64 -22, !12, !DIExpression(), debug-location !13
DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !DIExpression(), debug-location !13 DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !DIExpression(), debug-location !13
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
$eax = COPY %0 $eax = COPY %0
RETQ $eax RET64 $eax
... ...
--- ---
name: test_mir_created name: test_mir_created
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gr32 } - { id: 0, class: gr32 }
frameInfo: frameInfo:
maxAlignment: 4 maxAlignment: 4
Show All 11 Linesbody: |
; CHECK: MOV32mr %stack.0.x.addr, 1, $noreg, 0, $noreg, %0, debug-location !DILocation(line: 4, scope: !14, inlinedAt: !15) ; CHECK: MOV32mr %stack.0.x.addr, 1, $noreg, 0, $noreg, %0, debug-location !DILocation(line: 4, scope: !14, inlinedAt: !15)
; CHECK: MOV32mr %stack.0.x.addr, 1, $noreg, 0, $noreg, %0, debug-location !DILocation(line: 5, scope: !14, inlinedAt: !DILocation(line: 4, scope: !14)) ; CHECK: MOV32mr %stack.0.x.addr, 1, $noreg, 0, $noreg, %0, debug-location !DILocation(line: 5, scope: !14, inlinedAt: !DILocation(line: 4, scope: !14))
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0, debug-location !DILocation(line: 1, scope: !15) MOV32mr %stack.0.x.addr, 1, _, 0, _, %0, debug-location !DILocation(line: 1, scope: !15)
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0, debug-location !DILocation(line: 2, column: 2, scope: !15) MOV32mr %stack.0.x.addr, 1, _, 0, _, %0, debug-location !DILocation(line: 2, column: 2, scope: !15)
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0, debug-location !DILocation(line: 3, column: 2, scope: !15, isImplicitCode: true) MOV32mr %stack.0.x.addr, 1, _, 0, _, %0, debug-location !DILocation(line: 3, column: 2, scope: !15, isImplicitCode: true)
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0, debug-location !DILocation(line: 4, scope: !15, inlinedAt: !16) MOV32mr %stack.0.x.addr, 1, _, 0, _, %0, debug-location !DILocation(line: 4, scope: !15, inlinedAt: !16)
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0, debug-location !DILocation(line: 5, scope: !15, inlinedAt: !DILocation(line: 4, scope: !15)) MOV32mr %stack.0.x.addr, 1, _, 0, _, %0, debug-location !DILocation(line: 5, scope: !15, inlinedAt: !DILocation(line: 4, scope: !15))
$eax = COPY %0 $eax = COPY %0
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir

Show All 14 Lines
name: test name: test
constants: constants:
- id: 0 - id: 0
value: 'double 3.250000e+00' value: 'double 3.250000e+00'
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: [[@LINE+1]]:47: use of undefined constant '%const.10' ; CHECK: [[@LINE+1]]:47: use of undefined constant '%const.10'
$xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.10, _ $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.10, _
RETQ $xmm0 RET64 $xmm0
... ...

llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir

Show All 14 Lines
--- ---
name: inc name: inc
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: [[@LINE+1]]:45: use of undefined target flag 'x86-test' ; CHECK: [[@LINE+1]]:45: use of undefined target flag 'x86-test'
$rax = MOV64rm $rip, 1, _, target-flags(x86-test) @G, _ $rax = MOV64rm $rip, 1, _, target-flags(x86-test) @G, _
$eax = MOV32rm killed $rax, 1, _, 0, _ $eax = MOV32rm killed $rax, 1, _, 0, _
$eax = INC32r killed $eax, implicit-def dead $eflags $eax = INC32r killed $eax, implicit-def dead $eflags
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir

Show All 14 Linesliveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: [[@LINE+1]]:58: use of invalid tied-def operand index '300'; instruction has only 6 operands ; CHECK: [[@LINE+1]]:58: use of invalid tied-def operand index '300'; instruction has only 6 operands
INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(tied-def 300) INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(tied-def 300)
$rax = COPY killed $rdi $rax = COPY killed $rdi
RETQ killed $rax RET64 killed $rax
... ...

llvm/test/CodeGen/MIR/X86/jump-table-info.mir

Show First 20 Lines • Show All 80 Lines • ▼ Show 20 Lines bb.1.entry:
; CHECK: $rcx = LEA64r $rip, 1, $noreg, %jump-table.0, $noreg ; CHECK: $rcx = LEA64r $rip, 1, $noreg, %jump-table.0, $noreg
$rcx = LEA64r $rip, 1, _, %jump-table.0, _ $rcx = LEA64r $rip, 1, _, %jump-table.0, _
$rax = MOVSX64rm32 $rcx, 4, $rax, 0, _ $rax = MOVSX64rm32 $rcx, 4, $rax, 0, _
$rax = ADD64rr $rax, $rcx, implicit-def $eflags $rax = ADD64rr $rax, $rcx, implicit-def $eflags
JMP64r $rax JMP64r $rax
bb.2.def: bb.2.def:
$eax = MOV32r0 implicit-def $eflags $eax = MOV32r0 implicit-def $eflags
RETQ $eax RET64 $eax
bb.3.lbl1: bb.3.lbl1:
$eax = MOV32ri 1 $eax = MOV32ri 1
RETQ $eax RET64 $eax
bb.4.lbl2: bb.4.lbl2:
$eax = MOV32ri 2 $eax = MOV32ri 2
RETQ $eax RET64 $eax
bb.5.lbl3: bb.5.lbl3:
$eax = MOV32ri 4 $eax = MOV32ri 4
RETQ $eax RET64 $eax
bb.6.lbl4: bb.6.lbl4:
$eax = MOV32ri 8 $eax = MOV32ri 8
RETQ $eax RET64 $eax
... ...
--- ---
name: test_jumptable2 name: test_jumptable2
jumpTable: jumpTable:
kind: label-difference32 kind: label-difference32
entries: entries:
- id: 1 - id: 1
blocks: [ '%bb.3', '%bb.4', '%bb.5', '%bb.6' ] blocks: [ '%bb.3', '%bb.4', '%bb.5', '%bb.6' ]
Show All 11 Lines bb.1.entry:
; CHECK: $rcx = LEA64r $rip, 1, $noreg, %jump-table.0, $noreg ; CHECK: $rcx = LEA64r $rip, 1, $noreg, %jump-table.0, $noreg
$rcx = LEA64r $rip, 1, _, %jump-table.1, _ $rcx = LEA64r $rip, 1, _, %jump-table.1, _
$rax = MOVSX64rm32 $rcx, 4, $rax, 0, _ $rax = MOVSX64rm32 $rcx, 4, $rax, 0, _
$rax = ADD64rr $rax, $rcx, implicit-def $eflags $rax = ADD64rr $rax, $rcx, implicit-def $eflags
JMP64r $rax JMP64r $rax
bb.2.def: bb.2.def:
$eax = MOV32r0 implicit-def $eflags $eax = MOV32r0 implicit-def $eflags
RETQ $eax RET64 $eax
bb.3.lbl1: bb.3.lbl1:
$eax = MOV32ri 1 $eax = MOV32ri 1
RETQ $eax RET64 $eax
bb.4.lbl2: bb.4.lbl2:
$eax = MOV32ri 2 $eax = MOV32ri 2
RETQ $eax RET64 $eax
bb.5.lbl3: bb.5.lbl3:
$eax = MOV32ri 4 $eax = MOV32ri 4
RETQ $eax RET64 $eax
bb.6.lbl4: bb.6.lbl4:
$eax = MOV32ri 8 $eax = MOV32ri 8
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines bb.1.entry:
$rcx = LEA64r $rip, 1, _, %jump-table.0, _ $rcx = LEA64r $rip, 1, _, %jump-table.0, _
$rax = MOVSX64rm32 $rcx, 4, $rax, 0, _ $rax = MOVSX64rm32 $rcx, 4, $rax, 0, _
$rax = ADD64rr $rax, $rcx, implicit-def $eflags $rax = ADD64rr $rax, $rcx, implicit-def $eflags
JMP64r $rax JMP64r $rax
bb.2.def: bb.2.def:
$eax = MOV32r0 implicit-def $eflags $eax = MOV32r0 implicit-def $eflags
RETQ $eax RET64 $eax
bb.3.lbl1: bb.3.lbl1:
$eax = MOV32ri 1 $eax = MOV32ri 1
RETQ $eax RET64 $eax
bb.4.lbl2: bb.4.lbl2:
$eax = MOV32ri 2 $eax = MOV32ri 2
RETQ $eax RET64 $eax
bb.5.lbl3: bb.5.lbl3:
$eax = MOV32ri 4 $eax = MOV32ri 4
RETQ $eax RET64 $eax
bb.6.lbl4: bb.6.lbl4:
$eax = MOV32ri 8 $eax = MOV32ri 8
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/killed-register-flag.mir

Show All 22 Linesbody: |
bb.0.entry: bb.0.entry:
successors: %bb.1.less, %bb.2.exit successors: %bb.1.less, %bb.2.exit
CMP32ri8 $edi, 10, implicit-def $eflags CMP32ri8 $edi, 10, implicit-def $eflags
JCC_1 %bb.2.exit, 15, implicit $eflags JCC_1 %bb.2.exit, 15, implicit $eflags
bb.1.less: bb.1.less:
; CHECK: $eax = MOV32r0 ; CHECK: $eax = MOV32r0
; CHECK-NEXT: RETQ killed $eax ; CHECK-NEXT: RET64 killed $eax
$eax = MOV32r0 implicit-def $eflags $eax = MOV32r0 implicit-def $eflags
RETQ killed $eax RET64 killed $eax
bb.2.exit: bb.2.exit:
; CHECK: $eax = COPY killed $edi ; CHECK: $eax = COPY killed $edi
; CHECK-NEXT: RETQ killed $eax ; CHECK-NEXT: RET64 killed $eax
$eax = COPY killed $edi $eax = COPY killed $edi
RETQ killed $eax RET64 killed $eax
... ...

llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir

Show All 16 Lines
stack: stack:
- { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 } - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
$rsp = SUB64ri32 $rsp, 4040, implicit-def dead $eflags $rsp = SUB64ri32 $rsp, 4040, implicit-def dead $eflags
; CHECK: [[@LINE+1]]:36: expected a 32 bit integer (the cfi offset is too large) ; CHECK: [[@LINE+1]]:36: expected a 32 bit integer (the cfi offset is too large)
CFI_INSTRUCTION def_cfa_offset 123456789123456 CFI_INSTRUCTION def_cfa_offset 123456789123456
$rsp = ADD64ri32 $rsp, 4040, implicit-def dead $eflags $rsp = ADD64ri32 $rsp, 4040, implicit-def dead $eflags
RETQ RET64
... ...

llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir

# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- | --- |
define i32 @foo() { define i32 @foo() {
entry: entry:
ret i32 42 ret i32 42
} }
... ...
--- ---
name: foo name: foo
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: [[@LINE+1]]:20: integer literal is too large to be an immediate operand ; CHECK: [[@LINE+1]]:20: integer literal is too large to be an immediate operand
$eax = MOV32ri 12346127502983478823754212949184914 $eax = MOV32ri 12346127502983478823754212949184914
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/large-index-number-error.mir

Show All 23 Lines bb.0.entry:
CMP32ri8 $eax, 10, implicit-def $eflags CMP32ri8 $eax, 10, implicit-def $eflags
; CHECK: [[@LINE+1]]:11: expected 32-bit integer (too large) ; CHECK: [[@LINE+1]]:11: expected 32-bit integer (too large)
JCC_1 %bb.123456789123456, 15, implicit $eflags JCC_1 %bb.123456789123456, 15, implicit $eflags
bb.1: bb.1:
$eax = MOV32r0 implicit-def $eflags $eax = MOV32r0 implicit-def $eflags
bb.2: bb.2:
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir

Show All 14 Lines
--- ---
name: inc name: inc
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: [[@LINE+1]]:37: expected 64-bit integer (too large) ; CHECK: [[@LINE+1]]:37: expected 64-bit integer (too large)
$rax = MOV64rm $rip, 1, _, @G + 123456789123456789123456789, _ $rax = MOV64rm $rip, 1, _, @G + 123456789123456789123456789, _
$eax = MOV32rm $rax, 1, _, 0, _ $eax = MOV32rm $rax, 1, _, 0, _
$eax = INC32r $eax implicit-def $eflags $eax = INC32r $eax implicit-def $eflags
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir

Show All 13 Lines
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: [[@LINE+1]]:53: expected 64-bit integer (too large) ; CHECK: [[@LINE+1]]:53: expected 64-bit integer (too large)
$eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load 12345678912345678924218574857 from %ir.a) $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load 12345678912345678924218574857 from %ir.a)
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir

Show All 32 Lines bb.0.entry:
frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
CFI_INSTRUCTION offset $rbp, -16 CFI_INSTRUCTION offset $rbp, -16
$rbp = frame-setup MOV64rr $rsp $rbp = frame-setup MOV64rr $rsp
CFI_INSTRUCTION def_cfa_register $rbp CFI_INSTRUCTION def_cfa_register $rbp
; CHECK: PATCHPOINT 5, 5, 0, 2, 0, $rdi, $rsi, csr_64, liveout($esp, $rsp, $sp, $spl), ; CHECK: PATCHPOINT 5, 5, 0, 2, 0, $rdi, $rsi, csr_64, liveout($esp, $rsp, $sp, $spl),
PATCHPOINT 5, 5, 0, 2, 0, $rdi, $rsi, csr_64, liveout($esp, $rsp, $sp, $spl), implicit-def dead early-clobber $r11, implicit-def $rsp, implicit-def dead $rax PATCHPOINT 5, 5, 0, 2, 0, $rdi, $rsi, csr_64, liveout($esp, $rsp, $sp, $spl), implicit-def dead early-clobber $r11, implicit-def $rsp, implicit-def dead $rax
$rbp = POP64r implicit-def $rsp, implicit $rsp $rbp = POP64r implicit-def $rsp, implicit $rsp
RETQ RET64
... ...

llvm/test/CodeGen/MIR/X86/load-with-max-alignment.mir

Show All 15 LinesframeInfo:
maxAlignment: 1 maxAlignment: 1
maxCallFrameSize: 0 maxCallFrameSize: 0
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
bb.0: bb.0:
liveins: $rdi liveins: $rdi
renamable $eax = MOV32rm killed renamable $rdi, 1, $noreg, 0, $noreg :: (load (s32) from unknown-address, align 4294967296) renamable $eax = MOV32rm killed renamable $rdi, 1, $noreg, 0, $noreg :: (load (s32) from unknown-address, align 4294967296)
RETQ $eax RET64 $eax
... ...
--- ---
name: basealigned_load name: basealigned_load
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
frameInfo: frameInfo:
maxAlignment: 1 maxAlignment: 1
maxCallFrameSize: 0 maxCallFrameSize: 0
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
bb.0: bb.0:
liveins: $rdi liveins: $rdi
renamable $eax = MOV32rm killed renamable $rdi, 1, $noreg, 0, $noreg :: (load (s32) from unknown-address + 4, basealign 4294967296) renamable $eax = MOV32rm killed renamable $rdi, 1, $noreg, 0, $noreg :: (load (s32) from unknown-address + 4, basealign 4294967296)
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines bb.0.entry:
CMP32ri8 $eax, 10, implicit-def $eflags CMP32ri8 $eax, 10, implicit-def $eflags
JCC_1 %bb.2, 15, implicit $eflags JCC_1 %bb.2, 15, implicit $eflags
; CHECK: bb.1.less: ; CHECK: bb.1.less:
bb.1.less: bb.1.less:
$eax = MOV32r0 implicit-def $eflags $eax = MOV32r0 implicit-def $eflags
bb.2.exit: bb.2.exit:
RETQ $eax RET64 $eax
... ...
--- ---
# CHECK: name: bar # CHECK: name: bar
name: bar name: bar
body: | body: |
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
bb.0.entry: bb.0.entry:
successors: %bb.1, %bb.3 successors: %bb.1, %bb.3
$eax = MOV32rm $rdi, 1, _, 0, _ $eax = MOV32rm $rdi, 1, _, 0, _
; CHECK: CMP32ri8 $eax, 10 ; CHECK: CMP32ri8 $eax, 10
; CHECK-NEXT: JCC_1 %bb.2, 15 ; CHECK-NEXT: JCC_1 %bb.2, 15
CMP32ri8 $eax, 10, implicit-def $eflags CMP32ri8 $eax, 10, implicit-def $eflags
JCC_1 %bb.3, 15, implicit $eflags JCC_1 %bb.3, 15, implicit $eflags
bb.1: bb.1:
$eax = MOV32r0 implicit-def $eflags $eax = MOV32r0 implicit-def $eflags
bb.3: bb.3:
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/machine-instructions.mir

Show All 11 Lines
... ...
--- ---
# CHECK: name: inc # CHECK: name: inc
name: inc name: inc
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: MOV32rr ; CHECK: MOV32rr
; CHECK-NEXT: RETQ ; CHECK-NEXT: RET64
$eax = MOV32rr $eax $eax = MOV32rr $eax
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/machine-verifier.mir

Show All 13 Lines
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $edi liveins: $edi
; CHECK: *** Bad machine code: Too few operands *** ; CHECK: *** Bad machine code: Too few operands ***
; CHECK: instruction: COPY ; CHECK: instruction: COPY
; CHECK: 2 operands expected, but 0 given. ; CHECK: 2 operands expected, but 0 given.
COPY COPY
RETQ RET64
... ...

llvm/test/CodeGen/MIR/X86/memory-operands.mir

Show First 20 Lines • Show All 199 Lines • ▼ Show 20 Linesliveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: $eax = MOV32rm $rdi, 1, $noreg, 0, $noreg :: (load (s32) from %ir.a) ; CHECK: $eax = MOV32rm $rdi, 1, $noreg, 0, $noreg :: (load (s32) from %ir.a)
; CHECK-NEXT: MOV32mi killed $rdi, 1, $noreg, 0, $noreg, 42 :: (store (s32) into %ir.a) ; CHECK-NEXT: MOV32mi killed $rdi, 1, $noreg, 0, $noreg, 42 :: (store (s32) into %ir.a)
$eax = MOV32rm $rdi, 1, _, 0, _ :: (load (s32) from %ir.a) $eax = MOV32rm $rdi, 1, _, 0, _ :: (load (s32) from %ir.a)
MOV32mi killed $rdi, 1, _, 0, _, 42 :: (store (s32) into %ir.a) MOV32mi killed $rdi, 1, _, 0, _, 42 :: (store (s32) into %ir.a)
RETQ $eax RET64 $eax
... ...
--- ---
name: test2 name: test2
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry2: bb.0.entry2:
liveins: $rdi liveins: $rdi
; CHECK: INC32m killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (store (s32) into %ir."a value"), (load (s32) from %ir."a value") ; CHECK: INC32m killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (store (s32) into %ir."a value"), (load (s32) from %ir."a value")
INC32m killed $rdi, 1, _, 0, _, implicit-def dead $eflags :: (store (s32) into %ir."a value"), (load (s32) from %ir."a value") INC32m killed $rdi, 1, _, 0, _, implicit-def dead $eflags :: (store (s32) into %ir."a value"), (load (s32) from %ir."a value")
RETQ RET64
... ...
--- ---
name: test3 name: test3
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
frameInfo: frameInfo:
maxAlignment: 4 maxAlignment: 4
stack: stack:
- { id: 0, offset: -12, size: 4, alignment: 4 } - { id: 0, offset: -12, size: 4, alignment: 4 }
body: | body: |
bb.0.entry3: bb.0.entry3:
liveins: $rdi liveins: $rdi
; Verify that the unnamed local values can be serialized. ; Verify that the unnamed local values can be serialized.
; CHECK-LABEL: name: test3 ; CHECK-LABEL: name: test3
; CHECK: $eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg :: (load (s32) from %ir.0) ; CHECK: $eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg :: (load (s32) from %ir.0)
; CHECK: MOV32mr $rsp, 1, $noreg, -4, $noreg, killed $eax :: (store (s32) into %ir.1) ; CHECK: MOV32mr $rsp, 1, $noreg, -4, $noreg, killed $eax :: (store (s32) into %ir.1)
$eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load (s32) from %ir.0) $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load (s32) from %ir.0)
$eax = INC32r killed $eax, implicit-def dead $eflags $eax = INC32r killed $eax, implicit-def dead $eflags
MOV32mr $rsp, 1, _, -4, _, killed $eax :: (store (s32) into %ir.1) MOV32mr $rsp, 1, _, -4, _, killed $eax :: (store (s32) into %ir.1)
RETQ RET64
... ...
--- ---
name: volatile_inc name: volatile_inc
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: name: volatile_inc ; CHECK: name: volatile_inc
; CHECK: $eax = MOV32rm $rdi, 1, $noreg, 0, $noreg :: (volatile load (s32) from %ir.x) ; CHECK: $eax = MOV32rm $rdi, 1, $noreg, 0, $noreg :: (volatile load (s32) from %ir.x)
; CHECK: MOV32mr killed $rdi, 1, $noreg, 0, $noreg, $eax :: (volatile store (s32) into %ir.x) ; CHECK: MOV32mr killed $rdi, 1, $noreg, 0, $noreg, $eax :: (volatile store (s32) into %ir.x)
$eax = MOV32rm $rdi, 1, _, 0, _ :: (volatile load (s32) from %ir.x) $eax = MOV32rm $rdi, 1, _, 0, _ :: (volatile load (s32) from %ir.x)
$eax = INC32r killed $eax, implicit-def dead $eflags $eax = INC32r killed $eax, implicit-def dead $eflags
MOV32mr killed $rdi, 1, _, 0, _, $eax :: (volatile store (s32) into %ir.x) MOV32mr killed $rdi, 1, _, 0, _, $eax :: (volatile store (s32) into %ir.x)
RETQ $eax RET64 $eax
... ...
--- ---
name: non_temporal_store name: non_temporal_store
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
- { reg: '$esi' } - { reg: '$esi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $esi, $rdi liveins: $esi, $rdi
; CHECK: name: non_temporal_store ; CHECK: name: non_temporal_store
; CHECK: MOVNTImr killed $rdi, 1, $noreg, 0, $noreg, killed $esi :: (non-temporal store (s32) into %ir.a) ; CHECK: MOVNTImr killed $rdi, 1, $noreg, 0, $noreg, killed $esi :: (non-temporal store (s32) into %ir.a)
MOVNTImr killed $rdi, 1, _, 0, _, killed $esi :: (non-temporal store (s32) into %ir.a) MOVNTImr killed $rdi, 1, _, 0, _, killed $esi :: (non-temporal store (s32) into %ir.a)
RETQ RET64
... ...
--- ---
name: invariant_load name: invariant_load
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: name: invariant_load ; CHECK: name: invariant_load
; CHECK: $eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg :: (invariant load (s32) from %ir.x) ; CHECK: $eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg :: (invariant load (s32) from %ir.x)
$eax = MOV32rm killed $rdi, 1, _, 0, _ :: (invariant load (s32) from %ir.x) $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (invariant load (s32) from %ir.x)
RETQ $eax RET64 $eax
... ...
--- ---
name: memory_offset name: memory_offset
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: name: memory_offset ; CHECK: name: memory_offset
; CHECK: $xmm0 = MOVAPSrm $rdi, 1, $noreg, 0, $noreg :: (load (s128) from %ir.vec) ; CHECK: $xmm0 = MOVAPSrm $rdi, 1, $noreg, 0, $noreg :: (load (s128) from %ir.vec)
; CHECK-NEXT: $xmm1 = MOVAPSrm $rdi, 1, $noreg, 16, $noreg :: (load (s128) from %ir.vec + 16) ; CHECK-NEXT: $xmm1 = MOVAPSrm $rdi, 1, $noreg, 16, $noreg :: (load (s128) from %ir.vec + 16)
; CHECK: MOVAPSmr $rdi, 1, $noreg, 0, $noreg, killed $xmm0 :: (store (s128) into %ir.vec) ; CHECK: MOVAPSmr $rdi, 1, $noreg, 0, $noreg, killed $xmm0 :: (store (s128) into %ir.vec)
; CHECK-NEXT: MOVAPSmr killed $rdi, 1, $noreg, 16, $noreg, killed $xmm1 :: (store (s128) into %ir.vec + 16) ; CHECK-NEXT: MOVAPSmr killed $rdi, 1, $noreg, 16, $noreg, killed $xmm1 :: (store (s128) into %ir.vec + 16)
$xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load (s128) from %ir.vec) $xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load (s128) from %ir.vec)
$xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load (s128) from %ir.vec + 16) $xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load (s128) from %ir.vec + 16)
$xmm2 = FsFLD0SS $xmm2 = FsFLD0SS
$xmm1 = MOVSSrr killed $xmm1, killed $xmm2 $xmm1 = MOVSSrr killed $xmm1, killed $xmm2
MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store (s128) into %ir.vec) MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store (s128) into %ir.vec)
MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store (s128) into %ir.vec + 16) MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store (s128) into %ir.vec + 16)
RETQ RET64
... ...
--- ---
name: memory_alignment name: memory_alignment
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
Show All 12 Lines ; CHECK-NEXT: MOVAPSmr killed $rdi, 1, $noreg, 48, $noreg, killed $xmm3 :: (store (s128) into %ir.vec + 48, basealign 64)
$xmm2 = MOVAPSrm $rdi, 1, _, 32, _ :: (load (s128) from %ir.vec + 32, align 32, basealign 64) $xmm2 = MOVAPSrm $rdi, 1, _, 32, _ :: (load (s128) from %ir.vec + 32, align 32, basealign 64)
$xmm3 = MOVAPSrm $rdi, 1, _, 48, _ :: (load (s128) from %ir.vec + 48, basealign 64) $xmm3 = MOVAPSrm $rdi, 1, _, 48, _ :: (load (s128) from %ir.vec + 48, basealign 64)
$xmm4 = FsFLD0SS $xmm4 = FsFLD0SS
$xmm1 = MOVSSrr killed $xmm1, killed $xmm4 $xmm1 = MOVSSrr killed $xmm1, killed $xmm4
MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store (s128) into %ir.vec, align 64) MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store (s128) into %ir.vec, align 64)
MOVAPSmr $rdi, 1, _, 16, _, killed $xmm1 :: (store (s128) into %ir.vec + 16, basealign 64) MOVAPSmr $rdi, 1, _, 16, _, killed $xmm1 :: (store (s128) into %ir.vec + 16, basealign 64)
MOVAPSmr $rdi, 1, _, 32, _, killed $xmm2 :: (store (s128) into %ir.vec + 32, align 32, basealign 64) MOVAPSmr $rdi, 1, _, 32, _, killed $xmm2 :: (store (s128) into %ir.vec + 32, align 32, basealign 64)
MOVAPSmr killed $rdi, 1, _, 48, _, killed $xmm3 :: (store (s128) into %ir.vec + 48, basealign 64) MOVAPSmr killed $rdi, 1, _, 48, _, killed $xmm3 :: (store (s128) into %ir.vec + 48, basealign 64)
RETQ RET64
... ...
--- ---
name: constant_pool_psv name: constant_pool_psv
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$xmm0' } - { reg: '$xmm0' }
constants: constants:
- id: 0 - id: 0
value: 'double 3.250000e+00' value: 'double 3.250000e+00'
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $xmm0 liveins: $xmm0
; CHECK: name: constant_pool_psv ; CHECK: name: constant_pool_psv
; CHECK: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.0, $noreg, implicit $mxcsr :: (load (s64) from constant-pool) ; CHECK: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.0, $noreg, implicit $mxcsr :: (load (s64) from constant-pool)
; CHECK-NEXT: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.0, $noreg, implicit $mxcsr :: (load (s64) from constant-pool + 8) ; CHECK-NEXT: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.0, $noreg, implicit $mxcsr :: (load (s64) from constant-pool + 8)
$xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _, implicit $mxcsr :: (load (s64) from constant-pool) $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _, implicit $mxcsr :: (load (s64) from constant-pool)
$xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _, implicit $mxcsr :: (load (s64) from constant-pool + 8) $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _, implicit $mxcsr :: (load (s64) from constant-pool + 8)
RETQ $xmm0 RET64 $xmm0
... ...
--- ---
name: stack_psv name: stack_psv
tracksRegLiveness: true tracksRegLiveness: true
frameInfo: frameInfo:
stackSize: 24 stackSize: 24
maxAlignment: 16 maxAlignment: 16
adjustsStack: true adjustsStack: true
hasCalls: true hasCalls: true
maxCallFrameSize: 16 maxCallFrameSize: 16
fixedStack: fixedStack:
- { id: 0, offset: 0, size: 10, alignment: 16, isImmutable: true, isAliased: false } - { id: 0, offset: 0, size: 10, alignment: 16, isImmutable: true, isAliased: false }
body: | body: |
bb.0.entry: bb.0.entry:
$rsp = frame-setup SUB64ri8 $rsp, 24, implicit-def dead $eflags $rsp = frame-setup SUB64ri8 $rsp, 24, implicit-def dead $eflags
CFI_INSTRUCTION def_cfa_offset 32 CFI_INSTRUCTION def_cfa_offset 32
LD_F80m $rsp, 1, $noreg, 32, $noreg, implicit-def dead $fpsw, implicit $fpcw LD_F80m $rsp, 1, $noreg, 32, $noreg, implicit-def dead $fpsw, implicit $fpcw
; CHECK: name: stack_psv ; CHECK: name: stack_psv
; CHECK: ST_FP80m $rsp, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (store (s80) into stack, align 16) ; CHECK: ST_FP80m $rsp, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (store (s80) into stack, align 16)
ST_FP80m $rsp, 1, _, 0, _, implicit-def dead $fpsw, implicit $fpcw :: (store (s80) into stack, align 16) ST_FP80m $rsp, 1, _, 0, _, implicit-def dead $fpsw, implicit $fpcw :: (store (s80) into stack, align 16)
CALL64pcrel32 &cosl, csr_64, implicit $rsp, implicit-def $rsp, implicit-def $fp0 CALL64pcrel32 &cosl, csr_64, implicit $rsp, implicit-def $rsp, implicit-def $fp0
$rsp = ADD64ri8 $rsp, 24, implicit-def dead $eflags $rsp = ADD64ri8 $rsp, 24, implicit-def dead $eflags
RETQ RET64
... ...
--- ---
name: got_psv name: got_psv
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: name: got_psv ; CHECK: name: got_psv
; CHECK: $rax = MOV64rm $rip, 1, $noreg, @G, $noreg :: (load (s64) from got) ; CHECK: $rax = MOV64rm $rip, 1, $noreg, @G, $noreg :: (load (s64) from got)
$rax = MOV64rm $rip, 1, _, @G, _ :: (load (s64) from got) $rax = MOV64rm $rip, 1, _, @G, _ :: (load (s64) from got)
$eax = MOV32rm killed $rax, 1, _, 0, _ $eax = MOV32rm killed $rax, 1, _, 0, _
$eax = INC32r killed $eax, implicit-def dead $eflags $eax = INC32r killed $eax, implicit-def dead $eflags
RETQ $eax RET64 $eax
... ...
--- ---
name: global_value name: global_value
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.entry: bb.0.entry:
$rax = MOV64rm $rip, 1, _, @G, _ $rax = MOV64rm $rip, 1, _, @G, _
; CHECK-LABEL: name: global_value ; CHECK-LABEL: name: global_value
; CHECK: $eax = MOV32rm killed $rax, 1, $noreg, 0, $noreg, implicit-def $rax :: (load (s32) from @G) ; CHECK: $eax = MOV32rm killed $rax, 1, $noreg, 0, $noreg, implicit-def $rax :: (load (s32) from @G)
; CHECK: $ecx = MOV32rm killed $rcx, 1, $noreg, 0, $noreg, implicit-def $rcx :: (load (s32) from @0) ; CHECK: $ecx = MOV32rm killed $rcx, 1, $noreg, 0, $noreg, implicit-def $rcx :: (load (s32) from @0)
$eax = MOV32rm killed $rax, 1, _, 0, _, implicit-def $rax :: (load (s32) from @G) $eax = MOV32rm killed $rax, 1, _, 0, _, implicit-def $rax :: (load (s32) from @G)
$rcx = MOV64rm $rip, 1, _, @0, _ $rcx = MOV64rm $rip, 1, _, @0, _
$ecx = MOV32rm killed $rcx, 1, _, 0, _, implicit-def $rcx :: (load (s32) from @0) $ecx = MOV32rm killed $rcx, 1, _, 0, _, implicit-def $rcx :: (load (s32) from @0)
$eax = LEA64_32r killed $rax, 1, killed $rcx, 1, _ $eax = LEA64_32r killed $rax, 1, killed $rcx, 1, _
RETQ $eax RET64 $eax
... ...
--- ---
name: jumptable_psv name: jumptable_psv
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$edi' } - { reg: '$edi' }
jumpTable: jumpTable:
kind: label-difference32 kind: label-difference32
Show All 17 Linesbody: |
; CHECK: name: jumptable_psv ; CHECK: name: jumptable_psv
; CHECK: $rax = MOVSX64rm32 $rcx, 4, killed $rax, 0, $noreg :: (load (s32) from jump-table, align 8) ; CHECK: $rax = MOVSX64rm32 $rcx, 4, killed $rax, 0, $noreg :: (load (s32) from jump-table, align 8)
$rax = MOVSX64rm32 $rcx, 4, killed $rax, 0, _ :: (load (s32) from jump-table, align 8) $rax = MOVSX64rm32 $rcx, 4, killed $rax, 0, _ :: (load (s32) from jump-table, align 8)
$rax = ADD64rr killed $rax, killed $rcx, implicit-def dead $eflags $rax = ADD64rr killed $rax, killed $rcx, implicit-def dead $eflags
JMP64r killed $rax JMP64r killed $rax
bb.2.def: bb.2.def:
$eax = MOV32r0 implicit-def dead $eflags $eax = MOV32r0 implicit-def dead $eflags
RETQ $eax RET64 $eax
bb.3.lbl1: bb.3.lbl1:
$eax = MOV32ri 1 $eax = MOV32ri 1
RETQ $eax RET64 $eax
bb.4.lbl2: bb.4.lbl2:
$eax = MOV32ri 2 $eax = MOV32ri 2
RETQ $eax RET64 $eax
bb.5.lbl3: bb.5.lbl3:
$eax = MOV32ri 4 $eax = MOV32ri 4
RETQ $eax RET64 $eax
bb.6.lbl4: bb.6.lbl4:
$eax = MOV32ri 8 $eax = MOV32ri 8
RETQ $eax RET64 $eax
... ...
--- ---
name: tbaa_metadata name: tbaa_metadata
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.entry: bb.0.entry:
$rax = MOV64rm $rip, 1, _, @a, _ :: (load (s64) from got) $rax = MOV64rm $rip, 1, _, @a, _ :: (load (s64) from got)
; CHECK-LABEL: name: tbaa_metadata ; CHECK-LABEL: name: tbaa_metadata
; CHECK: $eax = MOV32rm killed $rax, 1, $noreg, 0, $noreg, implicit-def $rax :: (load (s32) from @a, !tbaa !2) ; CHECK: $eax = MOV32rm killed $rax, 1, $noreg, 0, $noreg, implicit-def $rax :: (load (s32) from @a, !tbaa !2)
; CHECK-NEXT: $eax = MOV32rm killed $rax, 1, $noreg, 0, $noreg :: (load (s32) from %ir.total_len2, !tbaa !6) ; CHECK-NEXT: $eax = MOV32rm killed $rax, 1, $noreg, 0, $noreg :: (load (s32) from %ir.total_len2, !tbaa !6)
$eax = MOV32rm killed $rax, 1, _, 0, _, implicit-def $rax :: (load (s32) from @a, !tbaa !2) $eax = MOV32rm killed $rax, 1, _, 0, _, implicit-def $rax :: (load (s32) from @a, !tbaa !2)
$eax = MOV32rm killed $rax, 1, _, 0, _ :: (load (s32) from %ir.total_len2, !tbaa !6) $eax = MOV32rm killed $rax, 1, _, 0, _ :: (load (s32) from %ir.total_len2, !tbaa !6)
RETQ $eax RET64 $eax
... ...
--- ---
name: aa_scope name: aa_scope
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
- { reg: '$rsi' } - { reg: '$rsi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi, $rsi liveins: $rdi, $rsi
; CHECK-LABEL: name: aa_scope ; CHECK-LABEL: name: aa_scope
; CHECK: $xmm0 = MOVSSrm_alt $rsi, 1, $noreg, 0, $noreg :: (load (s32) from %ir.c, !alias.scope !9) ; CHECK: $xmm0 = MOVSSrm_alt $rsi, 1, $noreg, 0, $noreg :: (load (s32) from %ir.c, !alias.scope !9)
$xmm0 = MOVSSrm_alt $rsi, 1, _, 0, _ :: (load (s32) from %ir.c, !alias.scope !9) $xmm0 = MOVSSrm_alt $rsi, 1, _, 0, _ :: (load (s32) from %ir.c, !alias.scope !9)
; CHECK-NEXT: MOVSSmr $rdi, 1, $noreg, 20, $noreg, killed $xmm0 :: (store (s32) into %ir.arrayidx.i, !noalias !9) ; CHECK-NEXT: MOVSSmr $rdi, 1, $noreg, 20, $noreg, killed $xmm0 :: (store (s32) into %ir.arrayidx.i, !noalias !9)
MOVSSmr $rdi, 1, _, 20, _, killed $xmm0 :: (store (s32) into %ir.arrayidx.i, !noalias !9) MOVSSmr $rdi, 1, _, 20, _, killed $xmm0 :: (store (s32) into %ir.arrayidx.i, !noalias !9)
$xmm0 = MOVSSrm_alt killed $rsi, 1, _, 0, _ :: (load (s32) from %ir.c) $xmm0 = MOVSSrm_alt killed $rsi, 1, _, 0, _ :: (load (s32) from %ir.c)
MOVSSmr killed $rdi, 1, _, 28, _, killed $xmm0 :: (store (s32) into %ir.arrayidx) MOVSSmr killed $rdi, 1, _, 28, _, killed $xmm0 :: (store (s32) into %ir.arrayidx)
RETQ RET64
... ...
--- ---
name: range_metadata name: range_metadata
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK-LABEL: name: range_metadata ; CHECK-LABEL: name: range_metadata
; CHECK: $al = MOV8rm killed $rdi, 1, $noreg, 0, $noreg :: (load (s8) from %ir.x, !range !11) ; CHECK: $al = MOV8rm killed $rdi, 1, $noreg, 0, $noreg :: (load (s8) from %ir.x, !range !11)
$al = MOV8rm killed $rdi, 1, _, 0, _ :: (load (s8) from %ir.x, !range !11) $al = MOV8rm killed $rdi, 1, _, 0, _ :: (load (s8) from %ir.x, !range !11)
RETQ $al RET64 $al
... ...
--- ---
name: gep_value name: gep_value
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
$rax = MOV64rm $rip, 1, _, @values, _ :: (load (s64) from got) $rax = MOV64rm $rip, 1, _, @values, _ :: (load (s64) from got)
; CHECK-LABEL: gep_value ; CHECK-LABEL: gep_value
; CHECK: MOV32mr killed $rax, 1, $noreg, 0, $noreg, $edi, implicit killed $rdi :: (store (s32) into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16) ; CHECK: MOV32mr killed $rax, 1, $noreg, 0, $noreg, $edi, implicit killed $rdi :: (store (s32) into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16)
MOV32mr killed $rax, 1, _, 0, _, $edi, implicit killed $rdi :: (store (s32) into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16) MOV32mr killed $rax, 1, _, 0, _, $edi, implicit killed $rdi :: (store (s32) into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16)
RETQ RET64
... ...
--- ---
name: undef_value name: undef_value
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: undef_value ; CHECK-LABEL: name: undef_value
; CHECK: $rax = MOV64rm undef $rax, 1, $noreg, 0, $noreg :: (load (s64) from `i8** undef`) ; CHECK: $rax = MOV64rm undef $rax, 1, $noreg, 0, $noreg :: (load (s64) from `i8** undef`)
$rax = MOV64rm undef $rax, 1, _, 0, _ :: (load (s64) from `i8** undef`) $rax = MOV64rm undef $rax, 1, _, 0, _ :: (load (s64) from `i8** undef`)
RETQ $rax RET64 $rax
... ...
--- ---
# Test memory operand without associated value. # Test memory operand without associated value.
# CHECK-LABEL: name: dummy0 # CHECK-LABEL: name: dummy0
# CHECK: $rax = MOV64rm undef $rax, 1, $noreg, 0, $noreg :: (load (s64)) # CHECK: $rax = MOV64rm undef $rax, 1, $noreg, 0, $noreg :: (load (s64))
name: dummy0 name: dummy0
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
$rax = MOV64rm undef $rax, 1, _, 0, _ :: (load (s64)) $rax = MOV64rm undef $rax, 1, _, 0, _ :: (load (s64))
RETQ $rax RET64 $rax
... ...
--- ---
# Test parsing of stack references in machine memory operands. # Test parsing of stack references in machine memory operands.
# CHECK-LABEL: name: dummy1 # CHECK-LABEL: name: dummy1
# CHECK: $rax = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load (s64) from %stack.0) # CHECK: $rax = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load (s64) from %stack.0)
name: dummy1 name: dummy1
tracksRegLiveness: true tracksRegLiveness: true
stack: stack:
- { id: 0, size: 4, alignment: 4 } - { id: 0, size: 4, alignment: 4 }
body: | body: |
bb.0: bb.0:
$rax = MOV64rm $rsp, 1, _, 0, _ :: (load (s64) from %stack.0) $rax = MOV64rm $rsp, 1, _, 0, _ :: (load (s64) from %stack.0)
RETQ $rax RET64 $rax
... ...
--- ---
# Test parsing of unknown size in machine memory operands without alignment. # Test parsing of unknown size in machine memory operands without alignment.
# CHECK-LABEL: name: dummy2 # CHECK-LABEL: name: dummy2
# CHECK: $rax = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load unknown-size from %stack.0, align 1) # CHECK: $rax = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load unknown-size from %stack.0, align 1)
name: dummy2 name: dummy2
tracksRegLiveness: true tracksRegLiveness: true
stack: stack:
- { id: 0, size: 4, alignment: 4 } - { id: 0, size: 4, alignment: 4 }
body: | body: |
bb.0: bb.0:
$rax = MOV64rm $rsp, 1, _, 0, _ :: (load unknown-size from %stack.0) $rax = MOV64rm $rsp, 1, _, 0, _ :: (load unknown-size from %stack.0)
RETQ $rax RET64 $rax
... ...
--- ---
# Test parsing of unknown size in machine memory operands with alignment. # Test parsing of unknown size in machine memory operands with alignment.
# CHECK-LABEL: name: dummy3 # CHECK-LABEL: name: dummy3
# CHECK: $rax = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load unknown-size from %stack.0, align 4) # CHECK: $rax = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load unknown-size from %stack.0, align 4)
name: dummy3 name: dummy3
tracksRegLiveness: true tracksRegLiveness: true
stack: stack:
- { id: 0, size: 4, alignment: 4 } - { id: 0, size: 4, alignment: 4 }
body: | body: |
bb.0: bb.0:
$rax = MOV64rm $rsp, 1, _, 0, _ :: (load unknown-size from %stack.0, align 4) $rax = MOV64rm $rsp, 1, _, 0, _ :: (load unknown-size from %stack.0, align 4)
RETQ $rax RET64 $rax
... ...

llvm/test/CodeGen/MIR/X86/metadata-operands.mir

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $edi liveins: $edi
; CHECK: %0:gr32 = COPY $edi ; CHECK: %0:gr32 = COPY $edi
; CHECK-NEXT: DBG_VALUE $noreg, 0, !11, !DIExpression() ; CHECK-NEXT: DBG_VALUE $noreg, 0, !11, !DIExpression()
%0 = COPY $edi %0 = COPY $edi
DBG_VALUE _, 0, !12, !DIExpression(), debug-location !13 DBG_VALUE _, 0, !12, !DIExpression(), debug-location !13
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
$eax = COPY %0 $eax = COPY %0
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir

Show All 12 Lines
... ...
--- ---
name: test name: test
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: [[@LINE+1]]:48: end of machine instruction reached before the closing '"' ; CHECK: [[@LINE+1]]:48: end of machine instruction reached before the closing '"'
$rax = MOV64rm $rip, 1, _, @"quoted name, _ $rax = MOV64rm $rip, 1, _, @"quoted name, _
$eax = MOV32rm killed $rax, 1, _, 0, _ $eax = MOV32rm killed $rax, 1, _, 0, _
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/missing-comma.mir

# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- | --- |
define i32 @foo() { define i32 @foo() {
entry: entry:
ret i32 0 ret i32 0
} }
... ...
--- ---
name: foo name: foo
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: [[@LINE+1]]:25: expected ',' before the next machine operand ; CHECK: [[@LINE+1]]:25: expected ',' before the next machine operand
$eax = XOR32rr $eax $eflags $eax = XOR32rr $eax $eflags
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir

Show All 28 Lines bb.0.entry:
CMP32ri8 $eax, 10, implicit-def $eflags CMP32ri8 $eax, 10, implicit-def $eflags
; CHECK: [[@LINE+1]]:25: missing implicit register operand 'implicit $eflags' ; CHECK: [[@LINE+1]]:25: missing implicit register operand 'implicit $eflags'
JCC_1 %bb.2.exit, 15 JCC_1 %bb.2.exit, 15
bb.1.less: bb.1.less:
$eax = MOV32r0 implicit-def $eflags $eax = MOV32r0 implicit-def $eflags
bb.2.exit: bb.2.exit:
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/named-registers.mir

Show All 9 Lines
... ...
--- ---
# CHECK: name: foo # CHECK: name: foo
name: foo name: foo
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: $eax = MOV32r0 ; CHECK: $eax = MOV32r0
; CHECK-NEXT: RETQ $eax ; CHECK-NEXT: RET64 $eax
$eax = MOV32r0 implicit-def $eflags $eax = MOV32r0 implicit-def $eflags
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/newline-handling.mir

Show All 36 Lines
# CHECK-NEXT: bb.0.entry: # CHECK-NEXT: bb.0.entry:
# CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) # CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
# CHECK-NEXT: liveins: $edi # CHECK-NEXT: liveins: $edi
# CHECK: CMP32ri8 $edi, 10, implicit-def $eflags # CHECK: CMP32ri8 $edi, 10, implicit-def $eflags
# CHECK-NEXT: JCC_1 %bb.2, 15, implicit killed $eflags # CHECK-NEXT: JCC_1 %bb.2, 15, implicit killed $eflags
# CHECK: bb.1.less: # CHECK: bb.1.less:
# CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags # CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags
# CHECK-NEXT: RETQ killed $eax # CHECK-NEXT: RET64 killed $eax
# CHECK: bb.2.exit: # CHECK: bb.2.exit:
# CHECK-NEXT: liveins: $edi # CHECK-NEXT: liveins: $edi
# CHECK: $eax = COPY killed $edi # CHECK: $eax = COPY killed $edi
# CHECK-NEXT: RETQ killed $eax # CHECK-NEXT: RET64 killed $eax
body: | body: |
bb.0.entry: bb.0.entry:
successors: %bb.1, %bb.2 successors: %bb.1, %bb.2
liveins: $edi liveins: $edi
CMP32ri8 $edi, 10, implicit-def $eflags CMP32ri8 $edi, 10, implicit-def $eflags
JCC_1 %bb.2, 15, implicit killed $eflags JCC_1 %bb.2, 15, implicit killed $eflags
bb.1.less: bb.1.less:
$eax = MOV32r0 implicit-def dead $eflags $eax = MOV32r0 implicit-def dead $eflags
RETQ killed $eax RET64 killed $eax
bb.2.exit: bb.2.exit:
liveins: $edi liveins: $edi
$eax = COPY killed $edi $eax = COPY killed $edi
RETQ killed $eax RET64 killed $eax
... ...
--- ---
name: bar name: bar
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$edi' } - { reg: '$edi' }
# CHECK-LABEL: name: bar # CHECK-LABEL: name: bar
# CHECK: body: | # CHECK: body: |
# CHECK-NEXT: bb.0.entry: # CHECK-NEXT: bb.0.entry:
# CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) # CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
# CHECK-NEXT: liveins: $edi # CHECK-NEXT: liveins: $edi
# CHECK: CMP32ri8 $edi, 10, implicit-def $eflags # CHECK: CMP32ri8 $edi, 10, implicit-def $eflags
# CHECK-NEXT: JCC_1 %bb.2, 15, implicit killed $eflags # CHECK-NEXT: JCC_1 %bb.2, 15, implicit killed $eflags
# CHECK: bb.1.less: # CHECK: bb.1.less:
# CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags # CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags
# CHECK-NEXT: RETQ killed $eax # CHECK-NEXT: RET64 killed $eax
# CHECK: bb.2.exit: # CHECK: bb.2.exit:
# CHECK-NEXT: liveins: $edi # CHECK-NEXT: liveins: $edi
# CHECK: $eax = COPY killed $edi # CHECK: $eax = COPY killed $edi
# CHECK-NEXT: RETQ killed $eax # CHECK-NEXT: RET64 killed $eax
body: | body: |
bb.0.entry: bb.0.entry:
successors: %bb.1, %bb.2 successors: %bb.1, %bb.2
liveins: $edi liveins: $edi
CMP32ri8 $edi, 10, implicit-def $eflags CMP32ri8 $edi, 10, implicit-def $eflags
JCC_1 %bb.2, 15, implicit killed $eflags JCC_1 %bb.2, 15, implicit killed $eflags
bb.1.less: $eax = MOV32r0 implicit-def dead $eflags bb.1.less: $eax = MOV32r0 implicit-def dead $eflags
RETQ killed $eax RET64 killed $eax
bb.2.exit: liveins: $edi bb.2.exit: liveins: $edi
$eax = COPY killed $edi $eax = COPY killed $edi
RETQ killed $eax RET64 killed $eax
... ...

llvm/test/CodeGen/MIR/X86/null-register-operands.mir

Show All 10 Lines
... ...
--- ---
# CHECK: name: deref # CHECK: name: deref
name: deref name: deref
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: $eax = MOV32rm $rdi, 1, $noreg, 0, $noreg ; CHECK: $eax = MOV32rm $rdi, 1, $noreg, 0, $noreg
; CHECK-NEXT: RETQ $eax ; CHECK-NEXT: RET64 $eax
$eax = MOV32rm $rdi, 1, _, 0, $noreg $eax = MOV32rm $rdi, 1, _, 0, $noreg
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/register-mask-operands.mir

Show All 17 Lines--- |
attributes #0 = { "frame-pointer"="none" } attributes #0 = { "frame-pointer"="none" }
... ...
--- ---
name: compute name: compute
body: | body: |
bb.0.body: bb.0.body:
$eax = IMUL32rri8 $edi, 11, implicit-def $eflags $eax = IMUL32rri8 $edi, 11, implicit-def $eflags
RETQ $eax RET64 $eax
... ...
--- ---
# CHECK: name: foo # CHECK: name: foo
name: foo name: foo
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: PUSH64r $rax ; CHECK: PUSH64r $rax
; CHECK-NEXT: CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax ; CHECK-NEXT: CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax
PUSH64r $rax, implicit-def $rsp, implicit $rsp PUSH64r $rax, implicit-def $rsp, implicit $rsp
CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax
$rdx = POP64r implicit-def $rsp, implicit $rsp $rdx = POP64r implicit-def $rsp, implicit $rsp
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir

Show All 14 Lines
--- ---
name: inc name: inc
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: [[@LINE+1]]:42: register operands can't have target flags ; CHECK: [[@LINE+1]]:42: register operands can't have target flags
$rax = MOV64rm target-flags(x86-got) $rip, 1, _, @G, _ $rax = MOV64rm target-flags(x86-got) $rip, 1, _, @G, _
$eax = MOV32rm killed $rax, 1, _, 0, _ $eax = MOV32rm killed $rax, 1, _, 0, _
$eax = INC32r killed $eax, implicit-def dead $eflags $eax = INC32r killed $eax, implicit-def dead $eflags
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir

# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the 'renamable' register flags # This test ensures that the MIR parser parses the 'renamable' register flags
# correctly. # correctly.
--- | --- |
define void @foo() { ret void } define void @foo() { ret void }
... ...
--- ---
name: foo name: foo
body: | body: |
; CHECK: bb.0: ; CHECK: bb.0:
bb.0: bb.0:
; CHECK: renamable $eax = IMUL32rri8 $edi, 11, implicit-def dead $eflags ; CHECK: renamable $eax = IMUL32rri8 $edi, 11, implicit-def dead $eflags
renamable $eax = IMUL32rri8 $edi, 11, implicit-def dead $eflags renamable $eax = IMUL32rri8 $edi, 11, implicit-def dead $eflags
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/roundtrip.mir

# RUN: llc -o - %s -mtriple=x86_64-- -run-pass=none | llc -o - -x mir - -mtriple=x86_64-- -run-pass=none | FileCheck %s # RUN: llc -o - %s -mtriple=x86_64-- -run-pass=none | llc -o - -x mir - -mtriple=x86_64-- -run-pass=none | FileCheck %s
--- ---
# CHECK-LABEL: name: func0 # CHECK-LABEL: name: func0
# CHECK: registers: # CHECK: registers:
# CHECK: - { id: 0, class: gr32, preferred-register: '' } # CHECK: - { id: 0, class: gr32, preferred-register: '' }
# CHECK: - { id: 1, class: gr32, preferred-register: '' } # CHECK: - { id: 1, class: gr32, preferred-register: '' }
# CHECK: body: | # CHECK: body: |
# CHECK: bb.0: # CHECK: bb.0:
# CHECK: %0:gr32 = MOV32r0 implicit-def $eflags # CHECK: %0:gr32 = MOV32r0 implicit-def $eflags
# CHECK: dead %1:gr32 = COPY %0 # CHECK: dead %1:gr32 = COPY %0
# CHECK: MOV32mr undef $rcx, 1, $noreg, 0, $noreg, killed %0 :: (volatile store (s32)) # CHECK: MOV32mr undef $rcx, 1, $noreg, 0, $noreg, killed %0 :: (volatile store (s32))
# CHECK: RETQ undef $eax # CHECK: RET64 undef $eax
name: func0 name: func0
body: | body: |
bb.0: bb.0:
%0 : gr32 = MOV32r0 implicit-def $eflags %0 : gr32 = MOV32r0 implicit-def $eflags
dead %1 : gr32 = COPY %0 dead %1 : gr32 = COPY %0
MOV32mr undef $rcx, 1, _, 0, _, killed %0 :: (volatile store (s32)) MOV32mr undef $rcx, 1, _, 0, _, killed %0 :: (volatile store (s32))
RETQ undef $eax RET64 undef $eax
... ...

llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir

Show All 24 Lines
body: | body: |
bb.0.body: bb.0.body:
liveins: $edi, $esi liveins: $edi, $esi
%1 = COPY $esi %1 = COPY $esi
%2 = COPY $edi %2 = COPY $edi
%2 = IMUL32rr %2, %1, implicit-def dead $eflags %2 = IMUL32rr %2, %1, implicit-def dead $eflags
$eax = COPY %2 $eax = COPY %2
RETQ killed $eax RET64 killed $eax
... ...

llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir

Show All 20 LinesfixedStack:
# CHECK: [[@LINE+1]]:52: unknown key 'isAliased' # CHECK: [[@LINE+1]]:52: unknown key 'isAliased'
- { id: 0, type: spill-slot, offset: 0, size: 4, isAliased: true } - { id: 0, type: spill-slot, offset: 0, size: 4, isAliased: true }
stack: stack:
- { id: 0, offset: -12, size: 4, alignment: 4 } - { id: 0, offset: -12, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
MOV32mr %rsp, 1, _, -4, _, %edi MOV32mr %rsp, 1, _, -4, _, %edi
%eax = COPY %edi %eax = COPY %edi
RETQ %eax RET64 %eax
... ...

llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir

Show All 20 LinesfixedStack:
# CHECK: [[@LINE+1]]:52: unknown key 'isImmutable' # CHECK: [[@LINE+1]]:52: unknown key 'isImmutable'
- { id: 0, type: spill-slot, offset: 0, size: 4, isImmutable: true } - { id: 0, type: spill-slot, offset: 0, size: 4, isImmutable: true }
stack: stack:
- { id: 0, offset: -12, size: 4, alignment: 4 } - { id: 0, offset: -12, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
MOV32mr %rsp, 1, _, -4, _, %edi MOV32mr %rsp, 1, _, -4, _, %edi
%eax = COPY %edi %eax = COPY %edi
RETQ %eax RET64 %eax
... ...

llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir

Show All 24 Lines
fixedStack: fixedStack:
- { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 } - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 }
stack: stack:
- { id: 0, offset: -12, size: 4, alignment: 4 } - { id: 0, offset: -12, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
MOV32mr $rsp, 1, _, -4, _, $edi MOV32mr $rsp, 1, _, -4, _, $edi
$eax = COPY $edi $eax = COPY $edi
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir

Show All 18 LinesframeInfo:
maxAlignment: 4 maxAlignment: 4
stack: stack:
# CHECK: [[@LINE+1]]:20: alloca instruction named 'x' isn't defined in the function 'test' # CHECK: [[@LINE+1]]:20: alloca instruction named 'x' isn't defined in the function 'test'
- { id: 0, name: x, offset: -12, size: 4, alignment: 4 } - { id: 0, name: x, offset: -12, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
MOV32mr $rsp, 1, _, -4, _, $edi MOV32mr $rsp, 1, _, -4, _, $edi
$eax = MOV32rm $rsp, 1, _, -4, _ $eax = MOV32rm $rsp, 1, _, -4, _
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir

Show All 22 Lines
stack: stack:
- { id: 0, name: b, size: 4, alignment: 4 } - { id: 0, name: b, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
%0 = COPY $edi %0 = COPY $edi
; CHECK: [[@LINE+1]]:13: the name of the stack object '%stack.0' isn't 'x' ; CHECK: [[@LINE+1]]:13: the name of the stack object '%stack.0' isn't 'x'
MOV32mr %stack.0.x, 1, _, 0, _, %0 MOV32mr %stack.0.x, 1, _, 0, _, %0
$eax = COPY %0 $eax = COPY %0
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/stack-object-operands.mir

Show All 31 Lines
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test ; CHECK-LABEL: name: test
; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg
; CHECK: MOV32mr %stack.0.b, 1, $noreg, 0, $noreg, [[MOV32rm]] ; CHECK: MOV32mr %stack.0.b, 1, $noreg, 0, $noreg, [[MOV32rm]]
; CHECK: MOV32mi %stack.1, 1, $noreg, 0, $noreg, 2 ; CHECK: MOV32mi %stack.1, 1, $noreg, 0, $noreg, 2
; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.0.b, 1, $noreg, 0, $noreg ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.0.b, 1, $noreg, 0, $noreg
; CHECK: $eax = COPY [[MOV32rm1]] ; CHECK: $eax = COPY [[MOV32rm1]]
; CHECK: RETL $eax ; CHECK: RET32 $eax
%0 = MOV32rm %fixed-stack.0, 1, _, 0, _ %0 = MOV32rm %fixed-stack.0, 1, _, 0, _
MOV32mr %stack.0.b, 1, _, 0, _, %0 MOV32mr %stack.0.b, 1, _, 0, _, %0
MOV32mi %stack.1, 1, _, 0, _, 2 MOV32mi %stack.1, 1, _, 0, _, 2
%1 = MOV32rm %stack.0, 1, _, 0, _ %1 = MOV32rm %stack.0, 1, _, 0, _
$eax = COPY %1 $eax = COPY %1
RETL $eax RET32 $eax
... ...

llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir

Show All 27 Lines# CHECK: [[@LINE+1]]:11: redefinition of stack object '%stack.0'
- { id: 0, name: x, offset: -24, size: 8, alignment: 8 } - { id: 0, name: x, offset: -24, size: 8, alignment: 8 }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $edi liveins: $edi
MOV32mr $rsp, 1, _, -4, _, killed $edi MOV32mr $rsp, 1, _, -4, _, killed $edi
MOV64mi32 $rsp, 1, _, -16, _, 2 MOV64mi32 $rsp, 1, _, -16, _, 2
$eax = MOV32rm $rsp, 1, _, -4, _ $eax = MOV32rm $rsp, 1, _, -4, _
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/stack-objects.mir

Show All 33 Linesstack:
- { id: 0, name: b, offset: -12, size: 4, alignment: 4 } - { id: 0, name: b, offset: -12, size: 4, alignment: 4 }
- { id: 1, name: x, offset: -24, size: 8, alignment: 8 } - { id: 1, name: x, offset: -24, size: 8, alignment: 8 }
- { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 } - { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
MOV32mr $rsp, 1, _, -4, _, $edi MOV32mr $rsp, 1, _, -4, _, $edi
MOV64mi32 $rsp, 1, _, -16, _, 2 MOV64mi32 $rsp, 1, _, -16, _, 2
$eax = MOV32rm $rsp, 1, _, -4, _ $eax = MOV32rm $rsp, 1, _, -4, _
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/standalone-register-error.mir

Show All 13 Lines
# CHECK: [[@LINE+1]]:13: unknown register name 'register' # CHECK: [[@LINE+1]]:13: unknown register name 'register'
- { reg: '$register', virtual-reg: '%0' } - { reg: '$register', virtual-reg: '%0' }
body: | body: |
bb.0.body: bb.0.body:
liveins: $edi liveins: $edi
%0 = COPY $edi %0 = COPY $edi
$eax = COPY %0 $eax = COPY %0
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir

Show All 19 Lines
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $edi, $eax liveins: $edi, $eax
; CHECK-LABEL: name: t ; CHECK-LABEL: name: t
; CHECK: liveins: $edi, $eax ; CHECK: liveins: $edi, $eax
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG $edi, $al, %subreg.sub_8bit ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG $edi, $al, %subreg.sub_8bit
; CHECK: [[EXTRACT_SUBREG:%[0-9]+]]:gr8 = EXTRACT_SUBREG $eax, %subreg.sub_8bit_hi ; CHECK: [[EXTRACT_SUBREG:%[0-9]+]]:gr8 = EXTRACT_SUBREG $eax, %subreg.sub_8bit_hi
; CHECK: $ax = REG_SEQUENCE [[EXTRACT_SUBREG]], %subreg.sub_8bit, [[EXTRACT_SUBREG]], %subreg.sub_8bit_hi ; CHECK: $ax = REG_SEQUENCE [[EXTRACT_SUBREG]], %subreg.sub_8bit, [[EXTRACT_SUBREG]], %subreg.sub_8bit_hi
; CHECK: RETQ $ax ; CHECK: RET64 $ax
%0 = INSERT_SUBREG $edi, $al, %subreg.sub_8bit %0 = INSERT_SUBREG $edi, $al, %subreg.sub_8bit
%1 = EXTRACT_SUBREG $eax, %subreg.sub_8bit_hi %1 = EXTRACT_SUBREG $eax, %subreg.sub_8bit_hi
$ax = REG_SEQUENCE %1, %subreg.sub_8bit, %1, %subreg.sub_8bit_hi $ax = REG_SEQUENCE %1, %subreg.sub_8bit, %1, %subreg.sub_8bit_hi
RETQ $ax RET64 $ax
... ...

llvm/test/CodeGen/MIR/X86/subregister-operands.mir

Show All 21 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $edi liveins: $edi
; CHECK-LABEL: name: t ; CHECK-LABEL: name: t
; CHECK: liveins: $edi ; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; CHECK: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def $eflags ; CHECK: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def $eflags
; CHECK: $al = COPY [[AND8ri]] ; CHECK: $al = COPY [[AND8ri]]
; CHECK: RETQ $al ; CHECK: RET64 $al
%0 = COPY $edi %0 = COPY $edi
%1 = COPY %0.sub_8bit %1 = COPY %0.sub_8bit
%2 = AND8ri %1, 1, implicit-def $eflags %2 = AND8ri %1, 1, implicit-def $eflags
$al = COPY %2 $al = COPY %2
RETQ $al RET64 $al
... ...

llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir

Show All 26 Lines bb.0.entry:
successors: %bb.1 (33), %bb.2(67) successors: %bb.1 (33), %bb.2(67)
liveins: $edi liveins: $edi
CMP32ri8 $edi, 10, implicit-def $eflags CMP32ri8 $edi, 10, implicit-def $eflags
JCC_1 %bb.2, 15, implicit killed $eflags JCC_1 %bb.2, 15, implicit killed $eflags
bb.1.less: bb.1.less:
$eax = MOV32r0 implicit-def dead $eflags $eax = MOV32r0 implicit-def dead $eflags
RETQ killed $eax RET64 killed $eax
bb.2.exit: bb.2.exit:
liveins: $edi liveins: $edi
$eax = COPY killed $edi $eax = COPY killed $edi
RETQ killed $eax RET64 killed $eax
... ...

llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir

Show All 36 Lines bb.0.entry:
successors: %bb.1.less, %bb.2.exit successors: %bb.1.less, %bb.2.exit
liveins: $edi liveins: $edi
CMP32ri8 $edi, 10, implicit-def $eflags CMP32ri8 $edi, 10, implicit-def $eflags
JCC_1 %bb.2.exit, 15, implicit killed $eflags JCC_1 %bb.2.exit, 15, implicit killed $eflags
bb.1.less: bb.1.less:
$eax = MOV32r0 implicit-def dead $eflags $eax = MOV32r0 implicit-def dead $eflags
RETQ killed $eax RET64 killed $eax
bb.2.exit: bb.2.exit:
liveins: $edi liveins: $edi
$eax = COPY killed $edi $eax = COPY killed $edi
RETQ killed $eax RET64 killed $eax
... ...
--- ---
name: bar name: bar
body: | body: |
; CHECK-LABEL: name: bar ; CHECK-LABEL: name: bar
; Verify that we can have multiple lists of successors that will be merged ; Verify that we can have multiple lists of successors that will be merged
; into one. ; into one.
; CHECK-LABEL: bb.0.entry: ; CHECK-LABEL: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000), %bb.2(0x00000000) ; CHECK: successors: %bb.1(0x80000000), %bb.2(0x00000000)
bb.0.entry: bb.0.entry:
liveins: $edi liveins: $edi
successors: %bb.1 successors: %bb.1
successors: %bb.2 successors: %bb.2
CMP32ri8 $edi, 10, implicit-def $eflags CMP32ri8 $edi, 10, implicit-def $eflags
JCC_1 %bb.2, 15, implicit killed $eflags JCC_1 %bb.2, 15, implicit killed $eflags
; Verify that we can have an empty list of successors. ; Verify that we can have an empty list of successors.
; CHECK-LABEL: bb.1: ; CHECK-LABEL: bb.1:
; CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags ; CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags
bb.1: bb.1:
successors: successors:
$eax = MOV32r0 implicit-def dead $eflags $eax = MOV32r0 implicit-def dead $eflags
RETQ killed $eax RET64 killed $eax
bb.2: bb.2:
liveins: $edi liveins: $edi
$eax = COPY killed $edi $eax = COPY killed $edi
RETQ killed $eax RET64 killed $eax
... ...

llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir

Show All 14 Linesliveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: [[@LINE+1]]:58: use of invalid tied-def operand index '0'; the operand #0 isn't a defined register ; CHECK: [[@LINE+1]]:58: use of invalid tied-def operand index '0'; the operand #0 isn't a defined register
INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(tied-def 0) INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(tied-def 0)
$rax = COPY killed $rdi $rax = COPY killed $rdi
RETQ killed $rax RET64 killed $rax
... ...

llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir

Show All 12 Lines
--- ---
name: foo name: foo
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: Tied physical registers must match. ; CHECK: Tied physical registers must match.
$rbx = AND64rm killed $rdx, killed $rdi, 1, _, 0, _, implicit-def dead $eflags $rbx = AND64rm killed $rdx, killed $rdi, 1, _, 0, _, implicit-def dead $eflags
RETQ $rbx RET64 $rbx
... ...

llvm/test/CodeGen/MIR/X86/undef-register-flag.mir

Show All 18 Lines--- |
attributes #0 = { "frame-pointer"="none" } attributes #0 = { "frame-pointer"="none" }
... ...
--- ---
name: compute name: compute
body: | body: |
bb.0.body: bb.0.body:
$eax = IMUL32rri8 $edi, 11, implicit-def $eflags $eax = IMUL32rri8 $edi, 11, implicit-def $eflags
RETQ $eax RET64 $eax
... ...
--- ---
name: foo name: foo
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: PUSH64r undef $rax ; CHECK: PUSH64r undef $rax
PUSH64r undef $rax, implicit-def $rsp, implicit $rsp PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax
$rdx = POP64r implicit-def $rsp, implicit $rsp $rdx = POP64r implicit-def $rsp, implicit $rsp
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir

Show All 27 Lines
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: [[@LINE+1]]:18: use of undefined fixed stack object '%fixed-stack.11' ; CHECK: [[@LINE+1]]:18: use of undefined fixed stack object '%fixed-stack.11'
%0 = MOV32rm %fixed-stack.11, 1, _, 0, _ %0 = MOV32rm %fixed-stack.11, 1, _, 0, _
MOV32mr %stack.0, 1, _, 0, _, %0 MOV32mr %stack.0, 1, _, 0, _, %0
MOV32mi %stack.1, 1, _, 0, _, 2 MOV32mi %stack.1, 1, _, 0, _, 2
%1 = MOV32rm %stack.0, 1, _, 0, _ %1 = MOV32rm %stack.0, 1, _, 0, _
$eax = COPY %1 $eax = COPY %1
RETL $eax RET32 $eax
... ...

llvm/test/CodeGen/MIR/X86/undefined-global-value.mir

Show All 16 Lines
--- ---
name: inc name: inc
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: [[@LINE+1]]:32: use of undefined global value '@2' ; CHECK: [[@LINE+1]]:32: use of undefined global value '@2'
$rax = MOV64rm $rip, 1, _, @2, _ $rax = MOV64rm $rip, 1, _, @2, _
$eax = MOV32rm $rax, 1, _, 0, _ $eax = MOV32rm $rax, 1, _, 0, _
$eax = INC32r $eax $eax = INC32r $eax
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir

Show All 20 Linesbody: |
bb.0.entry: bb.0.entry:
successors: %bb.1.block successors: %bb.1.block
; CHECK: [[@LINE+1]]:51: use of undefined IR block '%ir-block."block "' ; CHECK: [[@LINE+1]]:51: use of undefined IR block '%ir-block."block "'
$rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block."block "), _ $rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block."block "), _
MOV64mr $rip, 1, _, @addr, _, killed $rax MOV64mr $rip, 1, _, @addr, _, killed $rax
JMP64m $rip, 1, _, @addr, _ JMP64m $rip, 1, _, @addr, _
bb.1.block (address-taken): bb.1.block (address-taken):
RETQ RET64
... ...

llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir

Show All 19 Linesbody: |
bb.0.entry: bb.0.entry:
successors: %bb.1 successors: %bb.1
; CHECK: [[@LINE+1]]:51: use of undefined IR block '%ir-block.1' ; CHECK: [[@LINE+1]]:51: use of undefined IR block '%ir-block.1'
$rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block.1), _ $rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block.1), _
MOV64mr $rip, 1, _, @addr, _, killed $rax MOV64mr $rip, 1, _, @addr, _, killed $rax
JMP64m $rip, 1, _, @addr, _ JMP64m $rip, 1, _, @addr, _
bb.1 (address-taken): bb.1 (address-taken):
RETQ RET64
... ...

llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines bb.1.entry:
; CHECK: [[@LINE+1]]:31: use of undefined jump table '%jump-table.2' ; CHECK: [[@LINE+1]]:31: use of undefined jump table '%jump-table.2'
$rcx = LEA64r $rip, 1, _, %jump-table.2, _ $rcx = LEA64r $rip, 1, _, %jump-table.2, _
$rax = MOVSX64rm32 $rcx, 4, $rax, 0, _ $rax = MOVSX64rm32 $rcx, 4, $rax, 0, _
$rax = ADD64rr $rax, $rcx, implicit-def $eflags $rax = ADD64rr $rax, $rcx, implicit-def $eflags
JMP64r $rax JMP64r $rax
bb.2.def: bb.2.def:
$eax = MOV32r0 implicit-def $eflags $eax = MOV32r0 implicit-def $eflags
RETQ $eax RET64 $eax
bb.3.lbl1: bb.3.lbl1:
$eax = MOV32ri 1 $eax = MOV32ri 1
RETQ $eax RET64 $eax
bb.4.lbl2: bb.4.lbl2:
$eax = MOV32ri 2 $eax = MOV32ri 2
RETQ $eax RET64 $eax
bb.5.lbl3: bb.5.lbl3:
$eax = MOV32ri 4 $eax = MOV32ri 4
RETQ $eax RET64 $eax
bb.6.lbl4: bb.6.lbl4:
$eax = MOV32ri 8 $eax = MOV32ri 8
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir

Show All 16 Lines
--- ---
name: inc name: inc
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: [[@LINE+1]]:32: use of undefined global value '@GG' ; CHECK: [[@LINE+1]]:32: use of undefined global value '@GG'
$rax = MOV64rm $rip, 1, _, @GG, _ $rax = MOV64rm $rip, 1, _, @GG, _
$eax = MOV32rm $rax, 1, _, 0, _ $eax = MOV32rm $rax, 1, _, 0, _
$eax = INC32r $eax $eax = INC32r $eax
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/undefined-register-class.mir

Show All 12 Lines
--- ---
name: test name: test
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
# CHECK: [[@LINE+1]]:20: use of undefined register class or register bank 'gr3200' # CHECK: [[@LINE+1]]:20: use of undefined register class or register bank 'gr3200'
- {id: 0, class: 'gr3200'} - {id: 0, class: 'gr3200'}
body: | body: |
bb.0.entry: bb.0.entry:
RETQ %eax RET64 %eax
... ...

llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir

Show All 19 Lines
stack: stack:
- { id: 0, name: b, size: 4, alignment: 4 } - { id: 0, name: b, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
%0 = COPY $edi %0 = COPY $edi
; CHECK: [[@LINE+1]]:13: use of undefined stack object '%stack.2' ; CHECK: [[@LINE+1]]:13: use of undefined stack object '%stack.2'
MOV32mr %stack.2, 1, _, 0, _, %0 MOV32mr %stack.2, 1, _, 0, _, %0
$eax = COPY %0 $eax = COPY %0
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir

Show All 13 Lines
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: [[@LINE+1]]:64: use of undefined IR value '%ir.c' ; CHECK: [[@LINE+1]]:64: use of undefined IR value '%ir.c'
$eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load (s32) from %ir.c) $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load (s32) from %ir.c)
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir

Show All 14 Lines
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gr32 } - { id: 0, class: gr32 }
body: | body: |
bb.0.entry: bb.0.entry:
%0 = COPY $edi %0 = COPY $edi
; CHECK: Cannot determine class/bank of virtual register 1 in function 'test' ; CHECK: Cannot determine class/bank of virtual register 1 in function 'test'
$eax = COPY %1 $eax = COPY %1
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir

Show All 26 Lines bb.0.entry:
CMP32ri8 $eax, 10, implicit-def $eflags CMP32ri8 $eax, 10, implicit-def $eflags
; CHECK: [[@LINE+1]]:11: use of undefined machine basic block #4 ; CHECK: [[@LINE+1]]:11: use of undefined machine basic block #4
JCC_1 %bb.4, 15, implicit $eflags JCC_1 %bb.4, 15, implicit $eflags
bb.1: bb.1:
$eax = MOV32r0 implicit-def $eflags $eax = MOV32r0 implicit-def $eflags
bb.2: bb.2:
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir

Show All 15 Linesliveins:
- { reg: '$rdi' } - { reg: '$rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rdi liveins: $rdi
; CHECK: [[@LINE+1]]:64: use of unknown metadata keyword '!tba' ; CHECK: [[@LINE+1]]:64: use of unknown metadata keyword '!tba'
$eax = MOV32rm $rdi, 1, _, 0, _ :: (load (s32) from %ir.x, !tba !0) $eax = MOV32rm $rdi, 1, _, 0, _ :: (load (s32) from %ir.x, !tba !0)
$eax = INC32r killed $eax, implicit-def dead $eflags $eax = INC32r killed $eax, implicit-def dead $eflags
MOV32mr killed $rdi, 1, _, 0, _, $eax :: (store (s32) into %ir.x) MOV32mr killed $rdi, 1, _, 0, _, $eax :: (store (s32) into %ir.x)
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Linesstack:
- { id: 0, name: x.addr, size: 4, alignment: 4 } - { id: 0, name: x.addr, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
%0 = COPY $edi %0 = COPY $edi
; CHECK: [[@LINE+1]]:21: use of undefined metadata '!42' ; CHECK: [[@LINE+1]]:21: use of undefined metadata '!42'
DBG_VALUE _, 0, !42, !13 DBG_VALUE _, 0, !42, !13
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
$eax = COPY %0 $eax = COPY %0
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir

Show All 25 Lines bb.0.entry:
CMP32ri8 $eax, 10, implicit-def $eflags CMP32ri8 $eax, 10, implicit-def $eflags
; CHECK: [[@LINE+1]]:11: the name of machine basic block #2 isn't 'hit' ; CHECK: [[@LINE+1]]:11: the name of machine basic block #2 isn't 'hit'
JCC_1 %bb.2.hit, 15, implicit $eflags JCC_1 %bb.2.hit, 15, implicit $eflags
bb.1.less: bb.1.less:
$eax = MOV32r0 implicit-def $eflags $eax = MOV32r0 implicit-def $eflags
bb.2.exit: bb.2.exit:
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/unknown-register.mir

Show All 10 Lines
... ...
--- ---
name: foo name: foo
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: [[@LINE+1]]:5: unknown register name 'xax' ; CHECK: [[@LINE+1]]:5: unknown register name 'xax'
$xax = MOV32r0 $xax = MOV32r0
RETQ $xax RET64 $xax
... ...

llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir

Show All 15 Lines
registers: registers:
- { id: 0, class: gr32 } - { id: 0, class: gr32 }
- { id: 1, class: gr8 } - { id: 1, class: gr8 }
- { id: 2, class: gr8 } - { id: 2, class: gr8 }
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: [[@LINE+1]]:35: unknown subregister index 'bit8' ; CHECK: [[@LINE+1]]:35: unknown subregister index 'bit8'
%0 = INSERT_SUBREG $edi, $al, %subreg.bit8 %0 = INSERT_SUBREG $edi, $al, %subreg.bit8
RETQ %0 RET64 %0
... ...

llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir

Show All 18 Linesregisters:
- { id: 2, class: gr8 } - { id: 2, class: gr8 }
body: | body: |
bb.0.entry: bb.0.entry:
%0 = COPY $edi %0 = COPY $edi
; CHECK: [[@LINE+1]]:18: use of unknown subregister index 'bit8' ; CHECK: [[@LINE+1]]:18: use of unknown subregister index 'bit8'
%1 = COPY %0.bit8 %1 = COPY %0.bit8
%2 = AND8ri %1, 1, implicit-def $eflags %2 = AND8ri %1, 1, implicit-def $eflags
$al = COPY %2 $al = COPY %2
RETQ $al RET64 $al
... ...

llvm/test/CodeGen/MIR/X86/unrecognized-character.mir

# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- | --- |
define void @foo() { define void @foo() {
entry: entry:
ret void ret void
} }
... ...
--- ---
name: foo name: foo
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: [[@LINE+1]]:5: unexpected character '\' ; CHECK: [[@LINE+1]]:5: unexpected character '\'
\ RETQ \ RET64
... ...

llvm/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir

Show All 24 Linesstack:
- { id: 1, offset: -32, size: 8, alignment: 8 } - { id: 1, offset: -32, size: 8, alignment: 8 }
# CHECK: [[@LINE+1]]:49: unknown key 'size' # CHECK: [[@LINE+1]]:49: unknown key 'size'
- { id: 2, type: variable-sized, offset: -32, size: 42, alignment: 1 } - { id: 2, type: variable-sized, offset: -32, size: 42, alignment: 1 }
body: | body: |
bb.0.entry: bb.0.entry:
MOV32mr %rsp, 1, _, -4, _, %edi MOV32mr %rsp, 1, _, -4, _, %edi
MOV64mi32 %rsp, 1, _, -16, _, 2 MOV64mi32 %rsp, 1, _, -16, _, 2
%eax = MOV32rm %rsp, 1, _, -4, _ %eax = MOV32rm %rsp, 1, _, -4, _
RETQ %eax RET64 %eax
... ...

llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir

Show All 34 Linesstack:
- { id: 0, offset: -20, size: 4, alignment: 4 } - { id: 0, offset: -20, size: 4, alignment: 4 }
- { id: 1, offset: -32, size: 8, alignment: 8 } - { id: 1, offset: -32, size: 8, alignment: 8 }
- { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1 } - { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1 }
body: | body: |
bb.0.entry: bb.0.entry:
MOV32mr $rsp, 1, _, -4, _, $edi MOV32mr $rsp, 1, _, -4, _, $edi
MOV64mi32 $rsp, 1, _, -16, _, 2 MOV64mi32 $rsp, 1, _, -16, _, 2
$eax = MOV32rm $rsp, 1, _, -4, _ $eax = MOV32rm $rsp, 1, _, -4, _
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir

Show All 15 Lines
# CHECK: [[@LINE+1]]:11: redefinition of virtual register '%0' # CHECK: [[@LINE+1]]:11: redefinition of virtual register '%0'
- { id: 0, class: gr32 } - { id: 0, class: gr32 }
body: | body: |
bb.0.body: bb.0.body:
liveins: %edi liveins: %edi
%0 = COPY %edi %0 = COPY %edi
%eax = COPY %0 %eax = COPY %0
RETQ %eax RET64 %eax
... ...

llvm/test/CodeGen/MIR/X86/virtual-registers.mir

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines bb.0.entry:
JCC_1 %bb.2.exit, 15, implicit $eflags JCC_1 %bb.2.exit, 15, implicit $eflags
JMP_1 %bb.1.less JMP_1 %bb.1.less
bb.1.less: bb.1.less:
; CHECK: %2:gr32 = MOV32r0 ; CHECK: %2:gr32 = MOV32r0
; CHECK-NEXT: $eax = COPY %2 ; CHECK-NEXT: $eax = COPY %2
%2 = MOV32r0 implicit-def $eflags %2 = MOV32r0 implicit-def $eflags
$eax = COPY %2 $eax = COPY %2
RETQ $eax RET64 $eax
bb.2.exit: bb.2.exit:
$eax = COPY %0 $eax = COPY %0
RETQ $eax RET64 $eax
... ...
--- ---
name: foo name: foo
tracksRegLiveness: true tracksRegLiveness: true
# CHECK: name: foo # CHECK: name: foo
# CHECK: registers: # CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } # CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } # CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
Show All 13 Lines bb.0.entry:
JCC_1 %bb.2.exit, 15, implicit $eflags JCC_1 %bb.2.exit, 15, implicit $eflags
JMP_1 %bb.1.less JMP_1 %bb.1.less
bb.1.less: bb.1.less:
; CHECK: %2:gr32 = MOV32r0 ; CHECK: %2:gr32 = MOV32r0
; CHECK-NEXT: $eax = COPY %2 ; CHECK-NEXT: $eax = COPY %2
%10 = MOV32r0 implicit-def $eflags %10 = MOV32r0 implicit-def $eflags
$eax = COPY %10 $eax = COPY %10
RETQ $eax RET64 $eax
bb.2.exit: bb.2.exit:
; CHECK: $eax = COPY %0 ; CHECK: $eax = COPY %0
$eax = COPY %2 $eax = COPY %2
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/X86/basic-block-sections-mir-parse.mir

Show First 20 Lines • Show All 112 Lines • ▼ Show 20 Lines bb.2 (%ir-block.8, bbsections 2):
MOV32mi $rbp, 1, $noreg, -8, $noreg, 0 :: (store (s32) into %ir.2) MOV32mi $rbp, 1, $noreg, -8, $noreg, 0 :: (store (s32) into %ir.2)
JMP_1 %bb.3 JMP_1 %bb.3
bb.3 (%ir-block.9, bbsections 3): bb.3 (%ir-block.9, bbsections 3):
renamable $eax = MOV32rm $rbp, 1, $noreg, -8, $noreg :: (load (s32) from %ir.2) renamable $eax = MOV32rm $rbp, 1, $noreg, -8, $noreg :: (load (s32) from %ir.2)
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa $rsp, 8 CFI_INSTRUCTION def_cfa $rsp, 8
RETQ implicit $eax RET64 implicit $eax
... ...
# CHECK: .section .text._Z3foob,"ax",@progbits # CHECK: .section .text._Z3foob,"ax",@progbits
# CHECK: _Z3foob: # CHECK: _Z3foob:
# CHECK: .section .text._Z3foob,"ax",@progbits,unique # CHECK: .section .text._Z3foob,"ax",@progbits,unique
# CHECK: _Z3foob.__part.1: # CHECK: _Z3foob.__part.1:
# CHECK: .section .text._Z3foob,"ax",@progbits,unique # CHECK: .section .text._Z3foob,"ax",@progbits,unique
# CHECK: _Z3foob.__part.2: # CHECK: _Z3foob.__part.2:
# CHECK: .section .text._Z3foob,"ax",@progbits,unique # CHECK: .section .text._Z3foob,"ax",@progbits,unique
# CHECK: _Z3foob.__part.3: # CHECK: _Z3foob.__part.3:

llvm/test/CodeGen/X86/block-placement.mir

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines bb.1.left:
$eax = FAULTING_OP 1, %bb.2, 1684, killed $rdi, 1, $noreg, 0, $noreg :: (load (s32) from %ir.ptr) $eax = FAULTING_OP 1, %bb.2, 1684, killed $rdi, 1, $noreg, 0, $noreg :: (load (s32) from %ir.ptr)
JMP_1 %bb.4 JMP_1 %bb.4
bb.4.not_null: bb.4.not_null:
liveins: $rdi, $eax liveins: $rdi, $eax
$rcx = POP64r implicit-def $rsp, implicit $rsp $rcx = POP64r implicit-def $rsp, implicit $rsp
RETQ $eax RET64 $eax
bb.2.null: bb.2.null:
liveins: $rdi liveins: $rdi
CALL64pcrel32 @stub, csr_64, implicit $rsp, implicit $rdi, implicit-def $rsp CALL64pcrel32 @stub, csr_64, implicit $rsp, implicit $rdi, implicit-def $rsp
bb.3.right: bb.3.right:
dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi
CALL64pcrel32 @stub, csr_64, implicit $rsp, implicit $rdi, implicit-def $rsp CALL64pcrel32 @stub, csr_64, implicit $rsp, implicit $rdi, implicit-def $rsp
... ...

llvm/test/CodeGen/X86/bug47278.mir

Show All 18 Lines bb.0:
; CHECK: dead renamable $ecx = COPY renamable $edx ; CHECK: dead renamable $ecx = COPY renamable $edx
; CHECK: renamable $esi = IMPLICIT_DEF ; CHECK: renamable $esi = IMPLICIT_DEF
; CHECK: renamable $ecx = IMPLICIT_DEF ; CHECK: renamable $ecx = IMPLICIT_DEF
; CHECK: renamable $ecx = CMOV32rr renamable $ecx, killed renamable $esi, 2, implicit undef $eflags ; CHECK: renamable $ecx = CMOV32rr renamable $ecx, killed renamable $esi, 2, implicit undef $eflags
; CHECK: renamable $cl = MOV8ri -128 ; CHECK: renamable $cl = MOV8ri -128
; CHECK: $cl = IMPLICIT_DEF ; CHECK: $cl = IMPLICIT_DEF
; CHECK: renamable $eax = COPY renamable $edx ; CHECK: renamable $eax = COPY renamable $edx
; CHECK: dead renamable $eax = SHRD32rrCL renamable $eax, killed renamable $edx, implicit-def dead $eflags, implicit killed $cl ; CHECK: dead renamable $eax = SHRD32rrCL renamable $eax, killed renamable $edx, implicit-def dead $eflags, implicit killed $cl
; CHECK: RETL ; CHECK: RET32
%0:gr32 = IMPLICIT_DEF %0:gr32 = IMPLICIT_DEF
%1:gr32 = MOVZX32rm8 %0, 1, $noreg, 0, $noreg :: (load (s8) from `i168* undef` + 20, align 4, basealign 16) %1:gr32 = MOVZX32rm8 %0, 1, $noreg, 0, $noreg :: (load (s8) from `i168* undef` + 20, align 4, basealign 16)
%2:gr32 = MOV32rm %0, 1, $noreg, 0, $noreg :: (load (s32) from `i168* undef` + 12, basealign 16) %2:gr32 = MOV32rm %0, 1, $noreg, 0, $noreg :: (load (s32) from `i168* undef` + 12, basealign 16)
%3:gr8 = MOV8rm %0, 1, $noreg, 0, $noreg :: (load (s8) from `i32* undef`, align 4) %3:gr8 = MOV8rm %0, 1, $noreg, 0, $noreg :: (load (s8) from `i32* undef`, align 4)
%4:gr32 = COPY %1 %4:gr32 = COPY %1
%5:gr32 = COPY %1 %5:gr32 = COPY %1
%6:gr32 = COPY %1 %6:gr32 = COPY %1
%7:gr32 = IMPLICIT_DEF %7:gr32 = IMPLICIT_DEF
%8:gr32 = IMPLICIT_DEF %8:gr32 = IMPLICIT_DEF
%8:gr32 = CMOV32rr %8, killed %7, 2, implicit undef $eflags %8:gr32 = CMOV32rr %8, killed %7, 2, implicit undef $eflags
%9:gr8 = MOV8ri -128 %9:gr8 = MOV8ri -128
%9:gr8 = COPY %3 %9:gr8 = COPY %3
$cl = IMPLICIT_DEF $cl = IMPLICIT_DEF
%8:gr32 = COPY %1 %8:gr32 = COPY %1
%8:gr32 = SHRD32rrCL %8, %1, implicit-def dead $eflags, implicit $cl %8:gr32 = SHRD32rrCL %8, %1, implicit-def dead $eflags, implicit $cl
RETL RET32
... ...

llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding2.mir

Show First 20 Lines • Show All 103 Lines • ▼ Show 20 Lines bb.1.for.cond.cleanup:
JCC_1 %bb.3, 6, implicit $eflags JCC_1 %bb.3, 6, implicit $eflags
bb.2: bb.2:
successors: %bb.3 successors: %bb.3
liveins: $ebp, $ebx, $edx, $esi, $rdi, $r8d, $r9d, $r10d, $r11d, $r12d, $r13d, $r14d, $r15d liveins: $ebp, $ebx, $edx, $esi, $rdi, $r8d, $r9d, $r10d, $r11d, $r12d, $r13d, $r14d, $r15d
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
liveins: $rdi, $xmm3, $xmm4, $xmm5, $xmm6, $xmm7, $xmm9, $xmm13, $xmm14 liveins: $rdi, $xmm3, $xmm4, $xmm5, $xmm6, $xmm7, $xmm9, $xmm13, $xmm14
RETQ RET64
bb.4.for.body: bb.4.for.body:
successors: %bb.1, %bb.5 successors: %bb.1, %bb.5
liveins: $al, $rdi liveins: $al, $rdi
renamable $ecx = XOR32rr undef $ecx, undef $ecx, implicit-def dead $eflags renamable $ecx = XOR32rr undef $ecx, undef $ecx, implicit-def dead $eflags
TEST8rr killed renamable $al, renamable $al, implicit-def $eflags TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
JCC_1 %bb.1, 5, implicit $eflags JCC_1 %bb.1, 5, implicit $eflags
▲ Show 20 Lines • Show All 93 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/dbg-value-superreg-copy.mir

Show All 38 Linesbody: |
bb.1: bb.1:
DBG_VALUE %0.sub_8bit_hi, $noreg, !7, !DIExpression(), debug-location !9 DBG_VALUE %0.sub_8bit_hi, $noreg, !7, !DIExpression(), debug-location !9
%1:gr16 = COPY %0 %1:gr16 = COPY %0
%2:gr16 = COPY %0 %2:gr16 = COPY %0
bb.2: bb.2:
$ax = COPY %1 $ax = COPY %1
$dx = COPY %2 $dx = COPY %2
RETQ killed $ax, killed $dx RET64 killed $ax, killed $dx
... ...
# This test case was created as a reproducer for a bug when we got incorrect # This test case was created as a reproducer for a bug when we got incorrect
# DBG_VALUE instructions after regalloc like this: # DBG_VALUE instructions after regalloc like this:
# #
# movw $1, %cx # movw $1, %cx
# #DEBUG_VALUE: foo:zzz <- $ch # #DEBUG_VALUE: foo:zzz <- $ch
# movl %ecx, %eax # movl %ecx, %eax
Show All 12 Lines

llvm/test/CodeGen/X86/evex-to-vex-compress.mir

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 908 Lines • ▼ Show 20 Linesbody: |
$ymm0 = VSHUFI32X4Z256rmi $ymm0, $rip, 1, $noreg, 0, $noreg, 228 $ymm0 = VSHUFI32X4Z256rmi $ymm0, $rip, 1, $noreg, 0, $noreg, 228
; CHECK: $ymm0 = VPERM2I128rr $ymm0, $ymm1, 32 ; CHECK: $ymm0 = VPERM2I128rr $ymm0, $ymm1, 32
$ymm0 = VSHUFI32X4Z256rri $ymm0, $ymm1, 228 $ymm0 = VSHUFI32X4Z256rri $ymm0, $ymm1, 228
; CHECK: $ymm0 = VPERM2I128rm $ymm0, $rip, 1, $noreg, 0, $noreg, 32 ; CHECK: $ymm0 = VPERM2I128rm $ymm0, $rip, 1, $noreg, 0, $noreg, 32
$ymm0 = VSHUFI64X2Z256rmi $ymm0, $rip, 1, $noreg, 0, $noreg, 228 $ymm0 = VSHUFI64X2Z256rmi $ymm0, $rip, 1, $noreg, 0, $noreg, 228
; CHECK: $ymm0 = VPERM2I128rr $ymm0, $ymm1, 32 ; CHECK: $ymm0 = VPERM2I128rr $ymm0, $ymm1, 32
$ymm0 = VSHUFI64X2Z256rri $ymm0, $ymm1, 228 $ymm0 = VSHUFI64X2Z256rri $ymm0, $ymm1, 228
RETQ RET64
... ...
--- ---
# CHECK-LABEL: name: evex_z128_to_vex_test # CHECK-LABEL: name: evex_z128_to_vex_test
# CHECK: bb.0: # CHECK: bb.0:
name: evex_z128_to_vex_test name: evex_z128_to_vex_test
body: | body: |
bb.0: bb.0:
▲ Show 20 Lines • Show All 869 Lines • ▼ Show 20 Linesbody: |
$xmm0 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr $xmm0 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
; CHECK: $xmm0 = VROUNDPDr $xmm0, 15, implicit $mxcsr ; CHECK: $xmm0 = VROUNDPDr $xmm0, 15, implicit $mxcsr
$xmm0 = VRNDSCALEPDZ128rri $xmm0, 15, implicit $mxcsr $xmm0 = VRNDSCALEPDZ128rri $xmm0, 15, implicit $mxcsr
; CHECK: $xmm0 = VROUNDPSm $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr ; CHECK: $xmm0 = VROUNDPSm $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm0 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr $xmm0 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
; CHECK: $xmm0 = VROUNDPSr $xmm0, 15, implicit $mxcsr ; CHECK: $xmm0 = VROUNDPSr $xmm0, 15, implicit $mxcsr
$xmm0 = VRNDSCALEPSZ128rri $xmm0, 15, implicit $mxcsr $xmm0 = VRNDSCALEPSZ128rri $xmm0, 15, implicit $mxcsr
RETQ RET64
... ...
--- ---
# CHECK-LABEL: name: evex_scalar_to_vex_test # CHECK-LABEL: name: evex_scalar_to_vex_test
# CHECK: bb.0: # CHECK: bb.0:
name: evex_scalar_to_vex_test name: evex_scalar_to_vex_test
body: | body: |
bb.0: bb.0:
▲ Show 20 Lines • Show All 554 Lines • ▼ Show 20 Linesbody: |
$xmm0 = VRNDSCALESDZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr $xmm0 = VRNDSCALESDZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
; CHECK: $xmm0 = VROUNDSDr_Int $xmm0, $xmm1, 15, implicit $mxcsr ; CHECK: $xmm0 = VROUNDSDr_Int $xmm0, $xmm1, 15, implicit $mxcsr
$xmm0 = VRNDSCALESDZr_Int $xmm0, $xmm1, 15, implicit $mxcsr $xmm0 = VRNDSCALESDZr_Int $xmm0, $xmm1, 15, implicit $mxcsr
; CHECK: $xmm0 = VROUNDSSm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr ; CHECK: $xmm0 = VROUNDSSm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
$xmm0 = VRNDSCALESSZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr $xmm0 = VRNDSCALESSZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
; CHECK: $xmm0 = VROUNDSSr_Int $xmm0, $xmm1, 15, implicit $mxcsr ; CHECK: $xmm0 = VROUNDSSr_Int $xmm0, $xmm1, 15, implicit $mxcsr
$xmm0 = VRNDSCALESSZr_Int $xmm0, $xmm1, 15, implicit $mxcsr $xmm0 = VRNDSCALESSZr_Int $xmm0, $xmm1, 15, implicit $mxcsr
RETQ RET64
... ...
--- ---
# CHECK-LABEL: name: evex_z256_to_evex_test # CHECK-LABEL: name: evex_z256_to_evex_test
# CHECK: bb.0: # CHECK: bb.0:
name: evex_z256_to_evex_test name: evex_z256_to_evex_test
body: | body: |
bb.0: bb.0:
▲ Show 20 Lines • Show All 897 Lines • ▼ Show 20 Linesbody: |
$ymm16 = VSHUFI32X4Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 228 $ymm16 = VSHUFI32X4Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 228
; CHECK: $ymm16 = VSHUFI32X4Z256rri $ymm16, $ymm1, 228 ; CHECK: $ymm16 = VSHUFI32X4Z256rri $ymm16, $ymm1, 228
$ymm16 = VSHUFI32X4Z256rri $ymm16, $ymm1, 228 $ymm16 = VSHUFI32X4Z256rri $ymm16, $ymm1, 228
; CHECK: $ymm16 = VSHUFI64X2Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 228 ; CHECK: $ymm16 = VSHUFI64X2Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 228
$ymm16 = VSHUFI64X2Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 228 $ymm16 = VSHUFI64X2Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 228
; CHECK: $ymm16 = VSHUFI64X2Z256rri $ymm16, $ymm1, 228 ; CHECK: $ymm16 = VSHUFI64X2Z256rri $ymm16, $ymm1, 228
$ymm16 = VSHUFI64X2Z256rri $ymm16, $ymm1, 228 $ymm16 = VSHUFI64X2Z256rri $ymm16, $ymm1, 228
RETQ RET64
... ...
--- ---
# CHECK-LABEL: name: evex_z128_to_evex_test # CHECK-LABEL: name: evex_z128_to_evex_test
# CHECK: bb.0: # CHECK: bb.0:
name: evex_z128_to_evex_test name: evex_z128_to_evex_test
body: | body: |
bb.0: bb.0:
▲ Show 20 Lines • Show All 877 Lines • ▼ Show 20 Linesbody: |
$xmm0 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr $xmm0 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALEPDZ128rri $xmm0, 31, implicit $mxcsr ; CHECK: $xmm0 = VRNDSCALEPDZ128rri $xmm0, 31, implicit $mxcsr
$xmm0 = VRNDSCALEPDZ128rri $xmm0, 31, implicit $mxcsr $xmm0 = VRNDSCALEPDZ128rri $xmm0, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr ; CHECK: $xmm0 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
$xmm0 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr $xmm0 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALEPSZ128rri $xmm0, 31, implicit $mxcsr ; CHECK: $xmm0 = VRNDSCALEPSZ128rri $xmm0, 31, implicit $mxcsr
$xmm0 = VRNDSCALEPSZ128rri $xmm0, 31, implicit $mxcsr $xmm0 = VRNDSCALEPSZ128rri $xmm0, 31, implicit $mxcsr
RETQ RET64
... ...
--- ---
# CHECK-LABEL: name: evex_scalar_to_evex_test # CHECK-LABEL: name: evex_scalar_to_evex_test
# CHECK: bb.0: # CHECK: bb.0:
name: evex_scalar_to_evex_test name: evex_scalar_to_evex_test
body: | body: |
bb.0: bb.0:
▲ Show 20 Lines • Show All 565 Lines • ▼ Show 20 Linesbody: |
$xmm0 = VRNDSCALESDZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr $xmm0 = VRNDSCALESDZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESDZr_Int $xmm0, $xmm1, 31, implicit $mxcsr ; CHECK: $xmm0 = VRNDSCALESDZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
$xmm0 = VRNDSCALESDZr_Int $xmm0, $xmm1, 31, implicit $mxcsr $xmm0 = VRNDSCALESDZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESSZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr ; CHECK: $xmm0 = VRNDSCALESSZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
$xmm0 = VRNDSCALESSZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr $xmm0 = VRNDSCALESSZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
; CHECK: $xmm0 = VRNDSCALESSZr_Int $xmm0, $xmm1, 31, implicit $mxcsr ; CHECK: $xmm0 = VRNDSCALESSZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
$xmm0 = VRNDSCALESSZr_Int $xmm0, $xmm1, 31, implicit $mxcsr $xmm0 = VRNDSCALESSZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
RETQ RET64
... ...

llvm/test/CodeGen/X86/expand-call-rvmarker.mir

Show All 28 Lines
# CHECK-LABEL: name: test_objc_retainAutoreleaseReturnedValue # CHECK-LABEL: name: test_objc_retainAutoreleaseReturnedValue
# CHECK: bb.0 # CHECK: bb.0
# CHECK-NEXT: frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp # CHECK-NEXT: frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
# CHECK-NEXT: CFI_INSTRUCTION def_cfa_offset 16 # CHECK-NEXT: CFI_INSTRUCTION def_cfa_offset 16
# CHECK-NEXT: CALL64pcrel32 @fn, csr_64, implicit $rsp, implicit $ssp, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $rax # CHECK-NEXT: CALL64pcrel32 @fn, csr_64, implicit $rsp, implicit $ssp, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $rax
# CHECK-NEXT: $rdi = MOV64rr $rax # CHECK-NEXT: $rdi = MOV64rr $rax
# CHECK-NEXT: CALL64pcrel32 @objc_retainAutoreleasedReturnValue, csr_64, implicit $rsp, implicit $ssp, implicit-def $rax # CHECK-NEXT: CALL64pcrel32 @objc_retainAutoreleasedReturnValue, csr_64, implicit $rsp, implicit $ssp, implicit-def $rax
# CHECK-NEXT: $rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp # CHECK-NEXT: $rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp
# CHECK-NEXT: RETQ # CHECK-NEXT: RET64
# #
name: test_objc_retainAutoreleaseReturnedValue name: test_objc_retainAutoreleaseReturnedValue
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
frameInfo: frameInfo:
stackSize: 8 stackSize: 8
offsetAdjustment: -8 offsetAdjustment: -8
Show All 15 Lines
# CHECK-LABEL: name: test_objc_unsafeClaimAutoreleasedReturnValue # CHECK-LABEL: name: test_objc_unsafeClaimAutoreleasedReturnValue
# CHECK: bb.0 # CHECK: bb.0
# CHECK-NEXT: frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp # CHECK-NEXT: frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
# CHECK-NEXT: CFI_INSTRUCTION def_cfa_offset 16 # CHECK-NEXT: CFI_INSTRUCTION def_cfa_offset 16
# CHECK-NEXT: CALL64pcrel32 @fn, csr_64, implicit $rsp, implicit $ssp, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $rax # CHECK-NEXT: CALL64pcrel32 @fn, csr_64, implicit $rsp, implicit $ssp, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $rax
# CHECK-NEXT: $rdi = MOV64rr $rax # CHECK-NEXT: $rdi = MOV64rr $rax
# CHECK-NEXT: CALL64pcrel32 @objc_unsafeClaimAutoreleasedReturnValue, csr_64, implicit $rsp, implicit $ssp, implicit-def $rax # CHECK-NEXT: CALL64pcrel32 @objc_unsafeClaimAutoreleasedReturnValue, csr_64, implicit $rsp, implicit $ssp, implicit-def $rax
# CHECK-NEXT: $rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp # CHECK-NEXT: $rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp
# CHECK-NEXT: RETQ # CHECK-NEXT: RET64
# #
name: test_objc_unsafeClaimAutoreleasedReturnValue name: test_objc_unsafeClaimAutoreleasedReturnValue
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
frameInfo: frameInfo:
stackSize: 8 stackSize: 8
offsetAdjustment: -8 offsetAdjustment: -8
maxAlignment: 1 maxAlignment: 1
Show All 16 Lines
# CHECK: frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp # CHECK: frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
# CHECK-NEXT: $rax = MOV64rr $rdi # CHECK-NEXT: $rax = MOV64rr $rdi
# CHECK-NEXT: $rdi = MOV64rr killed $rdx # CHECK-NEXT: $rdi = MOV64rr killed $rdx
# CHECK-NEXT: $rdx = MOV64rr killed $rax # CHECK-NEXT: $rdx = MOV64rr killed $rax
# CHECK-NEXT: CALL64pcrel32 @fn, csr_64, implicit $rsp, implicit $ssp, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit-def $rsp, implicit-def $ssp, implicit-def $rax # CHECK-NEXT: CALL64pcrel32 @fn, csr_64, implicit $rsp, implicit $ssp, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit-def $rsp, implicit-def $ssp, implicit-def $rax
# CHECK-NEXT: $rdi = MOV64rr $rax # CHECK-NEXT: $rdi = MOV64rr $rax
# CHECK-NEXT: CALL64pcrel32 @objc_retainAutoreleasedReturnValue, csr_64, implicit $rsp, implicit $ssp, implicit-def dead $rax # CHECK-NEXT: CALL64pcrel32 @objc_retainAutoreleasedReturnValue, csr_64, implicit $rsp, implicit $ssp, implicit-def dead $rax
# CHECK-NEXT: $rax = frame-destroy POP64r implicit-def $rsp, implicit $rsp # CHECK-NEXT: $rax = frame-destroy POP64r implicit-def $rsp, implicit $rsp
# CHECK-NEXT: RETQ # CHECK-NEXT: RET64
# #
name: test_objc_unsafeClaimAutoreleasedReturnValue_2_args name: test_objc_unsafeClaimAutoreleasedReturnValue_2_args
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
frameInfo: frameInfo:
stackSize: 8 stackSize: 8
offsetAdjustment: -8 offsetAdjustment: -8
maxAlignment: 1 maxAlignment: 1
Show All 17 Lines
# CHECK-LABEL: name: test_ret_void # CHECK-LABEL: name: test_ret_void
# CHECK: bb.0 # CHECK: bb.0
# CHECK-NEXT: frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp # CHECK-NEXT: frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
# CHECK-NEXT: CFI_INSTRUCTION def_cfa_offset 16 # CHECK-NEXT: CFI_INSTRUCTION def_cfa_offset 16
# CHECK-NEXT: CALL64pcrel32 @fn, csr_64, implicit $rsp, implicit $ssp, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $rax # CHECK-NEXT: CALL64pcrel32 @fn, csr_64, implicit $rsp, implicit $ssp, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $rax
# CHECK-NEXT: $rdi = MOV64rr $rax # CHECK-NEXT: $rdi = MOV64rr $rax
# CHECK-NEXT: CALL64pcrel32 @objc_retainAutoreleasedReturnValue, csr_64, implicit $rsp, implicit $ssp, implicit-def dead $rax # CHECK-NEXT: CALL64pcrel32 @objc_retainAutoreleasedReturnValue, csr_64, implicit $rsp, implicit $ssp, implicit-def dead $rax
# CHECK-NEXT: $rax = frame-destroy POP64r implicit-def $rsp, implicit $rsp # CHECK-NEXT: $rax = frame-destroy POP64r implicit-def $rsp, implicit $rsp
# CHECK-NEXT: RETQ # CHECK-NEXT: RET64
# #
name: test_ret_void name: test_ret_void
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
frameInfo: frameInfo:
stackSize: 8 stackSize: 8
offsetAdjustment: -8 offsetAdjustment: -8
maxAlignment: 1 maxAlignment: 1
Show All 11 Lines

llvm/test/CodeGen/X86/expand-vr64-gr64-copy.mir

Show All 26 Lines bb.0.entry:
$mm0 = PSWAPDrm $rsp, 1, $noreg, -8, $noreg $mm0 = PSWAPDrm $rsp, 1, $noreg, -8, $noreg
; CHECK: $rax = MMX_MOVD64from64rr $mm0 ; CHECK: $rax = MMX_MOVD64from64rr $mm0
; CHECK-NEXT: $mm0 = MMX_MOVD64to64rr $rax ; CHECK-NEXT: $mm0 = MMX_MOVD64to64rr $rax
$rax = COPY $mm0 $rax = COPY $mm0
$mm0 = COPY $rax $mm0 = COPY $rax
MMX_MOVQ64mr $rsp, 1, $noreg, -16, $noreg, killed $mm0 MMX_MOVQ64mr $rsp, 1, $noreg, -16, $noreg, killed $mm0
$xmm0 = MOVQI2PQIrm $rsp, 1, $noreg, -16, $noreg $xmm0 = MOVQI2PQIrm $rsp, 1, $noreg, -16, $noreg
$xmm0 = PSHUFDri killed $xmm0, -44 $xmm0 = PSHUFDri killed $xmm0, -44
RETQ $xmm0 RET64 $xmm0
... ...

llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir

Show First 20 Lines • Show All 175 Lines • ▼ Show 20 Linesbody: |
; CHECK: dead $rcx = IMPLICIT_DEF ; CHECK: dead $rcx = IMPLICIT_DEF
; CHECK: dead $rdx = IMPLICIT_DEF ; CHECK: dead $rdx = IMPLICIT_DEF
; CHECK: renamable $rcx = IMPLICIT_DEF ; CHECK: renamable $rcx = IMPLICIT_DEF
; CHECK: renamable $eax = MOV32rm killed renamable $rax, 4, killed renamable $rcx, 0, $noreg, debug-location !44 :: (load (s32) from %ir.arrayidx3) ; CHECK: renamable $eax = MOV32rm killed renamable $rax, 4, killed renamable $rcx, 0, $noreg, debug-location !44 :: (load (s32) from %ir.arrayidx3)
; CHECK: $rsp = LEA64r $rbp, 1, $noreg, -8, $noreg, debug-location !45 ; CHECK: $rsp = LEA64r $rbp, 1, $noreg, -8, $noreg, debug-location !45
; CHECK: $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !45 ; CHECK: $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !45
; CHECK: $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !45 ; CHECK: $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !45
; CHECK: CFI_INSTRUCTION def_cfa $rsp, 8, debug-location !45 ; CHECK: CFI_INSTRUCTION def_cfa $rsp, 8, debug-location !45
; CHECK: RETQ implicit killed $eax, debug-location !45 ; CHECK: RET64 implicit killed $eax, debug-location !45
bb.0.entry: bb.0.entry:
liveins: $edi liveins: $edi
%0:gr32 = COPY $edi %0:gr32 = COPY $edi
%1:gr32 = MOV32rm %stack.0.a.addr, 1, $noreg, 0, $noreg, debug-location !13 :: (dereferenceable load (s32) from %ir.a.addr) %1:gr32 = MOV32rm %stack.0.a.addr, 1, $noreg, 0, $noreg, debug-location !13 :: (dereferenceable load (s32) from %ir.a.addr)
%2:gr64_nosp = SUBREG_TO_REG 0, killed %1, %subreg.sub_32bit, debug-location !13 %2:gr64_nosp = SUBREG_TO_REG 0, killed %1, %subreg.sub_32bit, debug-location !13
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !14 ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !14
%3:gr64 = COPY $rsp, debug-location !14 %3:gr64 = COPY $rsp, debug-location !14
Show All 19 Linesbody: |
bb.4.for.end: bb.4.for.end:
$rax = IMPLICIT_DEF $rax = IMPLICIT_DEF
$rbx = IMPLICIT_DEF $rbx = IMPLICIT_DEF
$rcx = IMPLICIT_DEF $rcx = IMPLICIT_DEF
$rdx = IMPLICIT_DEF $rdx = IMPLICIT_DEF
%7:gr64_nosp = IMPLICIT_DEF %7:gr64_nosp = IMPLICIT_DEF
%8:gr32 = MOV32rm %3, 4, %7, 0, $noreg, debug-location !44 :: (load (s32) from %ir.arrayidx3) %8:gr32 = MOV32rm %3, 4, %7, 0, $noreg, debug-location !44 :: (load (s32) from %ir.arrayidx3)
$eax = COPY %8, debug-location !45 $eax = COPY %8, debug-location !45
RETQ implicit $eax, debug-location !45 RET64 implicit $eax, debug-location !45
... ...

llvm/test/CodeGen/X86/fixup-bw-copy.mir

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
liveins: liveins:
- { reg: '$edi' } - { reg: '$edi' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $edi liveins: $edi
; CHECK: $eax = MOV32rr undef $edi, implicit $dil ; CHECK: $eax = MOV32rr undef $edi, implicit $dil
$al = MOV8rr killed $dil $al = MOV8rr killed $dil
RETQ killed $al RET64 killed $al
... ...
--- ---
name: test_movb_impuse name: test_movb_impuse
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$edi' } - { reg: '$edi' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $edi liveins: $edi
; CHECK: $eax = MOV32rr undef $edi, implicit $dil ; CHECK: $eax = MOV32rr undef $edi, implicit $dil
$al = MOV8rr $dil, implicit $edi $al = MOV8rr $dil, implicit $edi
RETQ killed $al RET64 killed $al
... ...
--- ---
name: test_movb_impdef_gr64 name: test_movb_impdef_gr64
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$edi' } - { reg: '$edi' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $edi liveins: $edi
; CHECK: $eax = MOV32rr undef $edi, implicit $dil, implicit-def $rax ; CHECK: $eax = MOV32rr undef $edi, implicit $dil, implicit-def $rax
$al = MOV8rr $dil, implicit-def $rax $al = MOV8rr $dil, implicit-def $rax
RETQ killed $al RET64 killed $al
... ...
--- ---
name: test_movb_impdef_gr32 name: test_movb_impdef_gr32
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$edi' } - { reg: '$edi' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $edi liveins: $edi
; CHECK: $eax = MOV32rr undef $edi, implicit $dil ; CHECK: $eax = MOV32rr undef $edi, implicit $dil
$al = MOV8rr $dil, implicit-def $eax $al = MOV8rr $dil, implicit-def $eax
RETQ killed $al RET64 killed $al
... ...
--- ---
name: test_movb_impdef_gr16 name: test_movb_impdef_gr16
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$edi' } - { reg: '$edi' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $edi liveins: $edi
; CHECK: $eax = MOV32rr undef $edi, implicit $dil ; CHECK: $eax = MOV32rr undef $edi, implicit $dil
$al = MOV8rr $dil, implicit-def $ax $al = MOV8rr $dil, implicit-def $ax
RETQ killed $al RET64 killed $al
... ...
--- ---
name: test_movw_impdef_gr32 name: test_movw_impdef_gr32
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$edi' } - { reg: '$edi' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $edi liveins: $edi
; CHECK: $eax = MOV32rr undef $edi, implicit $di ; CHECK: $eax = MOV32rr undef $edi, implicit $di
$ax = MOV16rr $di, implicit-def $eax $ax = MOV16rr $di, implicit-def $eax
RETQ killed $ax RET64 killed $ax
... ...
--- ---
name: test_movw_impdef_gr64 name: test_movw_impdef_gr64
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$edi' } - { reg: '$edi' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $edi liveins: $edi
; CHECK: $eax = MOV32rr undef $edi, implicit $di, implicit-def $rax ; CHECK: $eax = MOV32rr undef $edi, implicit $di, implicit-def $rax
$ax = MOV16rr $di, implicit-def $rax $ax = MOV16rr $di, implicit-def $rax
RETQ killed $ax RET64 killed $ax
... ...

llvm/test/CodeGen/X86/fixup-bw-inst.mir

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
# before the MOV and is killed by it. # before the MOV and is killed by it.
body: | body: |
bb.0: bb.0:
liveins: $rax liveins: $rax
$ax = MOV16rm killed $rax, 1, $noreg, 0, $noreg $ax = MOV16rm killed $rax, 1, $noreg, 0, $noreg
; CHECK: $eax = MOVZX32rm16 killed $rax ; CHECK: $eax = MOVZX32rm16 killed $rax
RETQ $ax RET64 $ax
... ...
--- ---
# CHECK-LABEL: name: test2 # CHECK-LABEL: name: test2
name: test2 name: test2
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rax' } - { reg: '$rax' }
# Imp-use of any super-register means the register is live before the MOV # Imp-use of any super-register means the register is live before the MOV
body: | body: |
bb.0: bb.0:
liveins: $dl, $rbx, $rcx, $r14 liveins: $dl, $rbx, $rcx, $r14
$cl = MOV8rr killed $dl, implicit killed $rcx, implicit-def $rcx $cl = MOV8rr killed $dl, implicit killed $rcx, implicit-def $rcx
; CHECK: $cl = MOV8rr killed $dl, implicit killed $rcx, implicit-def $rcx ; CHECK: $cl = MOV8rr killed $dl, implicit killed $rcx, implicit-def $rcx
JMP_1 %bb.1 JMP_1 %bb.1
bb.1: bb.1:
liveins: $rcx liveins: $rcx
RETQ $cl RET64 $cl
... ...
--- ---
# CHECK-LABEL: name: test3 # CHECK-LABEL: name: test3
name: test3 name: test3
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
Show All 12 Lines bb.0.entry:
JCC_1 %bb.1, 4, implicit $eflags JCC_1 %bb.1, 4, implicit $eflags
bb.2.if.then: bb.2.if.then:
liveins: $rdi liveins: $rdi
$ax = MOV16rm killed $rdi, 1, $noreg, 0, $noreg, implicit-def $eax :: (load (s16) from %ir.p) $ax = MOV16rm killed $rdi, 1, $noreg, 0, $noreg, implicit-def $eax :: (load (s16) from %ir.p)
; CHECK: $eax = MOVZX32rm16 killed $rdi, 1, $noreg, 0, $noreg, implicit-def $eax :: (load (s16) from %ir.p) ; CHECK: $eax = MOVZX32rm16 killed $rdi, 1, $noreg, 0, $noreg, implicit-def $eax :: (load (s16) from %ir.p)
$ax = KILL $ax, implicit killed $eax $ax = KILL $ax, implicit killed $eax
RETQ $ax RET64 $ax
bb.1: bb.1:
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
$ax = KILL $ax, implicit killed $eax $ax = KILL $ax, implicit killed $eax
RETQ $ax RET64 $ax
... ...
--- ---
# CHECK-LABEL: name: test4 # CHECK-LABEL: name: test4
name: test4 name: test4
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$r9d' } - { reg: '$r9d' }
# This code copies r10b into r9b and then uses r9w. We would like to promote # This code copies r10b into r9b and then uses r9w. We would like to promote
# the copy to a 32-bit copy, but because r9w is used this is not acceptable. # the copy to a 32-bit copy, but because r9w is used this is not acceptable.
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $r9d liveins: $r9d
$r9b = MOV8rr undef $r10b, implicit-def $r9d, implicit killed $r9d, implicit-def $eflags $r9b = MOV8rr undef $r10b, implicit-def $r9d, implicit killed $r9d, implicit-def $eflags
; CHECK: $r9b = MOV8rr undef $r10b, implicit-def $r9d, implicit killed $r9d, implicit-def $eflags ; CHECK: $r9b = MOV8rr undef $r10b, implicit-def $r9d, implicit killed $r9d, implicit-def $eflags
$ax = OR16rr undef $ax, $r9w, implicit-def $eflags $ax = OR16rr undef $ax, $r9w, implicit-def $eflags
RETQ $ax RET64 $ax
... ...
--- ---
# CHECK-LABEL: name: test5 # CHECK-LABEL: name: test5
name: test5 name: test5
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$ch', reg: '$bl' } - { reg: '$ch', reg: '$bl' }
body: | body: |
bb.0: bb.0:
liveins: $ch, $bl liveins: $ch, $bl
$cl = MOV8rr $bl, implicit-def $cx, implicit killed $ch, implicit-def $eflags $cl = MOV8rr $bl, implicit-def $cx, implicit killed $ch, implicit-def $eflags
; CHECK: $cl = MOV8rr $bl, implicit-def $cx, implicit killed $ch, implicit-def $eflags ; CHECK: $cl = MOV8rr $bl, implicit-def $cx, implicit killed $ch, implicit-def $eflags
RETQ $cx RET64 $cx
... ...

llvm/test/CodeGen/X86/implicit-null-checks.mir

Show First 20 Lines • Show All 421 Lines • ▼ Show 20 Lines bb.1.not_null:
$eax = MOV32ri 2200000 $eax = MOV32ri 2200000
$eax = AND32rm killed $eax, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.x) $eax = AND32rm killed $eax, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.x)
CMP32rr killed $eax, killed $esi, implicit-def $eflags CMP32rr killed $eax, killed $esi, implicit-def $eflags
JCC_1 %bb.4, 4, implicit $eflags JCC_1 %bb.4, 4, implicit $eflags
bb.2.ret_200: bb.2.ret_200:
$eax = MOV32ri 200 $eax = MOV32ri 200
RETQ $eax RET64 $eax
bb.3.is_null: bb.3.is_null:
$eax = MOV32ri 42 $eax = MOV32ri 42
RETQ $eax RET64 $eax
bb.4.ret_100: bb.4.ret_100:
$eax = MOV32ri 100 $eax = MOV32ri 100
RETQ $eax RET64 $eax
... ...
--- ---
name: imp_null_check_with_bitwise_op_1 name: imp_null_check_with_bitwise_op_1
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
Show All 22 Linesbody: |
bb.2.ret_200: bb.2.ret_200:
$eax = MOV32ri 200 $eax = MOV32ri 200
bb.3.is_null: bb.3.is_null:
liveins: $eax, $ah, $al, $ax, $bh, $bl, $bp, $bpl, $bx, $eax, $ebp, $ebx, $rax, $rbp, $rbx, $r12, $r13, $r14, $r15, $r12b, $r13b, $r14b, $r15b, $r12d, $r13d, $r14d, $r15d, $r12w, $r13w, $r14w, $r15w liveins: $eax, $ah, $al, $ax, $bh, $bl, $bp, $bpl, $bx, $eax, $ebp, $ebx, $rax, $rbp, $rbx, $r12, $r13, $r14, $r15, $r12b, $r13b, $r14b, $r15b, $r12d, $r13d, $r14d, $r15d, $r12w, $r13w, $r14w, $r15w
RETQ $eax RET64 $eax
bb.4.ret_100: bb.4.ret_100:
$eax = MOV32ri 100 $eax = MOV32ri 100
RETQ $eax RET64 $eax
... ...
--- ---
name: imp_null_check_with_bitwise_op_2 name: imp_null_check_with_bitwise_op_2
# CHECK-LABEL: name: imp_null_check_with_bitwise_op_2 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_2
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
Show All 16 Lines bb.1.not_null:
$eax = MOV32ri 2200000 $eax = MOV32ri 2200000
$eax = ADD32ri killed $eax, 100, implicit-def dead $eflags $eax = ADD32ri killed $eax, 100, implicit-def dead $eflags
$eax = AND32rm killed $eax, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.x) $eax = AND32rm killed $eax, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.x)
CMP32rr killed $eax, killed $esi, implicit-def $eflags CMP32rr killed $eax, killed $esi, implicit-def $eflags
JCC_1 %bb.4, 4, implicit $eflags JCC_1 %bb.4, 4, implicit $eflags
bb.2.ret_200: bb.2.ret_200:
$eax = MOV32ri 200 $eax = MOV32ri 200
RETQ $eax RET64 $eax
bb.3.is_null: bb.3.is_null:
$eax = MOV32ri 42 $eax = MOV32ri 42
RETQ $eax RET64 $eax
bb.4.ret_100: bb.4.ret_100:
$eax = MOV32ri 100 $eax = MOV32ri 100
RETQ $eax RET64 $eax
... ...
--- ---
name: imp_null_check_with_bitwise_op_3 name: imp_null_check_with_bitwise_op_3
# CHECK-LABEL: name: imp_null_check_with_bitwise_op_3 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_3
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
Show All 15 Lines bb.1.not_null:
$rdi = MOV64ri 5000 $rdi = MOV64ri 5000
$rdi = AND64rm killed $rdi, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.x) $rdi = AND64rm killed $rdi, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.x)
CMP64rr killed $rdi, killed $rsi, implicit-def $eflags CMP64rr killed $rdi, killed $rsi, implicit-def $eflags
JCC_1 %bb.4, 4, implicit $eflags JCC_1 %bb.4, 4, implicit $eflags
bb.2.ret_200: bb.2.ret_200:
$eax = MOV32ri 200 $eax = MOV32ri 200
RETQ $eax RET64 $eax
bb.3.is_null: bb.3.is_null:
$eax = MOV32ri 42 $eax = MOV32ri 42
RETQ $eax RET64 $eax
bb.4.ret_100: bb.4.ret_100:
$eax = MOV32ri 100 $eax = MOV32ri 100
RETQ $eax RET64 $eax
... ...
--- ---
name: imp_null_check_with_bitwise_op_4 name: imp_null_check_with_bitwise_op_4
# CHECK-LABEL: name: imp_null_check_with_bitwise_op_4 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_4
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
Show All 16 Lines bb.1.not_null:
$rbx = MOV64rr $rdx $rbx = MOV64rr $rdx
$rbx = AND64rm killed $rbx, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.x) $rbx = AND64rm killed $rbx, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.x)
$rdx = MOV64ri 0 $rdx = MOV64ri 0
CMP64rr killed $rbx, killed $rsi, implicit-def $eflags CMP64rr killed $rbx, killed $rsi, implicit-def $eflags
JCC_1 %bb.4, 4, implicit $eflags JCC_1 %bb.4, 4, implicit $eflags
bb.2.ret_200: bb.2.ret_200:
$eax = MOV32ri 200 $eax = MOV32ri 200
RETQ $eax RET64 $eax
bb.3.is_null: bb.3.is_null:
$eax = MOV32ri 42 $eax = MOV32ri 42
RETQ $eax RET64 $eax
bb.4.ret_100: bb.4.ret_100:
$eax = MOV32ri 100 $eax = MOV32ri 100
RETQ $eax RET64 $eax
... ...
--- ---
name: no_hoist_across_call name: no_hoist_across_call
# CHECK-LABEL: name: no_hoist_across_call # CHECK-LABEL: name: no_hoist_across_call
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
Show All 18 Lines bb.0.entry:
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.stay: bb.1.stay:
liveins: $rbx liveins: $rbx
CALL64pcrel32 @f, csr_64, implicit $rsp, implicit-def $rsp CALL64pcrel32 @f, csr_64, implicit $rsp, implicit-def $rsp
$eax = MOV32rm killed $rbx, 1, $noreg, 0, $noreg :: (load (s32) from %ir.ptr) $eax = MOV32rm killed $rbx, 1, $noreg, 0, $noreg :: (load (s32) from %ir.ptr)
$rbx = POP64r implicit-def $rsp, implicit $rsp $rbx = POP64r implicit-def $rsp, implicit $rsp
RETQ $eax RET64 $eax
bb.2.leave: bb.2.leave:
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
$rbx = POP64r implicit-def $rsp, implicit $rsp $rbx = POP64r implicit-def $rsp, implicit $rsp
RETQ $eax RET64 $eax
... ...
--- ---
name: dependency_live_in_hazard name: dependency_live_in_hazard
# CHECK-LABEL: name: dependency_live_in_hazard # CHECK-LABEL: name: dependency_live_in_hazard
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK-NOT: FAULTING_OP # CHECK-NOT: FAULTING_OP
# CHECK: bb.1.not_null: # CHECK: bb.1.not_null:
Show All 16 Linesbody: |
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
$rcx = MOV64rm killed $rsi, 1, $noreg, 0, $noreg :: (load (s64) from %ir.ptr2) $rcx = MOV64rm killed $rsi, 1, $noreg, 0, $noreg :: (load (s64) from %ir.ptr2)
$esi = MOV32ri 3076 $esi = MOV32ri 3076
$eax = BEXTR32rm killed $rdi, 1, $noreg, 0, $noreg, killed $esi, implicit-def dead $eflags :: (load (s32) from %ir.ptr) $eax = BEXTR32rm killed $rdi, 1, $noreg, 0, $noreg, killed $esi, implicit-def dead $eflags :: (load (s32) from %ir.ptr)
$eax = ADD32rm killed $eax, killed $rcx, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.val) $eax = ADD32rm killed $eax, killed $rcx, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.val)
RETQ $eax RET64 $eax
bb.2.is_null: bb.2.is_null:
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
RETQ $eax RET64 $eax
... ...
--- ---
name: use_alternate_load_op name: use_alternate_load_op
# CHECK-LABEL: name: use_alternate_load_op # CHECK-LABEL: name: use_alternate_load_op
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: $rax = FAULTING_OP 1, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 0, $noreg # CHECK: $rax = FAULTING_OP 1, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 0, $noreg
# CHECK-NEXT: JMP_1 %bb.1 # CHECK-NEXT: JMP_1 %bb.1
Show All 12 Lines bb.0.entry:
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
$rcx = MOV64rm killed $rsi, 1, $noreg, 0, $noreg $rcx = MOV64rm killed $rsi, 1, $noreg, 0, $noreg
$rcx = AND64rm killed $rcx, $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags $rcx = AND64rm killed $rcx, $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags
$rax = MOV64rm killed $rdi, 1, $noreg, 0, $noreg $rax = MOV64rm killed $rdi, 1, $noreg, 0, $noreg
RETQ $eax RET64 $eax
bb.2.is_null: bb.2.is_null:
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
RETQ $eax RET64 $eax
... ...
--- ---
name: imp_null_check_gep_load_with_use_dep name: imp_null_check_gep_load_with_use_dep
# CHECK-LABEL: name: imp_null_check_gep_load_with_use_dep # CHECK-LABEL: name: imp_null_check_gep_load_with_use_dep
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: $eax = FAULTING_OP 1, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 0, $noreg, implicit-def $rax :: (load (s32) from %ir.x) # CHECK: $eax = FAULTING_OP 1, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 0, $noreg, implicit-def $rax :: (load (s32) from %ir.x)
# CHECK-NEXT: JMP_1 %bb.1 # CHECK-NEXT: JMP_1 %bb.1
Show All 10 Lines bb.0.entry:
JCC_1 %bb.1, 4, implicit $eflags JCC_1 %bb.1, 4, implicit $eflags
bb.2.not_null: bb.2.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
$rsi = ADD64rr $rsi, $rdi, implicit-def dead $eflags $rsi = ADD64rr $rsi, $rdi, implicit-def dead $eflags
$eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg, implicit-def $rax :: (load (s32) from %ir.x) $eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg, implicit-def $rax :: (load (s32) from %ir.x)
$eax = LEA64_32r killed $rax, 1, killed $rsi, 4, $noreg $eax = LEA64_32r killed $rax, 1, killed $rsi, 4, $noreg
RETQ $eax RET64 $eax
bb.1.is_null: bb.1.is_null:
$eax = MOV32ri 42 $eax = MOV32ri 42
RETQ $eax RET64 $eax
... ...
--- ---
name: imp_null_check_load_with_base_sep name: imp_null_check_load_with_base_sep
# CHECK-LABEL: name: imp_null_check_load_with_base_sep # CHECK-LABEL: name: imp_null_check_load_with_base_sep
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: $rsi = ADD64rr $rsi, $rdi, implicit-def dead $eflags # CHECK: $rsi = ADD64rr $rsi, $rdi, implicit-def dead $eflags
# CHECK-NEXT: $esi = FAULTING_OP 1, %bb.2, {{[0-9]+}}, $esi, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags # CHECK-NEXT: $esi = FAULTING_OP 1, %bb.2, {{[0-9]+}}, $esi, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags
Show All 11 Lines bb.0.entry:
JCC_1 %bb.1, 4, implicit $eflags JCC_1 %bb.1, 4, implicit $eflags
bb.2.not_null: bb.2.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
$rsi = ADD64rr $rsi, $rdi, implicit-def dead $eflags $rsi = ADD64rr $rsi, $rdi, implicit-def dead $eflags
$esi = AND32rm killed $esi, $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags $esi = AND32rm killed $esi, $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags
$eax = MOV32rr $esi $eax = MOV32rr $esi
RETQ $eax RET64 $eax
bb.1.is_null: bb.1.is_null:
$eax = MOV32ri 42 $eax = MOV32ri 42
RETQ $eax RET64 $eax
... ...
--- ---
name: inc_store name: inc_store
# CHECK-LABEL: name: inc_store # CHECK-LABEL: name: inc_store
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: $noreg = FAULTING_OP 3, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 0, $noreg, $rsi # CHECK: $noreg = FAULTING_OP 3, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 0, $noreg, $rsi
# CHECK-NEXT: JMP_1 %bb.1 # CHECK-NEXT: JMP_1 %bb.1
Show All 10 Lines bb.0.entry:
TEST64rr $rdi, $rdi, implicit-def $eflags TEST64rr $rdi, $rdi, implicit-def $eflags
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
MOV64mr killed $rdi, 1, $noreg, 0, $noreg, killed $rsi MOV64mr killed $rdi, 1, $noreg, 0, $noreg, killed $rsi
RETQ RET64
bb.2.is_null: bb.2.is_null:
RETQ RET64
... ...
--- ---
name: inc_store_plus_offset name: inc_store_plus_offset
# CHECK-LABEL: inc_store_plus_offset # CHECK-LABEL: inc_store_plus_offset
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: $noreg = FAULTING_OP 3, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 16, $noreg, $rsi # CHECK: $noreg = FAULTING_OP 3, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 16, $noreg, $rsi
# CHECK-NEXT: JMP_1 %bb.1 # CHECK-NEXT: JMP_1 %bb.1
Show All 10 Lines bb.0.entry:
TEST64rr $rdi, $rdi, implicit-def $eflags TEST64rr $rdi, $rdi, implicit-def $eflags
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
MOV64mr killed $rdi, 1, $noreg, 16, $noreg, killed $rsi MOV64mr killed $rdi, 1, $noreg, 16, $noreg, killed $rsi
RETQ RET64
bb.2.is_null: bb.2.is_null:
RETQ RET64
... ...
--- ---
name: inc_store_with_dep name: inc_store_with_dep
# CHECK-LABEL: inc_store_with_dep # CHECK-LABEL: inc_store_with_dep
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: $esi = ADD32rr killed $esi, killed $esi, implicit-def dead $eflags # CHECK: $esi = ADD32rr killed $esi, killed $esi, implicit-def dead $eflags
# CHECK-NEXT: $noreg = FAULTING_OP 3, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 16, $noreg, $esi # CHECK-NEXT: $noreg = FAULTING_OP 3, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 16, $noreg, $esi
Show All 13 Lines bb.0.entry:
TEST64rr $rdi, $rdi, implicit-def $eflags TEST64rr $rdi, $rdi, implicit-def $eflags
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
$esi = ADD32rr killed $esi, killed $esi, implicit-def dead $eflags $esi = ADD32rr killed $esi, killed $esi, implicit-def dead $eflags
MOV32mr killed $rdi, 1, $noreg, 16, $noreg, killed $esi MOV32mr killed $rdi, 1, $noreg, 16, $noreg, killed $esi
RETQ RET64
bb.2.is_null: bb.2.is_null:
RETQ RET64
... ...
--- ---
name: inc_store_with_dep_in_null name: inc_store_with_dep_in_null
# CHECK-LABEL: inc_store_with_dep_in_null # CHECK-LABEL: inc_store_with_dep_in_null
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
Show All 12 Lines bb.0.entry:
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
$esi = ADD32rr $esi, $esi, implicit-def dead $eflags $esi = ADD32rr $esi, $esi, implicit-def dead $eflags
MOV32mr killed $rdi, 1, $noreg, 0, $noreg, $esi MOV32mr killed $rdi, 1, $noreg, 0, $noreg, $esi
$eax = MOV32rr killed $esi $eax = MOV32rr killed $esi
RETQ $eax RET64 $eax
bb.2.is_null: bb.2.is_null:
liveins: $rsi liveins: $rsi
$eax = MOV32rr killed $esi $eax = MOV32rr killed $esi
RETQ $eax RET64 $eax
... ...
--- ---
name: inc_store_with_volatile name: inc_store_with_volatile
# CHECK-LABEL: inc_store_with_volatile # CHECK-LABEL: inc_store_with_volatile
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
Show All 10 Lines bb.0.entry:
TEST64rr $rdi, $rdi, implicit-def $eflags TEST64rr $rdi, $rdi, implicit-def $eflags
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
MOV32mr killed $rdi, 1, $noreg, 0, $noreg, killed $esi :: (volatile store (s32) into %ir.ptr) MOV32mr killed $rdi, 1, $noreg, 0, $noreg, killed $esi :: (volatile store (s32) into %ir.ptr)
RETQ RET64
bb.2.is_null: bb.2.is_null:
RETQ RET64
... ...
--- ---
name: inc_store_with_two_dep name: inc_store_with_two_dep
# CHECK-LABEL: inc_store_with_two_dep # CHECK-LABEL: inc_store_with_two_dep
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
Show All 12 Lines bb.0.entry:
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
$esi = ADD32rr killed $esi, killed $esi, implicit-def dead $eflags $esi = ADD32rr killed $esi, killed $esi, implicit-def dead $eflags
$esi = ADD32ri killed $esi, 15, implicit-def dead $eflags $esi = ADD32ri killed $esi, 15, implicit-def dead $eflags
MOV32mr killed $rdi, 1, $noreg, 16, $noreg, killed $esi MOV32mr killed $rdi, 1, $noreg, 16, $noreg, killed $esi
RETQ RET64
bb.2.is_null: bb.2.is_null:
RETQ RET64
... ...
--- ---
name: inc_store_with_redefined_base name: inc_store_with_redefined_base
# CHECK-LABEL: inc_store_with_redefined_base # CHECK-LABEL: inc_store_with_redefined_base
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
Show All 11 Lines bb.0.entry:
TEST64rr $rdi, $rdi, implicit-def $eflags TEST64rr $rdi, $rdi, implicit-def $eflags
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
$rdi = ADD64rr killed $rdi, killed $rdi, implicit-def dead $eflags $rdi = ADD64rr killed $rdi, killed $rdi, implicit-def dead $eflags
MOV32mr killed $rdi, 1, $noreg, 16, $noreg, killed $esi MOV32mr killed $rdi, 1, $noreg, 16, $noreg, killed $esi
RETQ RET64
bb.2.is_null: bb.2.is_null:
RETQ RET64
... ...
--- ---
name: inc_store_with_reused_base name: inc_store_with_reused_base
# CHECK-LABEL: inc_store_with_reused_base # CHECK-LABEL: inc_store_with_reused_base
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: $noreg = FAULTING_OP 3, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 16, $noreg, $esi # CHECK: $noreg = FAULTING_OP 3, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 16, $noreg, $esi
# CHECK-NEXT: JMP_1 %bb.1 # CHECK-NEXT: JMP_1 %bb.1
Show All 11 Lines bb.0.entry:
TEST64rr $rdi, $rdi, implicit-def $eflags TEST64rr $rdi, $rdi, implicit-def $eflags
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
$rax = MOV64rr $rdi $rax = MOV64rr $rdi
MOV32mr killed $rdi, 1, $noreg, 16, $noreg, killed $esi MOV32mr killed $rdi, 1, $noreg, 16, $noreg, killed $esi
RETQ $eax RET64 $eax
bb.2.is_null: bb.2.is_null:
$rax = XOR64rr undef $rax, undef $rax, implicit-def dead $eflags $rax = XOR64rr undef $rax, undef $rax, implicit-def dead $eflags
RETQ $eax RET64 $eax
... ...
--- ---
name: inc_store_across_call name: inc_store_across_call
# CHECK-LABEL: inc_store_across_call # CHECK-LABEL: inc_store_across_call
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: TEST64rr $rbx, $rbx, implicit-def $eflags # CHECK: TEST64rr $rbx, $rbx, implicit-def $eflags
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
Show All 20 Linesbody: |
bb.1.not_null: bb.1.not_null:
liveins: $rbx liveins: $rbx
CALL64pcrel32 @f, csr_64, implicit $rsp, implicit-def $rsp CALL64pcrel32 @f, csr_64, implicit $rsp, implicit-def $rsp
MOV32mi $rbx, 1, $noreg, 0, $noreg, 20 MOV32mi $rbx, 1, $noreg, 0, $noreg, 20
$rax = MOV64rr killed $rbx $rax = MOV64rr killed $rbx
$rbx = POP64r implicit-def $rsp, implicit $rsp $rbx = POP64r implicit-def $rsp, implicit $rsp
RETQ $eax RET64 $eax
bb.2.is_null: bb.2.is_null:
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
$rbx = POP64r implicit-def $rsp, implicit $rsp $rbx = POP64r implicit-def $rsp, implicit $rsp
RETQ $eax RET64 $eax
... ...
--- ---
name: inc_store_with_dep_in_dep name: inc_store_with_dep_in_dep
# CHECK-LABEL: inc_store_with_dep_in_dep # CHECK-LABEL: inc_store_with_dep_in_dep
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
Show All 12 Lines bb.0.entry:
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
$eax = MOV32rr $esi $eax = MOV32rr $esi
$esi = ADD32ri killed $esi, 15, implicit-def dead $eflags $esi = ADD32ri killed $esi, 15, implicit-def dead $eflags
MOV32mr killed $rdi, 1, $noreg, 0, $noreg, killed $esi MOV32mr killed $rdi, 1, $noreg, 0, $noreg, killed $esi
RETQ $eax RET64 $eax
bb.2.is_null: bb.2.is_null:
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
RETQ $eax RET64 $eax
... ...
--- ---
name: inc_store_with_load_over_store name: inc_store_with_load_over_store
# CHECK-LABEL: inc_store_with_load_over_store # CHECK-LABEL: inc_store_with_load_over_store
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
Show All 11 Lines bb.0.entry:
TEST64rr $rdi, $rdi, implicit-def $eflags TEST64rr $rdi, $rdi, implicit-def $eflags
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
MOV32mi killed $rsi, 1, $noreg, 0, $noreg, 2 MOV32mi killed $rsi, 1, $noreg, 0, $noreg, 2
$eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg $eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg
RETQ $eax RET64 $eax
bb.2.is_null: bb.2.is_null:
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
RETQ $eax RET64 $eax
... ...
--- ---
name: inc_store_with_store_over_load name: inc_store_with_store_over_load
# CHECK-LABEL: inc_store_with_store_over_load # CHECK-LABEL: inc_store_with_store_over_load
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
Show All 11 Lines bb.0.entry:
TEST64rr $rdi, $rdi, implicit-def $eflags TEST64rr $rdi, $rdi, implicit-def $eflags
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
$eax = MOV32rm killed $rsi, 1, $noreg, 0, $noreg $eax = MOV32rm killed $rsi, 1, $noreg, 0, $noreg
MOV32mi killed $rdi, 1, $noreg, 0, $noreg, 2 MOV32mi killed $rdi, 1, $noreg, 0, $noreg, 2
RETQ $eax RET64 $eax
bb.2.is_null: bb.2.is_null:
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
RETQ $eax RET64 $eax
... ...
--- ---
name: inc_store_with_store_over_store name: inc_store_with_store_over_store
# CHECK-LABEL: inc_store_with_store_over_store # CHECK-LABEL: inc_store_with_store_over_store
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
Show All 11 Lines bb.0.entry:
TEST64rr $rdi, $rdi, implicit-def $eflags TEST64rr $rdi, $rdi, implicit-def $eflags
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
MOV32mi killed $rsi, 1, $noreg, 0, $noreg, 3 MOV32mi killed $rsi, 1, $noreg, 0, $noreg, 3
MOV32mi killed $rdi, 1, $noreg, 0, $noreg, 2 MOV32mi killed $rdi, 1, $noreg, 0, $noreg, 2
RETQ RET64
bb.2.is_null: bb.2.is_null:
RETQ RET64
... ...
--- ---
name: inc_store_with_load_and_store name: inc_store_with_load_and_store
# CHECK-LABEL: inc_store_with_load_and_store # CHECK-LABEL: inc_store_with_load_and_store
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: $noreg = FAULTING_OP 2, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 0, $noreg, $esi, implicit-def $eflags # CHECK: $noreg = FAULTING_OP 2, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 0, $noreg, $esi, implicit-def $eflags
# CHECK-NEXT: JMP_1 %bb.1 # CHECK-NEXT: JMP_1 %bb.1
Show All 11 Lines bb.0.entry:
TEST64rr $rdi, $rdi, implicit-def $eflags TEST64rr $rdi, $rdi, implicit-def $eflags
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
$esi = ADD32rr $esi, $esi, implicit-def dead $eflags $esi = ADD32rr $esi, $esi, implicit-def dead $eflags
ADD32mr killed $rdi, 1, $noreg, 0, $noreg, killed $esi, implicit-def dead $eflags ADD32mr killed $rdi, 1, $noreg, 0, $noreg, killed $esi, implicit-def dead $eflags
RETQ RET64
bb.2.is_null: bb.2.is_null:
RETQ RET64
... ...
--- ---
name: inc_store_and_load_no_alias name: inc_store_and_load_no_alias
# CHECK-LABEL: inc_store_and_load_no_alias # CHECK-LABEL: inc_store_and_load_no_alias
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: $eax = FAULTING_OP 1, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 0, $noreg :: (load (s32) from %ir.ptr) # CHECK: $eax = FAULTING_OP 1, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 0, $noreg :: (load (s32) from %ir.ptr)
# CHECK-NEXT: JMP_1 %bb.1 # CHECK-NEXT: JMP_1 %bb.1
Show All 11 Lines bb.0.entry:
TEST64rr $rdi, $rdi, implicit-def $eflags TEST64rr $rdi, $rdi, implicit-def $eflags
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
MOV32mi killed $rsi, 1, $noreg, 0, $noreg, 3 :: (store (s32) into %ir.ptr2) MOV32mi killed $rsi, 1, $noreg, 0, $noreg, 3 :: (store (s32) into %ir.ptr2)
$eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg :: (load (s32) from %ir.ptr) $eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg :: (load (s32) from %ir.ptr)
RETQ $eax RET64 $eax
bb.2.is_null: bb.2.is_null:
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
RETQ $eax RET64 $eax
... ...
--- ---
name: inc_store_and_load_alias name: inc_store_and_load_alias
# CHECK-LABEL: inc_store_and_load_alias # CHECK-LABEL: inc_store_and_load_alias
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
Show All 11 Lines bb.0.entry:
TEST64rr $rdi, $rdi, implicit-def $eflags TEST64rr $rdi, $rdi, implicit-def $eflags
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
MOV32mi killed $rsi, 1, $noreg, 0, $noreg, 3 :: (store (s32) into %ir.ptr2) MOV32mi killed $rsi, 1, $noreg, 0, $noreg, 3 :: (store (s32) into %ir.ptr2)
$eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg :: (load (s32) from %ir.ptr) $eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg :: (load (s32) from %ir.ptr)
RETQ $eax RET64 $eax
bb.2.is_null: bb.2.is_null:
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
RETQ $eax RET64 $eax
... ...
--- ---
name: inc_spill_dep name: inc_spill_dep
# CHECK-LABEL: inc_spill_dep # CHECK-LABEL: inc_spill_dep
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
Show All 17 Linesbody: |
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
$r14d = MOV32rm $rsp, 1, $noreg, 0, $noreg :: (load (s32) from %stack.0) $r14d = MOV32rm $rsp, 1, $noreg, 0, $noreg :: (load (s32) from %stack.0)
MOV64mr $rsp, 1, $noreg, 0, $noreg, $rdi :: (store (s64) into %stack.0) MOV64mr $rsp, 1, $noreg, 0, $noreg, $rdi :: (store (s64) into %stack.0)
$edi = MOV32rm $rdi, 1, $noreg, 8, $noreg :: (load (s32) from %ir.ptr) $edi = MOV32rm $rdi, 1, $noreg, 8, $noreg :: (load (s32) from %ir.ptr)
$eax = MOV32rr $edi $eax = MOV32rr $edi
RETQ $eax RET64 $eax
bb.2.is_null: bb.2.is_null:
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
RETQ $eax RET64 $eax
... ...
--- ---
name: imp_null_check_address_mul_overflow name: imp_null_check_address_mul_overflow
# CHECK-LABEL: name: imp_null_check_address_mul_overflow # CHECK-LABEL: name: imp_null_check_address_mul_overflow
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK-NOT: FAULTING_OP # CHECK-NOT: FAULTING_OP
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi' } - { reg: '$rdi' }
- { reg: '$rsi' } - { reg: '$rsi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rsi, $rdi liveins: $rsi, $rdi
TEST64rr $rdi, $rdi, implicit-def $eflags TEST64rr $rdi, $rdi, implicit-def $eflags
JCC_1 %bb.1, 4, implicit $eflags JCC_1 %bb.1, 4, implicit $eflags
bb.2.not_null: bb.2.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
$rcx = MOV64ri -9223372036854775808 $rcx = MOV64ri -9223372036854775808
$eax = MOV32rm killed $rdi, 2, $rcx, 0, $noreg, implicit-def $rax $eax = MOV32rm killed $rdi, 2, $rcx, 0, $noreg, implicit-def $rax
RETQ $eax RET64 $eax
bb.1.is_null: bb.1.is_null:
$eax = MOV32ri 42 $eax = MOV32ri 42
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir

Show All 35 Lines bb.0.entry:
; CHECK-NOT: FAULTING_OP ; CHECK-NOT: FAULTING_OP
renamable $rdi = MOV64ri 5000 renamable $rdi = MOV64ri 5000
JCC_1 %bb.2, 4, implicit $eflags JCC_1 %bb.2, 4, implicit $eflags
bb.1.not_null: bb.1.not_null:
liveins: $rdi, $rsi liveins: $rdi, $rsi
$rax = MOV64rm renamable $rdi, 1, $noreg, 4, $noreg $rax = MOV64rm renamable $rdi, 1, $noreg, 4, $noreg
RETQ $eax RET64 $eax
bb.2.is_null: bb.2.is_null:
$eax = MOV32ri 200 $eax = MOV32ri 200
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/X86/instr-symbols.mir

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Linesbody: |
; CHECK-NEXT: movq $.Lpost_f, %{{.*}} ; CHECK-NEXT: movq $.Lpost_f, %{{.*}}
; CHECK-NEXT: movq $.Lpre_g, %{{.*}} ; CHECK-NEXT: movq $.Lpre_g, %{{.*}}
; CHECK-NEXT: movq $.Lpost_h, %{{.*}} ; CHECK-NEXT: movq $.Lpost_h, %{{.*}}
%6:gr64 = ADD64rr killed %2, killed %3, implicit-def $eflags %6:gr64 = ADD64rr killed %2, killed %3, implicit-def $eflags
%7:gr64 = ADD64rr killed %4, killed %5, implicit-def $eflags %7:gr64 = ADD64rr killed %4, killed %5, implicit-def $eflags
%8:gr64 = ADD64rr killed %6, killed %7, implicit-def $eflags %8:gr64 = ADD64rr killed %6, killed %7, implicit-def $eflags
$rax = COPY %8 $rax = COPY %8
RETQ implicit $rax RET64 implicit $rax
... ...

llvm/test/CodeGen/X86/invalid-liveness.mir

Show All 19 Lines bb.0:
JMP_1 %bb.3 JMP_1 %bb.3
bb.2: bb.2:
%0 = IMPLICIT_DEF %0 = IMPLICIT_DEF
JMP_1 %bb.3 JMP_1 %bb.3
bb.3: bb.3:
$eax = COPY %0 $eax = COPY %0
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/X86/leaFixup32.mir

Show First 20 Lines • Show All 104 Lines • ▼ Show 20 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $eax, $ebp liveins: $eax, $ebp
; CHECK-LABEL: name: test2add_32 ; CHECK-LABEL: name: test2add_32
; CHECK: liveins: $eax, $ebp ; CHECK: liveins: $eax, $ebp
; CHECK: $eax = ADD32rr $eax, $ebp, implicit-def $eflags ; CHECK: $eax = ADD32rr $eax, $ebp, implicit-def $eflags
; CHECK: $eax = ADD32ri8 $eax, -5, implicit-def $eflags ; CHECK: $eax = ADD32ri8 $eax, -5, implicit-def $eflags
; CHECK: RETQ $eax ; CHECK: RET64 $eax
$eax = LEA32r killed $eax, 1, killed $ebp, -5, $noreg $eax = LEA32r killed $eax, 1, killed $ebp, -5, $noreg
RETQ $eax RET64 $eax
... ...
--- ---
name: test2add_ebp_32 name: test2add_ebp_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 19 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $eax, $ebp liveins: $eax, $ebp
; CHECK-LABEL: name: test2add_ebp_32 ; CHECK-LABEL: name: test2add_ebp_32
; CHECK: liveins: $eax, $ebp ; CHECK: liveins: $eax, $ebp
; CHECK: $ebp = ADD32rr $ebp, $eax, implicit-def $eflags ; CHECK: $ebp = ADD32rr $ebp, $eax, implicit-def $eflags
; CHECK: $ebp = ADD32ri8 $ebp, -5, implicit-def $eflags ; CHECK: $ebp = ADD32ri8 $ebp, -5, implicit-def $eflags
; CHECK: RETQ $ebp ; CHECK: RET64 $ebp
$ebp = LEA32r killed $ebp, 1, killed $eax, -5, $noreg $ebp = LEA32r killed $ebp, 1, killed $eax, -5, $noreg
RETQ $ebp RET64 $ebp
... ...
--- ---
name: test1add_ebp_32 name: test1add_ebp_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 18 LinesframeInfo:
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $eax, $ebp liveins: $eax, $ebp
; CHECK-LABEL: name: test1add_ebp_32 ; CHECK-LABEL: name: test1add_ebp_32
; CHECK: liveins: $eax, $ebp ; CHECK: liveins: $eax, $ebp
; CHECK: $ebp = ADD32rr $ebp, $eax, implicit-def $eflags ; CHECK: $ebp = ADD32rr $ebp, $eax, implicit-def $eflags
; CHECK: RETQ $ebp ; CHECK: RET64 $ebp
$ebp = LEA32r killed $ebp, 1, killed $eax, 0, $noreg $ebp = LEA32r killed $ebp, 1, killed $eax, 0, $noreg
RETQ $ebp RET64 $ebp
... ...
--- ---
name: testleaadd_32 name: testleaadd_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 20 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $eax, $ebp, $esi liveins: $eax, $ebp, $esi
; CHECK-LABEL: name: testleaadd_32 ; CHECK-LABEL: name: testleaadd_32
; CHECK: liveins: $eax, $ebp, $esi ; CHECK: liveins: $eax, $ebp, $esi
; CHECK: $ebx = LEA32r killed $eax, 1, killed $ebp, 0, $noreg ; CHECK: $ebx = LEA32r killed $eax, 1, killed $ebp, 0, $noreg
; CHECK: $ebx = ADD32ri8 $ebx, -5, implicit-def $eflags ; CHECK: $ebx = ADD32ri8 $ebx, -5, implicit-def $eflags
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
$ebx = LEA32r killed $eax, 1, killed $ebp, -5, $noreg $ebx = LEA32r killed $eax, 1, killed $ebp, -5, $noreg
RETQ $ebx RET64 $ebx
... ...
--- ---
name: testleaadd_ebp_32 name: testleaadd_ebp_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 20 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $eax, $ebp liveins: $eax, $ebp
; CHECK-LABEL: name: testleaadd_ebp_32 ; CHECK-LABEL: name: testleaadd_ebp_32
; CHECK: liveins: $eax, $ebp ; CHECK: liveins: $eax, $ebp
; CHECK: $ebx = LEA32r killed $eax, 1, killed $ebp, 0, $noreg ; CHECK: $ebx = LEA32r killed $eax, 1, killed $ebp, 0, $noreg
; CHECK: $ebx = ADD32ri8 $ebx, -5, implicit-def $eflags ; CHECK: $ebx = ADD32ri8 $ebx, -5, implicit-def $eflags
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
$ebx = LEA32r killed $ebp, 1, killed $eax, -5, $noreg $ebx = LEA32r killed $ebp, 1, killed $eax, -5, $noreg
RETQ $ebx RET64 $ebx
... ...
--- ---
name: test1lea_ebp_32 name: test1lea_ebp_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 19 LinesframeInfo:
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $eax, $ebp liveins: $eax, $ebp
; CHECK-LABEL: name: test1lea_ebp_32 ; CHECK-LABEL: name: test1lea_ebp_32
; CHECK: liveins: $eax, $ebp ; CHECK: liveins: $eax, $ebp
; CHECK: $ebx = LEA32r killed $eax, 1, killed $ebp, 0, $noreg ; CHECK: $ebx = LEA32r killed $eax, 1, killed $ebp, 0, $noreg
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
$ebx = LEA32r killed $ebp, 1, killed $eax, 0, $noreg $ebx = LEA32r killed $ebp, 1, killed $eax, 0, $noreg
RETQ $ebx RET64 $ebx
... ...
--- ---
name: test2addi32_32 name: test2addi32_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 19 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $eax, $ebp liveins: $eax, $ebp
; CHECK-LABEL: name: test2addi32_32 ; CHECK-LABEL: name: test2addi32_32
; CHECK: liveins: $eax, $ebp ; CHECK: liveins: $eax, $ebp
; CHECK: $eax = ADD32rr $eax, $ebp, implicit-def $eflags ; CHECK: $eax = ADD32rr $eax, $ebp, implicit-def $eflags
; CHECK: $eax = ADD32ri $eax, 129, implicit-def $eflags ; CHECK: $eax = ADD32ri $eax, 129, implicit-def $eflags
; CHECK: RETQ $eax ; CHECK: RET64 $eax
$eax = LEA32r killed $eax, 1, killed $ebp, 129, $noreg $eax = LEA32r killed $eax, 1, killed $ebp, 129, $noreg
RETQ $eax RET64 $eax
... ...
--- ---
name: test1mov1add_ebp_32 name: test1mov1add_ebp_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 20 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $eax, $ebp, $ebx liveins: $eax, $ebp, $ebx
; CHECK-LABEL: name: test1mov1add_ebp_32 ; CHECK-LABEL: name: test1mov1add_ebp_32
; CHECK: liveins: $eax, $ebp, $ebx ; CHECK: liveins: $eax, $ebp, $ebx
; CHECK: $ebx = MOV32rr $ebp ; CHECK: $ebx = MOV32rr $ebp
; CHECK: $ebx = ADD32rr $ebx, $ebp, implicit-def $eflags ; CHECK: $ebx = ADD32rr $ebx, $ebp, implicit-def $eflags
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
$ebx = LEA32r killed $ebp, 1, $ebp, 0, $noreg $ebx = LEA32r killed $ebp, 1, $ebp, 0, $noreg
RETQ $ebx RET64 $ebx
... ...
--- ---
name: testleaadd_ebp_index_32 name: testleaadd_ebp_index_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 19 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $eax, $ebp, $ebx liveins: $eax, $ebp, $ebx
; CHECK-LABEL: name: testleaadd_ebp_index_32 ; CHECK-LABEL: name: testleaadd_ebp_index_32
; CHECK: liveins: $eax, $ebp, $ebx ; CHECK: liveins: $eax, $ebp, $ebx
; CHECK: $ebx = LEA32r $noreg, 1, $ebp, 5, $noreg ; CHECK: $ebx = LEA32r $noreg, 1, $ebp, 5, $noreg
; CHECK: $ebx = ADD32rr $ebx, $ebp, implicit-def $eflags ; CHECK: $ebx = ADD32rr $ebx, $ebp, implicit-def $eflags
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
$ebx = LEA32r $ebp, 1, $ebp, 5, $noreg $ebx = LEA32r $ebp, 1, $ebp, 5, $noreg
RETQ $ebx RET64 $ebx
... ...
--- ---
name: testleaadd_ebp_index2_32 name: testleaadd_ebp_index2_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 19 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $eax, $ebp, $ebx liveins: $eax, $ebp, $ebx
; CHECK-LABEL: name: testleaadd_ebp_index2_32 ; CHECK-LABEL: name: testleaadd_ebp_index2_32
; CHECK: liveins: $eax, $ebp, $ebx ; CHECK: liveins: $eax, $ebp, $ebx
; CHECK: $ebx = LEA32r $noreg, 4, $ebp, 5, $noreg ; CHECK: $ebx = LEA32r $noreg, 4, $ebp, 5, $noreg
; CHECK: $ebx = ADD32rr $ebx, $ebp, implicit-def $eflags ; CHECK: $ebx = ADD32rr $ebx, $ebp, implicit-def $eflags
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
$ebx = LEA32r $ebp, 4, $ebp, 5, $noreg $ebx = LEA32r $ebp, 4, $ebp, 5, $noreg
RETQ $ebx RET64 $ebx
... ...
--- ---
name: test_skip_opt_32 name: test_skip_opt_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 18 LinesframeInfo:
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $eax, $ebp, $ebx liveins: $eax, $ebp, $ebx
; CHECK-LABEL: name: test_skip_opt_32 ; CHECK-LABEL: name: test_skip_opt_32
; CHECK: liveins: $eax, $ebp, $ebx ; CHECK: liveins: $eax, $ebp, $ebx
; CHECK: $ebp = LEA32r killed $ebp, 4, killed $ebp, 0, $noreg ; CHECK: $ebp = LEA32r killed $ebp, 4, killed $ebp, 0, $noreg
; CHECK: RETQ $ebp ; CHECK: RET64 $ebp
$ebp = LEA32r killed $ebp, 4, killed $ebp, 0, $noreg $ebp = LEA32r killed $ebp, 4, killed $ebp, 0, $noreg
RETQ $ebp RET64 $ebp
... ...
--- ---
name: test_skip_eflags_32 name: test_skip_eflags_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 19 Lines
body: | body: |
; CHECK-LABEL: name: test_skip_eflags_32 ; CHECK-LABEL: name: test_skip_eflags_32
; CHECK: bb.0 (%ir-block.0): ; CHECK: bb.0 (%ir-block.0):
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $eax, $ebp, $ebx ; CHECK: liveins: $eax, $ebp, $ebx
; CHECK: CMP32rr $eax, killed $ebx, implicit-def $eflags ; CHECK: CMP32rr $eax, killed $ebx, implicit-def $eflags
; CHECK: $ebx = LEA32r killed $eax, 4, killed $eax, 5, $noreg ; CHECK: $ebx = LEA32r killed $eax, 4, killed $eax, 5, $noreg
; CHECK: JCC_1 %bb.1, 4, implicit $eflags ; CHECK: JCC_1 %bb.1, 4, implicit $eflags
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: liveins: $eax, $ebp, $ebx ; CHECK: liveins: $eax, $ebp, $ebx
; CHECK: $ebp = LEA32r killed $ebx, 4, killed $ebx, 0, $noreg ; CHECK: $ebp = LEA32r killed $ebx, 4, killed $ebx, 0, $noreg
; CHECK: $ebp = ADD32ri8 $ebp, 5, implicit-def $eflags ; CHECK: $ebp = ADD32ri8 $ebp, 5, implicit-def $eflags
; CHECK: RETQ $ebp ; CHECK: RET64 $ebp
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $eax, $ebp, $ebx liveins: $eax, $ebp, $ebx
CMP32rr $eax, killed $ebx, implicit-def $eflags CMP32rr $eax, killed $ebx, implicit-def $eflags
$ebx = LEA32r killed $eax, 4, killed $eax, 5, $noreg $ebx = LEA32r killed $eax, 4, killed $eax, 5, $noreg
JCC_1 %bb.1, 4, implicit $eflags JCC_1 %bb.1, 4, implicit $eflags
RETQ $ebx RET64 $ebx
bb.1: bb.1:
liveins: $eax, $ebp, $ebx liveins: $eax, $ebp, $ebx
$ebp = LEA32r killed $ebx, 4, killed $ebx, 5, $noreg $ebp = LEA32r killed $ebx, 4, killed $ebx, 5, $noreg
RETQ $ebp RET64 $ebp
... ...

llvm/test/CodeGen/X86/leaFixup64.mir

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp liveins: $rax, $rbp
; CHECK-LABEL: name: testleaadd_64_32_1 ; CHECK-LABEL: name: testleaadd_64_32_1
; CHECK: liveins: $rax, $rbp ; CHECK: liveins: $rax, $rbp
; CHECK: $eax = ADD32rr $eax, $ebp, implicit-def $eflags, implicit $rax, implicit $rbp ; CHECK: $eax = ADD32rr $eax, $ebp, implicit-def $eflags, implicit $rax, implicit $rbp
; CHECK: $eax = ADD32ri8 $eax, -5, implicit-def $eflags ; CHECK: $eax = ADD32ri8 $eax, -5, implicit-def $eflags
; CHECK: RETQ $eax ; CHECK: RET64 $eax
$eax = LEA64_32r killed $rax, 1, killed $rbp, -5, $noreg $eax = LEA64_32r killed $rax, 1, killed $rbp, -5, $noreg
RETQ $eax RET64 $eax
... ...
--- ---
name: testleaadd_rbp_64_32_1 name: testleaadd_rbp_64_32_1
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 19 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp liveins: $rax, $rbp
; CHECK-LABEL: name: testleaadd_rbp_64_32_1 ; CHECK-LABEL: name: testleaadd_rbp_64_32_1
; CHECK: liveins: $rax, $rbp ; CHECK: liveins: $rax, $rbp
; CHECK: $ebp = ADD32rr $ebp, $eax, implicit-def $eflags, implicit $rbp, implicit $rax ; CHECK: $ebp = ADD32rr $ebp, $eax, implicit-def $eflags, implicit $rbp, implicit $rax
; CHECK: $ebp = ADD32ri8 $ebp, -5, implicit-def $eflags ; CHECK: $ebp = ADD32ri8 $ebp, -5, implicit-def $eflags
; CHECK: RETQ $ebp ; CHECK: RET64 $ebp
$ebp = LEA64_32r killed $rbp, 1, killed $rax, -5, $noreg $ebp = LEA64_32r killed $rbp, 1, killed $rax, -5, $noreg
RETQ $ebp RET64 $ebp
... ...
--- ---
name: test1lea_rbp_64_32_1 name: test1lea_rbp_64_32_1
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 18 LinesframeInfo:
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp liveins: $rax, $rbp
; CHECK-LABEL: name: test1lea_rbp_64_32_1 ; CHECK-LABEL: name: test1lea_rbp_64_32_1
; CHECK: liveins: $rax, $rbp ; CHECK: liveins: $rax, $rbp
; CHECK: $ebp = ADD32rr $ebp, $eax, implicit-def $eflags, implicit $rbp, implicit $rax ; CHECK: $ebp = ADD32rr $ebp, $eax, implicit-def $eflags, implicit $rbp, implicit $rax
; CHECK: RETQ $ebp ; CHECK: RET64 $ebp
$ebp = LEA64_32r killed $rbp, 1, killed $rax, 0, $noreg $ebp = LEA64_32r killed $rbp, 1, killed $rax, 0, $noreg
RETQ $ebp RET64 $ebp
... ...
--- ---
name: test2add_64 name: test2add_64
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 19 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp liveins: $rax, $rbp
; CHECK-LABEL: name: test2add_64 ; CHECK-LABEL: name: test2add_64
; CHECK: liveins: $rax, $rbp ; CHECK: liveins: $rax, $rbp
; CHECK: $rax = ADD64rr $rax, $rbp, implicit-def $eflags ; CHECK: $rax = ADD64rr $rax, $rbp, implicit-def $eflags
; CHECK: $rax = ADD64ri8 $rax, -5, implicit-def $eflags ; CHECK: $rax = ADD64ri8 $rax, -5, implicit-def $eflags
; CHECK: RETQ $eax ; CHECK: RET64 $eax
$rax = LEA64r killed $rax, 1, killed $rbp, -5, $noreg $rax = LEA64r killed $rax, 1, killed $rbp, -5, $noreg
RETQ $eax RET64 $eax
... ...
--- ---
name: test2add_rbp_64 name: test2add_rbp_64
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 19 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp liveins: $rax, $rbp
; CHECK-LABEL: name: test2add_rbp_64 ; CHECK-LABEL: name: test2add_rbp_64
; CHECK: liveins: $rax, $rbp ; CHECK: liveins: $rax, $rbp
; CHECK: $rbp = ADD64rr $rbp, $rax, implicit-def $eflags ; CHECK: $rbp = ADD64rr $rbp, $rax, implicit-def $eflags
; CHECK: $rbp = ADD64ri8 $rbp, -5, implicit-def $eflags ; CHECK: $rbp = ADD64ri8 $rbp, -5, implicit-def $eflags
; CHECK: RETQ $ebp ; CHECK: RET64 $ebp
$rbp = LEA64r killed $rbp, 1, killed $rax, -5, $noreg $rbp = LEA64r killed $rbp, 1, killed $rax, -5, $noreg
RETQ $ebp RET64 $ebp
... ...
--- ---
name: test1add_rbp_64 name: test1add_rbp_64
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 18 LinesframeInfo:
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp liveins: $rax, $rbp
; CHECK-LABEL: name: test1add_rbp_64 ; CHECK-LABEL: name: test1add_rbp_64
; CHECK: liveins: $rax, $rbp ; CHECK: liveins: $rax, $rbp
; CHECK: $rbp = ADD64rr $rbp, $rax, implicit-def $eflags ; CHECK: $rbp = ADD64rr $rbp, $rax, implicit-def $eflags
; CHECK: RETQ $ebp ; CHECK: RET64 $ebp
$rbp = LEA64r killed $rbp, 1, killed $rax, 0, $noreg $rbp = LEA64r killed $rbp, 1, killed $rax, 0, $noreg
RETQ $ebp RET64 $ebp
... ...
--- ---
name: testleaadd_64_32 name: testleaadd_64_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 20 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp liveins: $rax, $rbp
; CHECK-LABEL: name: testleaadd_64_32 ; CHECK-LABEL: name: testleaadd_64_32
; CHECK: liveins: $rax, $rbp ; CHECK: liveins: $rax, $rbp
; CHECK: $ebx = LEA64_32r killed $rax, 1, killed $rbp, 0, $noreg ; CHECK: $ebx = LEA64_32r killed $rax, 1, killed $rbp, 0, $noreg
; CHECK: $ebx = ADD32ri8 $ebx, -5, implicit-def $eflags ; CHECK: $ebx = ADD32ri8 $ebx, -5, implicit-def $eflags
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
$ebx = LEA64_32r killed $rax, 1, killed $rbp, -5, $noreg $ebx = LEA64_32r killed $rax, 1, killed $rbp, -5, $noreg
RETQ $ebx RET64 $ebx
... ...
--- ---
name: testleaadd_rbp_64_32 name: testleaadd_rbp_64_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 20 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp liveins: $rax, $rbp
; CHECK-LABEL: name: testleaadd_rbp_64_32 ; CHECK-LABEL: name: testleaadd_rbp_64_32
; CHECK: liveins: $rax, $rbp ; CHECK: liveins: $rax, $rbp
; CHECK: $ebx = LEA64_32r killed $rax, 1, killed $rbp, 0, $noreg ; CHECK: $ebx = LEA64_32r killed $rax, 1, killed $rbp, 0, $noreg
; CHECK: $ebx = ADD32ri8 $ebx, -5, implicit-def $eflags ; CHECK: $ebx = ADD32ri8 $ebx, -5, implicit-def $eflags
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
$ebx = LEA64_32r killed $rbp, 1, killed $rax, -5, $noreg $ebx = LEA64_32r killed $rbp, 1, killed $rax, -5, $noreg
RETQ $ebx RET64 $ebx
... ...
--- ---
name: test1lea_rbp_64_32 name: test1lea_rbp_64_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 19 LinesframeInfo:
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp liveins: $rax, $rbp
; CHECK-LABEL: name: test1lea_rbp_64_32 ; CHECK-LABEL: name: test1lea_rbp_64_32
; CHECK: liveins: $rax, $rbp ; CHECK: liveins: $rax, $rbp
; CHECK: $ebx = LEA64_32r killed $rax, 1, killed $rbp, 0, $noreg ; CHECK: $ebx = LEA64_32r killed $rax, 1, killed $rbp, 0, $noreg
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
$ebx = LEA64_32r killed $rbp, 1, killed $rax, 0, $noreg $ebx = LEA64_32r killed $rbp, 1, killed $rax, 0, $noreg
RETQ $ebx RET64 $ebx
... ...
--- ---
name: testleaadd_64 name: testleaadd_64
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 20 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp liveins: $rax, $rbp
; CHECK-LABEL: name: testleaadd_64 ; CHECK-LABEL: name: testleaadd_64
; CHECK: liveins: $rax, $rbp ; CHECK: liveins: $rax, $rbp
; CHECK: $rbx = LEA64r killed $rax, 1, killed $rbp, 0, $noreg ; CHECK: $rbx = LEA64r killed $rax, 1, killed $rbp, 0, $noreg
; CHECK: $rbx = ADD64ri8 $rbx, -5, implicit-def $eflags ; CHECK: $rbx = ADD64ri8 $rbx, -5, implicit-def $eflags
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
$rbx = LEA64r killed $rax, 1, killed $rbp, -5, $noreg $rbx = LEA64r killed $rax, 1, killed $rbp, -5, $noreg
RETQ $ebx RET64 $ebx
... ...
--- ---
name: testleaadd_rbp_64 name: testleaadd_rbp_64
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 20 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp liveins: $rax, $rbp
; CHECK-LABEL: name: testleaadd_rbp_64 ; CHECK-LABEL: name: testleaadd_rbp_64
; CHECK: liveins: $rax, $rbp ; CHECK: liveins: $rax, $rbp
; CHECK: $rbx = LEA64r killed $rax, 1, killed $rbp, 0, $noreg ; CHECK: $rbx = LEA64r killed $rax, 1, killed $rbp, 0, $noreg
; CHECK: $rbx = ADD64ri8 $rbx, -5, implicit-def $eflags ; CHECK: $rbx = ADD64ri8 $rbx, -5, implicit-def $eflags
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
$rbx = LEA64r killed $rbp, 1, killed $rax, -5, $noreg $rbx = LEA64r killed $rbp, 1, killed $rax, -5, $noreg
RETQ $ebx RET64 $ebx
... ...
--- ---
name: test1lea_rbp_64 name: test1lea_rbp_64
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 19 LinesframeInfo:
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp liveins: $rax, $rbp
; CHECK-LABEL: name: test1lea_rbp_64 ; CHECK-LABEL: name: test1lea_rbp_64
; CHECK: liveins: $rax, $rbp ; CHECK: liveins: $rax, $rbp
; CHECK: $rbx = LEA64r killed $rax, 1, killed $rbp, 0, $noreg ; CHECK: $rbx = LEA64r killed $rax, 1, killed $rbp, 0, $noreg
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
$rbx = LEA64r killed $rbp, 1, killed $rax, 0, $noreg $rbx = LEA64r killed $rbp, 1, killed $rax, 0, $noreg
RETQ $ebx RET64 $ebx
... ...
--- ---
name: test8 name: test8
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 20 Linesbody: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rdi, $rbp liveins: $rdi, $rbp
; CHECK-LABEL: name: test8 ; CHECK-LABEL: name: test8
; CHECK: liveins: $rdi, $rbp ; CHECK: liveins: $rdi, $rbp
; CHECK: $rbp = KILL $rbp, implicit-def $rbp ; CHECK: $rbp = KILL $rbp, implicit-def $rbp
; CHECK: $r13 = KILL $rdi, implicit-def $r13 ; CHECK: $r13 = KILL $rdi, implicit-def $r13
; CHECK: $r12 = LEA64r $noreg, 2, killed $r13, 5, $noreg ; CHECK: $r12 = LEA64r $noreg, 2, killed $r13, 5, $noreg
; CHECK: $r12 = ADD64rr $r12, killed $rbp, implicit-def $eflags ; CHECK: $r12 = ADD64rr $r12, killed $rbp, implicit-def $eflags
; CHECK: RETQ $r12 ; CHECK: RET64 $r12
$rbp = KILL $rbp, implicit-def $rbp $rbp = KILL $rbp, implicit-def $rbp
$r13 = KILL $rdi, implicit-def $r13 $r13 = KILL $rdi, implicit-def $r13
$r12 = LEA64r killed $rbp, 2, killed $r13, 5, $noreg $r12 = LEA64r killed $rbp, 2, killed $r13, 5, $noreg
RETQ $r12 RET64 $r12
... ...
--- ---
name: testleaaddi32_64_32 name: testleaaddi32_64_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 19 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp liveins: $rax, $rbp
; CHECK-LABEL: name: testleaaddi32_64_32 ; CHECK-LABEL: name: testleaaddi32_64_32
; CHECK: liveins: $rax, $rbp ; CHECK: liveins: $rax, $rbp
; CHECK: $eax = ADD32rr $eax, $ebp, implicit-def $eflags, implicit $rax, implicit $rbp ; CHECK: $eax = ADD32rr $eax, $ebp, implicit-def $eflags, implicit $rax, implicit $rbp
; CHECK: $eax = ADD32ri $eax, 129, implicit-def $eflags ; CHECK: $eax = ADD32ri $eax, 129, implicit-def $eflags
; CHECK: RETQ $eax ; CHECK: RET64 $eax
$eax = LEA64_32r killed $rax, 1, killed $rbp, 129, $noreg $eax = LEA64_32r killed $rax, 1, killed $rbp, 129, $noreg
RETQ $eax RET64 $eax
... ...
--- ---
name: test1mov1add_rbp_64_32 name: test1mov1add_rbp_64_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 18 LinesframeInfo:
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp, $rbx liveins: $rax, $rbp, $rbx
; CHECK-LABEL: name: test1mov1add_rbp_64_32 ; CHECK-LABEL: name: test1mov1add_rbp_64_32
; CHECK: liveins: $rax, $rbp, $rbx ; CHECK: liveins: $rax, $rbp, $rbx
; CHECK: $ebx = LEA64_32r killed $rbp, 1, killed $rbp, 0, $noreg ; CHECK: $ebx = LEA64_32r killed $rbp, 1, killed $rbp, 0, $noreg
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
$ebx = LEA64_32r killed $rbp, 1, killed $rbp, 0, $noreg $ebx = LEA64_32r killed $rbp, 1, killed $rbp, 0, $noreg
RETQ $ebx RET64 $ebx
... ...
--- ---
name: testleaadd_rbp_index_64_32 name: testleaadd_rbp_index_64_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 18 LinesframeInfo:
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp, $rbx liveins: $rax, $rbp, $rbx
; CHECK-LABEL: name: testleaadd_rbp_index_64_32 ; CHECK-LABEL: name: testleaadd_rbp_index_64_32
; CHECK: liveins: $rax, $rbp, $rbx ; CHECK: liveins: $rax, $rbp, $rbx
; CHECK: $ebx = LEA64_32r killed $rbp, 1, killed $rbp, 5, $noreg ; CHECK: $ebx = LEA64_32r killed $rbp, 1, killed $rbp, 5, $noreg
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
$ebx = LEA64_32r killed $rbp, 1, killed $rbp, 5, $noreg $ebx = LEA64_32r killed $rbp, 1, killed $rbp, 5, $noreg
RETQ $ebx RET64 $ebx
... ...
--- ---
name: testleaadd_rbp_index2_64_32 name: testleaadd_rbp_index2_64_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 18 LinesframeInfo:
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $eax, $ebp, $ebx liveins: $eax, $ebp, $ebx
; CHECK-LABEL: name: testleaadd_rbp_index2_64_32 ; CHECK-LABEL: name: testleaadd_rbp_index2_64_32
; CHECK: liveins: $eax, $ebp, $ebx ; CHECK: liveins: $eax, $ebp, $ebx
; CHECK: $ebx = LEA64_32r killed $rbp, 4, killed $rbp, 5, $noreg ; CHECK: $ebx = LEA64_32r killed $rbp, 4, killed $rbp, 5, $noreg
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
$ebx = LEA64_32r killed $rbp, 4, killed $rbp, 5, $noreg $ebx = LEA64_32r killed $rbp, 4, killed $rbp, 5, $noreg
RETQ $ebx RET64 $ebx
... ...
--- ---
name: test2addi32_64 name: test2addi32_64
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 19 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp liveins: $rax, $rbp
; CHECK-LABEL: name: test2addi32_64 ; CHECK-LABEL: name: test2addi32_64
; CHECK: liveins: $rax, $rbp ; CHECK: liveins: $rax, $rbp
; CHECK: $rax = ADD64rr $rax, $rbp, implicit-def $eflags ; CHECK: $rax = ADD64rr $rax, $rbp, implicit-def $eflags
; CHECK: $rax = ADD64ri32 $rax, 129, implicit-def $eflags ; CHECK: $rax = ADD64ri32 $rax, 129, implicit-def $eflags
; CHECK: RETQ $eax ; CHECK: RET64 $eax
$rax = LEA64r killed $rax, 1, killed $rbp, 129, $noreg $rax = LEA64r killed $rax, 1, killed $rbp, 129, $noreg
RETQ $eax RET64 $eax
... ...
--- ---
name: test1mov1add_rbp_64 name: test1mov1add_rbp_64
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 19 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp, $rbx liveins: $rax, $rbp, $rbx
; CHECK-LABEL: name: test1mov1add_rbp_64 ; CHECK-LABEL: name: test1mov1add_rbp_64
; CHECK: liveins: $rax, $rbp, $rbx ; CHECK: liveins: $rax, $rbp, $rbx
; CHECK: $rbx = MOV64rr $rbp ; CHECK: $rbx = MOV64rr $rbp
; CHECK: $rbx = ADD64rr $rbx, $rbp, implicit-def $eflags ; CHECK: $rbx = ADD64rr $rbx, $rbp, implicit-def $eflags
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
$rbx = LEA64r killed $rbp, 1, $rbp, 0, $noreg $rbx = LEA64r killed $rbp, 1, $rbp, 0, $noreg
RETQ $ebx RET64 $ebx
... ...
--- ---
name: testleaadd_rbp_index_64 name: testleaadd_rbp_index_64
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 19 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp, $rbx liveins: $rax, $rbp, $rbx
; CHECK-LABEL: name: testleaadd_rbp_index_64 ; CHECK-LABEL: name: testleaadd_rbp_index_64
; CHECK: liveins: $rax, $rbp, $rbx ; CHECK: liveins: $rax, $rbp, $rbx
; CHECK: $rbx = LEA64r $noreg, 1, $rbp, 5, $noreg ; CHECK: $rbx = LEA64r $noreg, 1, $rbp, 5, $noreg
; CHECK: $rbx = ADD64rr $rbx, $rbp, implicit-def $eflags ; CHECK: $rbx = ADD64rr $rbx, $rbp, implicit-def $eflags
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
$rbx = LEA64r $rbp, 1, $rbp, 5, $noreg $rbx = LEA64r $rbp, 1, $rbp, 5, $noreg
RETQ $ebx RET64 $ebx
... ...
--- ---
name: testleaadd_rbp_index2_64 name: testleaadd_rbp_index2_64
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 19 Lines
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp, $rbx liveins: $rax, $rbp, $rbx
; CHECK-LABEL: name: testleaadd_rbp_index2_64 ; CHECK-LABEL: name: testleaadd_rbp_index2_64
; CHECK: liveins: $rax, $rbp, $rbx ; CHECK: liveins: $rax, $rbp, $rbx
; CHECK: $rbx = LEA64r $noreg, 4, $rbp, 5, $noreg ; CHECK: $rbx = LEA64r $noreg, 4, $rbp, 5, $noreg
; CHECK: $rbx = ADD64rr $rbx, $rbp, implicit-def $eflags ; CHECK: $rbx = ADD64rr $rbx, $rbp, implicit-def $eflags
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
$rbx = LEA64r $rbp, 4, $rbp, 5, $noreg $rbx = LEA64r $rbp, 4, $rbp, 5, $noreg
RETQ $ebx RET64 $ebx
... ...
--- ---
name: test_skip_opt_64 name: test_skip_opt_64
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 18 LinesframeInfo:
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp, $rbx liveins: $rax, $rbp, $rbx
; CHECK-LABEL: name: test_skip_opt_64 ; CHECK-LABEL: name: test_skip_opt_64
; CHECK: liveins: $rax, $rbp, $rbx ; CHECK: liveins: $rax, $rbp, $rbx
; CHECK: $rbp = LEA64r killed $rbp, 4, killed $rbp, 0, $noreg ; CHECK: $rbp = LEA64r killed $rbp, 4, killed $rbp, 0, $noreg
; CHECK: RETQ $ebp ; CHECK: RET64 $ebp
$rbp = LEA64r killed $rbp, 4, killed $rbp, 0, $noreg $rbp = LEA64r killed $rbp, 4, killed $rbp, 0, $noreg
RETQ $ebp RET64 $ebp
... ...
--- ---
name: test_skip_eflags_64 name: test_skip_eflags_64
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 19 Lines
body: | body: |
; CHECK-LABEL: name: test_skip_eflags_64 ; CHECK-LABEL: name: test_skip_eflags_64
; CHECK: bb.0 (%ir-block.0): ; CHECK: bb.0 (%ir-block.0):
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $rax, $rbp, $rbx ; CHECK: liveins: $rax, $rbp, $rbx
; CHECK: CMP64rr $rax, killed $rbx, implicit-def $eflags ; CHECK: CMP64rr $rax, killed $rbx, implicit-def $eflags
; CHECK: $rbx = LEA64r killed $rax, 4, killed $rax, 5, $noreg ; CHECK: $rbx = LEA64r killed $rax, 4, killed $rax, 5, $noreg
; CHECK: JCC_1 %bb.1, 4, implicit $eflags ; CHECK: JCC_1 %bb.1, 4, implicit $eflags
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: liveins: $rax, $rbp, $rbx ; CHECK: liveins: $rax, $rbp, $rbx
; CHECK: $rbp = LEA64r killed $rbx, 4, killed $rbx, 0, $noreg ; CHECK: $rbp = LEA64r killed $rbx, 4, killed $rbx, 0, $noreg
; CHECK: $rbp = ADD64ri8 $rbp, 5, implicit-def $eflags ; CHECK: $rbp = ADD64ri8 $rbp, 5, implicit-def $eflags
; CHECK: RETQ $ebp ; CHECK: RET64 $ebp
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp, $rbx liveins: $rax, $rbp, $rbx
CMP64rr $rax, killed $rbx, implicit-def $eflags CMP64rr $rax, killed $rbx, implicit-def $eflags
$rbx = LEA64r killed $rax, 4, killed $rax, 5, $noreg $rbx = LEA64r killed $rax, 4, killed $rax, 5, $noreg
JCC_1 %bb.1, 4, implicit $eflags JCC_1 %bb.1, 4, implicit $eflags
RETQ $ebx RET64 $ebx
bb.1: bb.1:
liveins: $rax, $rbp, $rbx liveins: $rax, $rbp, $rbx
$rbp = LEA64r killed $rbx, 4, killed $rbx, 5, $noreg $rbp = LEA64r killed $rbx, 4, killed $rbx, 5, $noreg
RETQ $ebp RET64 $ebp
... ...
--- ---
name: test_skip_opt_64_32 name: test_skip_opt_64_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 18 LinesframeInfo:
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp, $rbx liveins: $rax, $rbp, $rbx
; CHECK-LABEL: name: test_skip_opt_64_32 ; CHECK-LABEL: name: test_skip_opt_64_32
; CHECK: liveins: $rax, $rbp, $rbx ; CHECK: liveins: $rax, $rbp, $rbx
; CHECK: $ebp = LEA64_32r killed $rbp, 4, killed $rbp, 0, $noreg ; CHECK: $ebp = LEA64_32r killed $rbp, 4, killed $rbp, 0, $noreg
; CHECK: RETQ $ebp ; CHECK: RET64 $ebp
$ebp = LEA64_32r killed $rbp, 4, killed $rbp, 0, $noreg $ebp = LEA64_32r killed $rbp, 4, killed $rbp, 0, $noreg
RETQ $ebp RET64 $ebp
... ...
--- ---
name: test_skip_eflags_64_32 name: test_skip_eflags_64_32
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 19 Lines
body: | body: |
; CHECK-LABEL: name: test_skip_eflags_64_32 ; CHECK-LABEL: name: test_skip_eflags_64_32
; CHECK: bb.0 (%ir-block.0): ; CHECK: bb.0 (%ir-block.0):
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $rax, $rbp, $rbx ; CHECK: liveins: $rax, $rbp, $rbx
; CHECK: CMP64rr $rax, killed $rbx, implicit-def $eflags ; CHECK: CMP64rr $rax, killed $rbx, implicit-def $eflags
; CHECK: $ebx = LEA64_32r killed $rax, 4, killed $rax, 5, $noreg ; CHECK: $ebx = LEA64_32r killed $rax, 4, killed $rax, 5, $noreg
; CHECK: JCC_1 %bb.1, 4, implicit $eflags ; CHECK: JCC_1 %bb.1, 4, implicit $eflags
; CHECK: RETQ $ebx ; CHECK: RET64 $ebx
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: liveins: $rax, $rbp, $rbx ; CHECK: liveins: $rax, $rbp, $rbx
; CHECK: $ebp = LEA64_32r killed $rbx, 4, killed $rbx, 0, $noreg ; CHECK: $ebp = LEA64_32r killed $rbx, 4, killed $rbx, 0, $noreg
; CHECK: $ebp = ADD32ri8 $ebp, 5, implicit-def $eflags ; CHECK: $ebp = ADD32ri8 $ebp, 5, implicit-def $eflags
; CHECK: RETQ $ebp ; CHECK: RET64 $ebp
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: $rax, $rbp, $rbx liveins: $rax, $rbp, $rbx
CMP64rr $rax, killed $rbx, implicit-def $eflags CMP64rr $rax, killed $rbx, implicit-def $eflags
$ebx = LEA64_32r killed $rax, 4, killed $rax, 5, $noreg $ebx = LEA64_32r killed $rax, 4, killed $rax, 5, $noreg
JCC_1 %bb.1, 4, implicit $eflags JCC_1 %bb.1, 4, implicit $eflags
RETQ $ebx RET64 $ebx
bb.1: bb.1:
liveins: $rax, $rbp, $rbx liveins: $rax, $rbp, $rbx
$ebp = LEA64_32r killed $rbx, 4, killed $rbx, 5, $noreg $ebp = LEA64_32r killed $rbx, 4, killed $rbx, 5, $noreg
RETQ $ebp RET64 $ebp
... ...
--- ---
name: pr43758 name: pr43758
alignment: 16 alignment: 16
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
Show All 27 Lines bb.0 (%ir-block.0):
; CHECK: NOOP ; CHECK: NOOP
; CHECK: NOOP ; CHECK: NOOP
; CHECK: NOOP ; CHECK: NOOP
; CHECK: $ebp = ADD32rr $ebp, $eax, implicit-def $eflags, implicit $rbp, implicit $rax ; CHECK: $ebp = ADD32rr $ebp, $eax, implicit-def $eflags, implicit $rbp, implicit $rax
; CHECK: NOOP ; CHECK: NOOP
; CHECK: NOOP ; CHECK: NOOP
; CHECK: NOOP ; CHECK: NOOP
; CHECK: NOOP ; CHECK: NOOP
; CHECK: RETQ $ebp ; CHECK: RET64 $ebp
DBG_VALUE 0, $noreg DBG_VALUE 0, $noreg
NOOP NOOP
NOOP NOOP
NOOP NOOP
NOOP NOOP
$ebp = LEA64_32r killed $rbp, 1, killed $rax, 0, $noreg $ebp = LEA64_32r killed $rbp, 1, killed $rax, 0, $noreg
NOOP NOOP
NOOP NOOP
NOOP NOOP
NOOP NOOP
RETQ $ebp RET64 $ebp
... ...
... ...

llvm/test/CodeGen/X86/machine-copy-dbgvalue.mir

# RUN: llc -mtriple=i686-- -run-pass machine-cp -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -mtriple=i686-- -run-pass machine-cp -verify-machineinstrs -o - %s | FileCheck %s
--- ---
# Test that machine copy propagation ignores DBG_VALUE and DBL_VALUE_LIST and updates it. # Test that machine copy propagation ignores DBG_VALUE and DBL_VALUE_LIST and updates it.
# CHECK-LABEL: name: foo # CHECK-LABEL: name: foo
# CHECK: bb.0: # CHECK: bb.0:
# CHECK-NEXT: $rax = MOV64ri 31 # CHECK-NEXT: $rax = MOV64ri 31
# CHECK-NEXT: DBG_VALUE $rax # CHECK-NEXT: DBG_VALUE $rax
# CHECK-NEXT: DBG_VALUE_LIST 0, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_constu, 4, DW_OP_mul, DW_OP_plus, DW_OP_stack_value), $rax, 0, 0 # CHECK-NEXT: DBG_VALUE_LIST 0, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_constu, 4, DW_OP_mul, DW_OP_plus, DW_OP_stack_value), $rax, 0, 0
# CHECK-NEXT: RETQ implicit killed $rax # CHECK-NEXT: RET64 implicit killed $rax
name: foo name: foo
body: | body: |
bb.0: bb.0:
renamable $rcx = MOV64ri 31 renamable $rcx = MOV64ri 31
DBG_VALUE $rcx, 0, 0, 0, 0 DBG_VALUE $rcx, 0, 0, 0, 0
DBG_VALUE_LIST 0, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_constu, 4, DW_OP_mul, DW_OP_plus, DW_OP_stack_value), $rcx, 0, 0 DBG_VALUE_LIST 0, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_constu, 4, DW_OP_mul, DW_OP_plus, DW_OP_stack_value), $rcx, 0, 0
$rax = COPY killed renamable $rcx $rax = COPY killed renamable $rcx
RETQ implicit killed $rax RET64 implicit killed $rax
... ...

llvm/test/CodeGen/X86/machine-outliner-cfi-tail-some.mir

Show All 33 Lines bb.0:
$ecx = MOV32ri 3 $ecx = MOV32ri 3
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
CFI_INSTRUCTION offset $rbp, -16 CFI_INSTRUCTION offset $rbp, -16
CFI_INSTRUCTION def_cfa_register $rsp CFI_INSTRUCTION def_cfa_register $rsp
$esi = MOV32ri 1 $esi = MOV32ri 1
$edx = MOV32ri 2 $edx = MOV32ri 2
$edi = MOV32ri 3 $edi = MOV32ri 3
$eax = MOV32ri 4 $eax = MOV32ri 4
RETQ RET64
... ...
--- ---
name: bar name: bar
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
;liveins: $lr ;liveins: $lr
; CHECK-LABEL: name: bar ; CHECK-LABEL: name: bar
; CHECK: CALL64pcrel32 @OUTLINED_FUNCTION_1, implicit $rsp, implicit $ssp, implicit-def $eax, implicit-def $ebx, implicit-def $ecx, implicit $rsp, implicit $ssp ; CHECK: CALL64pcrel32 @OUTLINED_FUNCTION_1, implicit $rsp, implicit $ssp, implicit-def $eax, implicit-def $ebx, implicit-def $ecx, implicit $rsp, implicit $ssp
; CHECK: CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: CFI_INSTRUCTION def_cfa_offset 16
; CHECK: CFI_INSTRUCTION offset $rbp, -16 ; CHECK: CFI_INSTRUCTION offset $rbp, -16
; CHECK: CFI_INSTRUCTION def_cfa_register $rsp ; CHECK: CFI_INSTRUCTION def_cfa_register $rsp
; CHECK: TAILJMPd64 @OUTLINED_FUNCTION_0, implicit $rsp, implicit $ssp, implicit-def $eax, implicit-def $edi, implicit-def $edx, implicit-def $esi, implicit $rsp, implicit $ssp ; CHECK: TAILJMPd64 @OUTLINED_FUNCTION_0, implicit $rsp, implicit $ssp, implicit-def $eax, implicit-def $edi, implicit-def $edx, implicit-def $esi, implicit $rsp, implicit $ssp
$eax = MOV32ri 1 $eax = MOV32ri 1
$ebx = MOV32ri 2 $ebx = MOV32ri 2
$ecx = MOV32ri 3 $ecx = MOV32ri 3
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
CFI_INSTRUCTION offset $rbp, -16 CFI_INSTRUCTION offset $rbp, -16
CFI_INSTRUCTION def_cfa_register $rsp CFI_INSTRUCTION def_cfa_register $rsp
$esi = MOV32ri 1 $esi = MOV32ri 1
$edx = MOV32ri 2 $edx = MOV32ri 2
$edi = MOV32ri 3 $edi = MOV32ri 3
$eax = MOV32ri 4 $eax = MOV32ri 4
RETQ RET64
... ...
--- ---
name: baz name: baz
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
;liveins: $lr ;liveins: $lr
; CHECK-LABEL: name: baz ; CHECK-LABEL: name: baz
; CHECK: CALL64pcrel32 @OUTLINED_FUNCTION_1, implicit $rsp, implicit $ssp, implicit-def $eax, implicit-def $ebx, implicit-def $ecx, implicit $rsp, implicit $ssp ; CHECK: CALL64pcrel32 @OUTLINED_FUNCTION_1, implicit $rsp, implicit $ssp, implicit-def $eax, implicit-def $ebx, implicit-def $ecx, implicit $rsp, implicit $ssp
; CHECK: CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: CFI_INSTRUCTION def_cfa_offset 16
; CHECK: CFI_INSTRUCTION offset $rbp, -16 ; CHECK: CFI_INSTRUCTION offset $rbp, -16
; CHECK: CFI_INSTRUCTION def_cfa_register $rsp ; CHECK: CFI_INSTRUCTION def_cfa_register $rsp
; CHECK: TAILJMPd64 @OUTLINED_FUNCTION_0, implicit $rsp, implicit $ssp, implicit-def $eax, implicit-def $edi, implicit-def $edx, implicit-def $esi, implicit $rsp, implicit $ssp ; CHECK: TAILJMPd64 @OUTLINED_FUNCTION_0, implicit $rsp, implicit $ssp, implicit-def $eax, implicit-def $edi, implicit-def $edx, implicit-def $esi, implicit $rsp, implicit $ssp
$eax = MOV32ri 1 $eax = MOV32ri 1
$ebx = MOV32ri 2 $ebx = MOV32ri 2
$ecx = MOV32ri 3 $ecx = MOV32ri 3
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
CFI_INSTRUCTION offset $rbp, -16 CFI_INSTRUCTION offset $rbp, -16
CFI_INSTRUCTION def_cfa_register $rsp CFI_INSTRUCTION def_cfa_register $rsp
$esi = MOV32ri 1 $esi = MOV32ri 1
$edx = MOV32ri 2 $edx = MOV32ri 2
$edi = MOV32ri 3 $edi = MOV32ri 3
$eax = MOV32ri 4 $eax = MOV32ri 4
RETQ RET64

llvm/test/CodeGen/X86/machine-outliner-cfi-tail.mir

Show All 24 Lines bb.0:
$ecx = MOV32ri 3 $ecx = MOV32ri 3
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
CFI_INSTRUCTION offset $rbp, -16 CFI_INSTRUCTION offset $rbp, -16
CFI_INSTRUCTION def_cfa_register $rsp CFI_INSTRUCTION def_cfa_register $rsp
$esi = MOV32ri 1 $esi = MOV32ri 1
$edx = MOV32ri 2 $edx = MOV32ri 2
$edi = MOV32ri 3 $edi = MOV32ri 3
$eax = MOV32ri 4 $eax = MOV32ri 4
RETQ RET64
... ...
--- ---
name: bar name: bar
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
;liveins: $lr ;liveins: $lr
; CHECK-LABEL: name: bar ; CHECK-LABEL: name: bar
; CHECK: $ecx = MOV32ri 3 ; CHECK: $ecx = MOV32ri 3
; CHECK: CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: CFI_INSTRUCTION def_cfa_offset 16
; CHECK: CFI_INSTRUCTION offset $rbp, -16 ; CHECK: CFI_INSTRUCTION offset $rbp, -16
; CHECK: CFI_INSTRUCTION def_cfa_register $rsp ; CHECK: CFI_INSTRUCTION def_cfa_register $rsp
; CHECK: TAILJMPd64 @OUTLINED_FUNCTION_0, implicit $rsp, implicit $ssp, implicit-def $eax, implicit-def $edi, implicit-def $edx, implicit-def $esi, implicit $rsp, implicit $ssp ; CHECK: TAILJMPd64 @OUTLINED_FUNCTION_0, implicit $rsp, implicit $ssp, implicit-def $eax, implicit-def $edi, implicit-def $edx, implicit-def $esi, implicit $rsp, implicit $ssp
$ecx = MOV32ri 3 $ecx = MOV32ri 3
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
CFI_INSTRUCTION offset $rbp, -16 CFI_INSTRUCTION offset $rbp, -16
CFI_INSTRUCTION def_cfa_register $rsp CFI_INSTRUCTION def_cfa_register $rsp
$esi = MOV32ri 1 $esi = MOV32ri 1
$edx = MOV32ri 2 $edx = MOV32ri 2
$edi = MOV32ri 3 $edi = MOV32ri 3
$eax = MOV32ri 4 $eax = MOV32ri 4
RETQ RET64
... ...
--- ---
name: baz name: baz
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
;liveins: $lr ;liveins: $lr
; CHECK-LABEL: name: baz ; CHECK-LABEL: name: baz
; CHECK: $ecx = MOV32ri 3 ; CHECK: $ecx = MOV32ri 3
; CHECK: CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: CFI_INSTRUCTION def_cfa_offset 16
; CHECK: CFI_INSTRUCTION offset $rbp, -16 ; CHECK: CFI_INSTRUCTION offset $rbp, -16
; CHECK: CFI_INSTRUCTION def_cfa_register $rsp ; CHECK: CFI_INSTRUCTION def_cfa_register $rsp
; CHECK: TAILJMPd64 @OUTLINED_FUNCTION_0, implicit $rsp, implicit $ssp, implicit-def $eax, implicit-def $edi, implicit-def $edx, implicit-def $esi, implicit $rsp, implicit $ssp ; CHECK: TAILJMPd64 @OUTLINED_FUNCTION_0, implicit $rsp, implicit $ssp, implicit-def $eax, implicit-def $edi, implicit-def $edx, implicit-def $esi, implicit $rsp, implicit $ssp
$ecx = MOV32ri 3 $ecx = MOV32ri 3
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
CFI_INSTRUCTION offset $rbp, -16 CFI_INSTRUCTION offset $rbp, -16
CFI_INSTRUCTION def_cfa_register $rsp CFI_INSTRUCTION def_cfa_register $rsp
$esi = MOV32ri 1 $esi = MOV32ri 1
$edx = MOV32ri 2 $edx = MOV32ri 2
$edi = MOV32ri 3 $edi = MOV32ri 3
$eax = MOV32ri 4 $eax = MOV32ri 4
RETQ RET64

llvm/test/CodeGen/X86/optimize-compare.mir

Show First 20 Lines • Show All 613 Lines • ▼ Show 20 Linesbody: |
; CHECK-NEXT: JMP_1 %bb.3 ; CHECK-NEXT: JMP_1 %bb.3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: JMP_1 %bb.3 ; CHECK-NEXT: JMP_1 %bb.3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3: ; CHECK-NEXT: bb.3:
; CHECK-NEXT: RETQ ; CHECK-NEXT: RET64
bb.0: bb.0:
%0:gr32 = COPY $eax %0:gr32 = COPY $eax
CMP32ri %0, 20, implicit-def $eflags CMP32ri %0, 20, implicit-def $eflags
JCC_1 %bb.1, 4, implicit $eflags JCC_1 %bb.1, 4, implicit $eflags
JMP_1 %bb.3 JMP_1 %bb.3
bb.1: bb.1:
; CMP can be removed when adjusting the JCC. ; CMP can be removed when adjusting the JCC.
CMP32ri %0, 21, implicit-def $eflags CMP32ri %0, 21, implicit-def $eflags
JCC_1 %bb.2, 13, implicit $eflags JCC_1 %bb.2, 13, implicit $eflags
JMP_1 %bb.3 JMP_1 %bb.3
bb.2: bb.2:
JMP_1 %bb.3 JMP_1 %bb.3
bb.3: bb.3:
RETQ RET64
... ...
--- ---
name: opt_adjusted_imm_multiple_blocks_noopt name: opt_adjusted_imm_multiple_blocks_noopt
body: | body: |
; CHECK-LABEL: name: opt_adjusted_imm_multiple_blocks_noopt ; CHECK-LABEL: name: opt_adjusted_imm_multiple_blocks_noopt
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000) ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
Show All 10 Linesbody: |
; CHECK-NEXT: JMP_1 %bb.3 ; CHECK-NEXT: JMP_1 %bb.3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $al = SETCCr 4, implicit $eflags ; CHECK-NEXT: $al = SETCCr 4, implicit $eflags
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3: ; CHECK-NEXT: bb.3:
; CHECK-NEXT: RETQ ; CHECK-NEXT: RET64
bb.0: bb.0:
%0:gr32 = COPY $eax %0:gr32 = COPY $eax
CMP32ri %0, 20, implicit-def $eflags CMP32ri %0, 20, implicit-def $eflags
JCC_1 %bb.1, 4, implicit $eflags JCC_1 %bb.1, 4, implicit $eflags
JMP_1 %bb.3 JMP_1 %bb.3
bb.1: bb.1:
; The following CMP should not be optimized because $eflags is live-out ; The following CMP should not be optimized because $eflags is live-out
CMP32ri %0, 21, implicit-def $eflags CMP32ri %0, 21, implicit-def $eflags
JCC_1 %bb.2, 13, implicit $eflags JCC_1 %bb.2, 13, implicit $eflags
JMP_1 %bb.3 JMP_1 %bb.3
bb.2: bb.2:
liveins: $eflags liveins: $eflags
$al = SETCCr 4, implicit $eflags $al = SETCCr 4, implicit $eflags
bb.3: bb.3:
RETQ RET64
... ...

llvm/test/CodeGen/X86/patchpoint-verifiable.mir

Show All 32 Lines bb.0.entry:
frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
CFI_INSTRUCTION offset $rbp, -16 CFI_INSTRUCTION offset $rbp, -16
$rbp = frame-setup MOV64rr $rsp $rbp = frame-setup MOV64rr $rsp
CFI_INSTRUCTION def_cfa_register $rbp CFI_INSTRUCTION def_cfa_register $rbp
; CHECK: PATCHPOINT 5, 5, 0, 2, 0, $rdi, $rsi, csr_64, implicit-def dead early-clobber $r11, implicit-def $rsp, implicit-def dead $rax ; CHECK: PATCHPOINT 5, 5, 0, 2, 0, $rdi, $rsi, csr_64, implicit-def dead early-clobber $r11, implicit-def $rsp, implicit-def dead $rax
PATCHPOINT 5, 5, 0, 2, 0, $rdi, $rsi, csr_64, implicit-def dead early-clobber $r11, implicit-def $rsp, implicit-def dead $rax PATCHPOINT 5, 5, 0, 2, 0, $rdi, $rsi, csr_64, implicit-def dead early-clobber $r11, implicit-def $rsp, implicit-def dead $rax
$rbp = POP64r implicit-def $rsp, implicit $rsp $rbp = POP64r implicit-def $rsp, implicit $rsp
RETQ RET64
... ...

llvm/test/CodeGen/X86/phielim-undef.mir

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Linesbody: |
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4: ; CHECK-NEXT: bb.4:
; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:gr16 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr16 = IMPLICIT_DEF
; CHECK-NEXT: JMP_1 %bb.2 ; CHECK-NEXT: JMP_1 %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5: ; CHECK-NEXT: bb.5:
; CHECK-NEXT: RETQ ; CHECK-NEXT: RET64
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6: ; CHECK-NEXT: bb.6:
bb.0: bb.0:
successors: %bb.6(0x40000000), %bb.1(0x40000000) successors: %bb.6(0x40000000), %bb.1(0x40000000)
%5:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @b114, $noreg %5:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @b114, $noreg
%6:gr16 = MOV16rm killed %5, 1, $noreg, 0, $noreg :: (load (s16) from @b114, align 1) %6:gr16 = MOV16rm killed %5, 1, $noreg, 0, $noreg :: (load (s16) from @b114, align 1)
TEST8ri undef %4:gr8, 1, implicit-def $eflags TEST8ri undef %4:gr8, 1, implicit-def $eflags
Show All 22 Lines bb.4:
JCC_1 %bb.7, 5, implicit killed $eflags JCC_1 %bb.7, 5, implicit killed $eflags
bb.5: bb.5:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
JMP_1 %bb.2 JMP_1 %bb.2
bb.6: bb.6:
RETQ RET64
bb.7: bb.7:
... ...

llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir

Show First 20 Lines • Show All 324 Lines • ▼ Show 20 Linesbody: |
bb.3: bb.3:
liveins: $rbp liveins: $rbp
$rsp = ADD64ri8 $rsp, 16, implicit-def dead $eflags $rsp = ADD64ri8 $rsp, 16, implicit-def dead $eflags
$rbx = POP64r implicit-def $rsp, implicit $rsp $rbx = POP64r implicit-def $rsp, implicit $rsp
$r14 = POP64r implicit-def $rsp, implicit $rsp $r14 = POP64r implicit-def $rsp, implicit $rsp
$rbp = POP64r implicit-def $rsp, implicit $rsp $rbp = POP64r implicit-def $rsp, implicit $rsp
RETQ RET64
... ...

llvm/test/CodeGen/X86/prologue-epilogue-remarks.mir

Show All 17 Lines
# CHECK-NEXT: Args: # CHECK-NEXT: Args:
# CHECK-NEXT: - NumStackBytes: '8' # CHECK-NEXT: - NumStackBytes: '8'
# CHECK-NEXT: - String: ' stack bytes in function' # CHECK-NEXT: - String: ' stack bytes in function'
# CHECK-NEXT: ... # CHECK-NEXT: ...
constants: constants:
body: | body: |
bb.0: bb.0:
RETQ RET64
... ...
--- ---
name: fun1 name: fun1
stack: stack:
- { id: 0, type: default, offset: 0, size: 19, alignment: 4 } - { id: 0, type: default, offset: 0, size: 19, alignment: 4 }
# --- !Analysis # --- !Analysis
# CHECK: Pass: prologepilog # CHECK: Pass: prologepilog
# CHECK-NEXT: Name: StackSize # CHECK-NEXT: Name: StackSize
# CHECK-NEXT: Function: fun1 # CHECK-NEXT: Function: fun1
# CHECK-NEXT: Args: # CHECK-NEXT: Args:
# CHECK-NEXT: - NumStackBytes: '20' # CHECK-NEXT: - NumStackBytes: '20'
# CHECK-NEXT: - String: ' stack bytes in function' # CHECK-NEXT: - String: ' stack bytes in function'
# CHECK-NEXT: ... # CHECK-NEXT: ...
constants: constants:
body: | body: |
bb.0: bb.0:
RETQ RET64
... ...
--- ---
name: fun2 name: fun2
stack: stack:
- { id: 0, type: default, offset: 0, size: 1024, alignment: 8 } - { id: 0, type: default, offset: 0, size: 1024, alignment: 8 }
# --- !Analysis # --- !Analysis
# CHECK: Pass: prologepilog # CHECK: Pass: prologepilog
# CHECK-NEXT: Name: StackSize # CHECK-NEXT: Name: StackSize
# CHECK-NEXT: Function: fun2 # CHECK-NEXT: Function: fun2
# CHECK-NEXT: Args: # CHECK-NEXT: Args:
# CHECK-NEXT: - NumStackBytes: '1024' # CHECK-NEXT: - NumStackBytes: '1024'
# CHECK-NEXT: - String: ' stack bytes in function' # CHECK-NEXT: - String: ' stack bytes in function'
# CHECK-NEXT: ... # CHECK-NEXT: ...
constants: constants:
body: | body: |
bb.0: bb.0:
RETQ RET64
... ...

llvm/test/CodeGen/X86/scavenger.mir

Show All 30 Lines bb.0:
%1 = ADD32ri8 %1, 5, implicit-def dead $eflags %1 = ADD32ri8 %1, 5, implicit-def dead $eflags
NOOP implicit $ebp NOOP implicit $ebp
; CHECK: NOOP implicit killed [[REG2]] ; CHECK: NOOP implicit killed [[REG2]]
; CHECK: NOOP implicit killed [[REG1]] ; CHECK: NOOP implicit killed [[REG1]]
NOOP implicit %2 NOOP implicit %2
NOOP implicit %1 NOOP implicit %1
RETQ $eax RET64 $eax
... ...
--- ---
# CHECK-LABEL: name: func3 # CHECK-LABEL: name: func3
name: func3 name: func3
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
; CHECK: dead {{\$e[a-z]+}} = MOV32ri 42 ; CHECK: dead {{\$e[a-z]+}} = MOV32ri 42
dead %0 : gr32 = MOV32ri 42 dead %0 : gr32 = MOV32ri 42
... ...

llvm/test/CodeGen/X86/tail-merge-after-mbp.mir

Show All 18 Linesbody: |
; CHECK: JCC_1 %bb.1, 4, implicit $eflags ; CHECK: JCC_1 %bb.1, 4, implicit $eflags
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000) ; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000)
; CHECK: CMP64mi8 killed $rax, 1, $noreg, 8, $noreg, 0, implicit-def $eflags :: (load (s64)) ; CHECK: CMP64mi8 killed $rax, 1, $noreg, 8, $noreg, 0, implicit-def $eflags :: (load (s64))
; CHECK: JCC_1 %bb.6, 4, implicit $eflags ; CHECK: JCC_1 %bb.6, 4, implicit $eflags
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: $ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags ; CHECK: $ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags
; CHECK: dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al ; CHECK: dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al
; CHECK: RETQ $eax ; CHECK: RET64 $eax
; CHECK: bb.6: ; CHECK: bb.6:
; CHECK: successors: %bb.1(0x30000000), %bb.7(0x50000000) ; CHECK: successors: %bb.1(0x30000000), %bb.7(0x50000000)
; CHECK: $rax = MOV64rm $r14, 1, $noreg, 0, $noreg :: (load (s64)) ; CHECK: $rax = MOV64rm $r14, 1, $noreg, 0, $noreg :: (load (s64))
; CHECK: TEST64rr $rax, $rax, implicit-def $eflags ; CHECK: TEST64rr $rax, $rax, implicit-def $eflags
; CHECK: JCC_1 %bb.1, 4, implicit $eflags ; CHECK: JCC_1 %bb.1, 4, implicit $eflags
; CHECK: bb.7 (align 16): ; CHECK: bb.7 (align 16):
; CHECK: successors: %bb.8(0x71555555), %bb.4(0x0eaaaaab) ; CHECK: successors: %bb.8(0x71555555), %bb.4(0x0eaaaaab)
; CHECK: CMP64mi8 killed $rax, 1, $noreg, 8, $noreg, 0, implicit-def $eflags :: (load (s64)), (load (s64)) ; CHECK: CMP64mi8 killed $rax, 1, $noreg, 8, $noreg, 0, implicit-def $eflags :: (load (s64)), (load (s64))
; CHECK: JCC_1 %bb.4, 5, implicit $eflags ; CHECK: JCC_1 %bb.4, 5, implicit $eflags
; CHECK: bb.8: ; CHECK: bb.8:
; CHECK: successors: %bb.1(0x04000000), %bb.7(0x7c000000) ; CHECK: successors: %bb.1(0x04000000), %bb.7(0x7c000000)
; CHECK: $rax = MOV64rm $r14, 1, $noreg, 0, $noreg :: (load (s64)) ; CHECK: $rax = MOV64rm $r14, 1, $noreg, 0, $noreg :: (load (s64))
; CHECK: TEST64rr $rax, $rax, implicit-def $eflags ; CHECK: TEST64rr $rax, $rax, implicit-def $eflags
; CHECK: JCC_1 %bb.7, 5, implicit $eflags ; CHECK: JCC_1 %bb.7, 5, implicit $eflags
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: $ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags ; CHECK: $ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags
; CHECK: RETQ $eax ; CHECK: RET64 $eax
bb.0: bb.0:
successors: %bb.1(0x40000000), %bb.7(0x40000000) successors: %bb.1(0x40000000), %bb.7(0x40000000)
TEST8ri $dl, 1, implicit-def $eflags, implicit killed $edx TEST8ri $dl, 1, implicit-def $eflags, implicit killed $edx
JCC_1 %bb.7, 4, implicit $eflags JCC_1 %bb.7, 4, implicit $eflags
bb.1: bb.1:
successors: %bb.16(0x80000000) successors: %bb.16(0x80000000)
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Linesbody: |
bb.15: bb.15:
successors: %bb.16(0x80000000) successors: %bb.16(0x80000000)
$ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags $ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags
dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al
bb.16: bb.16:
RETQ $eax RET64 $eax
... ...

llvm/test/CodeGen/X86/tied-depbreak.mir

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines bb.0:
$eax = MOV32rr $esi $eax = MOV32rr $esi
$eax = LEA64_32r $rdi, 1, $rsi, 0, $noreg $eax = LEA64_32r $rdi, 1, $rsi, 0, $noreg
$edi = MOV32rr $esi $edi = MOV32rr $esi
$esi = MOV32ri 4 $esi = MOV32ri 4
; Verify that XOR is untouched by the dependency breaker ; Verify that XOR is untouched by the dependency breaker
; CHECK: $esi = XOR32rr undef $esi, undef $esi, implicit-def dead $eflags, implicit-def $rsi ; CHECK: $esi = XOR32rr undef $esi, undef $esi, implicit-def dead $eflags, implicit-def $rsi
$esi = XOR32rr undef $esi, undef $esi, implicit-def dead $eflags, implicit-def $rsi $esi = XOR32rr undef $esi, undef $esi, implicit-def dead $eflags, implicit-def $rsi
RETQ killed $eax RET64 killed $eax
... ...

llvm/test/CodeGen/X86/twoaddr-dbg-value.mir

# RUN: llc -run-pass=livevars,twoaddressinstruction -mtriple=x86_64-- -o - %s | FileCheck %s # RUN: llc -run-pass=livevars,twoaddressinstruction -mtriple=x86_64-- -o - %s | FileCheck %s
--- ---
name: foo name: foo
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $edi liveins: $edi
%0:gr32 = COPY killed $edi %0:gr32 = COPY killed $edi
%1:gr32 = COPY killed %0 %1:gr32 = COPY killed %0
%4:gr32 = XOR32ri8 %1, 1, implicit-def dead $eflags %4:gr32 = XOR32ri8 %1, 1, implicit-def dead $eflags
DBG_VALUE %4 DBG_VALUE %4
%5:gr32 = COPY %4 %5:gr32 = COPY %4
PUSH32r killed %1, implicit-def $esp, implicit $esp PUSH32r killed %1, implicit-def $esp, implicit $esp
$eax = COPY killed %5 $eax = COPY killed %5
RETQ implicit killed $eax RET64 implicit killed $eax
... ...
# Verify that the DBG_VALUE instruction does not inhibit # Verify that the DBG_VALUE instruction does not inhibit
# TwoAddressInstructionPass::rescheduleMIBelowKill optimization # TwoAddressInstructionPass::rescheduleMIBelowKill optimization
# CHECK: PUSH32r %1, implicit-def $esp, implicit $esp # CHECK: PUSH32r %1, implicit-def $esp, implicit $esp
# CHECK-NEXT: %2:gr32 = COPY killed %1 # CHECK-NEXT: %2:gr32 = COPY killed %1
# CHECK-NEXT: %2:gr32 = XOR32ri8 %2, 1, implicit-def dead $eflags # CHECK-NEXT: %2:gr32 = XOR32ri8 %2, 1, implicit-def dead $eflags
# CHECK-NEXT: DBG_VALUE %2 # CHECK-NEXT: DBG_VALUE %2
# CHECK-NEXT: %3:gr32 = COPY killed %2 # CHECK-NEXT: %3:gr32 = COPY killed %2

llvm/test/CodeGen/X86/update-terminator.mir

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Linesbody: |
bb.3: bb.3:
successors: %bb.2(100) successors: %bb.2(100)
CALL64pcrel32 @dummy3, csr_64, implicit $rsp, implicit-def $rsp CALL64pcrel32 @dummy3, csr_64, implicit $rsp, implicit-def $rsp
CALL64pcrel32 @dummy3, csr_64, implicit $rsp, implicit-def $rsp CALL64pcrel32 @dummy3, csr_64, implicit $rsp, implicit-def $rsp
CALL64pcrel32 @dummy3, csr_64, implicit $rsp, implicit-def $rsp CALL64pcrel32 @dummy3, csr_64, implicit $rsp, implicit-def $rsp
JMP_1 %bb.2 JMP_1 %bb.2
bb.4: bb.4:
RETQ RET64
... ...

llvm/test/CodeGen/X86/win64-eh-empty-block-2.mir

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines bb.5.if.end6:
TEST8rr killed renamable $r8b, renamable $r8b, implicit-def $eflags TEST8rr killed renamable $r8b, renamable $r8b, implicit-def $eflags
JCC_1 %bb.6, 5, implicit $eflags JCC_1 %bb.6, 5, implicit $eflags
bb.8.return (address-taken): bb.8.return (address-taken):
$eax = MOV32rm $rbp, 1, $noreg, -12, $noreg :: (load (s32) from %stack.0) $eax = MOV32rm $rbp, 1, $noreg, -12, $noreg :: (load (s32) from %stack.0)
SEH_Epilogue SEH_Epilogue
$rsp = frame-destroy ADD64ri8 $rsp, 48, implicit-def dead $eflags $rsp = frame-destroy ADD64ri8 $rsp, 48, implicit-def dead $eflags
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp
RETQ $eax RET64 $eax
bb.1.if.then: bb.1.if.then:
successors: %bb.2(0x7ffff800), %bb.7(0x00000800) successors: %bb.2(0x7ffff800), %bb.7(0x00000800)
EH_LABEL <mcsymbol .Leh1> EH_LABEL <mcsymbol .Leh1>
CALL64pcrel32 @mythrow, csr_win64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp CALL64pcrel32 @mythrow, csr_win64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp
EH_LABEL <mcsymbol .Leh2> EH_LABEL <mcsymbol .Leh2>
JMP_1 %bb.2 JMP_1 %bb.2
Show All 39 Lines

llvm/test/CodeGen/X86/xray-multiplerets-in-blocks.mir

Show All 15 Lines
name: foo name: foo
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$edi'} - { reg: '$edi'}
body: | body: |
bb.0: bb.0:
liveins: $edi liveins: $edi
; CHECK: PATCHABLE_FUNCTION_ENTER ; CHECK: PATCHABLE_FUNCTION_ENTER
RETQ RET64
; CHECK-NEXT: PATCHABLE_RET ; CHECK-NEXT: PATCHABLE_RET
RETQ RET64
; CHECK-NEXT: PATCHABLE_RET ; CHECK-NEXT: PATCHABLE_RET
... ...

llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $edi liveins: $edi
DBG_PHI $edi, 1 DBG_PHI $edi, 1
DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13 DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13
renamable $rax = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @someglobal, $noreg, debug-location !13 :: (load (s64) from got) renamable $rax = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @someglobal, $noreg, debug-location !13 :: (load (s64) from got)
MOV8mr killed renamable $rax, 1, $noreg, 0, $noreg, renamable $dil, debug-location !13 :: (store (s8) into @someglobal) MOV8mr killed renamable $rax, 1, $noreg, 0, $noreg, renamable $dil, debug-location !13 :: (store (s8) into @someglobal)
RETQ debug-location !13 RET64 debug-location !13
... ...

llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir

Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines bb.2.if.end:
CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !24 CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !24
$eax = MOV32rr $ebx, implicit killed $rbx, debug-location !26 $eax = MOV32rr $ebx, implicit killed $rbx, debug-location !26
$rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !26 $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !26
CFI_INSTRUCTION def_cfa_offset 24, debug-location !26 CFI_INSTRUCTION def_cfa_offset 24, debug-location !26
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !26 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !26
CFI_INSTRUCTION def_cfa_offset 16, debug-location !26 CFI_INSTRUCTION def_cfa_offset 16, debug-location !26
$r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !26 $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !26
CFI_INSTRUCTION def_cfa_offset 8, debug-location !26 CFI_INSTRUCTION def_cfa_offset 8, debug-location !26
RETQ implicit $eax, debug-location !26 RET64 implicit $eax, debug-location !26
... ...

llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir

Show First 20 Lines • Show All 188 Lines • ▼ Show 20 Lines bb.3.if.end:
CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !29 CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !29
$eax = MOV32rr $ebx, implicit killed $rbx, debug-location !31 $eax = MOV32rr $ebx, implicit killed $rbx, debug-location !31
$rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !31 $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !31
CFI_INSTRUCTION def_cfa_offset 24, debug-location !31 CFI_INSTRUCTION def_cfa_offset 24, debug-location !31
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31
CFI_INSTRUCTION def_cfa_offset 16, debug-location !31 CFI_INSTRUCTION def_cfa_offset 16, debug-location !31
$r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31 $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31
CFI_INSTRUCTION def_cfa_offset 8, debug-location !31 CFI_INSTRUCTION def_cfa_offset 8, debug-location !31
RETQ implicit $eax, debug-location !31 RET64 implicit $eax, debug-location !31
... ...

llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir

Show First 20 Lines • Show All 194 Lines • ▼ Show 20 Lines bb.4:
CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !29 CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !29
$eax = MOV32rr $ebx, implicit killed $rbx, debug-location !31 $eax = MOV32rr $ebx, implicit killed $rbx, debug-location !31
$rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !31 $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !31
CFI_INSTRUCTION def_cfa_offset 24, debug-location !31 CFI_INSTRUCTION def_cfa_offset 24, debug-location !31
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31
CFI_INSTRUCTION def_cfa_offset 16, debug-location !31 CFI_INSTRUCTION def_cfa_offset 16, debug-location !31
$r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31 $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31
CFI_INSTRUCTION def_cfa_offset 8, debug-location !31 CFI_INSTRUCTION def_cfa_offset 8, debug-location !31
RETQ implicit $eax, debug-location !31 RET64 implicit $eax, debug-location !31
... ...

llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir

Show First 20 Lines • Show All 322 Lines • ▼ Show 20 Lines bb.10.while.body.i.i625:
$r13 = frame-destroy POP64r implicit-def $rsp, implicit $rsp $r13 = frame-destroy POP64r implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 32 CFI_INSTRUCTION def_cfa_offset 32
$r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 24 CFI_INSTRUCTION def_cfa_offset 24
$r15 = frame-destroy POP64r implicit-def $rsp, implicit $rsp $r15 = frame-destroy POP64r implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 8 CFI_INSTRUCTION def_cfa_offset 8
RETQ RET64
... ...

llvm/test/DebugInfo/MIR/InstrRef/ignore-dbg-value-list.mir

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines bb.1:
$rbx = MOV64ri 0, debug-location !13 $rbx = MOV64ri 0, debug-location !13
DBG_VALUE_LIST !12, !DIExpression(), $rax, $rbx, debug-location !13 DBG_VALUE_LIST !12, !DIExpression(), $rax, $rbx, debug-location !13
; CHECK: DBG_VALUE_LIST ; CHECK: DBG_VALUE_LIST
$rbx = COPY killed $rax, debug-location !13 $rbx = COPY killed $rax, debug-location !13
$rax = MOV64ri 0, debug-location !13 $rax = MOV64ri 0, debug-location !13
; This clobber of $rax might cause LDV to re-issue a DBG_VALUE stating the ; This clobber of $rax might cause LDV to re-issue a DBG_VALUE stating the
; variable location as $rbx. However, the preceeding DBG_VALUE_LIST should ; variable location as $rbx. However, the preceeding DBG_VALUE_LIST should
; terminate the earlier location. ; terminate the earlier location.
RETQ implicit $rbx, debug-location !13 RET64 implicit $rbx, debug-location !13
... ...

llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir

# RUN: llc %s -march=x86-64 -run-pass=machineverifier -o - -experimental-debug-variable-locations | FileCheck %s # RUN: llc %s -march=x86-64 -run-pass=machineverifier -o - -experimental-debug-variable-locations | FileCheck %s
# #
# REQUIRES: x86-registered-target # REQUIRES: x86-registered-target
# #
# CHECK: MOV64rr $rdi, debug-instr-number 1 # CHECK: MOV64rr $rdi, debug-instr-number 1
--- ---
name: test name: test
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi', virtual-reg: '' } - { reg: '$rdi', virtual-reg: '' }
body: | body: |
bb.0: bb.0:
liveins: $rdi, $rax liveins: $rdi, $rax
$rbp = MOV64rr $rdi, debug-instr-number 1 $rbp = MOV64rr $rdi, debug-instr-number 1
dead $rcx = MOV64ri 0 dead $rcx = MOV64ri 0
CMP64ri8 renamable $rax, 1, implicit-def $eflags CMP64ri8 renamable $rax, 1, implicit-def $eflags
RETQ $rax RET64 $rax
... ...

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir

Show First 20 Lines • Show All 148 Lines • ▼ Show 20 Linesbody: |
bb.13: bb.13:
; Live in, ; Live in,
; CHECK: DBG_VALUE $rax, $noreg ; CHECK: DBG_VALUE $rax, $noreg
$rbx = MOV64ri 11, debug-instr-number 10, debug-location !17 $rbx = MOV64ri 11, debug-instr-number 10, debug-location !17
; This is instruction 10 referred to in bb.10. However, as the variable ; This is instruction 10 referred to in bb.10. However, as the variable
; location/value has been modified in the meantime, no DBG_VALUE should be ; location/value has been modified in the meantime, no DBG_VALUE should be
; generated here. ; generated here.
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Lines bb.0.entry:
;; Similarly, with a register mask ;; Similarly, with a register mask
$ebx = COPY $eax $ebx = COPY $eax
CALL64pcrel32 @use, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, debug-location !17 CALL64pcrel32 @use, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, debug-location !17
; CHECK-NEXT: $ebx = COPY $eax ; CHECK-NEXT: $ebx = COPY $eax
; CHECK-NEXT: CALL64pcrel32 ; CHECK-NEXT: CALL64pcrel32
; CHECK-NEXT: DBG_VALUE $ebx ; CHECK-NEXT: DBG_VALUE $ebx
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines liveins: $rdi, $rax, $rbx
; Clobber other registers that contain the value we're to track. ; Clobber other registers that contain the value we're to track.
MOV64mr $rsp, 1, $noreg, 16, $noreg, $rbx :: (store 8 into %stack.0) MOV64mr $rsp, 1, $noreg, 16, $noreg, $rbx :: (store 8 into %stack.0)
$rax = MOV64ri 0 $rax = MOV64ri 0
$rdi = MOV64ri 0 $rdi = MOV64ri 0
DBG_INSTR_REF 1, 0, !11, !DIExpression(), debug-location !12 DBG_INSTR_REF 1, 0, !11, !DIExpression(), debug-location !12
; CHECK: DBG_INSTR_REF ; CHECK: DBG_INSTR_REF
; CHECK-NEXT: DBG_VALUE $esi ; CHECK-NEXT: DBG_VALUE $esi
RETQ $rsi, debug-location !12 RET64 $rsi, debug-location !12
... ...

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir

Show First 20 Lines • Show All 99 Lines • ▼ Show 20 Lines liveins: $rdi, $rax
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE $noreg
DBG_INSTR_REF 8, 0, !11, !DIExpression(), debug-location !12 DBG_INSTR_REF 8, 0, !11, !DIExpression(), debug-location !12
; CHECK-NEXT: DBG_INSTR_REF 8, 0 ; CHECK-NEXT: DBG_INSTR_REF 8, 0
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE $noreg
DBG_INSTR_REF 13, 0, !11, !DIExpression(), debug-location !12 DBG_INSTR_REF 13, 0, !11, !DIExpression(), debug-location !12
; CHECK-NEXT: DBG_INSTR_REF 13, 0 ; CHECK-NEXT: DBG_INSTR_REF 13, 0
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE $noreg
$rax = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0) $rax = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
RETQ $rax, debug-location !12 RET64 $rax, debug-location !12
... ...

llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines liveins: $rdi, $rax
;; Overwrite the stack: LiveDebugValues should explicitly undef the stack ;; Overwrite the stack: LiveDebugValues should explicitly undef the stack
;; location with DBG_VALUE $noreg, as DbgEntityHistoryCalculator doesn't ;; location with DBG_VALUE $noreg, as DbgEntityHistoryCalculator doesn't
;; look at the stack. ;; look at the stack.
INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-location !DILocation(line: 0, scope: !7) :: (store (s32) into %stack.0) INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-location !DILocation(line: 0, scope: !7) :: (store (s32) into %stack.0)
; CHECK: INC32m $rsp ; CHECK: INC32m $rsp
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE $noreg
$rax = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0) $rax = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
RETQ $rax, debug-location !12 RET64 $rax, debug-location !12
... ...

llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir

Show All 30 Lines
liveins: liveins:
- { reg: '$rdi', virtual-reg: '' } - { reg: '$rdi', virtual-reg: '' }
body: | body: |
bb.0: bb.0:
liveins: $rdi, $rax liveins: $rdi, $rax
$rbp = MOV64rr $rdi, debug-instr-number 1, debug-location !12 $rbp = MOV64rr $rdi, debug-instr-number 1, debug-location !12
dead $rcx = MOV64ri 0, debug-instr-number 1, debug-location !12 dead $rcx = MOV64ri 0, debug-instr-number 1, debug-location !12
CMP64ri8 renamable $rax, 1, implicit-def $eflags CMP64ri8 renamable $rax, 1, implicit-def $eflags
RETQ $rax RET64 $rax
... ...

llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir

Show All 31 Linesliveins:
- { reg: '$rdi', virtual-reg: '' } - { reg: '$rdi', virtual-reg: '' }
body: | body: |
bb.0: bb.0:
liveins: $rdi, $rax liveins: $rdi, $rax
$rbp = MOV64rr $rdi, debug-instr-number 1, debug-location !12 $rbp = MOV64rr $rdi, debug-instr-number 1, debug-location !12
$ebp = KILL killed $rbp, debug-instr-number 2, debug-location !12 $ebp = KILL killed $rbp, debug-instr-number 2, debug-location !12
dead $rcx = MOV64ri 0 dead $rcx = MOV64ri 0
CMP64ri8 renamable $rax, 1, implicit-def $eflags CMP64ri8 renamable $rax, 1, implicit-def $eflags
RETQ $rax RET64 $rax
... ...

llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir

Show First 20 Lines • Show All 150 Lines • ▼ Show 20 Lines ; CHECK: DBG_PHI $bp, 1
%26:gr16 = COPY killed %29.sub_16bit, debug-location !13 %26:gr16 = COPY killed %29.sub_16bit, debug-location !13
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13 ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
%24:gr32 = MOVSX32rr16 %26, debug-location !13 %24:gr32 = MOVSX32rr16 %26, debug-location !13
$edi = COPY %24, debug-location !13 $edi = COPY %24, debug-location !13
CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $edi, debug-location !13 CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $edi, debug-location !13
ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13 ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
%23:gr32 = MOVSX32rr16 %26, debug-location !13 %23:gr32 = MOVSX32rr16 %26, debug-location !13
$eax = COPY %23, debug-location !13 $eax = COPY %23, debug-location !13
RETQ implicit $eax, debug-location !13 RET64 implicit $eax, debug-location !13
... ...

llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir

Show First 20 Lines • Show All 149 Lines • ▼ Show 20 Lines ; CHECK: DBG_PHI $rbx, 1
DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13 DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13
%14:gr64 = ADD64rr killed %2, %6, implicit-def $eflags, debug-location !13 %14:gr64 = ADD64rr killed %2, %6, implicit-def $eflags, debug-location !13
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13 ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
$rdi = COPY %14, debug-location !13 $rdi = COPY %14, debug-location !13
CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !13 CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !13
ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13 ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
%13:gr32 = COPY %14.sub_32bit, debug-location !13 %13:gr32 = COPY %14.sub_32bit, debug-location !13
$eax = COPY %13, debug-location !13 $eax = COPY %13, debug-location !13
RETQ implicit $eax, debug-location !13 RET64 implicit $eax, debug-location !13
... ...

llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Lines bb.5:
successors: %bb.5(0x7c000000), %bb.6(0x04000000) successors: %bb.5(0x7c000000), %bb.6(0x04000000)
liveins: $rdi, $rdx, $eflags liveins: $rdi, $rdx, $eflags
$rcx = MOV64rr $rdx, debug-location !22 $rcx = MOV64rr $rdx, debug-location !22
$rdx = MOV64ri 0 ; jmorse -- disabling this makes variable live-through $rdx = MOV64ri 0 ; jmorse -- disabling this makes variable live-through
JCC_1 %bb.5, 6, implicit $eflags, debug-location !22 JCC_1 %bb.5, 6, implicit $eflags, debug-location !22
bb.6: bb.6:
RETQ debug-location !22 RET64 debug-location !22
... ...

llvm/test/DebugInfo/MIR/InstrRef/restore-to-rsp-crash.mir

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $rax, $rbx liveins: $rax, $rbx
DBG_VALUE $rax, $noreg, !12, !DIExpression(), debug-location !13 DBG_VALUE $rax, $noreg, !12, !DIExpression(), debug-location !13
MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $rax :: (store 8 into %stack.0) MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $rax :: (store 8 into %stack.0)
$rsp = MOV64rm $rsp, 1, $noreg, 0, $noreg, debug-location !13 :: (load 8 from %stack.0) $rsp = MOV64rm $rsp, 1, $noreg, 0, $noreg, debug-location !13 :: (load 8 from %stack.0)
RETQ implicit $rbx, debug-location !13 RET64 implicit $rbx, debug-location !13
... ...

llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir

Show All 16 LinesdebugValueSubstitutions:
- { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 } - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 }
body: | body: |
bb.0: bb.0:
liveins: $rdi, $rax liveins: $rdi, $rax
$rbp = MOV64rr $rdi, debug-instr-number 2 $rbp = MOV64rr $rdi, debug-instr-number 2
DBG_INSTR_REF 1, 0 DBG_INSTR_REF 1, 0
dead $rcx = MOV64ri 0 dead $rcx = MOV64ri 0
CMP64ri8 renamable $rax, 1, implicit-def $eflags CMP64ri8 renamable $rax, 1, implicit-def $eflags
RETQ $rax RET64 $rax
... ...

llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir

Show All 35 Lines
# FASTREG-NEXT: CALL64pcrel32 # FASTREG-NEXT: CALL64pcrel32
# FASTREG-LABEL: bb.3: # FASTREG-LABEL: bb.3:
# FASTREG-DAG: MOV32rm # FASTREG-DAG: MOV32rm
# FASTREG-DAG: DBG_INSTR_REF 4, 0 # FASTREG-DAG: DBG_INSTR_REF 4, 0
# FASTREG-DAG: MOV32mr # FASTREG-DAG: MOV32mr
# FASTREG-NEXT: JMP_1 # FASTREG-NEXT: JMP_1
# FASTREG-LABEL: bb.4: # FASTREG-LABEL: bb.4:
# FASTREG: DBG_INSTR_REF 5, 0 # FASTREG: DBG_INSTR_REF 5, 0
# FASTREG-NEXT: RETQ # FASTREG-NEXT: RET64
--- | --- |
; ModuleID = 'tmp.ll' ; ModuleID = 'tmp.ll'
source_filename = "tmp.ll" source_filename = "tmp.ll"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
%struct.a = type { i32 } %struct.a = type { i32 }
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Linesbody: |
bb.3: bb.3:
%6:gr32 = MOV32rm %3, 1, $noreg, 0, $noreg, debug-location !17 %6:gr32 = MOV32rm %3, 1, $noreg, 0, $noreg, debug-location !17
DBG_INSTR_REF 4, 0, !9, !DIExpression(), debug-location !16 DBG_INSTR_REF 4, 0, !9, !DIExpression(), debug-location !16
JMP_1 %bb.2 JMP_1 %bb.2
bb.4: bb.4:
$eax = COPY %5, debug-location !18 $eax = COPY %5, debug-location !18
DBG_INSTR_REF 5, 0, !9, !DIExpression(), debug-location !16 DBG_INSTR_REF 5, 0, !9, !DIExpression(), debug-location !16
RETQ implicit $eax, debug-location !18 RET64 implicit $eax, debug-location !18
... ...

llvm/test/DebugInfo/MIR/InstrRef/x86-fixup-bw-inst-subreb.mir

Show All 22 Lines
## Subreg 4 -> sub_16bit ## Subreg 4 -> sub_16bit
body: | body: |
bb.0: bb.0:
liveins: $rax liveins: $rax
$ax = MOV16rm killed $rax, 1, $noreg, 0, $noreg, debug-instr-number 1 $ax = MOV16rm killed $rax, 1, $noreg, 0, $noreg, debug-instr-number 1
; CHECK: $eax = MOVZX32rm16 killed $rax, {{.*}} debug-instr-number 2 ; CHECK: $eax = MOVZX32rm16 killed $rax, {{.*}} debug-instr-number 2
RETQ $ax RET64 $ax
... ...
--- ---
# CHECK-LABEL: name: test3 # CHECK-LABEL: name: test3
name: test3 name: test3
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
Show All 10 Lines bb.0:
JCC_1 %bb.1, 4, implicit $eflags JCC_1 %bb.1, 4, implicit $eflags
bb.2: bb.2:
liveins: $rdi liveins: $rdi
$ax = MOV16rm killed $rdi, 1, $noreg, 0, $noreg, implicit-def $eax, debug-instr-number 1 $ax = MOV16rm killed $rdi, 1, $noreg, 0, $noreg, implicit-def $eax, debug-instr-number 1
; CHECK: $eax = MOVZX32rm16 killed $rdi, {{.*}} debug-instr-number 2 ; CHECK: $eax = MOVZX32rm16 killed $rdi, {{.*}} debug-instr-number 2
$ax = KILL $ax, implicit killed $eax $ax = KILL $ax, implicit killed $eax
RETQ $ax RET64 $ax
bb.1: bb.1:
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
$ax = KILL $ax, implicit killed $eax $ax = KILL $ax, implicit killed $eax
RETQ $ax RET64 $ax
... ...

llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir

Show All 12 Lines
# CHECK: debugValueSubstitutions: # CHECK: debugValueSubstitutions:
# CHECK-NAME: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 } # CHECK-NAME: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 }
body: | body: |
bb.0: bb.0:
liveins: $eax, $ebp liveins: $eax, $ebp
; CHECK: $eax = ADD32ri8 {{.*}} debug-instr-number 2 ; CHECK: $eax = ADD32ri8 {{.*}} debug-instr-number 2
$eax = LEA32r killed $eax, 1, killed $ebp, -5, $noreg, debug-instr-number 1 $eax = LEA32r killed $eax, 1, killed $ebp, -5, $noreg, debug-instr-number 1
RETQ $eax RET64 $eax
... ...
--- ---
name: test1mov1add_ebp_32 name: test1mov1add_ebp_32
# CHECK-LABEL: name: test1mov1add_ebp_32 # CHECK-LABEL: name: test1mov1add_ebp_32
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$eax' } - { reg: '$eax' }
- { reg: '$ebx' } - { reg: '$ebx' }
- { reg: '$ebp' } - { reg: '$ebp' }
# CHECK: debugValueSubstitutions: # CHECK: debugValueSubstitutions:
# CHECK-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 } # CHECK-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 }
body: | body: |
bb.0: bb.0:
liveins: $eax, $ebp, $ebx liveins: $eax, $ebp, $ebx
; CHECK: $ebx = ADD32rr {{.*}} debug-instr-number 2 ; CHECK: $ebx = ADD32rr {{.*}} debug-instr-number 2
$ebx = LEA32r killed $ebp, 1, $ebp, 0, $noreg, debug-instr-number 1 $ebx = LEA32r killed $ebp, 1, $ebp, 0, $noreg, debug-instr-number 1
RETQ $ebx RET64 $ebx
... ...
--- ---
name: testleaadd_ebp_index_32 name: testleaadd_ebp_index_32
# CHECK-LABEL: name: testleaadd_ebp_index_32 # CHECK-LABEL: name: testleaadd_ebp_index_32
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$ebx' } - { reg: '$ebx' }
- { reg: '$ebp' } - { reg: '$ebp' }
# CHECK: debugValueSubstitutions: # CHECK: debugValueSubstitutions:
# CHECK-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 } # CHECK-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 }
body: | body: |
bb.0: bb.0:
liveins: $eax, $ebp, $ebx liveins: $eax, $ebp, $ebx
; CHECK: $ebx = ADD32rr {{.*}} debug-instr-number 2 ; CHECK: $ebx = ADD32rr {{.*}} debug-instr-number 2
$ebx = LEA32r $ebp, 1, $ebp, 5, $noreg, debug-instr-number 1 $ebx = LEA32r $ebp, 1, $ebp, 5, $noreg, debug-instr-number 1
RETQ $ebx RET64 $ebx
... ...

llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir

Show All 18 Lines
# COREI7: debugValueSubstitutions: # COREI7: debugValueSubstitutions:
# COREI7-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 } # COREI7-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 }
body: | body: |
bb.0: bb.0:
liveins: $rax, $rbp liveins: $rax, $rbp
$ebp = LEA64_32r killed $rbp, 1, killed $rax, 0, $noreg, debug-instr-number 1 $ebp = LEA64_32r killed $rbp, 1, killed $rax, 0, $noreg, debug-instr-number 1
; COREI7: ADD32rr {{.*}} debug-instr-number 2 ; COREI7: ADD32rr {{.*}} debug-instr-number 2
RETQ $ebp RET64 $ebp
... ...
--- ---
name: test_mul_spec name: test_mul_spec
# HASWELL-LABEL: name: test_mul_spec # HASWELL-LABEL: name: test_mul_spec
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
Show All 10 Lines bb.0:
liveins: $edi liveins: $edi
renamable $edi = KILL $edi, implicit-def $rdi renamable $edi = KILL $edi, implicit-def $rdi
renamable $ecx = nsw LEA64_32r renamable $rdi, 8, renamable $rdi, 42, $noreg, debug-instr-number 1 renamable $ecx = nsw LEA64_32r renamable $rdi, 8, renamable $rdi, 42, $noreg, debug-instr-number 1
; HASWELL: ADD32ri8 {{.*}} debug-instr-number 3 ; HASWELL: ADD32ri8 {{.*}} debug-instr-number 3
renamable $eax = nsw LEA64_32r killed renamable $rdi, 4, renamable $rdi, 2, $noreg, debug-instr-number 2 renamable $eax = nsw LEA64_32r killed renamable $rdi, 4, renamable $rdi, 2, $noreg, debug-instr-number 2
; HASWELL: ADD32ri8 {{.*}} debug-instr-number 4 ; HASWELL: ADD32ri8 {{.*}} debug-instr-number 4
renamable $eax = nsw IMUL32rr killed renamable $eax, killed renamable $ecx, implicit-def dead $eflags renamable $eax = nsw IMUL32rr killed renamable $eax, killed renamable $ecx, implicit-def dead $eflags
RETQ $eax RET64 $eax
... ...
--- ---
name: testthree name: testthree
# ATOM-LABEL: name: testthree # ATOM-LABEL: name: testthree
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
frameInfo: frameInfo:
maxAlignment: 1 maxAlignment: 1
maxCallFrameSize: 0 maxCallFrameSize: 0
machineFunctionInfo: {} machineFunctionInfo: {}
# ATOM: debugValueSubstitutions: # ATOM: debugValueSubstitutions:
# ATOM-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 } # ATOM-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 }
body: | body: |
bb.0.entry: bb.0.entry:
renamable $ecx = MOV32ri 0 renamable $ecx = MOV32ri 0
renamable $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags renamable $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
renamable $ecx = nsw ADD32rr renamable $ecx, renamable $eax, implicit-def dead $eflags, implicit killed $rax, implicit killed $rcx, implicit-def $rcx, debug-instr-number 1 renamable $ecx = nsw ADD32rr renamable $ecx, renamable $eax, implicit-def dead $eflags, implicit killed $rax, implicit killed $rcx, implicit-def $rcx, debug-instr-number 1
; ATOM: LEA64_32r {{.*}} debug-instr-number 2 ; ATOM: LEA64_32r {{.*}} debug-instr-number 2
renamable $eax = MOV32rm killed renamable $rcx, 1, $noreg, 0, $noreg :: (load (s32) from `i32 *undef`) renamable $eax = MOV32rm killed renamable $rcx, 1, $noreg, 0, $noreg :: (load (s32) from `i32 *undef`)
RETQ $eax RET64 $eax
... ...

llvm/test/DebugInfo/MIR/X86/backup-entry-values-usage.mir

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines bb.0.entry:
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
MOV32mr $rip, 1, $noreg, @side_effect, $noreg, killed renamable $edi, debug-location !15 :: (store 4 into @side_effect, !tbaa !16) MOV32mr $rip, 1, $noreg, @side_effect, $noreg, killed renamable $edi, debug-location !15 :: (store 4 into @side_effect, !tbaa !16)
renamable $edi = MOV32rm $rip, 1, $noreg, @value, $noreg, debug-location !20 :: (dereferenceable load 4 from @value, !tbaa !16) renamable $edi = MOV32rm $rip, 1, $noreg, @value, $noreg, debug-location !20 :: (dereferenceable load 4 from @value, !tbaa !16)
DBG_VALUE $edi, $noreg, !13, !DIExpression(), debug-location !14 DBG_VALUE $edi, $noreg, !13, !DIExpression(), debug-location !14
CALL64pcrel32 @bar, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, debug-location !21 CALL64pcrel32 @bar, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, debug-location !21
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !22 $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !22
$rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !22 $rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !22
CFI_INSTRUCTION def_cfa_offset 8, debug-location !22 CFI_INSTRUCTION def_cfa_offset 8, debug-location !22
RETQ killed $eax, debug-location !22 RET64 killed $eax, debug-location !22
... ...

llvm/test/DebugInfo/MIR/X86/bit-piece-dh.mir

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines bb.0.entry:
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
CFI_INSTRUCTION offset $rbp, -16 CFI_INSTRUCTION offset $rbp, -16
$rbp = frame-setup MOV64rr $rsp $rbp = frame-setup MOV64rr $rsp
CFI_INSTRUCTION def_cfa_register $rbp CFI_INSTRUCTION def_cfa_register $rbp
DBG_VALUE $dh, _, !14, !15, debug-location !16 DBG_VALUE $dh, _, !14, !15, debug-location !16
$edi = SHR32ri killed $edi, 8, implicit-def dead $eflags, debug-location !17 $edi = SHR32ri killed $edi, 8, implicit-def dead $eflags, debug-location !17
$eax = MOVSX32rr8 $dil, implicit killed $edi, debug-location !20 $eax = MOVSX32rr8 $dil, implicit killed $edi, debug-location !20
$rbp = POP64r implicit-def $rsp, implicit $rsp, debug-location !20 $rbp = POP64r implicit-def $rsp, implicit $rsp, debug-location !20
RETQ $eax, debug-location !20 RET64 $eax, debug-location !20
... ...

llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir

Show First 20 Lines • Show All 185 Lines • ▼ Show 20 Linesbody: |
bb.1.cleanup: bb.1.cleanup:
DBG_VALUE $eax, $noreg, !24, !DIExpression(), debug-location !25 DBG_VALUE $eax, $noreg, !24, !DIExpression(), debug-location !25
DBG_VALUE $rbx, $noreg, !23, !DIExpression(), debug-location !25 DBG_VALUE $rbx, $noreg, !23, !DIExpression(), debug-location !25
$eax = MOV32ri -1, debug-location !33 $eax = MOV32ri -1, debug-location !33
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !33 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !33
DBG_VALUE $rdi, $noreg, !23, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !25 DBG_VALUE $rdi, $noreg, !23, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !25
CFI_INSTRUCTION def_cfa_offset 8, debug-location !33 CFI_INSTRUCTION def_cfa_offset 8, debug-location !33
RETQ $eax, debug-location !33 RET64 $eax, debug-location !33
bb.2.if.then: bb.2.if.then:
CFI_INSTRUCTION def_cfa_offset 16, debug-location !32 CFI_INSTRUCTION def_cfa_offset 16, debug-location !32
DBG_VALUE $eax, $noreg, !24, !DIExpression(), debug-location !25 DBG_VALUE $eax, $noreg, !24, !DIExpression(), debug-location !25
DBG_VALUE $rbx, $noreg, !23, !DIExpression(), debug-location !25 DBG_VALUE $rbx, $noreg, !23, !DIExpression(), debug-location !25
dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al, debug-location !32 dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al, debug-location !32
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !32 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !32
DBG_VALUE $rdi, $noreg, !23, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !25 DBG_VALUE $rdi, $noreg, !23, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !25
CFI_INSTRUCTION def_cfa_offset 8, debug-location !32 CFI_INSTRUCTION def_cfa_offset 8, debug-location !32
TAILJMPd64 @fn3, csr_64, implicit $rsp, implicit $ssp, implicit $rsp, implicit $ssp, implicit $al, debug-location !32 TAILJMPd64 @fn3, csr_64, implicit $rsp, implicit $ssp, implicit $rsp, implicit $ssp, implicit $al, debug-location !32
... ...

llvm/test/DebugInfo/MIR/X86/clobbered-fragments.mir

Show First 20 Lines • Show All 99 Lines • ▼ Show 20 Lines bb.0.entry:
renamable $edi = MOV32rm $rip, 1, $noreg, @global1, $noreg, debug-location !16 :: (dereferenceable load (s32) from @global1) renamable $edi = MOV32rm $rip, 1, $noreg, @global1, $noreg, debug-location !16 :: (dereferenceable load (s32) from @global1)
DBG_VALUE 456, $noreg, !12, !DIExpression(DW_OP_LLVM_fragment, 64, 32), debug-location !16 DBG_VALUE 456, $noreg, !12, !DIExpression(DW_OP_LLVM_fragment, 64, 32), debug-location !16
DBG_VALUE 123, $noreg, !12, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !16 DBG_VALUE 123, $noreg, !12, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !16
DBG_VALUE $edi, $noreg, !12, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !16 DBG_VALUE $edi, $noreg, !12, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !16
$esi = MOV32ri 123, debug-location !16 $esi = MOV32ri 123, debug-location !16
CALL64pcrel32 @ext2, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit killed $esi, implicit-def $rsp, implicit-def $ssp, debug-location !16 CALL64pcrel32 @ext2, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit killed $esi, implicit-def $rsp, implicit-def $ssp, debug-location !16
$eax = MOV32ri 123, debug-location !17 $eax = MOV32ri 123, debug-location !17
$rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !17 $rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !17
RETQ killed $eax, debug-location !17 RET64 killed $eax, debug-location !17
... ...
# CHECK: .Ltmp1 # CHECK: .Ltmp1
# CHECK-NEXT: #DEBUG_VALUE: test1:local <- [DW_OP_LLVM_fragment 64 32] 456 # CHECK-NEXT: #DEBUG_VALUE: test1:local <- [DW_OP_LLVM_fragment 64 32] 456
# CHECK-NEXT: #DEBUG_VALUE: test1:local <- [DW_OP_LLVM_fragment 32 32] 123 # CHECK-NEXT: #DEBUG_VALUE: test1:local <- [DW_OP_LLVM_fragment 32 32] 123
# CHECK-NEXT: #DEBUG_VALUE: test1:local <- [DW_OP_LLVM_fragment 0 32] $edi # CHECK-NEXT: #DEBUG_VALUE: test1:local <- [DW_OP_LLVM_fragment 0 32] $edi
# CHECK: callq ext2 # CHECK: callq ext2
Show All 13 Lines bb.0.entry:
renamable $esi = MOV32rm $rip, 1, $noreg, @global2, $noreg, debug-location !20 :: (dereferenceable load (s32) from @global2) renamable $esi = MOV32rm $rip, 1, $noreg, @global2, $noreg, debug-location !20 :: (dereferenceable load (s32) from @global2)
DBG_VALUE $esi, $noreg, !19, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !20 DBG_VALUE $esi, $noreg, !19, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !20
renamable $edx = MOV32rm $rip, 1, $noreg, @global3, $noreg, debug-location !20 :: (dereferenceable load (s32) from @global3) renamable $edx = MOV32rm $rip, 1, $noreg, @global3, $noreg, debug-location !20 :: (dereferenceable load (s32) from @global3)
DBG_VALUE $edx, $noreg, !19, !DIExpression(DW_OP_LLVM_fragment, 64, 32), debug-location !20 DBG_VALUE $edx, $noreg, !19, !DIExpression(DW_OP_LLVM_fragment, 64, 32), debug-location !20
$edi = MOV32rr $ebx, debug-location !20 $edi = MOV32rr $ebx, debug-location !20
CALL64pcrel32 @ext3, csr_64, implicit $rsp, implicit $ssp, implicit killed $edi, implicit $esi, implicit $edx, implicit-def $rsp, implicit-def $ssp, debug-location !20 CALL64pcrel32 @ext3, csr_64, implicit $rsp, implicit $ssp, implicit killed $edi, implicit $esi, implicit $edx, implicit-def $rsp, implicit-def $ssp, debug-location !20
$eax = MOV32rr killed $ebx, debug-location !20 $eax = MOV32rr killed $ebx, debug-location !20
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !20 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !20
RETQ killed $eax, debug-location !21 RET64 killed $eax, debug-location !21
... ...
# CHECK: .Ltmp4: # CHECK: .Ltmp4:
# CHECK-NEXT: #DEBUG_VALUE: test2:local <- [DW_OP_LLVM_fragment 0 32] $ebx # CHECK-NEXT: #DEBUG_VALUE: test2:local <- [DW_OP_LLVM_fragment 0 32] $ebx
# CHECK: .Ltmp5: # CHECK: .Ltmp5:
# CHECK-NEXT: #DEBUG_VALUE: test2:local <- [DW_OP_LLVM_fragment 32 32] $esi # CHECK-NEXT: #DEBUG_VALUE: test2:local <- [DW_OP_LLVM_fragment 32 32] $esi
# CHECK: .Ltmp6: # CHECK: .Ltmp6:
▲ Show 20 Lines • Show All 92 Lines • Show Last 20 Lines

llvm/test/DebugInfo/MIR/X86/complex-entryvalue.mir

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
--- ---
name: f name: f
body: | body: |
bb.0.entry: bb.0.entry:
DBG_VALUE $edi, $noreg, !14, !DIExpression(DW_OP_LLVM_entry_value, 1, DW_OP_lit0, DW_OP_plus), debug-location !15 DBG_VALUE $edi, $noreg, !14, !DIExpression(DW_OP_LLVM_entry_value, 1, DW_OP_lit0, DW_OP_plus), debug-location !15
frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp
$rbp = frame-setup MOV64rr $rsp $rbp = frame-setup MOV64rr $rsp
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !16 $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !16
RETQ debug-location !16 RET64 debug-location !16
... ...

llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg-multiple-defs.mir

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Lines bb.0.entry:
$r13 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !18 $r13 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !18
CFI_INSTRUCTION def_cfa_offset 32, debug-location !18 CFI_INSTRUCTION def_cfa_offset 32, debug-location !18
$r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !18 $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !18
CFI_INSTRUCTION def_cfa_offset 24, debug-location !18 CFI_INSTRUCTION def_cfa_offset 24, debug-location !18
$r15 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !18 $r15 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !18
CFI_INSTRUCTION def_cfa_offset 16, debug-location !18 CFI_INSTRUCTION def_cfa_offset 16, debug-location !18
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !18 $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !18
CFI_INSTRUCTION def_cfa_offset 8, debug-location !18 CFI_INSTRUCTION def_cfa_offset 8, debug-location !18
RETQ debug-location !18 RET64 debug-location !18
... ...

llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir

Show First 20 Lines • Show All 166 Lines • ▼ Show 20 Lines bb.0.entry:
DBG_VALUE $edi, $noreg, !15, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !16 DBG_VALUE $edi, $noreg, !15, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !16
$rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !20 $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !20
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !20 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !20
$r12 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !20 $r12 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !20
$r13 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !20 $r13 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !20
$r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !20 $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !20
$r15 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !20 $r15 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !20
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !20 $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !20
RETQ debug-location !20 RET64 debug-location !20
... ...

llvm/test/DebugInfo/MIR/X86/dbg-stack-value-range.mir

Show First 20 Lines • Show All 171 Lines • ▼ Show 20 Lines bb.3.if.end:
DBG_VALUE $noreg, $noreg, !14, !DIExpression(), debug-location !15 DBG_VALUE $noreg, $noreg, !14, !DIExpression(), debug-location !15
dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al, debug-location !15 dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al, debug-location !15
CALL64pcrel32 @init2, csr_64, implicit $rsp, implicit $ssp, implicit $al, implicit-def $rsp, implicit-def $ssp, implicit-def dead $eax, debug-location !15 CALL64pcrel32 @init2, csr_64, implicit $rsp, implicit $ssp, implicit $al, implicit-def $rsp, implicit-def $ssp, implicit-def dead $eax, debug-location !15
DBG_VALUE $noreg, $noreg, !14, !DIExpression(), debug-location !15 DBG_VALUE $noreg, $noreg, !14, !DIExpression(), debug-location !15
renamable $eax = MOV32rm $rbp, 1, $noreg, -4, $noreg, debug-location !15 :: (dereferenceable load (s32) from %ir.local1, !tbaa !16) renamable $eax = MOV32rm $rbp, 1, $noreg, -4, $noreg, debug-location !15 :: (dereferenceable load (s32) from %ir.local1, !tbaa !16)
$rsp = frame-destroy ADD64ri8 $rsp, 16, implicit-def dead $eflags, debug-location !15 $rsp = frame-destroy ADD64ri8 $rsp, 16, implicit-def dead $eflags, debug-location !15
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !15 $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !15
CFI_INSTRUCTION def_cfa $rsp, 8, debug-location !15 CFI_INSTRUCTION def_cfa $rsp, 8, debug-location !15
RETQ $eax, debug-location !15 RET64 $eax, debug-location !15
... ...

llvm/test/DebugInfo/MIR/X86/dbgcall-site-copy-super-sub.mir

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Lines bb.0.entry:
CALL64pcrel32 @value32, csr_64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !29 CALL64pcrel32 @value32, csr_64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !29
$ebx = MOV32rr $eax, debug-location !29 $ebx = MOV32rr $eax, debug-location !29
DBG_VALUE $ebx, $noreg, !28, !DIExpression(), debug-location !30 DBG_VALUE $ebx, $noreg, !28, !DIExpression(), debug-location !30
renamable $edi = MOV32rr $ebx, implicit-def $rdi, debug-location !31 renamable $edi = MOV32rr $ebx, implicit-def $rdi, debug-location !31
CALL64pcrel32 @call64, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, debug-location !31 CALL64pcrel32 @call64, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, debug-location !31
$eax = MOV32rr killed $ebx, debug-location !32 $eax = MOV32rr killed $ebx, debug-location !32
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !32 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !32
CFI_INSTRUCTION def_cfa_offset 8, debug-location !32 CFI_INSTRUCTION def_cfa_offset 8, debug-location !32
RETQ killed $eax, debug-location !32 RET64 killed $eax, debug-location !32
... ...
# Verify that a call site value is emitted for the 64-bit parameter that is # Verify that a call site value is emitted for the 64-bit parameter that is
# loaded using the zero-extending MOV32rr. # loaded using the zero-extending MOV32rr.
# CHECK: DW_TAG_GNU_call_site_parameter # CHECK: DW_TAG_GNU_call_site_parameter
# CHECK-NEXT: DW_AT_location (DW_OP_reg5 RDI) # CHECK-NEXT: DW_AT_location (DW_OP_reg5 RDI)
# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg3 RBX+0) # CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg3 RBX+0)

llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir

Show First 20 Lines • Show All 193 Lines • ▼ Show 20 Lines bb.0.entry:
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !21 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !21
CFI_INSTRUCTION def_cfa_offset 24, debug-location !21 CFI_INSTRUCTION def_cfa_offset 24, debug-location !21
$r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !21 $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !21
DBG_VALUE $ecx, $noreg, !17, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !21 DBG_VALUE $ecx, $noreg, !17, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !21
CFI_INSTRUCTION def_cfa_offset 16, debug-location !21 CFI_INSTRUCTION def_cfa_offset 16, debug-location !21
$r15 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !21 $r15 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !21
DBG_VALUE $esi, $noreg, !15, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !21 DBG_VALUE $esi, $noreg, !15, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !21
CFI_INSTRUCTION def_cfa_offset 8, debug-location !21 CFI_INSTRUCTION def_cfa_offset 8, debug-location !21
RETQ $eax, debug-location !21 RET64 $eax, debug-location !21
... ...

llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir

Show First 20 Lines • Show All 129 Lines • ▼ Show 20 Lines bb.0.entry:
ADD32mr $rsp, 1, $noreg, 4, $noreg, killed renamable $eax, implicit-def dead $eflags, debug-location !14 :: (store (s32) into %ir.local1), (dereferenceable load (s32) from %ir.local1) ADD32mr $rsp, 1, $noreg, 4, $noreg, killed renamable $eax, implicit-def dead $eflags, debug-location !14 :: (store (s32) into %ir.local1), (dereferenceable load (s32) from %ir.local1)
$rdi = LEA64r $r14, 1, killed $r14, 0, $noreg $rdi = LEA64r $r14, 1, killed $r14, 0, $noreg
CALL64pcrel32 @foo2, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def dead $eax, debug-location !14 CALL64pcrel32 @foo2, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def dead $eax, debug-location !14
renamable $eax = MOV32rm $rsp, 1, $noreg, 4, $noreg, debug-location !14 :: (dereferenceable load (s32) from %ir.local1) renamable $eax = MOV32rm $rsp, 1, $noreg, 4, $noreg, debug-location !14 :: (dereferenceable load (s32) from %ir.local1)
$rsp = frame-destroy ADD64ri8 $rsp, 16, implicit-def dead $eflags, debug-location !14 $rsp = frame-destroy ADD64ri8 $rsp, 16, implicit-def dead $eflags, debug-location !14
CFI_INSTRUCTION def_cfa_offset 16, debug-location !14 CFI_INSTRUCTION def_cfa_offset 16, debug-location !14
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !14 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !14
CFI_INSTRUCTION def_cfa_offset 8, debug-location !14 CFI_INSTRUCTION def_cfa_offset 8, debug-location !14
RETQ $eax, debug-location !14 RET64 $eax, debug-location !14
... ...

llvm/test/DebugInfo/MIR/X86/dbgcall-site-partial-describe.mir

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Linesbody: |
bb.0.entry: bb.0.entry:
frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
$esi = MOV32ri 123, debug-location !15 $esi = MOV32ri 123, debug-location !15
$edi = MOV32rr $esi, implicit-def $esi, debug-location !15 $edi = MOV32rr $esi, implicit-def $esi, debug-location !15
CALL64pcrel32 @call, csr_64, implicit $rsp, implicit $ssp, implicit killed $edi, implicit undef $esi, implicit-def $rsp, implicit-def $ssp, debug-location !15 CALL64pcrel32 @call, csr_64, implicit $rsp, implicit $ssp, implicit killed $edi, implicit undef $esi, implicit-def $rsp, implicit-def $ssp, debug-location !15
$rax = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !16 $rax = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !16
CFI_INSTRUCTION def_cfa_offset 8, debug-location !16 CFI_INSTRUCTION def_cfa_offset 8, debug-location !16
RETQ debug-location !16 RET64 debug-location !16
... ...
# In this test an implicit-def has been added to the MOV32rr instruction to # In this test an implicit-def has been added to the MOV32rr instruction to
# simulate a situation where one instruction defines two call site worklist # simulate a situation where one instruction defines two call site worklist
# registers, and where we end up with one of the registers being described by # registers, and where we end up with one of the registers being described by
# the previous value of the other register that is clobbered by this # the previous value of the other register that is clobbered by this
# instruction. # instruction.
Show All 17 Lines

llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir

Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Lines bb.0.entry:
DBG_VALUE $rdi, $noreg, !32, !DIExpression(), debug-location !35 DBG_VALUE $rdi, $noreg, !32, !DIExpression(), debug-location !35
DBG_VALUE $rsi, $noreg, !34, !DIExpression(DW_OP_deref), debug-location !36 DBG_VALUE $rsi, $noreg, !34, !DIExpression(DW_OP_deref), debug-location !36
frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
$rsi = MOV64rr $rsp $rsi = MOV64rr $rsp
CALL64pcrel32 @_ZN1CC2E1B, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp, debug-location !36 CALL64pcrel32 @_ZN1CC2E1B, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp, debug-location !36
$rax = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !36 $rax = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !36
CFI_INSTRUCTION def_cfa_offset 8, debug-location !36 CFI_INSTRUCTION def_cfa_offset 8, debug-location !36
RETQ debug-location !36 RET64 debug-location !36
... ...

llvm/test/DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines bb.0.entry:
$edx = MOV32rr $eax $edx = MOV32rr $eax
$edi = MOV32rr $esi $edi = MOV32rr $esi
$esi = MOV32rr $edx $esi = MOV32rr $edx
CALL64pcrel32 @call2, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit-def $rsp, implicit-def $ssp, debug-location !15 CALL64pcrel32 @call2, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit-def $rsp, implicit-def $ssp, debug-location !15
$rax = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !16 $rax = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !16
CFI_INSTRUCTION def_cfa_offset 8, debug-location !16 CFI_INSTRUCTION def_cfa_offset 8, debug-location !16
RETQ debug-location !16 RET64 debug-location !16
... ...
# Verify that we emit correct call site parameter entries even after moving # Verify that we emit correct call site parameter entries even after moving
# around the call site values between different registers. # around the call site values between different registers.
# #
# This test uses an implicit CHECK-NOT to verify that only two call site # This test uses an implicit CHECK-NOT to verify that only two call site
# parameter entries are emitted. # parameter entries are emitted.
# CHECK: DW_TAG_GNU_call_site_parameter # CHECK: DW_TAG_GNU_call_site_parameter
# CHECK-NEXT: DW_AT_location (DW_OP_reg5 RDI) # CHECK-NEXT: DW_AT_location (DW_OP_reg5 RDI)
# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_constu 0x7b) # CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_constu 0x7b)
# CHECK: DW_TAG_GNU_call_site_parameter # CHECK: DW_TAG_GNU_call_site_parameter
# CHECK-NEXT: DW_AT_location (DW_OP_reg4 RSI) # CHECK-NEXT: DW_AT_location (DW_OP_reg4 RSI)
# CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_GNU_entry_value(DW_OP_reg5 RDI)) # CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_GNU_entry_value(DW_OP_reg5 RDI))

llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines bb.0.entry:
frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
CFI_INSTRUCTION offset $rbp, -16 CFI_INSTRUCTION offset $rbp, -16
$rbp = frame-setup MOV64rr $rsp $rbp = frame-setup MOV64rr $rsp
CFI_INSTRUCTION def_cfa_register $rbp CFI_INSTRUCTION def_cfa_register $rbp
renamable $eax = MOV32rm $rip, 1, $noreg, @a, $noreg, debug-location !16 :: (dereferenceable load (s32) from @a) renamable $eax = MOV32rm $rip, 1, $noreg, @a, $noreg, debug-location !16 :: (dereferenceable load (s32) from @a)
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !16 $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !16
CFI_INSTRUCTION def_cfa $rsp, 8, debug-location !16 CFI_INSTRUCTION def_cfa $rsp, 8, debug-location !16
RETQ $eax, debug-location !16 RET64 $eax, debug-location !16
... ...
--- ---
name: main name: main
tracksRegLiveness: true tracksRegLiveness: true
callSites: callSites:
- { bb: 0, offset: 10 } - { bb: 0, offset: 10 }
- { bb: 0, offset: 14, fwdArgRegs: - { bb: 0, offset: 14, fwdArgRegs:
Show All 18 Lines bb.0.entry:
renamable $rdi = MOVSX64rr32 killed renamable $ebx, debug-location !21 renamable $rdi = MOVSX64rr32 killed renamable $ebx, debug-location !21
$esi = MOV32rr $edi, debug-location !21 $esi = MOV32rr $edi, debug-location !21
CALL64pcrel32 @call, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit killed $esi, implicit-def $rsp, implicit-def $ssp, debug-location !21 CALL64pcrel32 @call, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit killed $esi, implicit-def $rsp, implicit-def $ssp, debug-location !21
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !22 $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !22
$rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !22 $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !22
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !22 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !22
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !22 $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !22
CFI_INSTRUCTION def_cfa $rsp, 8, debug-location !22 CFI_INSTRUCTION def_cfa $rsp, 8, debug-location !22
RETQ $eax, debug-location !22 RET64 $eax, debug-location !22
... ...
# Verify that call site entries are emitted for both parameters in the call to # Verify that call site entries are emitted for both parameters in the call to
# %call. Both parameters should be described by the preserved $ebx register, # %call. Both parameters should be described by the preserved $ebx register,
# and the value for the first parameter (passed in $rdi) should be # and the value for the first parameter (passed in $rdi) should be
# sign-extended to 64 bits. # sign-extended to 64 bits.
# CHECK: DW_TAG_call_site_parameter # CHECK: DW_TAG_call_site_parameter
# CHECK-NEXT: DW_AT_location (DW_OP_reg5 RDI) # CHECK-NEXT: DW_AT_location (DW_OP_reg5 RDI)
# CHECK-NEXT: DW_AT_call_value (DW_OP_breg3 RBX+0, DW_OP_constu 0xffffffff, DW_OP_and, DW_OP_convert ({{.*}}) "DW_ATE_signed_32", DW_OP_convert ({{.*}}) "DW_ATE_signed_64") # CHECK-NEXT: DW_AT_call_value (DW_OP_breg3 RBX+0, DW_OP_constu 0xffffffff, DW_OP_and, DW_OP_convert ({{.*}}) "DW_ATE_signed_32", DW_OP_convert ({{.*}}) "DW_ATE_signed_64")
# #
# CHECK: DW_TAG_call_site_parameter # CHECK: DW_TAG_call_site_parameter
# CHECK-NEXT: DW_AT_location (DW_OP_reg4 RSI) # CHECK-NEXT: DW_AT_location (DW_OP_reg4 RSI)
# CHECK-NEXT: DW_AT_call_value (DW_OP_breg3 RBX+0) # CHECK-NEXT: DW_AT_call_value (DW_OP_breg3 RBX+0)

llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir

Show First 20 Lines • Show All 184 Lines • ▼ Show 20 Lines bb.0.entry:
$rsp = frame-destroy ADD64ri8 $rsp, 16, implicit-def dead $eflags, debug-location !24 $rsp = frame-destroy ADD64ri8 $rsp, 16, implicit-def dead $eflags, debug-location !24
CFI_INSTRUCTION def_cfa_offset 32, debug-location !24 CFI_INSTRUCTION def_cfa_offset 32, debug-location !24
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !24 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !24
CFI_INSTRUCTION def_cfa_offset 24, debug-location !24 CFI_INSTRUCTION def_cfa_offset 24, debug-location !24
$r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !24 $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !24
CFI_INSTRUCTION def_cfa_offset 16, debug-location !24 CFI_INSTRUCTION def_cfa_offset 16, debug-location !24
$r15 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !24 $r15 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !24
CFI_INSTRUCTION def_cfa_offset 8, debug-location !24 CFI_INSTRUCTION def_cfa_offset 8, debug-location !24
RETQ debug-location !24 RET64 debug-location !24
... ...

llvm/test/DebugInfo/MIR/X86/debug-entry-value-operation.mir

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines bb.0.entry:
DBG_VALUE $edi, $noreg, !15, !DIExpression(), debug-location !18 DBG_VALUE $edi, $noreg, !15, !DIExpression(), debug-location !18
DBG_VALUE $edi, $noreg, !15, !DIExpression(), debug-location !18 DBG_VALUE $edi, $noreg, !15, !DIExpression(), debug-location !18
DBG_VALUE $esi, $noreg, !16, !DIExpression(), debug-location !18 DBG_VALUE $esi, $noreg, !16, !DIExpression(), debug-location !18
DBG_VALUE $edx, $noreg, !17, !DIExpression(), debug-location !18 DBG_VALUE $edx, $noreg, !17, !DIExpression(), debug-location !18
renamable $edi = nsw INC32r killed renamable $edi, implicit-def dead $eflags, debug-location !18 renamable $edi = nsw INC32r killed renamable $edi, implicit-def dead $eflags, debug-location !18
MOV32mr $rip, 1, $noreg, @global, $noreg, killed renamable $edi, debug-location !18 :: (store (s32) into @global) MOV32mr $rip, 1, $noreg, @global, $noreg, killed renamable $edi, debug-location !18 :: (store (s32) into @global)
INLINEASM &"", 1, 12, implicit-def dead early-clobber $edi, 12, implicit-def dead early-clobber $esi, 12, implicit-def dead early-clobber $edx, 12, implicit-def dead early-clobber $df, 12, implicit-def dead early-clobber $fpsw, 12, implicit-def dead early-clobber $eflags, !19, debug-location !18 INLINEASM &"", 1, 12, implicit-def dead early-clobber $edi, 12, implicit-def dead early-clobber $esi, 12, implicit-def dead early-clobber $edx, 12, implicit-def dead early-clobber $df, 12, implicit-def dead early-clobber $fpsw, 12, implicit-def dead early-clobber $eflags, !19, debug-location !18
$eax = MOV32ri 123, debug-location !18 $eax = MOV32ri 123, debug-location !18
RETQ killed $eax, debug-location !18 RET64 killed $eax, debug-location !18
... ...

llvm/test/DebugInfo/MIR/X86/dvl-livedebugvalues-clobber.mir

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Linesbody: |
bb.3: bb.3:
liveins: $rbx, $rsi liveins: $rbx, $rsi
DBG_VALUE $noreg, $noreg, !14, !DIExpression(), debug-location !15 DBG_VALUE $noreg, $noreg, !14, !DIExpression(), debug-location !15
JMP_1 %bb.4 JMP_1 %bb.4
bb.4: bb.4:
liveins: $rbx, $rsi liveins: $rbx, $rsi
RETQ $rbx, debug-location !17 RET64 $rbx, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/dvl-livedebugvalues-join.mir

Show First 20 Lines • Show All 148 Lines • ▼ Show 20 Lines bb.9:
liveins: $rdi, $rsi liveins: $rdi, $rsi
; Replace add with sub in the expr ; Replace add with sub in the expr
$rax = MOV64ri 1 $rax = MOV64ri 1
DBG_VALUE_LIST !14, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_minus), $rdi, $rsi, debug-location !15 DBG_VALUE_LIST !14, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_minus), $rdi, $rsi, debug-location !15
bb.10: bb.10:
liveins: $rdi, $rsi liveins: $rdi, $rsi
; Should _not_ be a live-in loc here. ; Should _not_ be a live-in loc here.
RETQ RET64
... ...

llvm/test/DebugInfo/MIR/X86/dvl-livedebugvalues-movements.mir

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Linesbody: |
bb.1: bb.1:
liveins: $rbx, $rsi liveins: $rbx, $rsi
$rbp = COPY killed $rsi $rbp = COPY killed $rsi
$rsi = MOV64ri 0 $rsi = MOV64ri 0
JMP_1 %bb.2 JMP_1 %bb.2
bb.2: bb.2:
liveins: $rbx, $rbp liveins: $rbx, $rbp
RETQ $rbp, debug-location !17 RET64 $rbp, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/dvl-livedebugvalues-spillrestore.mir

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines bb.0.entry:
liveins: $rdi, $rsi liveins: $rdi, $rsi
$rsp = frame-setup SUB64ri8 $rsp, 24, implicit-def dead $eflags $rsp = frame-setup SUB64ri8 $rsp, 24, implicit-def dead $eflags
DBG_VALUE_LIST !14, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus), $rdi, $rsi, debug-location !15 DBG_VALUE_LIST !14, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus), $rdi, $rsi, debug-location !15
MOV64mr $rsp, 1, _, -16, _, $rdi, debug-location !15 :: (store (s64) into %stack.0) MOV64mr $rsp, 1, _, -16, _, $rdi, debug-location !15 :: (store (s64) into %stack.0)
$rax = COPY killed $rdi $rax = COPY killed $rdi
$rdi = MOV64ri 0 $rdi = MOV64ri 0
$rdi = MOV64rm $rsp, 1, $noreg, -16, $noreg, debug-location !15 :: (load (s64) from %stack.0) $rdi = MOV64rm $rsp, 1, $noreg, -16, $noreg, debug-location !15 :: (load (s64) from %stack.0)
RETQ RET64
... ...

llvm/test/DebugInfo/MIR/X86/dvl-livedebugvars-movements.mir

Show First 20 Lines • Show All 99 Lines • ▼ Show 20 Lines bb.0.entry:
; Force a use of these two registers. ; Force a use of these two registers.
CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit %3, implicit %5 CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit %3, implicit %5
; Now make the register allocator move them to rcx and rdx! ; Now make the register allocator move them to rcx and rdx!
INLINEASM &"", 1, 12, implicit-def dead $rax, 12, implicit-def dead $rbx, 12, implicit-def dead $rsi, 12, implicit-def dead $rdi, 12, implicit-def $rbp, 12, implicit-def dead $r8, 12, implicit-def dead $r9, 12, implicit-def dead $r10, 12, implicit-def dead $r11, 12, implicit-def dead $r12, 12, implicit-def dead $r13, 12, implicit-def dead $r14, 12, implicit-def dead $r15, 12, !18, debug-location !17 INLINEASM &"", 1, 12, implicit-def dead $rax, 12, implicit-def dead $rbx, 12, implicit-def dead $rsi, 12, implicit-def dead $rdi, 12, implicit-def $rbp, 12, implicit-def dead $r8, 12, implicit-def dead $r9, 12, implicit-def dead $r10, 12, implicit-def dead $r11, 12, implicit-def dead $r12, 12, implicit-def dead $r13, 12, implicit-def dead $r14, 12, implicit-def dead $r15, 12, !18, debug-location !17
CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit %3, implicit %5 CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit %3, implicit %5
RETQ RET64
... ...

llvm/test/DebugInfo/MIR/X86/dvl-livedebugvars-stackptr.mir

Show First 20 Lines • Show All 103 Lines • ▼ Show 20 Lines bb.0.entry:
; Force a use of these two registers. ; Force a use of these two registers.
CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit %3, implicit %5 CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit %3, implicit %5
; Now make the register allocator move them to rcx and rdx! ; Now make the register allocator move them to rcx and rdx!
INLINEASM &"", 1, 12, implicit-def dead $rax, 12, implicit-def dead $rbx, 12, implicit-def dead $rsi, 12, implicit-def dead $rdi, 12, implicit-def $rbp, 12, implicit-def dead $r8, 12, implicit-def dead $r9, 12, implicit-def dead $r10, 12, implicit-def dead $r11, 12, implicit-def dead $r12, 12, implicit-def dead $r13, 12, implicit-def dead $r14, 12, implicit-def dead $r15, 12, !18, debug-location !17 INLINEASM &"", 1, 12, implicit-def dead $rax, 12, implicit-def dead $rbx, 12, implicit-def dead $rsi, 12, implicit-def dead $rdi, 12, implicit-def $rbp, 12, implicit-def dead $r8, 12, implicit-def dead $r9, 12, implicit-def dead $r10, 12, implicit-def dead $r11, 12, implicit-def dead $r12, 12, implicit-def dead $r13, 12, implicit-def dead $r14, 12, implicit-def dead $r15, 12, !18, debug-location !17
CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit %3, implicit %5 CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit %3, implicit %5
RETQ RET64
... ...

llvm/test/DebugInfo/MIR/X86/empty-inline.mir

Show First 20 Lines • Show All 103 Lines • ▼ Show 20 Lines bb.0 (%ir-block.1):
JCC_1 %bb.1, 4, implicit $eflags JCC_1 %bb.1, 4, implicit $eflags
bb.2 (%ir-block.5): bb.2 (%ir-block.5):
liveins: $rdi liveins: $rdi
$rax = MOV64rm $rdi, 1, _, 0, _ :: (load (s64) from %ir.6, align 4) $rax = MOV64rm $rdi, 1, _, 0, _ :: (load (s64) from %ir.6, align 4)
$al = MOV8rm killed $rax, 1, _, 0, _ :: (load (s8) from %ir.8) $al = MOV8rm killed $rax, 1, _, 0, _ :: (load (s8) from %ir.8)
MOV8mr killed $rdi, 1, _, 8, _, killed $al, debug-location !14 :: (store (s8) into %ir.12) MOV8mr killed $rdi, 1, _, 8, _, killed $al, debug-location !14 :: (store (s8) into %ir.12)
RETQ undef $eax RET64 undef $eax
bb.1: bb.1:
liveins: $rdi liveins: $rdi
$al = IMPLICIT_DEF debug-location !10 $al = IMPLICIT_DEF debug-location !10
MOV8mr killed $rdi, 1, _, 8, _, killed $al, debug-location !14 :: (store (s8) into %ir.12) MOV8mr killed $rdi, 1, _, 8, _, killed $al, debug-location !14 :: (store (s8) into %ir.12)
RETQ undef $eax RET64 undef $eax
... ...

llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Lines bb.0.entry:
$esi = MOV32ri 6, debug-location !22 $esi = MOV32ri 6, debug-location !22
CALL64pcrel32 @fn1, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit $edx, implicit-def $rsp, implicit-def $ssp, debug-location !22 CALL64pcrel32 @fn1, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit $edx, implicit-def $rsp, implicit-def $ssp, debug-location !22
DBG_VALUE $ebx, $noreg, !17, !DIExpression(DW_OP_plus_uconst, 7, DW_OP_stack_value), debug-location !20 DBG_VALUE $ebx, $noreg, !17, !DIExpression(DW_OP_plus_uconst, 7, DW_OP_stack_value), debug-location !20
renamable $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !23 renamable $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !23
CMP32ri8 killed renamable $ebx, 10, implicit-def $eflags, debug-location !23 CMP32ri8 killed renamable $ebx, 10, implicit-def $eflags, debug-location !23
renamable $al = SETCCr 12, implicit killed $eflags, implicit killed $eax, implicit-def $eax, debug-location !23 renamable $al = SETCCr 12, implicit killed $eflags, implicit killed $eax, implicit-def $eax, debug-location !23
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !26 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !26
CFI_INSTRUCTION def_cfa_offset 8, debug-location !26 CFI_INSTRUCTION def_cfa_offset 8, debug-location !26
RETQ $eax, debug-location !26 RET64 $eax, debug-location !26
... ...

llvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir

Show First 20 Lines • Show All 172 Lines • ▼ Show 20 Lines bb.3.if.end:
DBG_VALUE $ebx, $noreg, !17, !DIExpression(), debug-location !20 DBG_VALUE $ebx, $noreg, !17, !DIExpression(), debug-location !20
$eax = MOV32rr killed $ebx, debug-location !34 $eax = MOV32rr killed $ebx, debug-location !34
$rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !34 $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !34
CFI_INSTRUCTION def_cfa_offset 24, debug-location !34 CFI_INSTRUCTION def_cfa_offset 24, debug-location !34
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !34 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !34
CFI_INSTRUCTION def_cfa_offset 16, debug-location !34 CFI_INSTRUCTION def_cfa_offset 16, debug-location !34
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !34 $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !34
CFI_INSTRUCTION def_cfa_offset 8, debug-location !34 CFI_INSTRUCTION def_cfa_offset 8, debug-location !34
RETQ killed $eax, debug-location !34 RET64 killed $eax, debug-location !34
... ...

llvm/test/DebugInfo/MIR/X86/kill-after-spill.mir

Show First 20 Lines • Show All 376 Lines • ▼ Show 20 Lines bb.9.cleanup:
$eax = MOV32rr killed $ecx $eax = MOV32rr killed $ecx
$rsp = ADD64ri8 $rsp, 8, implicit-def dead $eflags $rsp = ADD64ri8 $rsp, 8, implicit-def dead $eflags
$rbx = POP64r implicit-def $rsp, implicit $rsp $rbx = POP64r implicit-def $rsp, implicit $rsp
$r12 = POP64r implicit-def $rsp, implicit $rsp $r12 = POP64r implicit-def $rsp, implicit $rsp
$r13 = POP64r implicit-def $rsp, implicit $rsp $r13 = POP64r implicit-def $rsp, implicit $rsp
$r14 = POP64r implicit-def $rsp, implicit $rsp $r14 = POP64r implicit-def $rsp, implicit $rsp
$r15 = POP64r implicit-def $rsp, implicit $rsp $r15 = POP64r implicit-def $rsp, implicit $rsp
$rbp = POP64r implicit-def $rsp, implicit $rsp $rbp = POP64r implicit-def $rsp, implicit $rsp
RETQ $eax, debug-location !57 RET64 $eax, debug-location !57
... ...

llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir

Show First 20 Lines • Show All 174 Lines • ▼ Show 20 Lines bb.3.if.end:
DBG_VALUE $ebx, $noreg, !17, !DIExpression(), debug-location !20 DBG_VALUE $ebx, $noreg, !17, !DIExpression(), debug-location !20
$eax = MOV32rr killed $ebx, debug-location !34 $eax = MOV32rr killed $ebx, debug-location !34
$rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !34 $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !34
CFI_INSTRUCTION def_cfa_offset 24, debug-location !34 CFI_INSTRUCTION def_cfa_offset 24, debug-location !34
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !34 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !34
CFI_INSTRUCTION def_cfa_offset 16, debug-location !34 CFI_INSTRUCTION def_cfa_offset 16, debug-location !34
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !34 $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !34
CFI_INSTRUCTION def_cfa_offset 8, debug-location !34 CFI_INSTRUCTION def_cfa_offset 8, debug-location !34
RETQ killed $eax, debug-location !34 RET64 killed $eax, debug-location !34
... ...

llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir

Show First 20 Lines • Show All 261 Lines • ▼ Show 20 Lines bb.4.if.then:
liveins: $ecx, $edi liveins: $ecx, $edi
DBG_VALUE $edi, _, !9, !17, debug-location !18 DBG_VALUE $edi, _, !9, !17, debug-location !18
DBG_VALUE $ecx, _, !12, !17, debug-location !23 DBG_VALUE $ecx, _, !12, !17, debug-location !23
DBG_VALUE 0, 0, !13, !17, debug-location !25 DBG_VALUE 0, 0, !13, !17, debug-location !25
$ecx = IMUL32rr killed $ecx, killed $edi, implicit-def dead $eflags, debug-location !36 $ecx = IMUL32rr killed $ecx, killed $edi, implicit-def dead $eflags, debug-location !36
DBG_VALUE 0, 0, !13, !17, debug-location !25 DBG_VALUE 0, 0, !13, !17, debug-location !25
$eax = MOV32rr killed $ecx, debug-location !50 $eax = MOV32rr killed $ecx, debug-location !50
RETQ $eax, debug-location !50 RET64 $eax, debug-location !50
bb.6.if.then.4: bb.6.if.then.4:
liveins: $ecx, $esi liveins: $ecx, $esi
DBG_VALUE $esi, _, !10, !17, debug-location !19 DBG_VALUE $esi, _, !10, !17, debug-location !19
DBG_VALUE $ecx, _, !12, !17, debug-location !23 DBG_VALUE $ecx, _, !12, !17, debug-location !23
DBG_VALUE 0, 0, !13, !17, debug-location !25 DBG_VALUE 0, 0, !13, !17, debug-location !25
$ecx = IMUL32rr killed $ecx, killed $esi, implicit-def dead $eflags, debug-location !40 $ecx = IMUL32rr killed $ecx, killed $esi, implicit-def dead $eflags, debug-location !40
DBG_VALUE 0, 0, !13, !17, debug-location !25 DBG_VALUE 0, 0, !13, !17, debug-location !25
$eax = MOV32rr killed $ecx, debug-location !50 $eax = MOV32rr killed $ecx, debug-location !50
RETQ $eax, debug-location !50 RET64 $eax, debug-location !50
bb.8.if.then.8: bb.8.if.then.8:
successors: %bb.9.for.end(0) successors: %bb.9.for.end(0)
liveins: $ecx, $edx liveins: $ecx, $edx
DBG_VALUE $edx, _, !11, !17, debug-location !21 DBG_VALUE $edx, _, !11, !17, debug-location !21
DBG_VALUE $ecx, _, !12, !17, debug-location !23 DBG_VALUE $ecx, _, !12, !17, debug-location !23
DBG_VALUE 0, 0, !13, !17, debug-location !25 DBG_VALUE 0, 0, !13, !17, debug-location !25
$ecx = IMUL32rr killed $ecx, killed $edx, implicit-def dead $eflags, debug-location !46 $ecx = IMUL32rr killed $ecx, killed $edx, implicit-def dead $eflags, debug-location !46
bb.9.for.end: bb.9.for.end:
liveins: $ecx liveins: $ecx
DBG_VALUE 0, 0, !13, !17, debug-location !25 DBG_VALUE 0, 0, !13, !17, debug-location !25
$eax = MOV32rr killed $ecx, debug-location !50 $eax = MOV32rr killed $ecx, debug-location !50
RETQ $eax, debug-location !50 RET64 $eax, debug-location !50
... ...

llvm/test/DebugInfo/MIR/X86/live-debug-values-bad-transfer.mir

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Lines bb.1.loop:
JCC_1 %bb.1, 5, implicit killed $eflags, debug-location !10 JCC_1 %bb.1, 5, implicit killed $eflags, debug-location !10
bb.2.exit: bb.2.exit:
liveins: $ebx liveins: $ebx
$eax = MOV32rr killed $ebx, debug-location !10 $eax = MOV32rr killed $ebx, debug-location !10
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 8 CFI_INSTRUCTION def_cfa_offset 8
RETQ $eax, debug-location !10 RET64 $eax, debug-location !10
... ...

llvm/test/DebugInfo/MIR/X86/live-debug-values-cutoffs.mir

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Lines bb.0.entry:
MOV32mr $rsp, 1, $noreg, 4, $noreg, killed $edi :: (store (s32) into %stack.0) MOV32mr $rsp, 1, $noreg, 4, $noreg, killed $edi :: (store (s32) into %stack.0)
DBG_VALUE $rsp, 0, !9, !DIExpression(DW_OP_plus_uconst, 4), debug-location !12 DBG_VALUE $rsp, 0, !9, !DIExpression(DW_OP_plus_uconst, 4), debug-location !12
bb.1.exit: bb.1.exit:
$edi = MOV32rm $rsp, 1, $noreg, 4, $noreg :: (load (s32) from %stack.0) $edi = MOV32rm $rsp, 1, $noreg, 4, $noreg :: (load (s32) from %stack.0)
CALL64pcrel32 @use, csr_64, implicit $rsp, implicit $ssp, implicit killed $edi, implicit-def $eax, debug-location !14 CALL64pcrel32 @use, csr_64, implicit $rsp, implicit $ssp, implicit killed $edi, implicit-def $eax, debug-location !14
DBG_VALUE renamable $eax, $noreg, !11, !DIExpression(), debug-location !14 DBG_VALUE renamable $eax, $noreg, !11, !DIExpression(), debug-location !14
$rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !15 $rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !15
RETQ implicit killed $eax, debug-location !15 RET64 implicit killed $eax, debug-location !15
... ...

llvm/test/DebugInfo/MIR/X86/live-debug-values-entry-transfer.mir

Show First 20 Lines • Show All 112 Lines • ▼ Show 20 Lines bb.2.loop:
JCC_1 %bb.1, 5, implicit $eflags JCC_1 %bb.1, 5, implicit $eflags
bb.3.exit: bb.3.exit:
liveins: $ebx liveins: $ebx
$eax = MOV32rr killed $ebx $eax = MOV32rr killed $ebx
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 8 CFI_INSTRUCTION def_cfa_offset 8
RETQ $eax RET64 $eax
... ...

llvm/test/DebugInfo/MIR/X86/live-debug-values-fragments.mir

Show All 14 Lines
# #
# CHECK-LABEL: foo # CHECK-LABEL: foo
# CHECK-LABEL: bb.3.bb3: # CHECK-LABEL: bb.3.bb3:
# CHECK: DBG_VALUE $ebx, $noreg, !{{[0-9]+}}, # CHECK: DBG_VALUE $ebx, $noreg, !{{[0-9]+}},
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 32, 32) # CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 32, 32)
# CHECK-NEXT: DBG_VALUE $eax, $noreg, !{{[0-9]+}}, # CHECK-NEXT: DBG_VALUE $eax, $noreg, !{{[0-9]+}},
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 0, 32) # CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 0, 32)
# CHECK-NEXT: XOR32rr # CHECK-NEXT: XOR32rr
# CHECK-NEXT: RETQ # CHECK-NEXT: RET64
# #
# CHECK-LABEL: bar # CHECK-LABEL: bar
# CHECK-LABEL: bb.0.entry: # CHECK-LABEL: bb.0.entry:
# CHECK: DBG_VALUE $cx, $noreg, !{{[0-9]+}}, # CHECK: DBG_VALUE $cx, $noreg, !{{[0-9]+}},
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 0, 16) # CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 0, 16)
# CHECK-LABEL: bb.1.bb1: # CHECK-LABEL: bb.1.bb1:
# CHECK: DBG_VALUE $cx, $noreg, !{{[0-9]+}}, # CHECK: DBG_VALUE $cx, $noreg, !{{[0-9]+}},
Show All 14 Lines
# CHECK-NEXT: JMP_1 # CHECK-NEXT: JMP_1
# CHECK-LABEL: bb.3.bb3: # CHECK-LABEL: bb.3.bb3:
# CHECK: DBG_VALUE $ebx, $noreg, !{{[0-9]+}}, # CHECK: DBG_VALUE $ebx, $noreg, !{{[0-9]+}},
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 32, 32) # CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 32, 32)
# CHECK-NEXT: DBG_VALUE $ax, $noreg, !{{[0-9]+}}, # CHECK-NEXT: DBG_VALUE $ax, $noreg, !{{[0-9]+}},
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 8, 16) # CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 8, 16)
# CHECK-NEXT: XOR32rr # CHECK-NEXT: XOR32rr
# CHECK-NEXT: RETQ # CHECK-NEXT: RET64
# CHECK-LABEL: baz # CHECK-LABEL: baz
# CHECK-LABEL: bb.0.entry: # CHECK-LABEL: bb.0.entry:
# CHECK: DBG_VALUE $cx, $noreg, !{{[0-9]+}}, # CHECK: DBG_VALUE $cx, $noreg, !{{[0-9]+}},
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 0, 16) # CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 0, 16)
# CHECK-NEXT: JMP_1 %bb.1 # CHECK-NEXT: JMP_1 %bb.1
# #
# CHECK-LABEL: bb.1.bb1: # CHECK-LABEL: bb.1.bb1:
Show All 13 Lines
# CHECK-NEXT: JMP_1 %bb.3 # CHECK-NEXT: JMP_1 %bb.3
# #
# CHECK-LABEL: bb.3.bb3: # CHECK-LABEL: bb.3.bb3:
# CHECK-NOT: DBG_VALUE $rdi # CHECK-NOT: DBG_VALUE $rdi
# CHECK-NOT: DBG_VALUE $cx # CHECK-NOT: DBG_VALUE $cx
# CHECK: DBG_VALUE $ebx, $noreg, !{{[0-9]+}}, # CHECK: DBG_VALUE $ebx, $noreg, !{{[0-9]+}},
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 32, 32) # CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 32, 32)
# CHECK-NEXT: XOR32rr # CHECK-NEXT: XOR32rr
# CHECK-NEXT: RETQ # CHECK-NEXT: RET64
--- | --- |
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define i32 @foo(i32* %bees, i32* %output) !dbg !4 { define i32 @foo(i32* %bees, i32* %output) !dbg !4 {
entry: entry:
br label %bb1 br label %bb1
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines bb.2.bb2:
$ebx = MOV32rr $eax $ebx = MOV32rr $eax
$ebx = ADD32ri8 $ebx, 3, implicit-def dead $eflags, implicit killed $rbx, implicit-def $rbx $ebx = ADD32ri8 $ebx, 3, implicit-def dead $eflags, implicit killed $rbx, implicit-def $rbx
DBG_VALUE $ebx, $noreg, !3, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !8 DBG_VALUE $ebx, $noreg, !3, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !8
JMP_1 %bb.3 JMP_1 %bb.3
bb.3.bb3: bb.3.bb3:
liveins: $eax, $ebx liveins: $eax, $ebx
$eax = XOR32rr killed $eax, killed $ebx, implicit-def $eflags $eax = XOR32rr killed $eax, killed $ebx, implicit-def $eflags
RETQ $eax, debug-location !8 RET64 $eax, debug-location !8
... ...
--- ---
name: bar name: bar
tracksRegLiveness: true tracksRegLiveness: true
registers: [] registers: []
liveins: liveins:
- { reg: '$rdi', virtual-reg: '' } - { reg: '$rdi', virtual-reg: '' }
Show All 21 Lines bb.2.bb2:
$ebx = MOV32rr $eax $ebx = MOV32rr $eax
$ebx = ADD32ri8 $ebx, 3, implicit-def dead $eflags, implicit killed $rbx, implicit-def $rbx $ebx = ADD32ri8 $ebx, 3, implicit-def dead $eflags, implicit killed $rbx, implicit-def $rbx
DBG_VALUE $ebx, $noreg, !43, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !48 DBG_VALUE $ebx, $noreg, !43, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !48
JMP_1 %bb.3 JMP_1 %bb.3
bb.3.bb3: bb.3.bb3:
liveins: $eax, $ebx liveins: $eax, $ebx
$eax = XOR32rr killed $eax, killed $ebx, implicit-def $eflags $eax = XOR32rr killed $eax, killed $ebx, implicit-def $eflags
RETQ $eax, debug-location !48 RET64 $eax, debug-location !48
... ...
--- ---
name: baz name: baz
tracksRegLiveness: true tracksRegLiveness: true
registers: [] registers: []
liveins: liveins:
- { reg: '$rdi', virtual-reg: '' } - { reg: '$rdi', virtual-reg: '' }
Show All 21 Lines bb.2.bb2:
$ebx = MOV32rr $eax $ebx = MOV32rr $eax
$ebx = ADD32ri8 $ebx, 3, implicit-def dead $eflags, implicit killed $rbx, implicit-def $rbx $ebx = ADD32ri8 $ebx, 3, implicit-def dead $eflags, implicit killed $rbx, implicit-def $rbx
DBG_VALUE $ebx, $noreg, !83, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !88 DBG_VALUE $ebx, $noreg, !83, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !88
JMP_1 %bb.3 JMP_1 %bb.3
bb.3.bb3: bb.3.bb3:
liveins: $eax, $ebx liveins: $eax, $ebx
$eax = XOR32rr killed $eax, killed $ebx, implicit-def $eflags $eax = XOR32rr killed $eax, killed $ebx, implicit-def $eflags
RETQ $eax, debug-location !88 RET64 $eax, debug-location !88
... ...

llvm/test/DebugInfo/MIR/X86/live-debug-values-restore-collide.mir

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines bb.0.entry:
; This load from the stack can be misinterpreted as a stack restore of ; This load from the stack can be misinterpreted as a stack restore of
; any DBG_VALUe pointing at $rsp. ; any DBG_VALUe pointing at $rsp.
$rsi = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load (s64) from %stack.1) $rsi = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load (s64) from %stack.1)
; Return faff ; Return faff
$eax = MOV32ri 0 $eax = MOV32ri 0
$rsp = frame-destroy ADD64ri8 $rsp, 24, implicit-def dead $eflags $rsp = frame-destroy ADD64ri8 $rsp, 24, implicit-def dead $eflags
RETQ debug-location !10 RET64 debug-location !10
... ...

llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir

Show First 20 Lines • Show All 320 Lines • ▼ Show 20 Lines bb.1.if.then:
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 8 CFI_INSTRUCTION def_cfa_offset 8
bb.2.if.end: bb.2.if.end:
liveins: $rdi, $rbx, $r12, $r13, $r14, $r15, $rbp liveins: $rdi, $rbx, $r12, $r13, $r14, $r15, $rbp
renamable $eax = MOV32rm killed renamable $rdi, 1, $noreg, 4, $noreg, debug-location !23 :: (load (s32) from %ir.add.ptr, !tbaa !24) renamable $eax = MOV32rm killed renamable $rdi, 1, $noreg, 4, $noreg, debug-location !23 :: (load (s32) from %ir.add.ptr, !tbaa !24)
RETQ $eax, debug-location !28 RET64 $eax, debug-location !28
... ...
--- ---
# This second function has been appended as a regression test against a # This second function has been appended as a regression test against a
# crash, caused by expressions being created from spill restores that did # crash, caused by expressions being created from spill restores that did
# not preserve fragment information. Test that no empty expressions are # not preserve fragment information. Test that no empty expressions are
# created at all, and the last block describes both variable fragments. # created at all, and the last block describes both variable fragments.
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines bb.2.if.end:
liveins: $rdi, $rbx, $r12, $r13, $r14, $r15, $rbp liveins: $rdi, $rbx, $r12, $r13, $r14, $r15, $rbp
DBG_VALUE $rbx, $noreg, !113, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !114 DBG_VALUE $rbx, $noreg, !113, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !114
MOV64mr $rsp, 1, $noreg, -8, $noreg, killed renamable $rbx :: (store (s64) into %stack.0) MOV64mr $rsp, 1, $noreg, -8, $noreg, killed renamable $rbx :: (store (s64) into %stack.0)
renamable $rsi = MOV64rm $rsp, 1, $noreg, -8, $noreg :: (load (s64) from %stack.0) renamable $rsi = MOV64rm $rsp, 1, $noreg, -8, $noreg :: (load (s64) from %stack.0)
renamable $eax = MOV32rm killed renamable $rsi, 1, $noreg, 4, $noreg, debug-location !123 :: (load (s32) from %ir.add.ptr, !tbaa !24) renamable $eax = MOV32rm killed renamable $rsi, 1, $noreg, 4, $noreg, debug-location !123 :: (load (s32) from %ir.add.ptr, !tbaa !24)
$rdi = MOV64ri 0 $rdi = MOV64ri 0
RETQ $eax, debug-location !128 RET64 $eax, debug-location !128
... ...
--- ---
# This third function tests that complex expressions are spilt, and restored # This third function tests that complex expressions are spilt, and restored
# correctly within a basic block. # correctly within a basic block.
# FIXME: the spilt location below is wrong, there should be a deref between # FIXME: the spilt location below is wrong, there should be a deref between
# the spill-offset and the DW_OP_plus_uconst. # the spill-offset and the DW_OP_plus_uconst.
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines bb.1.if.then:
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 8 CFI_INSTRUCTION def_cfa_offset 8
bb.2.if.end: bb.2.if.end:
liveins: $rdi, $rbx, $r12, $r13, $r14, $r15, $rbp liveins: $rdi, $rbx, $r12, $r13, $r14, $r15, $rbp
renamable $eax = MOV32rm killed renamable $rdi, 1, $noreg, 4, $noreg, debug-location !223 :: (load (s32) from %ir.add.ptr, !tbaa !24) renamable $eax = MOV32rm killed renamable $rdi, 1, $noreg, 4, $noreg, debug-location !223 :: (load (s32) from %ir.add.ptr, !tbaa !24)
RETQ $eax, debug-location !228 RET64 $eax, debug-location !228
... ...
--- ---
# Function four: test that spill restores are detected across block # Function four: test that spill restores are detected across block
# boundaries. The spill has been moved to bb.1, children of which are # boundaries. The spill has been moved to bb.1, children of which are
# bb 2 and 3, neither of which modifies the stack loc. The exit block (3) # bb 2 and 3, neither of which modifies the stack loc. The exit block (3)
▲ Show 20 Lines • Show All 104 Lines • ▼ Show 20 Lines bb.2.if.then:
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 8 CFI_INSTRUCTION def_cfa_offset 8
bb.3.if.end: bb.3.if.end:
liveins: $rbx, $r12, $r13, $r14, $r15, $rbp liveins: $rbx, $r12, $r13, $r14, $r15, $rbp
renamable $rdi = MOV64rm $rsp, 1, $noreg, -8, $noreg :: (load (s64) from %stack.0) renamable $rdi = MOV64rm $rsp, 1, $noreg, -8, $noreg :: (load (s64) from %stack.0)
renamable $eax = MOV32rm killed renamable $rdi, 1, $noreg, 4, $noreg, debug-location !323 :: (load (s32) from %ir.add.ptr, !tbaa !24) renamable $eax = MOV32rm killed renamable $rdi, 1, $noreg, 4, $noreg, debug-location !323 :: (load (s32) from %ir.add.ptr, !tbaa !24)
RETQ $eax, debug-location !328 RET64 $eax, debug-location !328
... ...
--- ---
# Test that if an unspilt DBG_VALUE starts as an indirect DBG_VALUE, then it # Test that if an unspilt DBG_VALUE starts as an indirect DBG_VALUE, then it
# is restored as an indirect DBG_VALUE. FIXME: Note that for the intervening # is restored as an indirect DBG_VALUE. FIXME: Note that for the intervening
# period of being a spilt location there is still a missing layer of # period of being a spilt location there is still a missing layer of
# indirection. # indirection.
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines bb.1.if.then:
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 8 CFI_INSTRUCTION def_cfa_offset 8
bb.2.if.end: bb.2.if.end:
liveins: $rdi, $rbx, $r12, $r13, $r14, $r15, $rbp liveins: $rdi, $rbx, $r12, $r13, $r14, $r15, $rbp
renamable $eax = MOV32rm killed renamable $rdi, 1, $noreg, 4, $noreg, debug-location !414 :: (load (s32) from %ir.add.ptr, !tbaa !24) renamable $eax = MOV32rm killed renamable $rdi, 1, $noreg, 4, $noreg, debug-location !414 :: (load (s32) from %ir.add.ptr, !tbaa !24)
RETQ $eax, debug-location !415 RET64 $eax, debug-location !415
... ...

llvm/test/DebugInfo/MIR/X86/live-debug-values-spill.mir

Show First 20 Lines • Show All 461 Lines • ▼ Show 20 Lines bb.5.cleanup:
$rsp = ADD64ri8 $rsp, 24, implicit-def dead $eflags, debug-location !90 $rsp = ADD64ri8 $rsp, 24, implicit-def dead $eflags, debug-location !90
$rbx = POP64r implicit-def $rsp, implicit $rsp, debug-location !90 $rbx = POP64r implicit-def $rsp, implicit $rsp, debug-location !90
$r12 = POP64r implicit-def $rsp, implicit $rsp, debug-location !90 $r12 = POP64r implicit-def $rsp, implicit $rsp, debug-location !90
$r13 = POP64r implicit-def $rsp, implicit $rsp, debug-location !90 $r13 = POP64r implicit-def $rsp, implicit $rsp, debug-location !90
$r14 = POP64r implicit-def $rsp, implicit $rsp, debug-location !90 $r14 = POP64r implicit-def $rsp, implicit $rsp, debug-location !90
$r15 = POP64r implicit-def $rsp, implicit $rsp, debug-location !90 $r15 = POP64r implicit-def $rsp, implicit $rsp, debug-location !90
$rbp = POP64r implicit-def $rsp, implicit $rsp, debug-location !90 $rbp = POP64r implicit-def $rsp, implicit $rsp, debug-location !90
RETQ debug-location !90 RET64 debug-location !90
... ...

llvm/test/DebugInfo/MIR/X86/live-debug-values-stack-clobber.mir

Show First 20 Lines • Show All 189 Lines • ▼ Show 20 Lines bb.4.return:
$rsp = frame-destroy ADD64ri8 $rsp, 24, implicit-def dead $eflags, debug-location !28 $rsp = frame-destroy ADD64ri8 $rsp, 24, implicit-def dead $eflags, debug-location !28
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !28 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !28
$r12 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !28 $r12 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !28
$r13 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !28 $r13 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !28
$r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !28 $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !28
$r15 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !28 $r15 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !28
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !28 $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !28
RETQ $rax, debug-location !28 RET64 $rax, debug-location !28
... ...

llvm/test/DebugInfo/MIR/X86/live-debug-values.mir

Show First 20 Lines • Show All 246 Lines • ▼ Show 20 Lines bb.5.if.end.7:
MOV32mr $rip, 1, _, @m, _, $ecx, debug-location !43 :: (store (s32) into @m, !tbaa !44) MOV32mr $rip, 1, _, @m, _, $ecx, debug-location !43 :: (store (s32) into @m, !tbaa !44)
dead undef $edi = MOV32ri @.str, implicit-def $rdi, debug-location !46 dead undef $edi = MOV32ri @.str, implicit-def $rdi, debug-location !46
dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al, debug-location !47 dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al, debug-location !47
$esi = MOV32rr killed $ecx, debug-location !46 $esi = MOV32rr killed $ecx, debug-location !46
CALL64pcrel32 @printf, csr_64, implicit $rsp, implicit $rdi, implicit $esi, implicit $al, implicit-def $rsp, implicit-def dead $eax, debug-location !46 CALL64pcrel32 @printf, csr_64, implicit $rsp, implicit $rdi, implicit $esi, implicit $al, implicit-def $rsp, implicit-def dead $eax, debug-location !46
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !47 $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !47
$rbx = POP64r implicit-def $rsp, implicit $rsp, debug-location !47 $rbx = POP64r implicit-def $rsp, implicit $rsp, debug-location !47
RETQ $eax, debug-location !47 RET64 $eax, debug-location !47
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues-ignores-metaInstructions.mir

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines bb.0.entry:
DBG_VALUE $ebx, $noreg, !16, !DIExpression(), debug-location !17 DBG_VALUE $ebx, $noreg, !16, !DIExpression(), debug-location !17
bb.1.bb1: bb.1.bb1:
successors: %bb.2 successors: %bb.2
renamable $ebx = KILL $ebx renamable $ebx = KILL $ebx
bb.2.bb2: bb.2.bb2:
successors: %bb.3 successors: %bb.3
renamable $ebx = KILL $ebx renamable $ebx = KILL $ebx
bb.3.bb3: bb.3.bb3:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond.mir

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Linesbody: |
bb.1.bb1: bb.1.bb1:
successors: %bb.3 successors: %bb.3
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
JMP_1 %bb.3 JMP_1 %bb.3
bb.2.bb2: bb.2.bb2:
successors: %bb.3 successors: %bb.3
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
bb.3.bb3: bb.3.bb3:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_match_clobber.mir

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Linesbody: |
bb.1.bb1: bb.1.bb1:
successors: %bb.3 successors: %bb.3
$ebx = MOV32ri 0, debug-location !17 $ebx = MOV32ri 0, debug-location !17
JMP_1 %bb.3 JMP_1 %bb.3
bb.2.bb2: bb.2.bb2:
successors: %bb.3 successors: %bb.3
$ebx = MOV32ri 0, debug-location !17 $ebx = MOV32ri 0, debug-location !17
bb.3.bb3: bb.3.bb3:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_match_move.mir

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines bb.1.bb1:
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
DBG_VALUE $eax, $noreg, !16, !DIExpression(), debug-location !17 DBG_VALUE $eax, $noreg, !16, !DIExpression(), debug-location !17
JMP_1 %bb.3 JMP_1 %bb.3
bb.2.bb2: bb.2.bb2:
successors: %bb.3 successors: %bb.3
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
DBG_VALUE $eax, $noreg, !16, !DIExpression(), debug-location !17 DBG_VALUE $eax, $noreg, !16, !DIExpression(), debug-location !17
bb.3.bb3: bb.3.bb3:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_one_clobber.mir

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Linesbody: |
bb.1.bb1: bb.1.bb1:
successors: %bb.3 successors: %bb.3
$ebx = MOV32ri 0, debug-location !17 $ebx = MOV32ri 0, debug-location !17
JMP_1 %bb.3 JMP_1 %bb.3
bb.2.bb2: bb.2.bb2:
successors: %bb.3 successors: %bb.3
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
bb.3.bb3: bb.3.bb3:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_one_move.mir

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Lines bb.1.bb1:
successors: %bb.3 successors: %bb.3
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
DBG_VALUE $eax, $noreg, !16, !DIExpression(), debug-location !17 DBG_VALUE $eax, $noreg, !16, !DIExpression(), debug-location !17
JMP_1 %bb.3 JMP_1 %bb.3
bb.2.bb2: bb.2.bb2:
successors: %bb.3 successors: %bb.3
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
bb.3.bb3: bb.3.bb3:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_loop.mir

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Linesbody: |
bb.1.bb1: bb.1.bb1:
successors: %bb.2 successors: %bb.2
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
bb.2.bb2: bb.2.bb2:
successors: %bb.1, %bb.3 successors: %bb.1, %bb.3
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
JCC_1 %bb.1, 4, implicit killed $eflags JCC_1 %bb.1, 4, implicit killed $eflags
bb.3.bb3: bb.3.bb3:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb.mir

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines bb.0.entry:
DBG_VALUE $ebx, $noreg, !16, !DIExpression(), debug-location !17 DBG_VALUE $ebx, $noreg, !16, !DIExpression(), debug-location !17
bb.1.bb1: bb.1.bb1:
successors: %bb.2 successors: %bb.2
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
bb.2.bb2: bb.2.bb2:
successors: %bb.3 successors: %bb.3
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
bb.3.bb3: bb.3.bb3:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb_clobbered.mir

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines bb.0.entry:
DBG_VALUE $ebx, $noreg, !16, !DIExpression(), debug-location !17 DBG_VALUE $ebx, $noreg, !16, !DIExpression(), debug-location !17
bb.1.bb1: bb.1.bb1:
successors: %bb.2 successors: %bb.2
$ebx = MOV32ri 0, debug-location !17 $ebx = MOV32ri 0, debug-location !17
bb.2.bb2: bb.2.bb2:
successors: %bb.3 successors: %bb.3
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
bb.3.bb3: bb.3.bb3:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb_move_to_clobber.mir

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Lines bb.1.bb1:
successors: %bb.2 successors: %bb.2
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
DBG_VALUE $eax, $noreg, !16, !DIExpression(), debug-location !17 DBG_VALUE $eax, $noreg, !16, !DIExpression(), debug-location !17
$ebx = MOV32ri 0, debug-location !17 $ebx = MOV32ri 0, debug-location !17
bb.2.bb2: bb.2.bb2:
successors: %bb.3 successors: %bb.3
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
bb.3.bb3: bb.3.bb3:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir

Show First 20 Lines • Show All 103 Lines • ▼ Show 20 Linesbody: |
bb.4: bb.4:
liveins: $rax, $rbp liveins: $rax, $rbp
MOV64mr $rsp, 1, $noreg, 8, $noreg, killed renamable $rbp :: (store (s64) into %stack.0) MOV64mr $rsp, 1, $noreg, 8, $noreg, killed renamable $rbp :: (store (s64) into %stack.0)
JMP_1 %bb.6 JMP_1 %bb.6
bb.5: bb.5:
liveins: $rax, $rbp liveins: $rax, $rbp
bb.6: bb.6:
liveins: $rax, $rbp liveins: $rax, $rbp
RETQ $rax, debug-location !17 RET64 $rax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_break.mir

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines bb.2.bb2:
successors: %bb.3, %bb.4 successors: %bb.3, %bb.4
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
JCC_1 %bb.4, 4, implicit killed $eflags JCC_1 %bb.4, 4, implicit killed $eflags
bb.3.bb3: bb.3.bb3:
successors: %bb.1, %bb.4 successors: %bb.1, %bb.4
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
JCC_1 %bb.1, 4, implicit killed $eflags JCC_1 %bb.1, 4, implicit killed $eflags
bb.4.bb4: bb.4.bb4:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_break_clobbered.mir

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines bb.2.bb2:
successors: %bb.3, %bb.4 successors: %bb.3, %bb.4
$ebx = MOV32ri 0, debug-location !17 $ebx = MOV32ri 0, debug-location !17
JCC_1 %bb.4, 4, implicit killed $eflags JCC_1 %bb.4, 4, implicit killed $eflags
bb.3.bb3: bb.3.bb3:
successors: %bb.1, %bb.4 successors: %bb.1, %bb.4
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
JCC_1 %bb.1, 4, implicit killed $eflags JCC_1 %bb.1, 4, implicit killed $eflags
bb.4.bb4: bb.4.bb4:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_clobbered.mir

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines bb.1.bb1:
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
bb.2.bb2: bb.2.bb2:
successors: %bb.1, %bb.3 successors: %bb.1, %bb.3
$ebx = MOV32ri 0, debug-location !17 $ebx = MOV32ri 0, debug-location !17
JCC_1 %bb.1, 4, implicit killed $eflags JCC_1 %bb.1, 4, implicit killed $eflags
bb.3.bb3: bb.3.bb3:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond.mir

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Linesbody: |
bb.3.bb3: bb.3.bb3:
successors: %bb.4 successors: %bb.4
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
bb.4.bb4: bb.4.bb4:
successors: %bb.1, %bb.5 successors: %bb.1, %bb.5
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
JCC_1 %bb.1, 4, implicit killed $eflags JCC_1 %bb.1, 4, implicit killed $eflags
bb.5.bb5: bb.5.bb5:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond_clobber.mir

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Linesbody: |
bb.3.bb3: bb.3.bb3:
successors: %bb.4 successors: %bb.4
$ebx = MOV32ri 0, debug-location !17 $ebx = MOV32ri 0, debug-location !17
bb.4.bb4: bb.4.bb4:
successors: %bb.1, %bb.5 successors: %bb.1, %bb.5
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
JCC_1 %bb.1, 4, implicit killed $eflags JCC_1 %bb.1, 4, implicit killed $eflags
bb.5.bb5: bb.5.bb5:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond_move.mir

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Linesbody: |
bb.3.bb3: bb.3.bb3:
successors: %bb.4 successors: %bb.4
$ebx = MOV32ri 0, debug-location !17 $ebx = MOV32ri 0, debug-location !17
bb.4.bb4: bb.4.bb4:
successors: %bb.1, %bb.5 successors: %bb.1, %bb.5
$ebx = MOV32ri 0, debug-location !17 $ebx = MOV32ri 0, debug-location !17
JCC_1 %bb.1, 4, implicit killed $eflags JCC_1 %bb.1, 4, implicit killed $eflags
bb.5.bb5: bb.5.bb5:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_early_clobber.mir

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Linesbody: |
bb.1.bb1: bb.1.bb1:
successors: %bb.2 successors: %bb.2
$ebx = MOV32ri 0, debug-location !17 $ebx = MOV32ri 0, debug-location !17
bb.2.bb2: bb.2.bb2:
successors: %bb.1, %bb.3 successors: %bb.1, %bb.3
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
JCC_1 %bb.1, 4, implicit killed $eflags JCC_1 %bb.1, 4, implicit killed $eflags
bb.3.bb3: bb.3.bb3:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_terminated.mir

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Linesbody: |
bb.2.bb2: bb.2.bb2:
successors: %bb.1, %bb.3 successors: %bb.1, %bb.3
$ecx = MOV32ri 1, debug-location !17 $ecx = MOV32ri 1, debug-location !17
DBG_VALUE $noreg, $noreg, !16, !DIExpression(), debug-location !17 DBG_VALUE $noreg, $noreg, !16, !DIExpression(), debug-location !17
JCC_1 %bb.1, 4, implicit killed $eflags JCC_1 %bb.1, 4, implicit killed $eflags
bb.3.bb3: bb.3.bb3:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_two_backedge.mir

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines bb.2.bb2:
successors: %bb.1, %bb.3 successors: %bb.1, %bb.3
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
JCC_1 %bb.1, 4, implicit killed $eflags JCC_1 %bb.1, 4, implicit killed $eflags
bb.3.bb3: bb.3.bb3:
successors: %bb.1, %bb.4 successors: %bb.1, %bb.4
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
JCC_1 %bb.1, 4, implicit killed $eflags JCC_1 %bb.1, 4, implicit killed $eflags
bb.4.bb4: bb.4.bb4:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_two_backedge_clobbered.mir

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines bb.2.bb2:
successors: %bb.1, %bb.3 successors: %bb.1, %bb.3
$ebx = MOV32ri 0, debug-location !17 $ebx = MOV32ri 0, debug-location !17
JCC_1 %bb.1, 4, implicit killed $eflags JCC_1 %bb.1, 4, implicit killed $eflags
bb.3.bb3: bb.3.bb3:
successors: %bb.1, %bb.4 successors: %bb.1, %bb.4
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
JCC_1 %bb.1, 4, implicit killed $eflags JCC_1 %bb.1, 4, implicit killed $eflags
bb.4.bb4: bb.4.bb4:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop.mir

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Lines bb.3.bb3:
successors: %bb.2, %bb.4 successors: %bb.2, %bb.4
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.4.bb4: bb.4.bb4:
successors: %bb.1, %bb.5 successors: %bb.1, %bb.5
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
JCC_1 %bb.1, 4, implicit killed $eflags JCC_1 %bb.1, 4, implicit killed $eflags
bb.5.bb5: bb.5.bb5:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_clobbered.mir

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines bb.3.bb3:
successors: %bb.2, %bb.4 successors: %bb.2, %bb.4
$ebx = MOV32ri 0, debug-location !17 $ebx = MOV32ri 0, debug-location !17
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.4.bb4: bb.4.bb4:
successors: %bb.1, %bb.5 successors: %bb.1, %bb.5
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
JCC_1 %bb.1, 4, implicit killed $eflags JCC_1 %bb.1, 4, implicit killed $eflags
bb.5.bb5: bb.5.bb5:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_moved.mir

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines bb.3.bb3:
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
DBG_VALUE $eax, $noreg, !16, !DIExpression(), debug-location !17 DBG_VALUE $eax, $noreg, !16, !DIExpression(), debug-location !17
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.4.bb4: bb.4.bb4:
successors: %bb.1, %bb.5 successors: %bb.1, %bb.5
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
JCC_1 %bb.1, 4, implicit killed $eflags JCC_1 %bb.1, 4, implicit killed $eflags
bb.5.bb5: bb.5.bb5:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_outer_moved.mir

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines bb.3.bb3:
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
JCC_1 %bb.2, 4, implicit killed $eflags JCC_1 %bb.2, 4, implicit killed $eflags
bb.4.bb4: bb.4.bb4:
successors: %bb.1, %bb.5 successors: %bb.1, %bb.5
$eax = MOV32ri 0, debug-location !17 $eax = MOV32ri 0, debug-location !17
DBG_VALUE $eax, $noreg, !16, !DIExpression(), debug-location !17 DBG_VALUE $eax, $noreg, !16, !DIExpression(), debug-location !17
JCC_1 %bb.1, 4, implicit killed $eflags JCC_1 %bb.1, 4, implicit killed $eflags
bb.5.bb5: bb.5.bb5:
RETQ $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvalues_many_loop_heads.mir

Show First 20 Lines • Show All 185 Lines • ▼ Show 20 Lines liveins: $rsi, $rdi, $eflags
JCC_1 %bb.2, 4, implicit $eflags, debug-location !17 JCC_1 %bb.2, 4, implicit $eflags, debug-location !17
bb.17: bb.17:
liveins: $rsi, $rdi, $eflags liveins: $rsi, $rdi, $eflags
JCC_1 %bb.1, 4, implicit $eflags, debug-location !17 JCC_1 %bb.1, 4, implicit $eflags, debug-location !17
bb.18: bb.18:
liveins: $rsi, $rdi, $eflags liveins: $rsi, $rdi, $eflags
RETQ RET64
... ...

llvm/test/DebugInfo/MIR/X86/livedebugvars-crossbb-interval.mir

Show First 20 Lines • Show All 127 Lines • ▼ Show 20 Lines bb.2.bb2:
JMP_1 %bb.1 JMP_1 %bb.1
bb.3.bb3: bb.3.bb3:
%6:gr32 = MOV32rm %3, 1, $noreg, 0, $noreg, debug-location !17 :: (load (s32) from %ir.tmp1) %6:gr32 = MOV32rm %3, 1, $noreg, 0, $noreg, debug-location !17 :: (load (s32) from %ir.tmp1)
JMP_1 %bb.2 JMP_1 %bb.2
bb.4.exit: bb.4.exit:
$eax = COPY %5, debug-location !18 $eax = COPY %5, debug-location !18
RETQ implicit $eax, debug-location !18 RET64 implicit $eax, debug-location !18
... ...

llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines bb.0.entry:
DBG_VALUE $edi, $noreg, !15, !DIExpression(), debug-location !18 DBG_VALUE $edi, $noreg, !15, !DIExpression(), debug-location !18
DBG_VALUE $esi, $noreg, !16, !DIExpression(), debug-location !18 DBG_VALUE $esi, $noreg, !16, !DIExpression(), debug-location !18
DBG_VALUE $edx, $noreg, !17, !DIExpression(), debug-location !18 DBG_VALUE $edx, $noreg, !17, !DIExpression(), debug-location !18
renamable $edi = nsw INC32r killed renamable $edi, implicit-def dead $eflags, debug-location !18 renamable $edi = nsw INC32r killed renamable $edi, implicit-def dead $eflags, debug-location !18
MOV32mr $rip, 1, $noreg, @global, $noreg, killed renamable $edi, debug-location !18 :: (store (s32) into @global) MOV32mr $rip, 1, $noreg, @global, $noreg, killed renamable $edi, debug-location !18 :: (store (s32) into @global)
INLINEASM &"", 1, 12, implicit-def dead early-clobber $edi, 12, implicit-def dead early-clobber $esi, 12, implicit-def dead early-clobber $edx, 12, implicit-def dead early-clobber $df, 12, implicit-def dead early-clobber $fpsw, 12, implicit-def dead early-clobber $eflags, !19, debug-location !18 INLINEASM &"", 1, 12, implicit-def dead early-clobber $edi, 12, implicit-def dead early-clobber $esi, 12, implicit-def dead early-clobber $edx, 12, implicit-def dead early-clobber $df, 12, implicit-def dead early-clobber $fpsw, 12, implicit-def dead early-clobber $eflags, !19, debug-location !18
$eax = MOV32ri 123, debug-location !18 $eax = MOV32ri 123, debug-location !18
RETQ killed $eax, debug-location !18 RET64 killed $eax, debug-location !18
... ...

llvm/test/DebugInfo/MIR/X86/piece-entryval.mir

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
name: f name: f
body: | body: |
bb.0.entry: bb.0.entry:
DBG_VALUE $edi, $noreg, !14, !DIExpression(DW_OP_LLVM_entry_value, 1, DW_OP_LLVM_fragment, 0, 16), debug-location !15 DBG_VALUE $edi, $noreg, !14, !DIExpression(DW_OP_LLVM_entry_value, 1, DW_OP_LLVM_fragment, 0, 16), debug-location !15
DBG_VALUE $edi, $noreg, !14, !DIExpression(DW_OP_constu, 16, DW_OP_shr, DW_OP_LLVM_fragment, 16, 16), debug-location !15 DBG_VALUE $edi, $noreg, !14, !DIExpression(DW_OP_constu, 16, DW_OP_shr, DW_OP_LLVM_fragment, 16, 16), debug-location !15
frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp
$rbp = frame-setup MOV64rr $rsp $rbp = frame-setup MOV64rr $rsp
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !16 $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !16
RETQ debug-location !16 RET64 debug-location !16
... ...

llvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir

Show First 20 Lines • Show All 165 Lines • ▼ Show 20 Lines bb.3.if.end:
DBG_VALUE $ebx, $noreg, !17, !DIExpression(), debug-location !20 DBG_VALUE $ebx, $noreg, !17, !DIExpression(), debug-location !20
$eax = MOV32rr killed $ebx, debug-location !34 $eax = MOV32rr killed $ebx, debug-location !34
$rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !34 $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !34
CFI_INSTRUCTION def_cfa_offset 24, debug-location !34 CFI_INSTRUCTION def_cfa_offset 24, debug-location !34
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !34 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !34
CFI_INSTRUCTION def_cfa_offset 16, debug-location !34 CFI_INSTRUCTION def_cfa_offset 16, debug-location !34
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !34 $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !34
CFI_INSTRUCTION def_cfa_offset 8, debug-location !34 CFI_INSTRUCTION def_cfa_offset 8, debug-location !34
RETQ killed $eax, debug-location !34 RET64 killed $eax, debug-location !34
... ...

llvm/test/DebugInfo/MIR/X86/remove-entry-value-from-loop.mir

Show First 20 Lines • Show All 148 Lines • ▼ Show 20 Lines bb.1.for.cond:
DBG_VALUE $noreg, $noreg, !16, !DIExpression(), debug-location !17 DBG_VALUE $noreg, $noreg, !16, !DIExpression(), debug-location !17
renamable $esi = ADD32ri8 killed renamable $esi, -1, implicit-def $eflags, debug-location !18 renamable $esi = ADD32ri8 killed renamable $esi, -1, implicit-def $eflags, debug-location !18
JCC_1 %bb.2, 5, implicit $eflags, debug-location !21 JCC_1 %bb.2, 5, implicit $eflags, debug-location !21
bb.4.for.end: bb.4.for.end:
liveins: $eax liveins: $eax
DBG_VALUE $eax, $noreg, !15, !DIExpression(), debug-location !17 DBG_VALUE $eax, $noreg, !15, !DIExpression(), debug-location !17
RETQ $eax, debug-location !32 RET64 $eax, debug-location !32
bb.3.if.then: bb.3.if.then:
liveins: $eax, $edi liveins: $eax, $edi
renamable $eax = nsw IMUL32rr killed renamable $eax, killed renamable $edi, implicit-def dead $eflags, debug-location !28 renamable $eax = nsw IMUL32rr killed renamable $eax, killed renamable $edi, implicit-def dead $eflags, debug-location !28
DBG_VALUE $eax, $noreg, !15, !DIExpression(), debug-location !17 DBG_VALUE $eax, $noreg, !15, !DIExpression(), debug-location !17
DBG_VALUE $eax, $noreg, !15, !DIExpression(), debug-location !17 DBG_VALUE $eax, $noreg, !15, !DIExpression(), debug-location !17
RETQ $eax, debug-location !32 RET64 $eax, debug-location !32
... ...

llvm/test/DebugInfo/MIR/X86/remove-redundant-dbg-vals.mir

Show First 20 Lines • Show All 163 Lines • ▼ Show 20 Lines bb.0.entry:
frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
MOV32mr $rip, 1, $noreg, @side_effect, $noreg, killed renamable $esi, debug-location !15 :: (store 4 into @side_effect) MOV32mr $rip, 1, $noreg, @side_effect, $noreg, killed renamable $esi, debug-location !15 :: (store 4 into @side_effect)
DBG_VALUE $edi, $noreg, !13, !DIExpression(), debug-location !14 DBG_VALUE $edi, $noreg, !13, !DIExpression(), debug-location !14
CALL64pcrel32 @bar, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, debug-location !21 CALL64pcrel32 @bar, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, debug-location !21
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !22 $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !22
$rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !22 $rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !22
CFI_INSTRUCTION def_cfa_offset 8, debug-location !22 CFI_INSTRUCTION def_cfa_offset 8, debug-location !22
RETQ killed $eax, debug-location !22 RET64 killed $eax, debug-location !22
... ...
--- ---
name: foo2 name: foo2
alignment: 16 alignment: 16
liveins: liveins:
- { reg: '$edi', virtual-reg: '' } - { reg: '$edi', virtual-reg: '' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $edi, $esi liveins: $edi, $esi
DBG_VALUE $edi, $noreg, !13, !DIExpression(), debug-location !14 DBG_VALUE $edi, $noreg, !13, !DIExpression(), debug-location !14
DBG_VALUE $edi, $noreg, !13, !DIExpression(), debug-location !14 DBG_VALUE $edi, $noreg, !13, !DIExpression(), debug-location !14
frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
MOV32mr $rip, 1, $noreg, @side_effect, $noreg, killed renamable $esi, debug-location !15 :: (store 4 into @side_effect) MOV32mr $rip, 1, $noreg, @side_effect, $noreg, killed renamable $esi, debug-location !15 :: (store 4 into @side_effect)
renamable $edi = MOV32rm $rip, 1, $noreg, @value, $noreg, debug-location !20 :: (dereferenceable load 4 from @value) renamable $edi = MOV32rm $rip, 1, $noreg, @value, $noreg, debug-location !20 :: (dereferenceable load 4 from @value)
DBG_VALUE $edi, $noreg, !13, !DIExpression(), debug-location !14 DBG_VALUE $edi, $noreg, !13, !DIExpression(), debug-location !14
CALL64pcrel32 @bar, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, debug-location !21 CALL64pcrel32 @bar, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, debug-location !21
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !22 $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !22
$rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !22 $rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !22
CFI_INSTRUCTION def_cfa_offset 8, debug-location !22 CFI_INSTRUCTION def_cfa_offset 8, debug-location !22
RETQ killed $eax, debug-location !22 RET64 killed $eax, debug-location !22
... ...
--- ---
name: foo3 name: foo3
alignment: 16 alignment: 16
liveins: liveins:
- { reg: '$edi', virtual-reg: '' } - { reg: '$edi', virtual-reg: '' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $edi, $esi liveins: $edi, $esi
DBG_VALUE $edi, $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !14 DBG_VALUE $edi, $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !14
frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
MOV32mr $rip, 1, $noreg, @side_effect, $noreg, killed renamable $esi, debug-location !15 :: (store 4 into @side_effect) MOV32mr $rip, 1, $noreg, @side_effect, $noreg, killed renamable $esi, debug-location !15 :: (store 4 into @side_effect)
renamable $esi = MOV32rm $rip, 1, $noreg, @value, $noreg, debug-location !20 :: (dereferenceable load 4 from @value) renamable $esi = MOV32rm $rip, 1, $noreg, @value, $noreg, debug-location !20 :: (dereferenceable load 4 from @value)
DBG_VALUE $esi, $noreg, !13, !DIExpression(), debug-location !14 DBG_VALUE $esi, $noreg, !13, !DIExpression(), debug-location !14
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !22 $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !22
DBG_VALUE $edi, $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !14 DBG_VALUE $edi, $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !14
$rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !22 $rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !22
CFI_INSTRUCTION def_cfa_offset 8, debug-location !22 CFI_INSTRUCTION def_cfa_offset 8, debug-location !22
RETQ killed $eax, debug-location !22 RET64 killed $eax, debug-location !22
... ...
--- ---
name: foo4 name: foo4
alignment: 16 alignment: 16
liveins: liveins:
- { reg: '$edi', virtual-reg: '' } - { reg: '$edi', virtual-reg: '' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $edi, $esi liveins: $edi, $esi
DBG_VALUE $edi, $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !14 DBG_VALUE $edi, $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !14
frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
MOV32mr $rip, 1, $noreg, @side_effect, $noreg, killed renamable $esi, debug-location !15 :: (store 4 into @side_effect) MOV32mr $rip, 1, $noreg, @side_effect, $noreg, killed renamable $esi, debug-location !15 :: (store 4 into @side_effect)
renamable $esi = MOV32rm $rip, 1, $noreg, @value, $noreg, debug-location !20 :: (dereferenceable load 4 from @value) renamable $esi = MOV32rm $rip, 1, $noreg, @value, $noreg, debug-location !20 :: (dereferenceable load 4 from @value)
DBG_VALUE_LIST !13, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_stack_value), $edi, $esi, debug-location !14 DBG_VALUE_LIST !13, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_stack_value), $edi, $esi, debug-location !14
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !22 $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !22
DBG_VALUE $edi, $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !14 DBG_VALUE $edi, $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !14
$rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !22 $rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !22
CFI_INSTRUCTION def_cfa_offset 8, debug-location !22 CFI_INSTRUCTION def_cfa_offset 8, debug-location !22
RETQ killed $eax, debug-location !22 RET64 killed $eax, debug-location !22
... ...
--- ---
name: foo5 name: foo5
alignment: 16 alignment: 16
liveins: liveins:
- { reg: '$edi', virtual-reg: '' } - { reg: '$edi', virtual-reg: '' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $edi, $esi liveins: $edi, $esi
DBG_VALUE $edi, $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !14 DBG_VALUE $edi, $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !14
frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
MOV32mr $rip, 1, $noreg, @side_effect, $noreg, killed renamable $esi, debug-location !15 :: (store 4 into @side_effect) MOV32mr $rip, 1, $noreg, @side_effect, $noreg, killed renamable $esi, debug-location !15 :: (store 4 into @side_effect)
renamable $esi = MOV32rm $rip, 1, $noreg, @value, $noreg, debug-location !20 :: (dereferenceable load 4 from @value) renamable $esi = MOV32rm $rip, 1, $noreg, @value, $noreg, debug-location !20 :: (dereferenceable load 4 from @value)
DBG_VALUE 0, $noreg, !13, !DIExpression(), debug-location !14 DBG_VALUE 0, $noreg, !13, !DIExpression(), debug-location !14
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !22 $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !22
DBG_VALUE $edi, $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !14 DBG_VALUE $edi, $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !14
$rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !22 $rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !22
CFI_INSTRUCTION def_cfa_offset 8, debug-location !22 CFI_INSTRUCTION def_cfa_offset 8, debug-location !22
RETQ killed $eax, debug-location !22 RET64 killed $eax, debug-location !22
... ...
--- ---
name: foo6 name: foo6
alignment: 16 alignment: 16
liveins: liveins:
- { reg: '$edi', virtual-reg: '' } - { reg: '$edi', virtual-reg: '' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $edi, $esi liveins: $edi, $esi
DBG_VALUE 0, $noreg, !13, !DIExpression(), debug-location !14 DBG_VALUE 0, $noreg, !13, !DIExpression(), debug-location !14
DBG_VALUE 1, $noreg, !13, !DIExpression(), debug-location !14 DBG_VALUE 1, $noreg, !13, !DIExpression(), debug-location !14
frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
MOV32mr $rip, 1, $noreg, @side_effect, $noreg, killed renamable $esi, debug-location !15 :: (store 4 into @side_effect) MOV32mr $rip, 1, $noreg, @side_effect, $noreg, killed renamable $esi, debug-location !15 :: (store 4 into @side_effect)
renamable $esi = MOV32rm $rip, 1, $noreg, @value, $noreg, debug-location !20 :: (dereferenceable load 4 from @value) renamable $esi = MOV32rm $rip, 1, $noreg, @value, $noreg, debug-location !20 :: (dereferenceable load 4 from @value)
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !22 $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !22
$rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !22 $rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !22
CFI_INSTRUCTION def_cfa_offset 8, debug-location !22 CFI_INSTRUCTION def_cfa_offset 8, debug-location !22
RETQ killed $eax, debug-location !22 RET64 killed $eax, debug-location !22
... ...

llvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Linesbody: |
bb.1: bb.1:
CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, debug-location !17 CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, debug-location !17
bb.2: bb.2:
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !18 $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !18
$rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !18 $rcx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !18
CFI_INSTRUCTION def_cfa_offset 8, debug-location !18 CFI_INSTRUCTION def_cfa_offset 8, debug-location !18
RETQ killed $eax, debug-location !18 RET64 killed $eax, debug-location !18
... ...

llvm/test/DebugInfo/X86/bbjoin.ll

Show All 11 Lines
; CHECK: ![[X:.*]] = !DILocalVariable(name: "x", ; CHECK: ![[X:.*]] = !DILocalVariable(name: "x",
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: DBG_VALUE 23, $noreg, ![[X]], ; CHECK: DBG_VALUE 23, $noreg, ![[X]],
; CHECK: DBG_VALUE $rsp, $noreg, ![[X]], !DIExpression(DW_OP_plus_uconst, 4, DW_OP_deref), ; CHECK: DBG_VALUE $rsp, $noreg, ![[X]], !DIExpression(DW_OP_plus_uconst, 4, DW_OP_deref),
; CHECK: bb.1.if.then: ; CHECK: bb.1.if.then:
; CHECK: DBG_VALUE 43, $noreg, ![[X]], ; CHECK: DBG_VALUE 43, $noreg, ![[X]],
; CHECK: bb.2.if.end: ; CHECK: bb.2.if.end:
; CHECK-NOT: DBG_VALUE 23, $noreg, ![[X]], ; CHECK-NOT: DBG_VALUE 23, $noreg, ![[X]],
; CHECK: RETQ $eax ; CHECK: RET64 $eax
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.11.0" target triple = "x86_64-apple-macosx10.11.0"
; Function Attrs: nounwind ssp uwtable ; Function Attrs: nounwind ssp uwtable
define i32 @f() #0 !dbg !4 { define i32 @f() #0 !dbg !4 {
entry: entry:
%x = alloca i32, align 4 %x = alloca i32, align 4
▲ Show 20 Lines • Show All 72 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/dbg_entity_calc_ignores_KILL_instruction_at_return.mir

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines bb.0.entry:
renamable $edi = KILL killed $edi, implicit-def $rdi renamable $edi = KILL killed $edi, implicit-def $rdi
renamable $eax = LEA64_32r killed renamable $rdi, 1, renamable $rdi, 0, $noreg, debug-location !23 renamable $eax = LEA64_32r killed renamable $rdi, 1, renamable $rdi, 0, $noreg, debug-location !23
DBG_VALUE $eax, $noreg, !21, !DIExpression(), debug-location !22 DBG_VALUE $eax, $noreg, !21, !DIExpression(), debug-location !22
; CHECK-LABEL: DW_TAG_variable ; CHECK-LABEL: DW_TAG_variable
; CHECK: DW_AT_location (0x00000000: ; CHECK: DW_AT_location (0x00000000:
; CHECK: [0x0000000000000003, 0x0000000000000004): DW_OP_reg0 RAX) ; CHECK: [0x0000000000000003, 0x0000000000000004): DW_OP_reg0 RAX)
; CHECK-NEXT: DW_AT_name ("result") ; CHECK-NEXT: DW_AT_name ("result")
renamable $eax = KILL killed $eax, implicit-def $rax renamable $eax = KILL killed $eax, implicit-def $rax
RETQ killed $eax, debug-location !24 RET64 killed $eax, debug-location !24
... ...

llvm/test/DebugInfo/X86/dbg_entity_calc_ignores_KILL_instruction_still_clobbers.mir

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines bb.0.entry:
; CHECK-LABEL: DW_TAG_variable ; CHECK-LABEL: DW_TAG_variable
; CHECK: DW_AT_location (0x00000000: ; CHECK: DW_AT_location (0x00000000:
; CHECK: [0x0000000000000003, 0x0000000000000007): DW_OP_reg0 RAX) ; CHECK: [0x0000000000000003, 0x0000000000000007): DW_OP_reg0 RAX)
; CHECK-NEXT: DW_AT_name ("result") ; CHECK-NEXT: DW_AT_name ("result")
renamable $eax = KILL killed $eax, implicit-def $rax renamable $eax = KILL killed $eax, implicit-def $rax
$edi = MOV32rr $eax, debug-location !24 $edi = MOV32rr $eax, debug-location !24
$eax = MOV32rr $eax, debug-location !24 $eax = MOV32rr $eax, debug-location !24
$edi = MOV32rr $eax, debug-location !24 $edi = MOV32rr $eax, debug-location !24
RETQ killed $eax, debug-location !24 RET64 killed $eax, debug-location !24
... ...

llvm/test/DebugInfo/X86/dbg_value_list_clobbers.mir

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines bb.0.entry:
; CHECK-NEXT: [{{.*}}): DW_OP_breg0 RAX+0, DW_OP_constu 0xffffffff, DW_OP_and, DW_OP_stack_value, DW_OP_piece 0x2, DW_OP_breg5 RDI+0, DW_OP_constu 0xffffffff, DW_OP_and, DW_OP_stack_value, DW_OP_piece 0x2 ; CHECK-NEXT: [{{.*}}): DW_OP_breg0 RAX+0, DW_OP_constu 0xffffffff, DW_OP_and, DW_OP_stack_value, DW_OP_piece 0x2, DW_OP_breg5 RDI+0, DW_OP_constu 0xffffffff, DW_OP_and, DW_OP_stack_value, DW_OP_piece 0x2
; Check that a (non-zero-offset) fragment works. ; Check that a (non-zero-offset) fragment works.
$ecx = MOV32ri 8 $ecx = MOV32ri 8
$ecx = MOV32ri 9 $ecx = MOV32ri 9
DBG_VALUE_LIST !12, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 16, 16), $eax, $ecx, debug-location !15 DBG_VALUE_LIST !12, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 16, 16), $eax, $ecx, debug-location !15
; CHECK-NEXT: [{{.*}}): DW_OP_breg0 RAX+0, DW_OP_constu 0xffffffff, DW_OP_and, DW_OP_stack_value, DW_OP_piece 0x2, DW_OP_breg0 RAX+0, DW_OP_constu 0xffffffff, DW_OP_and, DW_OP_breg2 RCX+0, DW_OP_constu 0xffffffff, DW_OP_and, DW_OP_plus, DW_OP_stack_value, DW_OP_piece 0x2 ; CHECK-NEXT: [{{.*}}): DW_OP_breg0 RAX+0, DW_OP_constu 0xffffffff, DW_OP_and, DW_OP_stack_value, DW_OP_piece 0x2, DW_OP_breg0 RAX+0, DW_OP_constu 0xffffffff, DW_OP_and, DW_OP_breg2 RCX+0, DW_OP_constu 0xffffffff, DW_OP_and, DW_OP_plus, DW_OP_stack_value, DW_OP_piece 0x2
RETQ debug-location !15 RET64 debug-location !15
... ...

llvm/test/DebugInfo/X86/dbg_value_list_emission.mir

Show First 20 Lines • Show All 91 Lines • ▼ Show 20 Lines bb.0.entry:
; CHECK-NEXT: DW_AT_name ("localg") ; CHECK-NEXT: DW_AT_name ("localg")
; (8) Check that a single $noreg location invalidates the entire entry. ; (8) Check that a single $noreg location invalidates the entire entry.
DBG_VALUE_LIST !30, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_stack_value), $eax, $noreg, debug-location !15 DBG_VALUE_LIST !30, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_stack_value), $eax, $noreg, debug-location !15
; CHECK: DW_TAG_variable ; CHECK: DW_TAG_variable
; CHECK-NEXT: DW_AT_name ("localh") ; CHECK-NEXT: DW_AT_name ("localh")
; CHECK-NOT: DW_AT_location ; CHECK-NOT: DW_AT_location
RETQ debug-location !15 RET64 debug-location !15
... ...

llvm/test/DebugInfo/X86/debug-loc-asan.mir

Show First 20 Lines • Show All 335 Lines • ▼ Show 20 Lines bb.10 (%ir-block.53):
MOV64mi32 killed renamable $rax, 1, $noreg, 0, $noreg, 0, debug-location !12 :: (store (s64) into %ir.55) MOV64mi32 killed renamable $rax, 1, $noreg, 0, $noreg, 0, debug-location !12 :: (store (s64) into %ir.55)
bb.11 (%ir-block.56): bb.11 (%ir-block.56):
DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11 DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
$eax = MOV32rm $rsp, 1, $noreg, 8, $noreg :: (load (s32) from %stack.9) $eax = MOV32rm $rsp, 1, $noreg, 8, $noreg :: (load (s32) from %stack.9)
$rsp = MOV64rr $rbp, debug-location !12 $rsp = MOV64rr $rbp, debug-location !12
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !12 $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !12
CFI_INSTRUCTION def_cfa $rsp, 8, debug-location !12 CFI_INSTRUCTION def_cfa $rsp, 8, debug-location !12
RETQ implicit killed $eax, debug-location !12 RET64 implicit killed $eax, debug-location !12
... ...

llvm/test/DebugInfo/X86/debug-loc-offset.mir

Show First 20 Lines • Show All 201 Lines • ▼ Show 20 Lines bb.0.entry:
renamable $ecx = MOV32rm $ebp, 1, $noreg, 8, $noreg, debug-location !16 :: (load (s32) from %ir.b.addr) renamable $ecx = MOV32rm $ebp, 1, $noreg, 8, $noreg, debug-location !16 :: (load (s32) from %ir.b.addr)
DBG_VALUE 1, 0, !14, !DIExpression(), debug-location !15 DBG_VALUE 1, 0, !14, !DIExpression(), debug-location !15
renamable $ecx = ADD32ri8 renamable $ecx, 4, implicit-def $eflags, debug-location !16 renamable $ecx = ADD32ri8 renamable $ecx, 4, implicit-def $eflags, debug-location !16
MOV32mr $ebp, 1, $noreg, -4, $noreg, killed $eax :: (store (s32) into %fixed-stack.1) MOV32mr $ebp, 1, $noreg, -4, $noreg, killed $eax :: (store (s32) into %fixed-stack.1)
$eax = MOV32rr killed $ecx, debug-location !16 $eax = MOV32rr killed $ecx, debug-location !16
$esp = frame-destroy ADD32ri8 $esp, 4, implicit-def dead $eflags, debug-location !16 $esp = frame-destroy ADD32ri8 $esp, 4, implicit-def dead $eflags, debug-location !16
$ebp = frame-destroy POP32r implicit-def $esp, implicit $esp, debug-location !16 $ebp = frame-destroy POP32r implicit-def $esp, implicit $esp, debug-location !16
CFI_INSTRUCTION def_cfa $esp, 4, debug-location !16 CFI_INSTRUCTION def_cfa $esp, 4, debug-location !16
RETL implicit killed $eax, debug-location !16 RET32 implicit killed $eax, debug-location !16
... ...
--- ---
name: _Z3baz1A name: _Z3baz1A
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
frameInfo: frameInfo:
stackSize: 28 stackSize: 28
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines bb.3.if.then2:
renamable $eax = ADD32ri8 renamable $eax, 1, implicit-def $eflags, debug-location !29 renamable $eax = ADD32ri8 renamable $eax, 1, implicit-def $eflags, debug-location !29
MOV32mr $ebp, 1, $noreg, -4, $noreg, killed renamable $eax, debug-location !29 :: (store (s32) into %ir.z) MOV32mr $ebp, 1, $noreg, -4, $noreg, killed renamable $eax, debug-location !29 :: (store (s32) into %ir.z)
bb.4.if.end4: bb.4.if.end4:
DBG_VALUE $ebp, 0, !20, !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref, DW_OP_deref), debug-location !21 DBG_VALUE $ebp, 0, !20, !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref, DW_OP_deref), debug-location !21
$esp = frame-destroy ADD32ri8 $esp, 24, implicit-def dead $eflags, debug-location !30 $esp = frame-destroy ADD32ri8 $esp, 24, implicit-def dead $eflags, debug-location !30
$ebp = frame-destroy POP32r implicit-def $esp, implicit $esp, debug-location !30 $ebp = frame-destroy POP32r implicit-def $esp, implicit $esp, debug-location !30
CFI_INSTRUCTION def_cfa $esp, 4, debug-location !30 CFI_INSTRUCTION def_cfa $esp, 4, debug-location !30
RETL debug-location !30 RET32 debug-location !30
... ...

llvm/test/DebugInfo/X86/dw_op_constu.mir

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines bb.0: ;-------------------------- DW_OP_plus -------------------------------
; -1 ; -1
renamable $rcx = MOV64rm renamable $noreg, 1, $noreg, 0, $fs renamable $rcx = MOV64rm renamable $noreg, 1, $noreg, 0, $fs
DBG_VALUE renamable $rcx, 0, !9, !DIExpression(DW_OP_constu, 18446744073709551615, DW_OP_minus), debug-location !14 DBG_VALUE renamable $rcx, 0, !9, !DIExpression(DW_OP_constu, 18446744073709551615, DW_OP_minus), debug-location !14
; -2 ; -2
renamable $rcx = MOV64rm renamable $noreg, 1, $noreg, 0, $fs renamable $rcx = MOV64rm renamable $noreg, 1, $noreg, 0, $fs
DBG_VALUE renamable $rcx, 0, !9, !DIExpression(DW_OP_constu, 18446744073709551614, DW_OP_minus), debug-location !14 DBG_VALUE renamable $rcx, 0, !9, !DIExpression(DW_OP_constu, 18446744073709551614, DW_OP_minus), debug-location !14
RETQ debug-location !14 RET64 debug-location !14
bb.1: ;-------------------------- DW_OP_plus ------------------------------- bb.1: ;-------------------------- DW_OP_plus -------------------------------
; UINT_MAX ; UINT_MAX
renamable $rcx = MOV64rm renamable $noreg, 1, $noreg, 0, $fs renamable $rcx = MOV64rm renamable $noreg, 1, $noreg, 0, $fs
DBG_VALUE renamable $rcx, 0, !9, !DIExpression(DW_OP_constu, 4294967295, DW_OP_plus), debug-location !14 DBG_VALUE renamable $rcx, 0, !9, !DIExpression(DW_OP_constu, 4294967295, DW_OP_plus), debug-location !14
Show All 16 Lines bb.1: ;-------------------------- DW_OP_plus -------------------------------
; -1 ; -1
renamable $rcx = MOV64rm renamable $noreg, 1, $noreg, 0, $fs renamable $rcx = MOV64rm renamable $noreg, 1, $noreg, 0, $fs
DBG_VALUE renamable $rcx, 0, !9, !DIExpression(DW_OP_constu, 18446744073709551615, DW_OP_plus), debug-location !14 DBG_VALUE renamable $rcx, 0, !9, !DIExpression(DW_OP_constu, 18446744073709551615, DW_OP_plus), debug-location !14
; -2 ; -2
renamable $rcx = MOV64rm renamable $noreg, 1, $noreg, 0, $fs renamable $rcx = MOV64rm renamable $noreg, 1, $noreg, 0, $fs
DBG_VALUE renamable $rcx, 0, !9, !DIExpression(DW_OP_constu, 18446744073709551614, DW_OP_plus), debug-location !14 DBG_VALUE renamable $rcx, 0, !9, !DIExpression(DW_OP_constu, 18446744073709551614, DW_OP_plus), debug-location !14
RETQ debug-location !14 RET64 debug-location !14
bb.2: ;-------------------------- DW_OP_plus_uconst ------------------------------- bb.2: ;-------------------------- DW_OP_plus_uconst -------------------------------
; UINT_MAX ; UINT_MAX
renamable $rcx = MOV64rm renamable $noreg, 1, $noreg, 0, $fs renamable $rcx = MOV64rm renamable $noreg, 1, $noreg, 0, $fs
DBG_VALUE renamable $rcx, 0, !9, !DIExpression(DW_OP_plus_uconst, 4294967295), debug-location !14 DBG_VALUE renamable $rcx, 0, !9, !DIExpression(DW_OP_plus_uconst, 4294967295), debug-location !14
Show All 16 Lines bb.2: ;-------------------------- DW_OP_plus_uconst -------------------------------
; -1 ; -1
renamable $rcx = MOV64rm renamable $noreg, 1, $noreg, 0, $fs renamable $rcx = MOV64rm renamable $noreg, 1, $noreg, 0, $fs
DBG_VALUE renamable $rcx, 0, !9, !DIExpression(DW_OP_plus_uconst, 18446744073709551615), debug-location !14 DBG_VALUE renamable $rcx, 0, !9, !DIExpression(DW_OP_plus_uconst, 18446744073709551615), debug-location !14
; -2 ; -2
renamable $rcx = MOV64rm renamable $noreg, 1, $noreg, 0, $fs renamable $rcx = MOV64rm renamable $noreg, 1, $noreg, 0, $fs
DBG_VALUE renamable $rcx, 0, !9, !DIExpression(DW_OP_plus_uconst, 18446744073709551614), debug-location !14 DBG_VALUE renamable $rcx, 0, !9, !DIExpression(DW_OP_plus_uconst, 18446744073709551614), debug-location !14
RETQ debug-location !14 RET64 debug-location !14
... ...
# CHECK-LABEL: .Ldebug_loc0: # CHECK-LABEL: .Ldebug_loc0:
# CHECK-NEXT: .quad .Ltmp0-.Lfunc_begin0 # CHECK-NEXT: .quad .Ltmp0-.Lfunc_begin0
# CHECK-NEXT: .quad .Ltmp1-.Lfunc_begin0 # CHECK-NEXT: .quad .Ltmp1-.Lfunc_begin0
# CHECK-NEXT: .short 9 # Loc expr size # CHECK-NEXT: .short 9 # Loc expr size
▲ Show 20 Lines • Show All 227 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/dw_op_minus.mir

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Lines bb.0.entry:
MOV64mr $rsp, 1, $noreg, 8, $noreg, killed $rcx :: (store (s64) into %stack.1) MOV64mr $rsp, 1, $noreg, 8, $noreg, killed $rcx :: (store (s64) into %stack.1)
DBG_VALUE $rsp, 0, !9, !DIExpression(DW_OP_plus_uconst, 8, DW_OP_deref, DW_OP_constu, 400, DW_OP_minus), debug-location !15 DBG_VALUE $rsp, 0, !9, !DIExpression(DW_OP_plus_uconst, 8, DW_OP_deref, DW_OP_constu, 400, DW_OP_minus), debug-location !15
CALL64pcrel32 @Capture, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp, debug-location !17 CALL64pcrel32 @Capture, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp, debug-location !17
$rax = MOV64rm $rsp, 1, $noreg, 16, $noreg :: (load (s64) from %stack.0) $rax = MOV64rm $rsp, 1, $noreg, 16, $noreg :: (load (s64) from %stack.0)
$rcx = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load (s64) from %stack.1) $rcx = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load (s64) from %stack.1)
MOV64mr killed renamable $rax, 1, $noreg, 0, $fs, killed renamable $rcx, debug-location !18 :: (store (s64) into @__safestack_unsafe_stack_ptr) MOV64mr killed renamable $rax, 1, $noreg, 0, $fs, killed renamable $rcx, debug-location !18 :: (store (s64) into @__safestack_unsafe_stack_ptr)
$rsp = frame-destroy ADD64ri8 $rsp, 24, implicit-def dead $eflags, debug-location !18 $rsp = frame-destroy ADD64ri8 $rsp, 24, implicit-def dead $eflags, debug-location !18
CFI_INSTRUCTION def_cfa_offset 8, debug-location !18 CFI_INSTRUCTION def_cfa_offset 8, debug-location !18
RETQ debug-location !18 RET64 debug-location !18
... ...

llvm/test/DebugInfo/X86/live-debug-values-constprop.mir

Show First 20 Lines • Show All 147 Lines • ▼ Show 20 Lines bb.2.bb2:
liveins: $rax liveins: $rax
$eax = ADD32ri8 $eax, 3, implicit-def dead $eflags, implicit killed $rax, implicit-def $rax $eax = ADD32ri8 $eax, 3, implicit-def dead $eflags, implicit killed $rax, implicit-def $rax
DBG_VALUE $eax, $noreg, !3, !DIExpression(), debug-location !8 DBG_VALUE $eax, $noreg, !3, !DIExpression(), debug-location !8
JMP_1 %bb.3 JMP_1 %bb.3
bb.3.bb3: bb.3.bb3:
liveins: $rax liveins: $rax
RETQ $eax, debug-location !9 RET64 $eax, debug-location !9
... ...
--- ---
name: bar name: bar
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
registers: [] registers: []
liveins: liveins:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines bb.2.bb2:
liveins: $rax liveins: $rax
$eax = ADD32ri8 $eax, 3, implicit-def dead $eflags, implicit killed $rax, implicit-def $rax $eax = ADD32ri8 $eax, 3, implicit-def dead $eflags, implicit killed $rax, implicit-def $rax
DBG_VALUE $eax, $noreg, !41, !DIExpression(), debug-location !42 DBG_VALUE $eax, $noreg, !41, !DIExpression(), debug-location !42
JMP_1 %bb.3 JMP_1 %bb.3
bb.3.bb3: bb.3.bb3:
liveins: $rax liveins: $rax
RETQ $eax, debug-location !42 RET64 $eax, debug-location !42
... ...
--- ---
name: baz name: baz
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
registers: [] registers: []
liveins: liveins:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines bb.2.bb2:
liveins: $rax liveins: $rax
$eax = ADD32ri8 $eax, 3, implicit-def dead $eflags, implicit killed $rax, implicit-def $rax $eax = ADD32ri8 $eax, 3, implicit-def dead $eflags, implicit killed $rax, implicit-def $rax
DBG_VALUE 0, $noreg, !81, !DIExpression(), debug-location !82 DBG_VALUE 0, $noreg, !81, !DIExpression(), debug-location !82
JMP_1 %bb.3 JMP_1 %bb.3
bb.3.bb3: bb.3.bb3:
liveins: $rax liveins: $rax
RETQ $eax, debug-location !82 RET64 $eax, debug-location !82
... ...
--- ---
name: qux name: qux
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
registers: [] registers: []
liveins: liveins:
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines bb.2.bb2:
liveins: $rax liveins: $rax
$eax = ADD32ri8 $eax, 3, implicit-def dead $eflags, implicit killed $rax, implicit-def $rax $eax = ADD32ri8 $eax, 3, implicit-def dead $eflags, implicit killed $rax, implicit-def $rax
DBG_VALUE 0, $noreg, !121, !DIExpression(), debug-location !122 DBG_VALUE 0, $noreg, !121, !DIExpression(), debug-location !122
JMP_1 %bb.3 JMP_1 %bb.3
bb.3.bb3: bb.3.bb3:
liveins: $rax liveins: $rax
RETQ $eax, debug-location !122 RET64 $eax, debug-location !122
... ...

llvm/test/DebugInfo/X86/location-range-inlined-xblock.mir

Show First 20 Lines • Show All 161 Lines • ▼ Show 20 Lines bb.3._ZL9inline_mev.exit:
DBG_VALUE $eax, $noreg, !28, !DIExpression(), debug-location !30 DBG_VALUE $eax, $noreg, !28, !DIExpression(), debug-location !30
DBG_VALUE $eax, $noreg, !28, !DIExpression(), debug-location !30 DBG_VALUE $eax, $noreg, !28, !DIExpression(), debug-location !30
renamable $eax = nsw IMUL32rr killed renamable $eax, killed renamable $ebx, implicit-def dead $eflags, debug-location !38 renamable $eax = nsw IMUL32rr killed renamable $eax, killed renamable $ebx, implicit-def dead $eflags, debug-location !38
MOV32mr $rip, 1, $noreg, @glob, $noreg, killed renamable $eax, debug-location !39 :: (store (s32) into @glob) MOV32mr $rip, 1, $noreg, @glob, $noreg, killed renamable $eax, debug-location !39 :: (store (s32) into @glob)
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !40 $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !40
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !40 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !40
DBG_VALUE $edi, $noreg, !15, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !16 DBG_VALUE $edi, $noreg, !15, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !16
CFI_INSTRUCTION def_cfa_offset 8, debug-location !40 CFI_INSTRUCTION def_cfa_offset 8, debug-location !40
RETQ $eax, debug-location !40 RET64 $eax, debug-location !40
... ...

llvm/test/DebugInfo/X86/location-range.mir

Show First 20 Lines • Show All 127 Lines • ▼ Show 20 Linesbody: |
bb.0.entry: bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000) successors: %bb.1(0x50000000), %bb.2(0x30000000)
CMP64mi8 $rip, 1, $noreg, @c, $noreg, 0, implicit-def $eflags, debug-location !21 :: (dereferenceable load (s64) from @c) CMP64mi8 $rip, 1, $noreg, @c, $noreg, 0, implicit-def $eflags, debug-location !21 :: (dereferenceable load (s64) from @c)
JCC_1 %bb.2, 4, implicit killed $eflags, debug-location !27 JCC_1 %bb.2, 4, implicit killed $eflags, debug-location !27
bb.1.if.then: bb.1.if.then:
renamable $rax = MOV64rm $rip, 1, $noreg, @b, $noreg, debug-location !21 :: (dereferenceable load (s64) from @b) renamable $rax = MOV64rm $rip, 1, $noreg, @b, $noreg, debug-location !21 :: (dereferenceable load (s64) from @b)
RETQ $rax, debug-location !27 RET64 $rax, debug-location !27
bb.2.if.end: bb.2.if.end:
DBG_VALUE 0, $noreg, !19, !DIExpression(), debug-location !27 DBG_VALUE 0, $noreg, !19, !DIExpression(), debug-location !27
renamable $rax = MOV64rm $rip, 1, $noreg, @a, $noreg, debug-location !27 :: (dereferenceable load (s64) from @a) renamable $rax = MOV64rm $rip, 1, $noreg, @a, $noreg, debug-location !27 :: (dereferenceable load (s64) from @a)
RETQ $rax, debug-location !27 RET64 $rax, debug-location !27
... ...
--- ---
name: funtwo name: funtwo
body: | body: |
bb.0.entry: bb.0.entry:
$eax = MOVZX32rm16 $noreg, 1, $noreg, 0, $noreg, debug-location !48 :: (load (s16) from `i16* null`, align 1) $eax = MOVZX32rm16 $noreg, 1, $noreg, 0, $noreg, debug-location !48 :: (load (s16) from `i16* null`, align 1)
DBG_VALUE $ax, $noreg, !39, !DIExpression(), debug-location !51 DBG_VALUE $ax, $noreg, !39, !DIExpression(), debug-location !51
RETQ $ax, debug-location !51 RET64 $ax, debug-location !51
... ...

llvm/test/DebugInfo/X86/pr19307.mir

Show First 20 Lines • Show All 213 Lines • ▼ Show 20 Lines bb.3.if.end:
$edx = MOV32ri 6, implicit-def $rdx, debug-location !51 $edx = MOV32ri 6, implicit-def $rdx, debug-location !51
CALL64pcrel32 @_ZNSs5eraseEmm, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit killed $rsi, implicit killed $rdx, implicit-def $rax, debug-location !51 CALL64pcrel32 @_ZNSs5eraseEmm, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit killed $rsi, implicit killed $rdx, implicit-def $rax, debug-location !51
renamable $rdx = MOV64rm $rbp, 1, $noreg, -16, $noreg, debug-location !52 :: (load (s64) from %ir.limit.addr) renamable $rdx = MOV64rm $rbp, 1, $noreg, -16, $noreg, debug-location !52 :: (load (s64) from %ir.limit.addr)
MOV64mi32 killed renamable $rdx, 1, $noreg, 0, $noreg, 2, debug-location !52 :: (store (s64) into %ir.2) MOV64mi32 killed renamable $rdx, 1, $noreg, 0, $noreg, 2, debug-location !52 :: (store (s64) into %ir.2)
MOV64mr $rbp, 1, $noreg, -32, $noreg, killed $rax :: (store (s64) into %stack.3) MOV64mr $rbp, 1, $noreg, -32, $noreg, killed $rax :: (store (s64) into %stack.3)
$rsp = frame-destroy ADD64ri8 $rsp, 32, implicit-def dead $eflags, debug-location !53 $rsp = frame-destroy ADD64ri8 $rsp, 32, implicit-def dead $eflags, debug-location !53
$rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !53 $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !53
CFI_INSTRUCTION def_cfa $rsp, 8, debug-location !53 CFI_INSTRUCTION def_cfa $rsp, 8, debug-location !53
RETQ debug-location !53 RET64 debug-location !53
... ...

llvm/test/DebugInfo/X86/pr34545.ll

; RUN: llc -O1 -filetype=asm -mtriple x86_64-unknown-linux-gnu -mcpu=x86-64 -o - %s -stop-after=livedebugvars | FileCheck %s ; RUN: llc -O1 -filetype=asm -mtriple x86_64-unknown-linux-gnu -mcpu=x86-64 -o - %s -stop-after=livedebugvars | FileCheck %s
; CHECK: $eax = MOV32rm ; CHECK: $eax = MOV32rm
; CHECK: DBG_VALUE $eax ; CHECK: DBG_VALUE $eax
; CHECK: $eax = SHL32rCL killed renamable $eax ; CHECK: $eax = SHL32rCL killed renamable $eax
; CHECK: DBG_VALUE $eax ; CHECK: DBG_VALUE $eax
; CHECK: DBG_VALUE $rsp, 0, !{{[0-9]+}}, !DIExpression(DW_OP_constu, 4, DW_OP_minus) ; CHECK: DBG_VALUE $rsp, 0, !{{[0-9]+}}, !DIExpression(DW_OP_constu, 4, DW_OP_minus)
; CHECK: DBG_VALUE $eax ; CHECK: DBG_VALUE $eax
; CHECK: $eax = SHL32rCL killed renamable $eax ; CHECK: $eax = SHL32rCL killed renamable $eax
; CHECK: DBG_VALUE $eax ; CHECK: DBG_VALUE $eax
; CHECK: RETQ $eax ; CHECK: RET64 $eax
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
@var = local_unnamed_addr global i32 8, !dbg !0 @var = local_unnamed_addr global i32 8, !dbg !0
@sc = local_unnamed_addr global i32 1, !dbg !6 @sc = local_unnamed_addr global i32 1, !dbg !6
define i32 @main() local_unnamed_addr !dbg !14 { define i32 @main() local_unnamed_addr !dbg !14 {
Show All 39 Lines

llvm/test/DebugInfo/X86/single-location-2.mir

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines bb.0.entry:
; CHECK-NEXT: DW_AT_location (DW_OP_reg4 RSI) ; CHECK-NEXT: DW_AT_location (DW_OP_reg4 RSI)
; CHECK-NEXT: DW_AT_name ("localc") ; CHECK-NEXT: DW_AT_name ("localc")
; ;
;; start scope, start location range ;; start scope, start location range
DBG_VALUE $esi, $noreg, !25, !DIExpression(), debug-location !26 DBG_VALUE $esi, $noreg, !25, !DIExpression(), debug-location !26
;; end scope, end location range ;; end scope, end location range
$esi = MOV32ri 2, debug-location !26 $esi = MOV32ri 2, debug-location !26
RETQ debug-location !15 RET64 debug-location !15
... ...

llvm/test/DebugInfo/X86/single-location-inlined-param.mir

Show First 20 Lines • Show All 99 Lines • ▼ Show 20 Lines bb.0.entry:
MOV32mr $rip, 1, $noreg, @glob, $noreg, renamable $edi, debug-location !27 :: (store (s32) into @glob) MOV32mr $rip, 1, $noreg, @glob, $noreg, renamable $edi, debug-location !27 :: (store (s32) into @glob)
renamable $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags renamable $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
TEST32rr killed renamable $edi, renamable $edi, implicit-def $eflags, debug-location !32 TEST32rr killed renamable $edi, renamable $edi, implicit-def $eflags, debug-location !32
JCC_1 %bb.1, 4, implicit $eflags, debug-location !34 JCC_1 %bb.1, 4, implicit $eflags, debug-location !34
bb.2.return: bb.2.return:
liveins: $eax liveins: $eax
RETQ $eax, debug-location !36 RET64 $eax, debug-location !36
bb.1.if.end: bb.1.if.end:
renamable $eax = MOV32ri 1 renamable $eax = MOV32ri 1
RETQ $eax, debug-location !36 RET64 $eax, debug-location !36
... ...

llvm/test/DebugInfo/X86/single-location-interrupted-scope.mir

Show First 20 Lines • Show All 149 Lines • ▼ Show 20 Lines bb.0.entry:
MOV32mr $rip, 1, $noreg, @globb, $noreg, killed renamable $esi, debug-location !31 :: (store (s32) into @globb) MOV32mr $rip, 1, $noreg, @globb, $noreg, killed renamable $esi, debug-location !31 :: (store (s32) into @globb)
JCC_1 %bb.1, 14, implicit $eflags, debug-location !34 JCC_1 %bb.1, 14, implicit $eflags, debug-location !34
bb.2.if.then: bb.2.if.then:
dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al, debug-location !35 dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al, debug-location !35
TAILJMPd64 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rsp, implicit $ssp, implicit killed $al, debug-location !35 TAILJMPd64 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rsp, implicit $ssp, implicit killed $al, debug-location !35
bb.1.if.end: bb.1.if.end:
RETQ debug-location !36 RET64 debug-location !36
... ...
--- ---
name: funtwo name: funtwo
body: | body: |
bb.0.entry: bb.0.entry:
successors: %bb.2(0x50000000), %bb.1(0x30000000) successors: %bb.2(0x50000000), %bb.1(0x30000000)
liveins: $edi, $esi liveins: $edi, $esi
DBG_VALUE $edi, $noreg, !20, !DIExpression(), debug-location !41 DBG_VALUE $edi, $noreg, !20, !DIExpression(), debug-location !41
MOV32mr $rip, 1, $noreg, @globa, $noreg, renamable $edi, debug-location !43 :: (store (s32) into @globa) MOV32mr $rip, 1, $noreg, @globa, $noreg, renamable $edi, debug-location !43 :: (store (s32) into @globa)
renamable $edi = nsw ADD32rr killed renamable $edi, renamable $esi, implicit-def dead $eflags, debug-location !44 renamable $edi = nsw ADD32rr killed renamable $edi, renamable $esi, implicit-def dead $eflags, debug-location !44
MOV32mr $rip, 1, $noreg, @globb, $noreg, killed renamable $edi, debug-location !45 :: (store (s32) into @globb) MOV32mr $rip, 1, $noreg, @globb, $noreg, killed renamable $edi, debug-location !45 :: (store (s32) into @globb)
TEST32rr killed renamable $esi, renamable $esi, implicit-def $eflags, debug-location !46 TEST32rr killed renamable $esi, renamable $esi, implicit-def $eflags, debug-location !46
JCC_1 %bb.1, 14, implicit $eflags, debug-location !48 JCC_1 %bb.1, 14, implicit $eflags, debug-location !48
bb.2.if.then: bb.2.if.then:
dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al, debug-location !49 dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al, debug-location !49
TAILJMPd64 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rsp, implicit $ssp, implicit killed $al, debug-location !49 TAILJMPd64 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rsp, implicit $ssp, implicit killed $al, debug-location !49
bb.1.if.end: bb.1.if.end:
RETQ debug-location !50 RET64 debug-location !50
... ...

llvm/test/DebugInfo/X86/trim-var-locs.mir

Show First 20 Lines • Show All 110 Lines • ▼ Show 20 Lines bb.0.entry:
; localc range 1 start in scope !7 ; localc range 1 start in scope !7
DBG_VALUE $edi, $noreg, !25, !DIExpression(), debug-location !18 DBG_VALUE $edi, $noreg, !25, !DIExpression(), debug-location !18
; localc range 1 clobber in scope !7 ; localc range 1 clobber in scope !7
$edi = MOV32ri 8, debug-location !15 $edi = MOV32ri 8, debug-location !15
; scope block !24 start and end range 2 ; scope block !24 start and end range 2
$edi = MOV32ri 9, debug-location !26 $edi = MOV32ri 9, debug-location !26
; scope fun !7 ; scope fun !7
RETQ debug-location !15 RET64 debug-location !15
... ...

llvm/test/Transforms/SampleProfile/pseudo-probe.mir

Show All 13 Linesbody: |
bb.0: bb.0:
TEST32rr killed renamable $edi, renamable $edi, implicit-def $eflags TEST32rr killed renamable $edi, renamable $edi, implicit-def $eflags
PSEUDO_PROBE 6699318081062747564, 1, 0, 0 PSEUDO_PROBE 6699318081062747564, 1, 0, 0
JCC_1 %bb.1, 4, implicit $eflags JCC_1 %bb.1, 4, implicit $eflags
bb.2: bb.2:
PSEUDO_PROBE 6699318081062747564, 3, 0, 0 PSEUDO_PROBE 6699318081062747564, 3, 0, 0
PSEUDO_PROBE 6699318081062747564, 4, 0, 0 PSEUDO_PROBE 6699318081062747564, 4, 0, 0
RETQ RET64
bb.1: bb.1:
PSEUDO_PROBE 6699318081062747564, 2, 0, 0 PSEUDO_PROBE 6699318081062747564, 2, 0, 0
PSEUDO_PROBE 6699318081062747564, 4, 0, 0 PSEUDO_PROBE 6699318081062747564, 4, 0, 0
RETQ RET64
... ...

llvm/unittests/CodeGen/InstrRefLDVTest.cpp

Show First 20 Lines • Show All 479 Lines • ▼ Show 20 Lines)MIR") + Twine(Input) + Twine("...\n"))
produceMLocTransferFunction(MachineFunction &MF, produceMLocTransferFunction(MachineFunction &MF,
SmallVectorImpl<MLocTransferMap> &MLocTransfer, SmallVectorImpl<MLocTransferMap> &MLocTransfer,
unsigned MaxNumBlocks) { unsigned MaxNumBlocks) {
LDV->produceMLocTransferFunction(MF, MLocTransfer, MaxNumBlocks); LDV->produceMLocTransferFunction(MF, MLocTransfer, MaxNumBlocks);
} }
}; };
TEST_F(InstrRefLDVTest, MTransferDefs) { TEST_F(InstrRefLDVTest, MTransferDefs) {
MachineFunction *MF = readMIRBlock( MachineFunction *MF = readMIRBlock(
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  MachineFunction *MF = readMIRBlock(
-   "    $rax = MOV64ri 0\n"
-   "    RET64 $rax\n");
+  MachineFunction *MF = readMIRBlock("    $rax = MOV64ri 0\n"
+                                     "    RET64 $rax\n");
Lint: Pre-merge checks: clang-format: please reformat the code ``` - MachineFunction *MF = readMIRBlock( - " $rax…
" $rax = MOV64ri 0\n" " $rax = MOV64ri 0\n"
" RETQ $rax\n"); " RET64 $rax\n");
setupLDVObj(MF); setupLDVObj(MF);
// We should start with only SP tracked. // We should start with only SP tracked.
EXPECT_TRUE(MTracker->getNumLocs() == 1); EXPECT_TRUE(MTracker->getNumLocs() == 1);
SmallVector<MLocTransferMap, 1> TransferMap; SmallVector<MLocTransferMap, 1> TransferMap;
TransferMap.resize(1); TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1); produceMLocTransferFunction(*MF, TransferMap, 1);
Show All 12 Lines for (const char *RegName : RegNames) {
// location it's defined in is itself. // location it's defined in is itself.
ValueIDNum ToCmp(0, 1, L); ValueIDNum ToCmp(0, 1, L);
EXPECT_EQ(V, ToCmp); EXPECT_EQ(V, ToCmp);
} }
// Do the same again, but with an aliasing write. This should write to all // Do the same again, but with an aliasing write. This should write to all
// the same registers again, except $ah and $hax (the upper 8 bits of $ax // the same registers again, except $ah and $hax (the upper 8 bits of $ax
// and 32 bits of $rax resp.). // and 32 bits of $rax resp.).
MF = readMIRBlock( MF = readMIRBlock(
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  MF = readMIRBlock(
-   "    $rax = MOV64ri 0\n"
-   "    $al = MOV8ri 0\n"
-   "    RET64 $rax\n");
+  MF = readMIRBlock("    $rax = MOV64ri 0\n"
+                    "    $al = MOV8ri 0\n"
+                    "    RET64 $rax\n");
Lint: Pre-merge checks: clang-format: please reformat the code ``` - MF = readMIRBlock( - " $rax = MOV64ri 0\n"…
" $rax = MOV64ri 0\n" " $rax = MOV64ri 0\n"
" $al = MOV8ri 0\n" " $al = MOV8ri 0\n"
" RETQ $rax\n"); " RET64 $rax\n");
setupLDVObj(MF); setupLDVObj(MF);
TransferMap.clear(); TransferMap.clear();
TransferMap.resize(1); TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1); produceMLocTransferFunction(*MF, TransferMap, 1);
auto TestRegSetSite = [&](const char *Name, unsigned InstrNum) { auto TestRegSetSite = [&](const char *Name, unsigned InstrNum) {
Register R = getRegByName(Name); Register R = getRegByName(Name);
ASSERT_TRUE(MTracker->isRegisterTracked(R)); ASSERT_TRUE(MTracker->isRegisterTracked(R));
Show All 13 LinesTEST_F(InstrRefLDVTest, MTransferDefs) {
// This call should: // This call should:
// * Def rax via the implicit-def, // * Def rax via the implicit-def,
// * Clobber rsi/rdi and all their subregs, via the register mask // * Clobber rsi/rdi and all their subregs, via the register mask
// * Same for rcx, despite it not being a use in the instr, it's in the mask // * Same for rcx, despite it not being a use in the instr, it's in the mask
// * NOT clobber $rsp / $esp $ sp, LiveDebugValues deliberately ignores // * NOT clobber $rsp / $esp $ sp, LiveDebugValues deliberately ignores
// these. // these.
// * NOT clobber $rbx, because it's non-volatile // * NOT clobber $rbx, because it's non-volatile
// * Not track every other register in the machine, only those needed. // * Not track every other register in the machine, only those needed.
MF = readMIRBlock( MF = readMIRBlock(
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

- MF = readMIRBlock(
-   "    $rax = MOV64ri 0\n" // instr 1
-   "    $rbx = MOV64ri 0\n" // instr 2
-   "    $rcx = MOV64ri 0\n" // instr 3
-   "    $rdi = MOV64ri 0\n" // instr 4
-   "    $rsi = MOV64ri 0\n" // instr 5
-   "    CALL64r $rax, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp, implicit-def $rax, implicit-def $esp, implicit-def $sp\n\n\n\n" // instr 6
-   "    RET64 $rax\n"); // instr 7
+  MF = readMIRBlock(
+      "    $rax = MOV64ri 0\n" // instr 1

8 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - MF = readMIRBlock( - " $rax = MOV64ri 0\n" //…
" $rax = MOV64ri 0\n" // instr 1 " $rax = MOV64ri 0\n" // instr 1
" $rbx = MOV64ri 0\n" // instr 2 " $rbx = MOV64ri 0\n" // instr 2
" $rcx = MOV64ri 0\n" // instr 3 " $rcx = MOV64ri 0\n" // instr 3
" $rdi = MOV64ri 0\n" // instr 4 " $rdi = MOV64ri 0\n" // instr 4
" $rsi = MOV64ri 0\n" // instr 5 " $rsi = MOV64ri 0\n" // instr 5
" CALL64r $rax, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp, implicit-def $rax, implicit-def $esp, implicit-def $sp\n\n\n\n" // instr 6 " CALL64r $rax, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp, implicit-def $rax, implicit-def $esp, implicit-def $sp\n\n\n\n" // instr 6
" RETQ $rax\n"); // instr 7 " RET64 $rax\n"); // instr 7
setupLDVObj(MF); setupLDVObj(MF);
TransferMap.clear(); TransferMap.clear();
TransferMap.resize(1); TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1); produceMLocTransferFunction(*MF, TransferMap, 1);
const char *RegsSetInCall[] = {"AL", "AH", "AX", "EAX", "HAX", "RAX", const char *RegsSetInCall[] = {"AL", "AH", "AX", "EAX", "HAX", "RAX",
"DIL", "DIH", "DI", "EDI", "HDI", "RDI", "DIL", "DIH", "DI", "EDI", "HDI", "RDI",
"SIL", "SIH", "SI", "ESI", "HSI", "RSI", "SIL", "SIH", "SI", "ESI", "HSI", "RSI",
Show All 15 Lines MF = readMIRBlock(
EXPECT_FALSE(MTracker->isRegisterTracked(getRegByName("HSP"))); EXPECT_FALSE(MTracker->isRegisterTracked(getRegByName("HSP")));
// Should only be tracking: 6 x {A, B, C, DI, SI} registers = 30, // Should only be tracking: 6 x {A, B, C, DI, SI} registers = 30,
// Plus RSP, SSP = 32. // Plus RSP, SSP = 32.
EXPECT_EQ(32u, MTracker->getNumLocs()); EXPECT_EQ(32u, MTracker->getNumLocs());
// When we DBG_PHI something, we should track all its subregs. // When we DBG_PHI something, we should track all its subregs.
MF = readMIRBlock( MF = readMIRBlock(
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  MF = readMIRBlock(
-   "    DBG_PHI $rdi, 0\n"
-   "    RET64\n");
+  MF = readMIRBlock("    DBG_PHI $rdi, 0\n"
+                    "    RET64\n");
Lint: Pre-merge checks: clang-format: please reformat the code ``` - MF = readMIRBlock( - " DBG_PHI $rdi, 0\n"…
" DBG_PHI $rdi, 0\n" " DBG_PHI $rdi, 0\n"
" RETQ\n"); " RET64\n");
setupLDVObj(MF); setupLDVObj(MF);
TransferMap.clear(); TransferMap.clear();
TransferMap.resize(1); TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1); produceMLocTransferFunction(*MF, TransferMap, 1);
// All DI regs and RSP tracked. // All DI regs and RSP tracked.
EXPECT_EQ(7u, MTracker->getNumLocs()); EXPECT_EQ(7u, MTracker->getNumLocs());
// All the DI registers should have block live-in values, i.e. the argument // All the DI registers should have block live-in values, i.e. the argument
// to the function. // to the function.
const char *DIRegs[] = {"DIL", "DIH", "DI", "EDI", "HDI", "RDI"}; const char *DIRegs[] = {"DIL", "DIH", "DI", "EDI", "HDI", "RDI"};
for (const char *DIReg : DIRegs) for (const char *DIReg : DIRegs)
TestRegSetSite(DIReg, 0); TestRegSetSite(DIReg, 0);
} }
TEST_F(InstrRefLDVTest, MTransferMeta) { TEST_F(InstrRefLDVTest, MTransferMeta) {
// Meta instructions should not have any effect on register values. // Meta instructions should not have any effect on register values.
SmallVector<MLocTransferMap, 1> TransferMap; SmallVector<MLocTransferMap, 1> TransferMap;
MachineFunction *MF = readMIRBlock( MachineFunction *MF = readMIRBlock(
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  MachineFunction *MF = readMIRBlock(
-   "    $rax = MOV64ri 0\n"
-   "    $rax = IMPLICIT_DEF\n"
-   "    $rax = KILL killed $rax\n"
-   "    RET64 $rax\n");
+  MachineFunction *MF = readMIRBlock("    $rax = MOV64ri 0\n"
+                                     "    $rax = IMPLICIT_DEF\n"
+                                     "    $rax = KILL killed $rax\n"
+                                     "    RET64 $rax\n");
Lint: Pre-merge checks: clang-format: please reformat the code ``` - MachineFunction *MF = readMIRBlock( - " $rax…
" $rax = MOV64ri 0\n" " $rax = MOV64ri 0\n"
" $rax = IMPLICIT_DEF\n" " $rax = IMPLICIT_DEF\n"
" $rax = KILL killed $rax\n" " $rax = KILL killed $rax\n"
" RETQ $rax\n"); " RET64 $rax\n");
setupLDVObj(MF); setupLDVObj(MF);
TransferMap.clear(); TransferMap.clear();
TransferMap.resize(1); TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1); produceMLocTransferFunction(*MF, TransferMap, 1);
LocIdx RaxLoc = MTracker->getRegMLoc(getRegByName("RAX")); LocIdx RaxLoc = MTracker->getRegMLoc(getRegByName("RAX"));
ValueIDNum V = MTracker->readMLoc(RaxLoc); ValueIDNum V = MTracker->readMLoc(RaxLoc);
// Def of rax should be from instruction 1, i.e., unmodified. // Def of rax should be from instruction 1, i.e., unmodified.
ValueIDNum Cmp(0, 1, RaxLoc); ValueIDNum Cmp(0, 1, RaxLoc);
EXPECT_EQ(Cmp, V); EXPECT_EQ(Cmp, V);
} }
TEST_F(InstrRefLDVTest, MTransferCopies) { TEST_F(InstrRefLDVTest, MTransferCopies) {
SmallVector<MLocTransferMap, 1> TransferMap; SmallVector<MLocTransferMap, 1> TransferMap;
// This memory spill should be recognised, and a spill slot created. // This memory spill should be recognised, and a spill slot created.
MachineFunction *MF = readMIRBlock( MachineFunction *MF = readMIRBlock(
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  MachineFunction *MF = readMIRBlock(
-   "    $rax = MOV64ri 0\n"
-   "    MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n"
-   "    RET64 $rax\n");
+  MachineFunction *MF = readMIRBlock("    $rax = MOV64ri 0\n"
+                                     "    MOV64mr $rsp, 1, $noreg, 16, $noreg, "
+                                     "$rax :: (store 8 into %stack.0)\n"
+                                     "    RET64 $rax\n");
Lint: Pre-merge checks: clang-format: please reformat the code ``` - MachineFunction *MF = readMIRBlock( - " $rax…
" $rax = MOV64ri 0\n" " $rax = MOV64ri 0\n"
" MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n" " MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n"
" RETQ $rax\n"); " RET64 $rax\n");
setupLDVObj(MF); setupLDVObj(MF);
TransferMap.clear(); TransferMap.clear();
TransferMap.resize(1); TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1); produceMLocTransferFunction(*MF, TransferMap, 1);
// Check that the spill location contains the value defined in rax by // Check that the spill location contains the value defined in rax by
// instruction 1. The MIR header says -16 offset, but it's stored as -8; // instruction 1. The MIR header says -16 offset, but it's stored as -8;
// it's not completely clear why, but here we only care about correctly // it's not completely clear why, but here we only care about correctly
// identifying the slot, not that all the surrounding data is correct. // identifying the slot, not that all the surrounding data is correct.
SpillLoc L = {getRegByName("RSP"), StackOffset::getFixed(-8)}; SpillLoc L = {getRegByName("RSP"), StackOffset::getFixed(-8)};
SpillLocationNo SpillNo = MTracker->getOrTrackSpillLoc(L); SpillLocationNo SpillNo = MTracker->getOrTrackSpillLoc(L);
unsigned SpillLocID = MTracker->getLocID(SpillNo, {64, 0}); unsigned SpillLocID = MTracker->getLocID(SpillNo, {64, 0});
LocIdx SpillLoc = MTracker->getSpillMLoc(SpillLocID); LocIdx SpillLoc = MTracker->getSpillMLoc(SpillLocID);
ValueIDNum V = MTracker->readMLoc(SpillLoc); ValueIDNum V = MTracker->readMLoc(SpillLoc);
Register RAX = getRegByName("RAX"); Register RAX = getRegByName("RAX");
LocIdx RaxLoc = MTracker->getRegMLoc(RAX); LocIdx RaxLoc = MTracker->getRegMLoc(RAX);
ValueIDNum Cmp(0, 1, RaxLoc); ValueIDNum Cmp(0, 1, RaxLoc);
EXPECT_EQ(V, Cmp); EXPECT_EQ(V, Cmp);
// A spill and restore should be recognised. // A spill and restore should be recognised.
MF = readMIRBlock( MF = readMIRBlock(
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  MF = readMIRBlock(
-   "    $rax = MOV64ri 0\n"
-   "    MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n"
-   "    $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n"
-   "    RET64\n");
+  MF = readMIRBlock("    $rax = MOV64ri 0\n"
+                    "    MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 "
+                    "into %stack.0)\n"
+                    "    $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 "
+                    "from %stack.0)\n"
+                    "    RET64\n");
Lint: Pre-merge checks: clang-format: please reformat the code ``` - MF = readMIRBlock( - " $rax = MOV64ri 0\n"…
" $rax = MOV64ri 0\n" " $rax = MOV64ri 0\n"
" MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n" " MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n"
" $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n" " $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n"
" RETQ\n"); " RET64\n");
setupLDVObj(MF); setupLDVObj(MF);
TransferMap.clear(); TransferMap.clear();
TransferMap.resize(1); TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1); produceMLocTransferFunction(*MF, TransferMap, 1);
// Test that rbx contains rax from instruction 1. // Test that rbx contains rax from instruction 1.
RAX = getRegByName("RAX"); RAX = getRegByName("RAX");
RaxLoc = MTracker->getRegMLoc(RAX); RaxLoc = MTracker->getRegMLoc(RAX);
Register RBX = getRegByName("RBX"); Register RBX = getRegByName("RBX");
LocIdx RbxLoc = MTracker->getRegMLoc(RBX); LocIdx RbxLoc = MTracker->getRegMLoc(RBX);
Cmp = ValueIDNum(0, 1, RaxLoc); Cmp = ValueIDNum(0, 1, RaxLoc);
ValueIDNum RbxVal = MTracker->readMLoc(RbxLoc); ValueIDNum RbxVal = MTracker->readMLoc(RbxLoc);
EXPECT_EQ(RbxVal, Cmp); EXPECT_EQ(RbxVal, Cmp);
// Testing that all the subregisters are transferred happens in // Testing that all the subregisters are transferred happens in
// MTransferSubregSpills. // MTransferSubregSpills.
// Copies and x86 movs should be recognised and honoured. In addition, all // Copies and x86 movs should be recognised and honoured. In addition, all
// of the subregisters should be copied across too. // of the subregisters should be copied across too.
MF = readMIRBlock( MF = readMIRBlock(
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  MF = readMIRBlock(
-   "    $rax = MOV64ri 0\n"
-   "    $rcx = COPY $rax\n"
-   "    $rbx = MOV64rr $rcx\n"
-   "    RET64\n");
+  MF = readMIRBlock("    $rax = MOV64ri 0\n"
+                    "    $rcx = COPY $rax\n"
+                    "    $rbx = MOV64rr $rcx\n"
+                    "    RET64\n");
Lint: Pre-merge checks: clang-format: please reformat the code ``` - MF = readMIRBlock( - " $rax = MOV64ri 0\n"…
" $rax = MOV64ri 0\n" " $rax = MOV64ri 0\n"
" $rcx = COPY $rax\n" " $rcx = COPY $rax\n"
" $rbx = MOV64rr $rcx\n" " $rbx = MOV64rr $rcx\n"
" RETQ\n"); " RET64\n");
setupLDVObj(MF); setupLDVObj(MF);
TransferMap.clear(); TransferMap.clear();
TransferMap.resize(1); TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1); produceMLocTransferFunction(*MF, TransferMap, 1);
const char *ARegs[] = {"AL", "AH", "AX", "EAX", "HAX", "RAX"}; const char *ARegs[] = {"AL", "AH", "AX", "EAX", "HAX", "RAX"};
const char *BRegs[] = {"BL", "BH", "BX", "EBX", "HBX", "RBX"}; const char *BRegs[] = {"BL", "BH", "BX", "EBX", "HBX", "RBX"};
const char *CRegs[] = {"CL", "CH", "CX", "ECX", "HCX", "RCX"}; const char *CRegs[] = {"CL", "CH", "CX", "ECX", "HCX", "RCX"};
Show All 10 Lines auto CheckReg = [&](unsigned int I) {
EXPECT_EQ(ARefVal, CVal); EXPECT_EQ(ARefVal, CVal);
}; };
for (unsigned int I = 0; I < 6; ++I) for (unsigned int I = 0; I < 6; ++I)
CheckReg(I); CheckReg(I);
// When we copy to a subregister, the super-register should be def'd too: it's // When we copy to a subregister, the super-register should be def'd too: it's
// value will have changed. // value will have changed.
MF = readMIRBlock( MF = readMIRBlock(
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  MF = readMIRBlock(
-   "    $rax = MOV64ri 0\n"
-   "    $ecx = COPY $eax\n"
-   "    RET64\n");
+  MF = readMIRBlock("    $rax = MOV64ri 0\n"
+                    "    $ecx = COPY $eax\n"
+                    "    RET64\n");
Lint: Pre-merge checks: clang-format: please reformat the code ``` - MF = readMIRBlock( - " $rax = MOV64ri 0\n"…
" $rax = MOV64ri 0\n" " $rax = MOV64ri 0\n"
" $ecx = COPY $eax\n" " $ecx = COPY $eax\n"
" RETQ\n"); " RET64\n");
setupLDVObj(MF); setupLDVObj(MF);
TransferMap.clear(); TransferMap.clear();
TransferMap.resize(1); TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1); produceMLocTransferFunction(*MF, TransferMap, 1);
// First four regs [al, ah, ax, eax] should be copied to *cx. // First four regs [al, ah, ax, eax] should be copied to *cx.
for (unsigned int I = 0; I < 4; ++I) { for (unsigned int I = 0; I < 4; ++I) {
LocIdx A = MTracker->getRegMLoc(getRegByName(ARegs[I])); LocIdx A = MTracker->getRegMLoc(getRegByName(ARegs[I]));
Show All 9 LinesTEST_F(InstrRefLDVTest, MTransferCopies) {
LocIdx RcxLoc = MTracker->getRegMLoc(getRegByName("RCX")); LocIdx RcxLoc = MTracker->getRegMLoc(getRegByName("RCX"));
ValueIDNum RcxVal = MTracker->readMLoc(RcxLoc); ValueIDNum RcxVal = MTracker->readMLoc(RcxLoc);
ValueIDNum RcxDefVal(0, 2, RcxLoc); // instr 2 -> the copy ValueIDNum RcxDefVal(0, 2, RcxLoc); // instr 2 -> the copy
EXPECT_EQ(RcxVal, RcxDefVal); EXPECT_EQ(RcxVal, RcxDefVal);
} }
TEST_F(InstrRefLDVTest, MTransferSubregSpills) { TEST_F(InstrRefLDVTest, MTransferSubregSpills) {
SmallVector<MLocTransferMap, 1> TransferMap; SmallVector<MLocTransferMap, 1> TransferMap;
MachineFunction *MF = readMIRBlock( MachineFunction *MF = readMIRBlock(
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  MachineFunction *MF = readMIRBlock(
-   "    $rax = MOV64ri 0\n"
-   "    MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n"
-   "    $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n"
-   "    RET64\n");
+  MachineFunction *MF = readMIRBlock("    $rax = MOV64ri 0\n"
+                                     "    MOV64mr $rsp, 1, $noreg, 16, $noreg, "
+                                     "$rax :: (store 8 into %stack.0)\n"
+                                     "    $rbx = MOV64rm $rsp, 1, $noreg, 0, "
+                                     "$noreg :: (load 8 from %stack.0)\n"
+                                     "    RET64\n");
Lint: Pre-merge checks: clang-format: please reformat the code ``` - MachineFunction *MF = readMIRBlock( - " $rax…
" $rax = MOV64ri 0\n" " $rax = MOV64ri 0\n"
" MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n" " MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n"
" $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n" " $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n"
" RETQ\n"); " RET64\n");
setupLDVObj(MF); setupLDVObj(MF);
TransferMap.clear(); TransferMap.clear();
TransferMap.resize(1); TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1); produceMLocTransferFunction(*MF, TransferMap, 1);
// Check that all the subregs of rax and rbx contain the same values. One // Check that all the subregs of rax and rbx contain the same values. One
// should completely transfer to the other. // should completely transfer to the other.
const char *ARegs[] = {"AL", "AH", "AX", "EAX", "HAX", "RAX"}; const char *ARegs[] = {"AL", "AH", "AX", "EAX", "HAX", "RAX"};
Show All 25 LinesTEST_F(InstrRefLDVTest, MTransferSubregSpills) {
// $rax, then we should still have exactly the same output in the lower five // $rax, then we should still have exactly the same output in the lower five
// subregisters. Storing $eax to the start of the slot will overwrite with the // subregisters. Storing $eax to the start of the slot will overwrite with the
// same values. $rax, as an aliasing register, should be reset to something // same values. $rax, as an aliasing register, should be reset to something
// else by that write. // else by that write.
// In theory, we could try and recognise that we're writing the _same_ values // In theory, we could try and recognise that we're writing the _same_ values
// to the stack again, and so $rax doesn't need to be reset to something else. // to the stack again, and so $rax doesn't need to be reset to something else.
// It seems vanishingly unlikely that LLVM would generate such code though, // It seems vanishingly unlikely that LLVM would generate such code though,
// so the benefits would be small. // so the benefits would be small.
MF = readMIRBlock( MF = readMIRBlock(
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  MF = readMIRBlock(
-   "    $rax = MOV64ri 0\n"
-   "    MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n"
-   "    MOV32mr $rsp, 1, $noreg, 16, $noreg, $eax :: (store 4 into %stack.0)\n"
-   "    $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n"
-   "    RET64\n");
+  MF = readMIRBlock("    $rax = MOV64ri 0\n"
+                    "    MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 "
+                    "into %stack.0)\n"
+                    "    MOV32mr $rsp, 1, $noreg, 16, $noreg, $eax :: (store 4 "

4 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - MF = readMIRBlock( - " $rax = MOV64ri 0\n"…
" $rax = MOV64ri 0\n" " $rax = MOV64ri 0\n"
" MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n" " MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n"
" MOV32mr $rsp, 1, $noreg, 16, $noreg, $eax :: (store 4 into %stack.0)\n" " MOV32mr $rsp, 1, $noreg, 16, $noreg, $eax :: (store 4 into %stack.0)\n"
" $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n" " $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n"
" RETQ\n"); " RET64\n");
setupLDVObj(MF); setupLDVObj(MF);
TransferMap.clear(); TransferMap.clear();
TransferMap.resize(1); TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1); produceMLocTransferFunction(*MF, TransferMap, 1);
// Check lower five registers up to and include $eax == $ebx, // Check lower five registers up to and include $eax == $ebx,
for (unsigned int I = 0; I < 5; ++I) { for (unsigned int I = 0; I < 5; ++I) {
LocIdx A = MTracker->getRegMLoc(getRegByName(ARegs[I])); LocIdx A = MTracker->getRegMLoc(getRegByName(ARegs[I]));
Show All 28 LinesTEST_F(InstrRefLDVTest, MTransferSubregSpills) {
// Stack slot for $rax should be a different value, today it's EmptyValue. // Stack slot for $rax should be a different value, today it's EmptyValue.
ValueIDNum SpillValue = MTracker->readMLoc(Spill64Loc); ValueIDNum SpillValue = MTracker->readMLoc(Spill64Loc);
EXPECT_EQ(SpillValue, DefAtSpill64); EXPECT_EQ(SpillValue, DefAtSpill64);
// If we write something to the stack, then over-write with some register // If we write something to the stack, then over-write with some register
// from a completely different hierarchy, none of the "old" values should be // from a completely different hierarchy, none of the "old" values should be
// readable. // readable.
// NB: slight hack, store 16 in to a 8 byte stack slot. // NB: slight hack, store 16 in to a 8 byte stack slot.
MF = readMIRBlock( MF = readMIRBlock(
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  MF = readMIRBlock(
-   "    $rax = MOV64ri 0\n"
-   "    MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n"
-   "    $xmm0 = IMPLICIT_DEF\n"
-   "    MOVUPDmr $rsp, 1, $noreg, 16, $noreg, killed $xmm0 :: (store (s128) into %stack.0)\n"
-   "    $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n"
-   "    RET64\n");
+  MF = readMIRBlock("    $rax = MOV64ri 0\n"
+                    "    MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 "
+                    "into %stack.0)\n"

6 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - MF = readMIRBlock( - " $rax = MOV64ri 0\n"…
" $rax = MOV64ri 0\n" " $rax = MOV64ri 0\n"
" MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n" " MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n"
" $xmm0 = IMPLICIT_DEF\n" " $xmm0 = IMPLICIT_DEF\n"
" MOVUPDmr $rsp, 1, $noreg, 16, $noreg, killed $xmm0 :: (store (s128) into %stack.0)\n" " MOVUPDmr $rsp, 1, $noreg, 16, $noreg, killed $xmm0 :: (store (s128) into %stack.0)\n"
" $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n" " $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n"
" RETQ\n"); " RET64\n");
setupLDVObj(MF); setupLDVObj(MF);
TransferMap.clear(); TransferMap.clear();
TransferMap.resize(1); TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1); produceMLocTransferFunction(*MF, TransferMap, 1);
for (unsigned int I = 0; I < 5; ++I) { for (unsigned int I = 0; I < 5; ++I) {
// Read subreg fields from the stack. // Read subreg fields from the stack.
SpillLocationNo SpillNo = MTracker->getOrTrackSpillLoc(L); SpillLocationNo SpillNo = MTracker->getOrTrackSpillLoc(L);
Show All 15 LinesTEST_F(InstrRefLDVTest, MTransferSubregSpills) {
SpillValue = MTracker->readMLoc(Spill128Loc); SpillValue = MTracker->readMLoc(Spill128Loc);
Register XMM0 = getRegByName("XMM0"); Register XMM0 = getRegByName("XMM0");
LocIdx Xmm0Loc = MTracker->getRegMLoc(XMM0); LocIdx Xmm0Loc = MTracker->getRegMLoc(XMM0);
EXPECT_EQ(ValueIDNum(0, 0, Xmm0Loc), SpillValue); EXPECT_EQ(ValueIDNum(0, 0, Xmm0Loc), SpillValue);
// What happens if we spill ah to the stack, then load al? It should find // What happens if we spill ah to the stack, then load al? It should find
// the same value. // the same value.
MF = readMIRBlock( MF = readMIRBlock(
" $rax = MOV64ri 0\n" " $rax = MOV64ri 0\n"
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   "    $rax = MOV64ri 0\n"
-   "    MOV8mr $rsp, 1, $noreg, 16, $noreg, $ah :: (store 1 into %stack.0)\n"
-   "    $al = MOV8rm $rsp, 1, $noreg, 0, $noreg :: (load 1 from %stack.0)\n"
-   "    RET64\n");
+      "    $rax = MOV64ri 0\n"
+      "    MOV8mr $rsp, 1, $noreg, 16, $noreg, $ah :: (store 1 into %stack.0)\n"
+      "    $al = MOV8rm $rsp, 1, $noreg, 0, $noreg :: (load 1 from %stack.0)\n"
+      "    RET64\n");
Lint: Pre-merge checks: clang-format: please reformat the code ``` - " $rax = MOV64ri 0\n" - " MOV8mr $rsp, 1…
" MOV8mr $rsp, 1, $noreg, 16, $noreg, $ah :: (store 1 into %stack.0)\n" " MOV8mr $rsp, 1, $noreg, 16, $noreg, $ah :: (store 1 into %stack.0)\n"
" $al = MOV8rm $rsp, 1, $noreg, 0, $noreg :: (load 1 from %stack.0)\n" " $al = MOV8rm $rsp, 1, $noreg, 0, $noreg :: (load 1 from %stack.0)\n"
" RETQ\n"); " RET64\n");
setupLDVObj(MF); setupLDVObj(MF);
TransferMap.clear(); TransferMap.clear();
TransferMap.resize(1); TransferMap.resize(1);
produceMLocTransferFunction(*MF, TransferMap, 1); produceMLocTransferFunction(*MF, TransferMap, 1);
Register AL = getRegByName("AL"); Register AL = getRegByName("AL");
Register AH = getRegByName("AH"); Register AH = getRegByName("AH");
LocIdx AlLoc = MTracker->getRegMLoc(AL); LocIdx AlLoc = MTracker->getRegMLoc(AL);
▲ Show 20 Lines • Show All 2,355 Lines • Show Last 20 Lines

llvm/unittests/tools/llvm-exegesis/X86/SnippetRepetitorTest.cpp

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
}; };
TEST_F(X86SnippetRepetitorTest, Duplicate) { TEST_F(X86SnippetRepetitorTest, Duplicate) {
TestCommon(InstructionBenchmark::Duplicate); TestCommon(InstructionBenchmark::Duplicate);
// Duplicating creates a single basic block that repeats the instructions. // Duplicating creates a single basic block that repeats the instructions.
ASSERT_EQ(MF->getNumBlockIDs(), 1u); ASSERT_EQ(MF->getNumBlockIDs(), 1u);
EXPECT_THAT(MF->getBlockNumbered(0)->instrs(), EXPECT_THAT(MF->getBlockNumbered(0)->instrs(),
ElementsAre(HasOpcode(X86::NOOP), HasOpcode(X86::NOOP), ElementsAre(HasOpcode(X86::NOOP), HasOpcode(X86::NOOP),
HasOpcode(X86::NOOP), HasOpcode(X86::RETQ))); HasOpcode(X86::NOOP), HasOpcode(X86::RET64)));
} }
TEST_F(X86SnippetRepetitorTest, Loop) { TEST_F(X86SnippetRepetitorTest, Loop) {
TestCommon(InstructionBenchmark::Loop); TestCommon(InstructionBenchmark::Loop);
// Duplicating creates an entry block, a loop body and a ret block. // Duplicating creates an entry block, a loop body and a ret block.
ASSERT_EQ(MF->getNumBlockIDs(), 3u); ASSERT_EQ(MF->getNumBlockIDs(), 3u);
const auto &LoopBlock = *MF->getBlockNumbered(1); const auto &LoopBlock = *MF->getBlockNumbered(1);
EXPECT_THAT(LoopBlock.instrs(), EXPECT_THAT(LoopBlock.instrs(),
ElementsAre(HasOpcode(X86::NOOP), HasOpcode(X86::NOOP), ElementsAre(HasOpcode(X86::NOOP), HasOpcode(X86::NOOP),
HasOpcode(X86::NOOP), HasOpcode(X86::NOOP), HasOpcode(X86::NOOP), HasOpcode(X86::NOOP),
HasOpcode(X86::NOOP), HasOpcode(X86::ADD64ri8), HasOpcode(X86::NOOP), HasOpcode(X86::ADD64ri8),
HasOpcode(X86::JCC_1))); HasOpcode(X86::JCC_1)));
EXPECT_THAT(LoopBlock.liveins(), EXPECT_THAT(LoopBlock.liveins(),
UnorderedElementsAre( UnorderedElementsAre(
LiveReg(X86::EAX), LiveReg(X86::EAX),
LiveReg(State.getExegesisTarget().getLoopCounterRegister( LiveReg(State.getExegesisTarget().getLoopCounterRegister(
State.getTargetMachine().getTargetTriple())))); State.getTargetMachine().getTargetTriple()))));
EXPECT_THAT(MF->getBlockNumbered(2)->instrs(), EXPECT_THAT(MF->getBlockNumbered(2)->instrs(),
ElementsAre(HasOpcode(X86::RETQ))); ElementsAre(HasOpcode(X86::RET64)));
} }
} // namespace } // namespace
} // namespace exegesis } // namespace exegesis
} // namespace llvm } // namespace llvm