[X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC

[RKSimon]

Summary

Be more consistent in the naming convention for the various RET instructions to help prevent future scheduler model mismatches like those that were only addressed in D44687.

[pengfei]

Not sure if I understand it correct or not. I used to take the number as system mode. E.g., CALL16m, POP32r etc. And W/L/Q as the size of memory operand. Maybe we should change RETL etc. to RET32 instead?

[RKSimon]

In D113302#3113304, @pengfei wrote:

Not sure if I understand it correct or not. I used to take the number as system mode. E.g., CALL16m, POP32r etc. And W/L/Q as the size of memory operand. Maybe we should change RETL etc. to RET32 instead?

Sure, that makes sense as well

[RKSimon]

update tests

[RKSimon]

more tests needs updating...

[RKSimon]

update tests

[pengfei]

Wow, I haven't thought we have so many use of the MI opcodes. Maybe I shouldn't have suggested this way :)

[RKSimon]

In D113302#3114128, @pengfei wrote:

Wow, I haven't thought we have so many use of the MI opcodes. Maybe I shouldn't have suggested this way :)

Cheers - I agree - I didn't expect the patch to be so bulky, but still I think it makes sense to get this done once and for all!

llvm/lib/Target/X86/X86ExpandPseudo.cpp

case X86::EH_RETURN64: {
     // The EH_RETURN pseudo is really removed during the MC Lowering.
     return true;
   }
   case X86::IRET: {
     // Adjust stack to erase error code
     int64_t StackAdj = MBBI->getOperand(0).getImm();
     X86FL->emitSPUpdate(MBB, MBBI, DL, StackAdj, true);
     // Replace pseudo with machine iret
-    unsigned RetOp = STI->is64Bit() ? X86::IRET64 : X86::IRET32;
+    unsigned RetOp = STI->is64Bit() ? X86::IRETQ : X86::IRETL;
     // Use UIRET if UINTR is present (except for building kernel)
     if (STI->is64Bit() && STI->hasUINTR() &&
         MBB.getParent()->getTarget().getCodeModel() != CodeModel::Kernel)
       RetOp = X86::UIRET;
     BuildMI(MBB, MBBI, DL, TII->get(RetOp));
     MBB.erase(MBBI);
     return true;
   }

llvm/lib/Target/X86/X86InstrControl.td

let isTerminator = 1, isReturn = 1, isBarrier = 1,
   def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
                     "{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>;
   def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
                     "{l}ret{w|f}\t$amt", []>, OpSize16;
 
   // The machine return from interrupt instruction, but sometimes we need to
   // perform a post-epilogue stack adjustment. Codegen emits the pseudo form
   // which expands to include an SP adjustment if necessary.
-  def IRET16 : I   <0xcf, RawFrm, (outs), (ins), "iret{w}", []>,
+  def IRETW  : I   <0xcf, RawFrm, (outs), (ins), "iret{w}", []>,
                OpSize16;
-  def IRET32 : I   <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32;
-  def IRET64 : RI  <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>;
+  def IRETL  : I   <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32;
+  def IRETQ  : RI  <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>;
   let isCodeGenOnly = 1 in
   def IRET : PseudoI<(outs), (ins i32imm:$adj), [(X86iret timm:$adj)]>;
   def RET  : PseudoI<(outs), (ins i32imm:$adj, variable_ops), [(X86retflag timm:$adj)]>;
 }
 
 // Unconditional branches.
 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
   def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),

llvm/lib/Target/X86/X86ScheduleAtom.td

 def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r,
                                        POP16rmr, POP32rmr, POP64rmr,
                                        PUSH16r, PUSH32r, PUSH64r,
                                        PUSHi16, PUSHi32,
                                        PUSH16rmr, PUSH32rmr, PUSH64rmr,
                                        PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32,
                                        XCH_F)>;
 def : InstRW<[AtomWrite0_1_1], (instregex "RETI(L|Q|W)$",
-                                          "IRET(16|32|64)?")>;
+                                          "IRET(L|Q|W)?")>;
 
 def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> {
   let Latency = 5;
   let ResourceCycles = [5, 5];
 }
 def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIirm, MMX_CVTTPS2PIirm)>;
 def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>;
 

llvm/lib/Target/X86/X86ScheduleZnver1.td

 
 def : InstRW<[WriteMicrocoded], (instregex "CALL(16|32)m")>;
 
 // RET.
 def ZnWriteRET : SchedWriteRes<[ZnALU03]> {
   let NumMicroOps = 2;
 }
 def : InstRW<[ZnWriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)",
-                            "IRET(16|32|64)")>;
+                            "IRET(L|Q|W)")>;
 
 //-- Logic instructions --//
 
 // AND OR XOR.
 // m,r/i.
 def : InstRW<[WriteALULd],
              (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)",
               "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>;

llvm/lib/Target/X86/X86ScheduleZnver2.td

 
 def : InstRW<[WriteMicrocoded], (instregex "CALL(16|32)m")>;
 
 // RET.
 def Zn2WriteRET : SchedWriteRes<[Zn2ALU03]> {
   let NumMicroOps = 2;
 }
 def : InstRW<[Zn2WriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)",
-                            "IRET(16|32|64)")>;
+                            "IRET(L|Q|W)")>;
 
 //-- Logic instructions --//
 
 // AND OR XOR.
 // m,r/i.
 def : InstRW<[WriteALULd],
              (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)",
               "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>;