[AArch64] Allow FP16 vector fixed point converts

[dmgreen]

Summary

This extends performFpToIntCombine to work on FP16 vectors as well as the f32 and f64 vectors it already supported.

[samtebbs]

LGTM

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() ||
     return SDValue();
 
   SDValue ConstVec = Op->getOperand(1);
   if (!isa<BuildVectorSDNode>(ConstVec))
     return SDValue();
 
   MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
   uint32_t FloatBits = FloatTy.getSizeInBits();
-  if (FloatBits != 32 && FloatBits != 64)
+  if (FloatBits != 32 && FloatBits != 64 &&
+      (FloatBits != 16 || !Subtarget->hasFullFP16()))
     return SDValue();
 
   MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
   uint32_t IntBits = IntTy.getSizeInBits();
   if (IntBits != 16 && IntBits != 32 && IntBits != 64)
     return SDValue();
 
   // Avoid conversions where iN is larger than the float (e.g., float -> i64).
   if (IntBits > FloatBits)
     return SDValue();
 
   BitVector UndefElements;
   BuildVectorSDNode *BV = cast<BuildVectorSDNode>(ConstVec);
   int32_t Bits = IntBits == 64 ? 64 : 32;
   int32_t C = BV->getConstantFPSplatPow2ToLog2Int(&UndefElements, Bits + 1);
   if (C == -1 || C == 0 || C > Bits)
     return SDValue();
 
-  MVT ResTy;
-  unsigned NumLanes = Op.getValueType().getVectorNumElements();
-  switch (NumLanes) {
-  default:
-    return SDValue();
-  case 2:
-    ResTy = FloatBits == 32 ? MVT::v2i32 : MVT::v2i64;
-    break;
-  case 4:
-    ResTy = FloatBits == 32 ? MVT::v4i32 : MVT::v4i64;
-    break;
-  }
-
-  if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps())
+  EVT ResTy = Op.getValueType().changeVectorElementTypeToInteger();
+  if (!DAG.getTargetLoweringInfo().isTypeLegal(ResTy))
     return SDValue();
 
-  assert((ResTy != MVT::v4i64 || DCI.isBeforeLegalizeOps()) &&
-         "Illegal vector type after legalization");
-
   if (N->getOpcode() == ISD::FP_TO_SINT_SAT ||
       N->getOpcode() == ISD::FP_TO_UINT_SAT) {
     EVT SatVT = cast<VTSDNode>(N->getOperand(1))->getVT();
     if (SatVT.getScalarSizeInBits() != IntBits)
       return SDValue();
   }
 
   SDLoc DL(N);

llvm/test/CodeGen/AArch64/fcvt_combine.ll

 ; CHECK-NO16-NEXT:    fcvtzs v0.4s, v0.4s
 ; CHECK-NO16-NEXT:    fcvtzs v1.4s, v1.4s
 ; CHECK-NO16-NEXT:    xtn v0.4h, v0.4s
 ; CHECK-NO16-NEXT:    xtn2 v0.8h, v1.4s
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: test_v8f16:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    movi v1.8h, #68, lsl #8
-; CHECK-FP16-NEXT:    fmul v0.8h, v0.8h, v1.8h
-; CHECK-FP16-NEXT:    fcvtzs v0.8h, v0.8h
+; CHECK-FP16-NEXT:    fcvtzs v0.8h, v0.8h, #2
 ; CHECK-FP16-NEXT:    ret
   %scale = fmul <8 x half> %in, <half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0>
   %val = fptosi <8 x half> %scale to <8 x i16>
   ret <8 x i16> %val
 }
 
 define <4 x i16> @test_v4f16(<4 x half> %in) {
 ; CHECK-NO16-LABEL: test_v4f16:
 ; CHECK-NO16:       // %bb.0:
 ; CHECK-NO16-NEXT:    fmov v1.4s, #4.00000000
 ; CHECK-NO16-NEXT:    fcvtl v0.4s, v0.4h
 ; CHECK-NO16-NEXT:    fmul v0.4s, v0.4s, v1.4s
 ; CHECK-NO16-NEXT:    fcvtn v0.4h, v0.4s
 ; CHECK-NO16-NEXT:    fcvtl v0.4s, v0.4h
 ; CHECK-NO16-NEXT:    fcvtzu v0.4s, v0.4s
 ; CHECK-NO16-NEXT:    xtn v0.4h, v0.4s
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: test_v4f16:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    movi v1.4h, #68, lsl #8
-; CHECK-FP16-NEXT:    fmul v0.4h, v0.4h, v1.4h
-; CHECK-FP16-NEXT:    fcvtzu v0.4h, v0.4h
+; CHECK-FP16-NEXT:    fcvtzu v0.4h, v0.4h, #2
 ; CHECK-FP16-NEXT:    ret
   %scale = fmul <4 x half> %in, <half 4.0, half 4.0, half 4.0, half 4.0>
   %val = fptoui <4 x half> %scale to <4 x i16>
   ret <4 x i16> %val
 }
 
 define <4 x i32> @test_v4f16_i32(<4 x half> %in) {
 ; CHECK-NO16-LABEL: test_v4f16_i32:

 ; CHECK-NO16-NEXT:    mov v1.s[3], w8
 ; CHECK-NO16-NEXT:    mov v2.s[3], w13
 ; CHECK-NO16-NEXT:    xtn v0.4h, v1.4s
 ; CHECK-NO16-NEXT:    xtn2 v0.8h, v2.4s
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: test_v8f16_sat:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    movi v1.8h, #68, lsl #8
-; CHECK-FP16-NEXT:    fmul v0.8h, v0.8h, v1.8h
-; CHECK-FP16-NEXT:    fcvtzs v0.8h, v0.8h
+; CHECK-FP16-NEXT:    fcvtzs v0.8h, v0.8h, #2
 ; CHECK-FP16-NEXT:    ret
   %mul.i = fmul <8 x half> %in, <half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0>
   %val = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %mul.i)
   ret <8 x i16> %val
 }
 
 define <4 x i16> @test_v4f16_sat(<4 x half> %in) {
 ; CHECK-NO16-LABEL: test_v4f16_sat:
 ; CHECK-NO16:       // %bb.0:
 ; CHECK-NO16-NEXT:    fmov v1.4s, #4.00000000
 ; CHECK-NO16-NEXT:    fcvtl v0.4s, v0.4h
 ; CHECK-NO16-NEXT:    fmul v0.4s, v0.4s, v1.4s
 ; CHECK-NO16-NEXT:    fcvtn v0.4h, v0.4s
 ; CHECK-NO16-NEXT:    fcvtl v0.4s, v0.4h
 ; CHECK-NO16-NEXT:    fcvtzu v0.4s, v0.4s
 ; CHECK-NO16-NEXT:    uqxtn v0.4h, v0.4s
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: test_v4f16_sat:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    movi v1.4h, #68, lsl #8
-; CHECK-FP16-NEXT:    fmul v0.4h, v0.4h, v1.4h
-; CHECK-FP16-NEXT:    fcvtzu v0.4h, v0.4h
+; CHECK-FP16-NEXT:    fcvtzu v0.4h, v0.4h, #2
 ; CHECK-FP16-NEXT:    ret
   %mul.i = fmul <4 x half> %in, <half 4.0, half 4.0, half 4.0, half 4.0>
   %val = call <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half> %mul.i)
   ret <4 x i16> %val
 }
 
 define <4 x i32> @test_v4f16_i32_sat(<4 x half> %in) {
 ; CHECK-NO16-LABEL: test_v4f16_i32_sat: