[AArch64] Combine fptoi.sat(fmul) to fixed point cvtf

[dmgreen]

Summary

We already have patterns for fptosi and fptoui plus fmul to fixed point convert, this adds equivalent patterns for fptosi.sat and fptoui.sat, which should apply equally well for the legal saturating variants.

[SjoerdMeijer]

If I am not mistaken, I don’t see any f16 test?

[dmgreen]

Rebase over some newly added fp16 tests.

[SjoerdMeijer]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

3772

Do we need to predicate this rule and the next on HasFullFP16?

[dmgreen]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

3772

Hmm. We haven't for any of the others here above or below. I don't think the nodes will be legal if we don't have fullfp16 - so they will never be possible to match against. I can add them if you think that's cleaner.

[SjoerdMeijer]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

3772

So yeah, there's definitely some inconsistency here. Other rewrite rules, but indeed not around here, do have it predicated on fullfp16. I am not sure to be honest, but it looks cleaner to me (although I of course agree that the nodes won't be matched if fullfp16 isn't enabled).

[dmgreen]

Add HasFullFP16 to these and nearby patterns.

[SjoerdMeijer]

Cheers, LGTM.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>;
 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>;
 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
 
 // AArch64's FCVT instructions saturate when out of range.
 multiclass FPToIntegerSatPats<SDNode to_int_sat, string INST> {
+  let Predicates = [HasFullFP16] in {
   def : Pat<(i32 (to_int_sat f16:$Rn, i32)),
             (!cast<Instruction>(INST # UWHr) f16:$Rn)>;
-  def : Pat<(i32 (to_int_sat f32:$Rn, i32)),
-            (!cast<Instruction>(INST # UWSr) f32:$Rn)>;
-  def : Pat<(i32 (to_int_sat f64:$Rn, i32)),
-            (!cast<Instruction>(INST # UWDr) f64:$Rn)>;
   def : Pat<(i64 (to_int_sat f16:$Rn, i64)),
             (!cast<Instruction>(INST # UXHr) f16:$Rn)>;
+  }
+  def : Pat<(i32 (to_int_sat f32:$Rn, i32)),
+            (!cast<Instruction>(INST # UWSr) f32:$Rn)>;
   def : Pat<(i64 (to_int_sat f32:$Rn, i64)),
             (!cast<Instruction>(INST # UXSr) f32:$Rn)>;
+  def : Pat<(i32 (to_int_sat f64:$Rn, i32)),
+            (!cast<Instruction>(INST # UWDr) f64:$Rn)>;
   def : Pat<(i64 (to_int_sat f64:$Rn, i64)),
             (!cast<Instruction>(INST # UXDr) f64:$Rn)>;
+
+  let Predicates = [HasFullFP16] in {
+  def : Pat<(i32 (to_int_sat (fmul f16:$Rn, fixedpoint_f16_i32:$scale), i32)),
+            (!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
+  def : Pat<(i64 (to_int_sat (fmul f16:$Rn, fixedpoint_f16_i64:$scale), i64)),
+            (!cast<Instruction>(INST # SXHri) $Rn, $scale)>;
+  }
+  def : Pat<(i32 (to_int_sat (fmul f32:$Rn, fixedpoint_f32_i32:$scale), i32)),
+            (!cast<Instruction>(INST # SWSri) $Rn, $scale)>;
+  def : Pat<(i64 (to_int_sat (fmul f32:$Rn, fixedpoint_f32_i64:$scale), i64)),
+            (!cast<Instruction>(INST # SXSri) $Rn, $scale)>;
+  def : Pat<(i32 (to_int_sat (fmul f64:$Rn, fixedpoint_f64_i32:$scale), i32)),
+            (!cast<Instruction>(INST # SWDri) $Rn, $scale)>;
+  def : Pat<(i64 (to_int_sat (fmul f64:$Rn, fixedpoint_f64_i64:$scale), i64)),
+            (!cast<Instruction>(INST # SXDri) $Rn, $scale)>;
 }
 
 defm : FPToIntegerSatPats<fp_to_sint_sat, "FCVTZS">;
 defm : FPToIntegerSatPats<fp_to_uint_sat, "FCVTZU">;
 
 multiclass FPToIntegerIntPats<Intrinsic round, string INST> {
+  let Predicates = [HasFullFP16] in {
   def : Pat<(i32 (round f16:$Rn)), (!cast<Instruction>(INST # UWHr) $Rn)>;
   def : Pat<(i64 (round f16:$Rn)), (!cast<Instruction>(INST # UXHr) $Rn)>;
+  }
   def : Pat<(i32 (round f32:$Rn)), (!cast<Instruction>(INST # UWSr) $Rn)>;
   def : Pat<(i64 (round f32:$Rn)), (!cast<Instruction>(INST # UXSr) $Rn)>;
   def : Pat<(i32 (round f64:$Rn)), (!cast<Instruction>(INST # UWDr) $Rn)>;
   def : Pat<(i64 (round f64:$Rn)), (!cast<Instruction>(INST # UXDr) $Rn)>;
 
+  let Predicates = [HasFullFP16] in {
   def : Pat<(i32 (round (fmul f16:$Rn, fixedpoint_f16_i32:$scale))),
             (!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
   def : Pat<(i64 (round (fmul f16:$Rn, fixedpoint_f16_i64:$scale))),
             (!cast<Instruction>(INST # SXHri) $Rn, $scale)>;
+  }
   def : Pat<(i32 (round (fmul f32:$Rn, fixedpoint_f32_i32:$scale))),
             (!cast<Instruction>(INST # SWSri) $Rn, $scale)>;
   def : Pat<(i64 (round (fmul f32:$Rn, fixedpoint_f32_i64:$scale))),
             (!cast<Instruction>(INST # SXSri) $Rn, $scale)>;
   def : Pat<(i32 (round (fmul f64:$Rn, fixedpoint_f64_i32:$scale))),
             (!cast<Instruction>(INST # SWDri) $Rn, $scale)>;
   def : Pat<(i64 (round (fmul f64:$Rn, fixedpoint_f64_i64:$scale))),
             (!cast<Instruction>(INST # SXDri) $Rn, $scale)>;
 }
 
 defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzs, "FCVTZS">;
 defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzu, "FCVTZU">;
 
 multiclass FPToIntegerPats<SDNode to_int, SDNode to_int_sat, SDNode round, string INST> {
   def : Pat<(i32 (to_int (round f32:$Rn))),
             (!cast<Instruction>(INST # UWSr) f32:$Rn)>;
   def : Pat<(i64 (to_int (round f32:$Rn))),
             (!cast<Instruction>(INST # UXSr) f32:$Rn)>;
   def : Pat<(i32 (to_int (round f64:$Rn))),
             (!cast<Instruction>(INST # UWDr) f64:$Rn)>;
   def : Pat<(i64 (to_int (round f64:$Rn))),
             (!cast<Instruction>(INST # UXDr) f64:$Rn)>;
 
   // These instructions saturate like fp_to_[su]int_sat.
+  let Predicates = [HasFullFP16] in {
   def : Pat<(i32 (to_int_sat (round f16:$Rn), i32)),
             (!cast<Instruction>(INST # UWHr) f16:$Rn)>;
   def : Pat<(i64 (to_int_sat (round f16:$Rn), i64)),
             (!cast<Instruction>(INST # UXHr) f16:$Rn)>;
+  }
   def : Pat<(i32 (to_int_sat (round f32:$Rn), i32)),
             (!cast<Instruction>(INST # UWSr) f32:$Rn)>;
   def : Pat<(i64 (to_int_sat (round f32:$Rn), i64)),
             (!cast<Instruction>(INST # UXSr) f32:$Rn)>;
   def : Pat<(i32 (to_int_sat (round f64:$Rn), i32)),
             (!cast<Instruction>(INST # UWDr) f64:$Rn)>;
   def : Pat<(i64 (to_int_sat (round f64:$Rn), i64)),
             (!cast<Instruction>(INST # UXDr) f64:$Rn)>;

llvm/test/CodeGen/AArch64/fcvt-fixed.ll

 declare i32 @llvm.fptosi.sat.i32.f64(double)
 declare i64 @llvm.fptosi.sat.i64.f64(double)
 declare i32 @llvm.fptosi.sat.i32.f16(half)
 declare i64 @llvm.fptosi.sat.i64.f16(half)
 
 define i32 @fcvtzs_sat_f32_i32_7(float %flt) {
 ; CHECK-LABEL: fcvtzs_sat_f32_i32_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #1124073472
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmul s0, s0, s1
-; CHECK-NEXT:    fcvtzs w0, s0
+; CHECK-NEXT:    fcvtzs w0, s0, #7
 ; CHECK-NEXT:    ret
   %fix = fmul float %flt, 128.0
   %cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)
   ret i32 %cvt
 }
 
 define i32 @fcvtzs_sat_f32_i32_32(float %flt) {
 ; CHECK-LABEL: fcvtzs_sat_f32_i32_32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #1333788672
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmul s0, s0, s1
-; CHECK-NEXT:    fcvtzs w0, s0
+; CHECK-NEXT:    fcvtzs w0, s0, #32
 ; CHECK-NEXT:    ret
   %fix = fmul float %flt, 4294967296.0
   %cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)
   ret i32 %cvt
 }
 
 define i64 @fcvtzs_sat_f32_i64_64(float %flt) {
 ; CHECK-LABEL: fcvtzs_sat_f32_i64_64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #1602224128
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmul s0, s0, s1
-; CHECK-NEXT:    fcvtzs x0, s0
+; CHECK-NEXT:    fcvtzs x0, s0, #64
 ; CHECK-NEXT:    ret
   %fix = fmul float %flt, 18446744073709551616.0
   %cvt = call i64 @llvm.fptosi.sat.i64.f32(float %fix)
   ret i64 %cvt
 }
 
 define i32 @fcvtzs_sat_f64_i32_7(double %dbl) {
 ; CHECK-LABEL: fcvtzs_sat_f64_i32_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #4638707616191610880
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmul d0, d0, d1
-; CHECK-NEXT:    fcvtzs w0, d0
+; CHECK-NEXT:    fcvtzs w0, d0, #7
 ; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 128.0
   %cvt = call i32 @llvm.fptosi.sat.i32.f64(double %fix)
   ret i32 %cvt
 }
 
 define i32 @fcvtzs_sat_f64_i32_32(double %dbl) {
 ; CHECK-LABEL: fcvtzs_sat_f64_i32_32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #4751297606875873280
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmul d0, d0, d1
-; CHECK-NEXT:    fcvtzs w0, d0
+; CHECK-NEXT:    fcvtzs w0, d0, #32
 ; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 4294967296.0
   %cvt = call i32 @llvm.fptosi.sat.i32.f64(double %fix)
   ret i32 %cvt
 }
 
 define i64 @fcvtzs_sat_f64_i64_7(double %dbl) {
 ; CHECK-LABEL: fcvtzs_sat_f64_i64_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #4638707616191610880
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmul d0, d0, d1
-; CHECK-NEXT:    fcvtzs x0, d0
+; CHECK-NEXT:    fcvtzs x0, d0, #7
 ; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 128.0
   %cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
   ret i64 %cvt
 }
 
 define i64 @fcvtzs_sat_f64_i64_64(double %dbl) {
 ; CHECK-LABEL: fcvtzs_sat_f64_i64_64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #4895412794951729152
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmul d0, d0, d1
-; CHECK-NEXT:    fcvtzs x0, d0
+; CHECK-NEXT:    fcvtzs x0, d0, #64
 ; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 18446744073709551616.0
   %cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
   ret i64 %cvt
 }
 
 define i32 @fcvtzs_sat_f16_i32_7(half %dbl) {
 ; CHECK-NO16-LABEL: fcvtzs_sat_f16_i32_7:
 ; CHECK-NO16:       // %bb.0:
 ; CHECK-NO16-NEXT:    mov w8, #1124073472
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzs w0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzs_sat_f16_i32_7:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    adrp x8, .LCPI55_0
-; CHECK-FP16-NEXT:    ldr h1, [x8, :lo12:.LCPI55_0]
-; CHECK-FP16-NEXT:    fmul h0, h0, h1
-; CHECK-FP16-NEXT:    fcvtzs w0, h0
+; CHECK-FP16-NEXT:    fcvtzs w0, h0, #7
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %dbl, 128.0
   %cvt = call i32 @llvm.fptosi.sat.i32.f16(half %fix)
   ret i32 %cvt
 }
 
 define i32 @fcvtzs_sat_f16_i32_15(half %dbl) {
 ; CHECK-NO16-LABEL: fcvtzs_sat_f16_i32_15:
 ; CHECK-NO16:       // %bb.0:
 ; CHECK-NO16-NEXT:    mov w8, #1191182336
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzs w0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzs_sat_f16_i32_15:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    adrp x8, .LCPI56_0
-; CHECK-FP16-NEXT:    ldr h1, [x8, :lo12:.LCPI56_0]
-; CHECK-FP16-NEXT:    fmul h0, h0, h1
-; CHECK-FP16-NEXT:    fcvtzs w0, h0
+; CHECK-FP16-NEXT:    fcvtzs w0, h0, #15
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %dbl, 32768.0
   %cvt = call i32 @llvm.fptosi.sat.i32.f16(half %fix)
   ret i32 %cvt
 }
 
 define i64 @fcvtzs_sat_f16_i64_7(half %dbl) {
 ; CHECK-NO16-LABEL: fcvtzs_sat_f16_i64_7:
 ; CHECK-NO16:       // %bb.0:
 ; CHECK-NO16-NEXT:    mov w8, #1124073472
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzs x0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzs_sat_f16_i64_7:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    adrp x8, .LCPI57_0
-; CHECK-FP16-NEXT:    ldr h1, [x8, :lo12:.LCPI57_0]
-; CHECK-FP16-NEXT:    fmul h0, h0, h1
-; CHECK-FP16-NEXT:    fcvtzs x0, h0
+; CHECK-FP16-NEXT:    fcvtzs x0, h0, #7
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %dbl, 128.0
   %cvt = call i64 @llvm.fptosi.sat.i64.f16(half %fix)
   ret i64 %cvt
 }
 
 define i64 @fcvtzs_sat_f16_i64_15(half %dbl) {
 ; CHECK-NO16-LABEL: fcvtzs_sat_f16_i64_15:
 ; CHECK-NO16:       // %bb.0:
 ; CHECK-NO16-NEXT:    mov w8, #1191182336
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzs x0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzs_sat_f16_i64_15:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    adrp x8, .LCPI58_0
-; CHECK-FP16-NEXT:    ldr h1, [x8, :lo12:.LCPI58_0]
-; CHECK-FP16-NEXT:    fmul h0, h0, h1
-; CHECK-FP16-NEXT:    fcvtzs x0, h0
+; CHECK-FP16-NEXT:    fcvtzs x0, h0, #15
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %dbl, 32768.0
   %cvt = call i64 @llvm.fptosi.sat.i64.f16(half %fix)
   ret i64 %cvt
 }
 
 ; fptoui
 
 declare i32 @llvm.fptoui.sat.i32.f32(float)
 declare i64 @llvm.fptoui.sat.i64.f32(float)
 declare i32 @llvm.fptoui.sat.i32.f64(double)
 declare i64 @llvm.fptoui.sat.i64.f64(double)
 declare i32 @llvm.fptoui.sat.i32.f16(half)
 declare i64 @llvm.fptoui.sat.i64.f16(half)
 
 define i32 @fcvtzu_sat_f32_i32_7(float %flt) {
 ; CHECK-LABEL: fcvtzu_sat_f32_i32_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #1124073472
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmul s0, s0, s1
-; CHECK-NEXT:    fcvtzu w0, s0
+; CHECK-NEXT:    fcvtzu w0, s0, #7
 ; CHECK-NEXT:    ret
   %fix = fmul float %flt, 128.0
   %cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)
   ret i32 %cvt
 }
 
 define i32 @fcvtzu_sat_f32_i32_32(float %flt) {
 ; CHECK-LABEL: fcvtzu_sat_f32_i32_32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #1333788672
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmul s0, s0, s1
-; CHECK-NEXT:    fcvtzu w0, s0
+; CHECK-NEXT:    fcvtzu w0, s0, #32
 ; CHECK-NEXT:    ret
   %fix = fmul float %flt, 4294967296.0
   %cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)
   ret i32 %cvt
 }
 
 define i64 @fcvtzu_sat_f32_i64_64(float %flt) {
 ; CHECK-LABEL: fcvtzu_sat_f32_i64_64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #1602224128
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fmul s0, s0, s1
-; CHECK-NEXT:    fcvtzu x0, s0
+; CHECK-NEXT:    fcvtzu x0, s0, #64
 ; CHECK-NEXT:    ret
   %fix = fmul float %flt, 18446744073709551616.0
   %cvt = call i64 @llvm.fptoui.sat.i64.f32(float %fix)
   ret i64 %cvt
 }
 
 define i32 @fcvtzu_sat_f64_i32_7(double %dbl) {
 ; CHECK-LABEL: fcvtzu_sat_f64_i32_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #4638707616191610880
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmul d0, d0, d1
-; CHECK-NEXT:    fcvtzu w0, d0
+; CHECK-NEXT:    fcvtzu w0, d0, #7
 ; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 128.0
   %cvt = call i32 @llvm.fptoui.sat.i32.f64(double %fix)
   ret i32 %cvt
 }
 
 define i32 @fcvtzu_sat_f64_i32_32(double %dbl) {
 ; CHECK-LABEL: fcvtzu_sat_f64_i32_32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #4751297606875873280
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmul d0, d0, d1
-; CHECK-NEXT:    fcvtzu w0, d0
+; CHECK-NEXT:    fcvtzu w0, d0, #32
 ; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 4294967296.0
   %cvt = call i32 @llvm.fptoui.sat.i32.f64(double %fix)
   ret i32 %cvt
 }
 
 define i64 @fcvtzu_sat_f64_i64_7(double %dbl) {
 ; CHECK-LABEL: fcvtzu_sat_f64_i64_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #4638707616191610880
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmul d0, d0, d1
-; CHECK-NEXT:    fcvtzu x0, d0
+; CHECK-NEXT:    fcvtzu x0, d0, #7
 ; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 128.0
   %cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)
   ret i64 %cvt
 }
 
 define i64 @fcvtzu_sat_f64_i64_64(double %dbl) {
 ; CHECK-LABEL: fcvtzu_sat_f64_i64_64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #4895412794951729152
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmul d0, d0, d1
-; CHECK-NEXT:    fcvtzu x0, d0
+; CHECK-NEXT:    fcvtzu x0, d0, #64
 ; CHECK-NEXT:    ret
   %fix = fmul double %dbl, 18446744073709551616.0
   %cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)
   ret i64 %cvt
 }
 
 define i32 @fcvtzu_sat_f16_i32_7(half %dbl) {
 ; CHECK-NO16-LABEL: fcvtzu_sat_f16_i32_7:
 ; CHECK-NO16:       // %bb.0:
 ; CHECK-NO16-NEXT:    mov w8, #1124073472
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzu w0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzu_sat_f16_i32_7:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    adrp x8, .LCPI66_0
-; CHECK-FP16-NEXT:    ldr h1, [x8, :lo12:.LCPI66_0]
-; CHECK-FP16-NEXT:    fmul h0, h0, h1
-; CHECK-FP16-NEXT:    fcvtzu w0, h0
+; CHECK-FP16-NEXT:    fcvtzu w0, h0, #7
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %dbl, 128.0
   %cvt = call i32 @llvm.fptoui.sat.i32.f16(half %fix)
   ret i32 %cvt
 }
 
 define i32 @fcvtzu_sat_f16_i32_15(half %dbl) {
 ; CHECK-NO16-LABEL: fcvtzu_sat_f16_i32_15:
 ; CHECK-NO16:       // %bb.0:
 ; CHECK-NO16-NEXT:    mov w8, #1191182336
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzu w0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzu_sat_f16_i32_15:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    adrp x8, .LCPI67_0
-; CHECK-FP16-NEXT:    ldr h1, [x8, :lo12:.LCPI67_0]
-; CHECK-FP16-NEXT:    fmul h0, h0, h1
-; CHECK-FP16-NEXT:    fcvtzu w0, h0
+; CHECK-FP16-NEXT:    fcvtzu w0, h0, #15
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %dbl, 32768.0
   %cvt = call i32 @llvm.fptoui.sat.i32.f16(half %fix)
   ret i32 %cvt
 }
 
 define i64 @fcvtzu_sat_f16_i64_7(half %dbl) {
 ; CHECK-NO16-LABEL: fcvtzu_sat_f16_i64_7:
 ; CHECK-NO16:       // %bb.0:
 ; CHECK-NO16-NEXT:    mov w8, #1124073472
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzu x0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzu_sat_f16_i64_7:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    adrp x8, .LCPI68_0
-; CHECK-FP16-NEXT:    ldr h1, [x8, :lo12:.LCPI68_0]
-; CHECK-FP16-NEXT:    fmul h0, h0, h1
-; CHECK-FP16-NEXT:    fcvtzu x0, h0
+; CHECK-FP16-NEXT:    fcvtzu x0, h0, #7
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %dbl, 128.0
   %cvt = call i64 @llvm.fptoui.sat.i64.f16(half %fix)
   ret i64 %cvt
 }
 
 define i64 @fcvtzu_sat_f16_i64_15(half %dbl) {
 ; CHECK-NO16-LABEL: fcvtzu_sat_f16_i64_15:
 ; CHECK-NO16:       // %bb.0:
 ; CHECK-NO16-NEXT:    mov w8, #1191182336
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fmov s1, w8
 ; CHECK-NO16-NEXT:    fmul s0, s0, s1
 ; CHECK-NO16-NEXT:    fcvt h0, s0
 ; CHECK-NO16-NEXT:    fcvt s0, h0
 ; CHECK-NO16-NEXT:    fcvtzu x0, s0
 ; CHECK-NO16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: fcvtzu_sat_f16_i64_15:
 ; CHECK-FP16:       // %bb.0:
-; CHECK-FP16-NEXT:    adrp x8, .LCPI69_0
-; CHECK-FP16-NEXT:    ldr h1, [x8, :lo12:.LCPI69_0]
-; CHECK-FP16-NEXT:    fmul h0, h0, h1
-; CHECK-FP16-NEXT:    fcvtzu x0, h0
+; CHECK-FP16-NEXT:    fcvtzu x0, h0, #15
 ; CHECK-FP16-NEXT:    ret
   %fix = fmul half %dbl, 32768.0
   %cvt = call i64 @llvm.fptoui.sat.i64.f16(half %fix)
   ret i64 %cvt
 }