[WIP][AARCH64] Enable GEP optimizations by default

[djtodoro]

Summary

This patch enables the SeparateConstOffsetFromGEP Pass for the AARCH64 target by default. It was disabled by default with cd2334.

Targets such as PPC, AMDGPU and NPTX run Straight Line Strength Reduce, GVN and Nary Reassociate Passes along with the SeparateConstOffsetFromGEP, so that may solve the issues found back then in the AARCH64 case.

This will address the [0].

TODO: Get the data on SPEC benchmark.

[0] https://bugs.llvm.org/show_bug.cgi?id=51184

Co-authored-by: @mmatic05, @milica-lazarevic, @dmilosevic141

llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

 static cl::opt<bool>
 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
                 cl::desc("Work around Cortex-A53 erratum 835769"),
                 cl::init(false));
 
 static cl::opt<bool>
     EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
                  cl::desc("Enable optimizations on complex GEPs"),
-                 cl::init(false));
+                 cl::init(true));
 
 static cl::opt<bool>
     BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
                      cl::desc("Relax out of range conditional branches"));
 
 static cl::opt<bool> EnableCompressJumpTables(
     "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
     cl::desc("Use smallest entry possible for jump tables"));

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll

 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 ; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O0
-; RUN: llc -O3 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
+; RUN: llc -O3 -stop-after=irtranslator -aarch64-enable-gep-opt=false -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64--"
 
 define i32 @cse_gep([4 x i32]* %ptr, i32 %idx) {
   ; O0-LABEL: name: cse_gep
   ; O0: bb.1 (%ir-block.0):
   ; O0:   liveins: $w1, $x0
   ; O0:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

 ; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
-; RUN: llc -O3 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
+; RUN: llc -O3 -aarch64-enable-atomic-cfg-tidy=0 -aarch64-enable-gep-opt=false -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
 
 ; This file checks that the translation from llvm IR to generic MachineInstr
 ; is correct.
 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64--"
 
 ; Tests for add.
 ; CHECK-LABEL: name: addi64

llvm/test/CodeGen/AArch64/O3-pipeline.ll

 ; CHECK-NEXT:       Function Alias Analysis Results
 ; CHECK-NEXT:       AArch64 Stack Tagging
 ; CHECK-NEXT:       Function Alias Analysis Results
 ; CHECK-NEXT:       Memory SSA
 ; CHECK-NEXT:       Interleaved Load Combine Pass
 ; CHECK-NEXT:       Dominator Tree Construction
 ; CHECK-NEXT:       Interleaved Access Pass
 ; CHECK-NEXT:       Natural Loop Information
+; CHECK-NEXT:      Scalar Evolution Analysis
+; CHECK-NEXT:      Split GEPs to a variadic base and a constant offset for better CSE
+; CHECK-NEXT:      Early CSE
+; CHECK-NEXT:      Basic Alias Analysis (stateless AA impl)
+; CHECK-NEXT:      Function Alias Analysis Results
+; CHECK-NEXT:      Memory SSA
+; CHECK-NEXT:      Canonicalize natural loops
+; CHECK-NEXT:      LCSSA Verifier
+; CHECK-NEXT:      Loop-Closed SSA Form Pass
+; CHECK-NEXT:      Scalar Evolution Analysis
+; CHECK-NEXT:      Lazy Branch Probability Analysis
+; CHECK-NEXT:      Lazy Block Frequency Analysis
+; CHECK-NEXT:      Loop Pass Manager
+; CHECK-NEXT:        Loop Invariant Code Motion
 ; CHECK-NEXT:       CodeGen Prepare
 ; CHECK-NEXT:       Dominator Tree Construction
 ; CHECK-NEXT:       Exception handling preparation
 ; CHECK-NEXT:     AArch64 Promote Constant
 ; CHECK-NEXT:       FunctionPass Manager
 ; CHECK-NEXT:         Dominator Tree Construction
 ; CHECK-NEXT:     FunctionPass Manager
 ; CHECK-NEXT:       Merge internal globals

llvm/test/CodeGen/AArch64/cond-br-tuning.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -debugify-and-strip-all-safe < %s -O3 -mtriple=aarch64-eabi -verify-machineinstrs | FileCheck %s
+; RUN: llc -aarch64-enable-gep-opt=false -debugify-and-strip-all-safe < %s -O3 -mtriple=aarch64-eabi -verify-machineinstrs | FileCheck %s
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-linaro-linux-gnueabi"
 
 ; CMN is an alias of ADDS.
 
 define void @test_add_cbz(i32 %a, i32 %b, i32* %ptr) {
 ; CHECK-LABEL: test_add_cbz: