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Differential D112942

target ABI: improve call parameters extensions handling
Needs ReviewPublic

Authored by jonpa on Nov 1 2021, 11:12 AM.

Details

Reviewers
uweigand
rnk
efriedma
Summary

As discussed on llvm-dev (https://lists.llvm.org/pipermail/llvm-dev/2021-October/153080.html), there has been a recurring problem of missing extension attributes on call arguments.

This patch tries to improve on the situation by intorducing a 'NoExt' attribute that is (at least in theory, at the moment) mandatory for a struct passed in an integer register. By demanding that a (narrow) integer argument has one of the sign/zero/no extension attributes, cases where this has been forgotten in the FE can be isolated.

Changes:

  • Clang FE:
    • A new bit ZeroExt in ABIArgInfo. If Kind is Extend, it is SignExt or ZeroExt, or else NoExt is implied.
    • A new method ABIArgInfo::getNoExtend(), used by SystemZABIInfo::classifyArgumentType() for a struct-in-reg argument. (CGCall.cpp:CodeGenTypes::arrangeLLVMFunctionInfo() calls SystemZABIInfo::computeInfo() and the argument types are classified. How about Swift (or SPIR_KERNEL) CCs: should they also have narrow integer arguments extended on SystemZ?)
  • IR: new attribute NoExt, handled by parser, emitter etc. Adding one bit IsNoExt ArgFlagsTy grew it past the 3-byte size, so the static_assert was incremented to match the new size of 4 bytes. Any problem with this?
  • SystemZ backend:
    • Default sign extension of <=32 bit arguments added, which can be disabled with '-no-arg-exts'.
    • New option -verify-int-arg-exts (default off), that when passed checks that all <=32 bit integer arguments have a valid extension attribute. Verifying extension of return values and outgoing call arguments: Incoming function parameters and call results could also be checked, but they are not needed for correctness, but only to let the backend assume they are sign-extended properly.
    • A lot of tests updated, mostly with -no-arg-exts, which makes sense in cases like testing for a three-address instruction selection. It seems reasonable to simply disable this default sign-extension during testing, but in a way it may in the future be better to instead update the tests. There are more tests that can be updated - I have only changed the ones that seemed trivial so far. (args-04.ll: This is testing incoming arguments, but it is returning them without extension. This is a little weird as structs are never returned in a reg..?)
  • Documentation: Explanation of the NoExt attribute and why it is mandatory.

The comment for getTypeForExtReturn() may be related to this issue..? "// Return the type that should be used to zero or sign extend a zeroext/signext integer return value. FIXME: Some C calling conventions require the return type to be promoted, but this is not true all the time, e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling conventions. The frontend should handle this and include all of the necessary information."

So far, this is a work in progress so feel free to make suggestions...

Diff Detail

Unit TestsFailed

TimeTest
1,200 msx64 debian > AddressSanitizer-x86_64-linux-dynamic.TestCases::exitcode.cpp
1,630 msx64 debian > AddressSanitizer-x86_64-linux.TestCases::exitcode.cpp

Event Timeline

jonpa created this revision.Nov 1 2021, 11:12 AM
Herald added subscribers: luke957, ormris, dexonsmith and 7 others. · View Herald TranscriptNov 1 2021, 11:12 AM
jonpa requested review of this revision.Nov 1 2021, 11:12 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 1 2021, 11:12 AM
vchuravy added a subscriber: vchuravy.Nov 1 2021, 11:18 AM
Harbormaster completed remote builds in B131771: Diff 383839.Nov 1 2021, 12:12 PM
rnk added a subscriber: aeubanks.Nov 1 2021, 3:17 PM

Seems reasonable to me. +@aeubanks, can you review this? I think you ran into these issues with SystemZ extension attributes when you made that change to only look at call site ABI attributes.

llvm/include/llvm/IR/Attributes.td
139

This is not SystemZ-specific, so instead of "struct in reg" I suggest "high bits are undefined". That should be accurate when this attribute is used on any target.

ormris removed a subscriber: ormris.Jan 24 2022, 11:30 AM
Herald added a subscriber: • pcwang-thead. · View Herald TranscriptJan 24 2022, 11:30 AM
jonpa added a comment.Mar 24 2022, 10:10 AM

I ran this on SPEC (with -mllvm -verify-int-arg-exts), and believe I found two things that need to be fixed:

Argument promotion: https://github.com/llvm/llvm-project/issues/54530
InstCombine libcalls: https://github.com/llvm/llvm-project/issues/54532

Herald added a project: Restricted Project. · View Herald TranscriptMar 24 2022, 10:10 AM
LiuChen3 added a subscriber: LiuChen3.Mar 24 2022, 11:13 PM
jonpa updated this revision to Diff 418399.Mar 26 2022, 9:01 AM
jonpa marked an inline comment as done.

Patch updated:

  • only do a verification / default sign extension when an externally visible function is involved. IR producers such as Argument Promotion is free to change the ABI and pass a non-extended argument as long as it is only in local scope.
  • Allow NoExt attribute also on returned values.
  • Tests updated so that no tests are changed, but instead the -no-arg-exts CL option is passed, which makes the default sign extension to be skipped.

I found that with this patch, which enables the default sign extension by default, on SPEC I mainly see a lot of lhi -> lghi changes, with not many more instructions overall:

lhi            :               219521               218299    -1222
lghi           :               445907               447129    +1222
llgfr          :                89262                89289      +27
chi            :                53164                53180      +16
lbh            :                 1141                 1125      -16
lb             :                19083                19099      +16
locfhrl        :                   27                   11      -16
locrl          :                 2922                 2938      +16
llcr           :                 5076                 5092      +16
lr             :                63302                63287      -15
risblg         :                17057                17042      -15
cih            :                 6728                 6715      -13
lgfr           :                89323                89329       +6

...
OPCDIFFS: +22

Herald added a subscriber: fedor.sergeev. · View Herald TranscriptMar 26 2022, 9:01 AM
Harbormaster completed remote builds in B156415: Diff 418399.Mar 27 2022, 12:01 AM
LiuChen3 mentioned this in D122963: [X86] Extend the integer parameter if the function isn't local linked.Apr 7 2022, 7:42 PM
jonpa mentioned this in D123198: [LibCalls] Add argument extension attributes to more functions..Apr 9 2022, 2:56 AM
jonpa updated this revision to Diff 427009.May 4 2022, 8:21 AM
jonpa added a reviewer: efriedma.

minor fixing after rebase.

After I committed the proper handling of libcalls emission I have now built SPEC17, the test-suite tests and also bootstrapped LLVM with this patch applied and verified it all without any more errors. So right now those attributes look "green" on SystemZ with the Clang front end and I think it would be useful to continue with this patch. There are two things here of interest:

  • verifying argument attributes.

Should this check be moved from the SystemZ backend out into common code and use TLI.getExtAttrForI32Param() to enable selectively? That function is for library calls, but I think they should apply to any call?

  • adding a default extension in case of a missing attribute which is better than nothing.

Maybe this should also be moved out in the same way and enabled with some similar hook? I think for SystemZ we will use a sign extension and think that is probably what everyone wants (the most likely to help).

Harbormaster completed remote builds in B162695: Diff 427009.May 4 2022, 10:57 AM
dexonsmith removed a subscriber: dexonsmith.May 4 2022, 6:28 PM
jonpa added a comment.May 17 2022, 10:37 AM

Ping!

Anyone else thinks this verification / default extension should be placed in common code instead of in just the SystemZ backend?

efriedma added a comment.May 18 2022, 4:16 PM

Not sure how much I like the rule about "externally visible functions"... I mean, I guess restricting the checking to external functions avoids triggering on a bunch of cases that would be difficult to handle, but it doesn't really seem self-consistent.

How about this: we introduce NoExt, but in LangRef we just say "If an integer argument to a function is not marked signext/zeroext/noext, the kind of extension is used is target-specific. Some targets may generate less efficient code if the kind of extension is not explicitly specified." This is basically what you're doing now: follow the attribute, and sign-extend in the caller if there's no attribute. But there isn't an implication that generating calls without any extension attributes is invalid on all targets.

For the lint in the backend, instead of checking whether the callee is an external symbol, maybe check whether the calling convention is "C" (as opposed to "fast").

jonpa added a comment.May 23 2022, 5:43 AM
In D112942#3523792, @efriedma wrote:

Not sure how much I like the rule about "externally visible functions"... I mean, I guess restricting the checking to external functions avoids triggering on a bunch of cases that would be difficult to handle, but it doesn't really seem self-consistent.

Well, if we decide to in llvm *not* do the optimization of removing an extension of an incoming argument (which the ABI says is legal), our only concern is when calling or returning a value from an externally visible function. I think this is a legacy issue and not important for performance, so acting on the attribute when compiling is not something we plan to do (at least on SystemZ).

How about this: we introduce NoExt, but in LangRef we just say "If an integer argument to a function is not marked signext/zeroext/noext, the kind of extension is used is target-specific. Some targets may generate less efficient code if the kind of extension is not explicitly specified." This is basically what you're doing now: follow the attribute, and sign-extend in the caller if there's no attribute. But there isn't an implication that generating calls without any extension attributes is invalid on all targets.

I consider the "default extension" to be related but not really the same idea: it merely serves as a "better than nothing" solution, but I think that may be removed in the future, and the verification instead is on by default. Actually, this could be done for SystemZ now at least as things look "green" now. Note that this default extension could be wrong (use SExt instead of ZExt on a very big unsigned value).

How about:
"If an integer argument to a function is not marked signext/zeroext/noext, the kind of extension used is target-specific. Some targets depend for correctness the kind of extension to be explicitly specified."

For the lint in the backend, instead of checking whether the callee is an external symbol, maybe check whether the calling convention is "C" (as opposed to "fast").

Do all externally visible functions always have the "C" calling convention?

Should the VerifyIntegerArg() and CheckNarrowIntegerArgs() remain in SystemZ or should I move them somewhere and let any target use them as desired? I think the default extension could be done if desired entirely in the target backend, or?

efriedma added a comment.May 23 2022, 2:12 PM
In D112942#3531179, @jonpa wrote:

How about:
"If an integer argument to a function is not marked signext/zeroext/noext, the kind of extension used is target-specific. Some targets depend for correctness the kind of extension to be explicitly specified."

I guess that's sufficient.

For the lint in the backend, instead of checking whether the callee is an external symbol, maybe check whether the calling convention is "C" (as opposed to "fast").

Do all externally visible functions always have the "C" calling convention?

Unless you're using some attribute to modify the calling convention, everything in clang defaults to "C". Some targets, like x86 Windows, frequently use alternate calling conventions, but I assume SystemZ doesn't.

Should the VerifyIntegerArg() and CheckNarrowIntegerArgs() remain in SystemZ or should I move them somewhere and let any target use them as desired? I think the default extension could be done if desired entirely in the target backend, or?

I think I'm okay leaving it in target-specific code; unifying anything related to calls is hard.

jonpa added a comment.Sep 13 2022, 4:20 AM

Unless you're using some attribute to modify the calling convention, everything in clang defaults to "C". Some targets, like x86 Windows, frequently use alternate calling conventions, but I assume SystemZ doesn't.

I still feel more comfortable with the "external / internal" heuristic, as the whole idea is that we actually are using a trick by assuming we will be safe in clang by never acting on this optimization. For me this attribute is more readable as it reflects the idea directly, compared to checking for "C". I also feel that it is very precise and can therefore never go wrong.

I think I'm okay leaving it in target-specific code; unifying anything related to calls is hard.

Ok, makes sense.

SPEC builds fine now after the handling of library calls arguments extensions we did earlier, but now have encountered problems when building the llvm tests: AddressSanitizer seems to be dropping these attributes:

Compiling gtest-all (reduced):

extern "C" void *memset(void *, int, long);
memset(&hints, 0, sizeof(hints));    

=>

declare ptr @memset(ptr noundef, i32 noundef signext, i64 noundef)
%call = call ptr @memset(ptr noundef %hints, i32 noundef signext 0, i64 noundef 16)

=>  InstCombine

declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg)
call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(16) %hints, i8 noundef signext 0, i64 nound
ef 16, i1 false)

=>  AddressSanitizer

declare ptr @__asan_memset(ptr, i32, i64)
%24 = call ptr @__asan_memset(ptr %12, i32 0, i64 16)

This last step is replacing an intrinsic with a call to a global function. I believe there may be some work in progress on how these attributes are supposed to be eventually managed (only in declaration, only on call instruction, either, or both), and would like to first ask how I should go about this: InstCombiner is transferring the attribute when it's building the replacing call, and it seems that AddressSanitizer should do the same. Or is there another preferred approach?

efriedma added a comment.Sep 13 2022, 11:38 AM

"signext" doesn't really make sense on llvm.memset: it's not a call. It's an intrinsic. It might be lowered to a call, but that's not really relevant: even if we do generate a call, there's no reason to expect that call's calling convention is the same as memset's calling convention. instcombine transferring it is just an accident.

The ASan instrumentation pass should be able to figure out the correct attributes for any functions it calls from first principles (possibly using TargetLibraryInfo::getExtAttrForI32Param(), like other instrumentation passes).

jonpa added a comment.Sep 15 2022, 8:48 AM
In D112942#3787224, @efriedma wrote:

"signext" doesn't really make sense on llvm.memset: it's not a call. It's an intrinsic. It might be lowered to a call, but that's not really relevant: even if we do generate a call, there's no reason to expect that call's calling convention is the same as memset's calling convention. instcombine transferring it is just an accident.

The ASan instrumentation pass should be able to figure out the correct attributes for any functions it calls from first principles (possibly using TargetLibraryInfo::getExtAttrForI32Param(), like other instrumentation passes).

ok - started working on that here: https://reviews.llvm.org/D133949

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Diff 383839

clang/include/clang/CodeGen/CGFunctionInfo.h

Show First 20 Lines • Show All 110 Lines • ▼ Show 20 Linesprivate:
bool InAllocaSRet : 1; // isInAlloca() bool InAllocaSRet : 1; // isInAlloca()
bool InAllocaIndirect : 1;// isInAlloca() bool InAllocaIndirect : 1;// isInAlloca()
bool IndirectByVal : 1; // isIndirect() bool IndirectByVal : 1; // isIndirect()
bool IndirectRealign : 1; // isIndirect() bool IndirectRealign : 1; // isIndirect()
bool SRetAfterThis : 1; // isIndirect() bool SRetAfterThis : 1; // isIndirect()
bool InReg : 1; // isDirect() || isExtend() || isIndirect() bool InReg : 1; // isDirect() || isExtend() || isIndirect()
bool CanBeFlattened: 1; // isDirect() bool CanBeFlattened: 1; // isDirect()
bool SignExt : 1; // isExtend() bool SignExt : 1; // isExtend()
bool ZeroExt : 1; // isExtend()
bool canHavePaddingType() const { bool canHavePaddingType() const {
return isDirect() || isExtend() || isIndirect() || isIndirectAliased() || return isDirect() || isExtend() || isIndirect() || isIndirectAliased() ||
isExpand(); isExpand();
} }
void setPaddingType(llvm::Type *T) { void setPaddingType(llvm::Type *T) {
assert(canHavePaddingType()); assert(canHavePaddingType());
PaddingType = T; PaddingType = T;
} }
void setUnpaddedCoerceToType(llvm::Type *T) { void setUnpaddedCoerceToType(llvm::Type *T) {
assert(isCoerceAndExpand()); assert(isCoerceAndExpand());
UnpaddedCoerceAndExpandType = T; UnpaddedCoerceAndExpandType = T;
} }
public: public:
ABIArgInfo(Kind K = Direct) ABIArgInfo(Kind K = Direct)
: TypeData(nullptr), PaddingType(nullptr), DirectAttr{0, 0}, TheKind(K), : TypeData(nullptr), PaddingType(nullptr), DirectAttr{0, 0}, TheKind(K),
PaddingInReg(false), InAllocaSRet(false), PaddingInReg(false), InAllocaSRet(false),
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-        PaddingInReg(false), InAllocaSRet(false),
-        InAllocaIndirect(false), IndirectByVal(false), IndirectRealign(false),
-        SRetAfterThis(false), InReg(false), CanBeFlattened(false),
-        SignExt(false), ZeroExt(false) {}
+        PaddingInReg(false), InAllocaSRet(false), InAllocaIndirect(false),
+        IndirectByVal(false), IndirectRealign(false), SRetAfterThis(false),
+        InReg(false), CanBeFlattened(false), SignExt(false), ZeroExt(false) {}
Lint: Pre-merge checks: clang-format: please reformat the code ``` - PaddingInReg(false), InAllocaSRet(false)…
InAllocaIndirect(false), IndirectByVal(false), IndirectRealign(false), InAllocaIndirect(false), IndirectByVal(false), IndirectRealign(false),
SRetAfterThis(false), InReg(false), CanBeFlattened(false), SRetAfterThis(false), InReg(false), CanBeFlattened(false),
SignExt(false) {} SignExt(false), ZeroExt(false) {}
static ABIArgInfo getDirect(llvm::Type *T = nullptr, unsigned Offset = 0, static ABIArgInfo getDirect(llvm::Type *T = nullptr, unsigned Offset = 0,
llvm::Type *Padding = nullptr, llvm::Type *Padding = nullptr,
bool CanBeFlattened = true, unsigned Align = 0) { bool CanBeFlattened = true, unsigned Align = 0) {
auto AI = ABIArgInfo(Direct); auto AI = ABIArgInfo(Direct);
AI.setCoerceToType(T); AI.setCoerceToType(T);
AI.setPaddingType(Padding); AI.setPaddingType(Padding);
AI.setDirectOffset(Offset); AI.setDirectOffset(Offset);
Show All 20 Linespublic:
static ABIArgInfo getZeroExtend(QualType Ty, llvm::Type *T = nullptr) { static ABIArgInfo getZeroExtend(QualType Ty, llvm::Type *T = nullptr) {
assert(Ty->isIntegralOrEnumerationType() && "Unexpected QualType"); assert(Ty->isIntegralOrEnumerationType() && "Unexpected QualType");
auto AI = ABIArgInfo(Extend); auto AI = ABIArgInfo(Extend);
AI.setCoerceToType(T); AI.setCoerceToType(T);
AI.setPaddingType(nullptr); AI.setPaddingType(nullptr);
AI.setDirectOffset(0); AI.setDirectOffset(0);
AI.setDirectAlign(0); AI.setDirectAlign(0);
AI.setSignExt(false); AI.setZeroExt(true);
return AI; return AI;
} }
// ABIArgInfo will record the argument as being extended based on the sign // ABIArgInfo will record the argument as being extended based on the sign
// of its type. // of its type. Produces a sign or zero extension.
static ABIArgInfo getExtend(QualType Ty, llvm::Type *T = nullptr) { static ABIArgInfo getExtend(QualType Ty, llvm::Type *T = nullptr) {
assert(Ty->isIntegralOrEnumerationType() && "Unexpected QualType"); assert(Ty->isIntegralOrEnumerationType() && "Unexpected QualType");
if (Ty->hasSignedIntegerRepresentation()) if (Ty->hasSignedIntegerRepresentation())
return getSignExtend(Ty, T); return getSignExtend(Ty, T);
return getZeroExtend(Ty, T); return getZeroExtend(Ty, T);
} }
// Struct in register marked explicitly as not needing extension.
static ABIArgInfo getNoExtend(llvm::IntegerType *T) {
auto AI = ABIArgInfo(Extend);
AI.setCoerceToType(T);
return AI;
}
static ABIArgInfo getExtendInReg(QualType Ty, llvm::Type *T = nullptr) { static ABIArgInfo getExtendInReg(QualType Ty, llvm::Type *T = nullptr) {
auto AI = getExtend(Ty, T); auto AI = getExtend(Ty, T);
AI.setInReg(true); AI.setInReg(true);
return AI; return AI;
} }
static ABIArgInfo getIgnore() { static ABIArgInfo getIgnore() {
return ABIArgInfo(Ignore); return ABIArgInfo(Ignore);
} }
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Lines unsigned getDirectAlign() const {
return DirectAttr.Align; return DirectAttr.Align;
} }
void setDirectAlign(unsigned Align) { void setDirectAlign(unsigned Align) {
assert((isDirect() || isExtend()) && "Not a direct or extend kind"); assert((isDirect() || isExtend()) && "Not a direct or extend kind");
DirectAttr.Align = Align; DirectAttr.Align = Align;
} }
bool isSignExt() const { bool isSignExt() const {
assert(isExtend() && "Invalid kind!"); assert(isExtend() && (SignExt + ZeroExt <= 1) && "Invalid kind / flags!");
return SignExt; return SignExt;
} }
void setSignExt(bool SExt) { void setSignExt(bool SExt) {
assert(isExtend() && "Invalid kind!"); assert(isExtend() && "Invalid kind!");
SignExt = SExt; SignExt = SExt;
} }
bool isZeroExt() const {
assert(isExtend() && (SignExt + ZeroExt <= 1) && "Invalid kind / flags!");
return ZeroExt;
}
void setZeroExt(bool ZExt) {
assert(isExtend() && "Invalid kind!");
ZeroExt = ZExt;
}
llvm::Type *getPaddingType() const { llvm::Type *getPaddingType() const {
return (canHavePaddingType() ? PaddingType : nullptr); return (canHavePaddingType() ? PaddingType : nullptr);
} }
bool getPaddingInReg() const { bool getPaddingInReg() const {
return PaddingInReg; return PaddingInReg;
} }
void setPaddingInReg(bool PIR) { void setPaddingInReg(bool PIR) {
▲ Show 20 Lines • Show All 446 Lines • Show Last 20 Lines

clang/lib/CodeGen/CGCall.cpp

Show First 20 Lines • Show All 2,259 Lines • ▼ Show 20 Lines if (!RetTy->isVoidType() && RetAI.getKind() != ABIArgInfo::Indirect &&
DetermineNoUndef(RetTy, getTypes(), DL, RetAI)) DetermineNoUndef(RetTy, getTypes(), DL, RetAI))
RetAttrs.addAttribute(llvm::Attribute::NoUndef); RetAttrs.addAttribute(llvm::Attribute::NoUndef);
} }
switch (RetAI.getKind()) { switch (RetAI.getKind()) {
case ABIArgInfo::Extend: case ABIArgInfo::Extend:
if (RetAI.isSignExt()) if (RetAI.isSignExt())
RetAttrs.addAttribute(llvm::Attribute::SExt); RetAttrs.addAttribute(llvm::Attribute::SExt);
else else if (RetAI.isZeroExt())
RetAttrs.addAttribute(llvm::Attribute::ZExt); RetAttrs.addAttribute(llvm::Attribute::ZExt);
else
RetAttrs.addAttribute(llvm::Attribute::NoExt);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case ABIArgInfo::Direct: case ABIArgInfo::Direct:
if (RetAI.getInReg()) if (RetAI.getInReg())
RetAttrs.addAttribute(llvm::Attribute::InReg); RetAttrs.addAttribute(llvm::Attribute::InReg);
break; break;
case ABIArgInfo::Ignore: case ABIArgInfo::Ignore:
break; break;
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines for (CGFunctionInfo::const_arg_iterator I = FI.arg_begin(),
// 'restrict' -> 'noalias' is done in EmitFunctionProlog when we // 'restrict' -> 'noalias' is done in EmitFunctionProlog when we
// have the corresponding parameter variable. It doesn't make // have the corresponding parameter variable. It doesn't make
// sense to do it here because parameters are so messed up. // sense to do it here because parameters are so messed up.
switch (AI.getKind()) { switch (AI.getKind()) {
case ABIArgInfo::Extend: case ABIArgInfo::Extend:
if (AI.isSignExt()) if (AI.isSignExt())
Attrs.addAttribute(llvm::Attribute::SExt); Attrs.addAttribute(llvm::Attribute::SExt);
else else if (AI.isZeroExt())
Attrs.addAttribute(llvm::Attribute::ZExt); Attrs.addAttribute(llvm::Attribute::ZExt);
else
Attrs.addAttribute(llvm::Attribute::NoExt);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case ABIArgInfo::Direct: case ABIArgInfo::Direct:
if (ArgNo == 0 && FI.isChainCall()) if (ArgNo == 0 && FI.isChainCall())
Attrs.addAttribute(llvm::Attribute::Nest); Attrs.addAttribute(llvm::Attribute::Nest);
else if (AI.getInReg()) else if (AI.getInReg())
Attrs.addAttribute(llvm::Attribute::InReg); Attrs.addAttribute(llvm::Attribute::InReg);
Attrs.addStackAlignmentAttr(llvm::MaybeAlign(AI.getDirectAlign())); Attrs.addStackAlignmentAttr(llvm::MaybeAlign(AI.getDirectAlign()));
break; break;
▲ Show 20 Lines • Show All 3,127 Lines • Show Last 20 Lines

clang/lib/CodeGen/TargetInfo.cpp

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Show First 20 Lines • Show All 7,660 Lines • ▼ Show 20 LinesABIArgInfo SystemZABIInfo::classifyArgumentType(QualType Ty) const {
if (const RecordType *RT = Ty->getAs<RecordType>()) { if (const RecordType *RT = Ty->getAs<RecordType>()) {
// Structures with flexible arrays have variable length, so really // Structures with flexible arrays have variable length, so really
// fail the size test above. // fail the size test above.
const RecordDecl *RD = RT->getDecl(); const RecordDecl *RD = RT->getDecl();
if (RD->hasFlexibleArrayMember()) if (RD->hasFlexibleArrayMember())
return getNaturalAlignIndirect(Ty, /*ByVal=*/false); return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
// The structure is passed as an unextended integer, a float, or a double. // The structure is passed as an unextended integer, a float, or a double.
llvm::Type *PassTy;
if (isFPArgumentType(SingleElementTy)) { if (isFPArgumentType(SingleElementTy)) {
assert(Size == 32 || Size == 64); assert(Size == 32 || Size == 64);
llvm::Type *PassTy;
if (Size == 32) if (Size == 32)
PassTy = llvm::Type::getFloatTy(getVMContext()); PassTy = llvm::Type::getFloatTy(getVMContext());
else else
PassTy = llvm::Type::getDoubleTy(getVMContext()); PassTy = llvm::Type::getDoubleTy(getVMContext());
} else
PassTy = llvm::IntegerType::get(getVMContext(), Size);
return ABIArgInfo::getDirect(PassTy); return ABIArgInfo::getDirect(PassTy);
} else {
llvm::IntegerType *PassTy = llvm::IntegerType::get(getVMContext(), Size);
if (Size <= 32)
return ABIArgInfo::getNoExtend(PassTy);
return ABIArgInfo::getDirect(PassTy);
}
} }
// Non-structure compounds are passed indirectly. // Non-structure compounds are passed indirectly.
if (isCompoundType(Ty)) if (isCompoundType(Ty))
return getNaturalAlignIndirect(Ty, /*ByVal=*/false); return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
return ABIArgInfo::getDirect(nullptr); return ABIArgInfo::getDirect(nullptr);
} }
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clang/test/CodeGen/SystemZ/systemz-abi-vector.c

Show First 20 Lines • Show All 138 Lines • ▼ Show 20 Lines
// CHECK-LABEL: define{{.*}} void @pass_v1f128(<1 x fp128>* noalias sret(<1 x fp128>) align 16 %{{.*}}, <1 x fp128>* %0) // CHECK-LABEL: define{{.*}} void @pass_v1f128(<1 x fp128>* noalias sret(<1 x fp128>) align 16 %{{.*}}, <1 x fp128>* %0)
// CHECK-VECTOR-LABEL: define{{.*}} <1 x fp128> @pass_v1f128(<1 x fp128> %{{.*}}) // CHECK-VECTOR-LABEL: define{{.*}} <1 x fp128> @pass_v1f128(<1 x fp128> %{{.*}})
// Vector-like aggregate types // Vector-like aggregate types
struct agg_v1i8 { v1i8 a; }; struct agg_v1i8 { v1i8 a; };
struct agg_v1i8 pass_agg_v1i8(struct agg_v1i8 arg) { return arg; } struct agg_v1i8 pass_agg_v1i8(struct agg_v1i8 arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @pass_agg_v1i8(%struct.agg_v1i8* noalias sret(%struct.agg_v1i8) align 1 %{{.*}}, i8 %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_agg_v1i8(%struct.agg_v1i8* noalias sret(%struct.agg_v1i8) align 1 %{{.*}}, i8 noext %{{.*}})
// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v1i8(%struct.agg_v1i8* noalias sret(%struct.agg_v1i8) align 1 %{{.*}}, <1 x i8> %{{.*}}) // CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v1i8(%struct.agg_v1i8* noalias sret(%struct.agg_v1i8) align 1 %{{.*}}, <1 x i8> %{{.*}})
struct agg_v2i8 { v2i8 a; }; struct agg_v2i8 { v2i8 a; };
struct agg_v2i8 pass_agg_v2i8(struct agg_v2i8 arg) { return arg; } struct agg_v2i8 pass_agg_v2i8(struct agg_v2i8 arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @pass_agg_v2i8(%struct.agg_v2i8* noalias sret(%struct.agg_v2i8) align 2 %{{.*}}, i16 %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_agg_v2i8(%struct.agg_v2i8* noalias sret(%struct.agg_v2i8) align 2 %{{.*}}, i16 noext %{{.*}})
// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v2i8(%struct.agg_v2i8* noalias sret(%struct.agg_v2i8) align 2 %{{.*}}, <2 x i8> %{{.*}}) // CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v2i8(%struct.agg_v2i8* noalias sret(%struct.agg_v2i8) align 2 %{{.*}}, <2 x i8> %{{.*}})
struct agg_v4i8 { v4i8 a; }; struct agg_v4i8 { v4i8 a; };
struct agg_v4i8 pass_agg_v4i8(struct agg_v4i8 arg) { return arg; } struct agg_v4i8 pass_agg_v4i8(struct agg_v4i8 arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @pass_agg_v4i8(%struct.agg_v4i8* noalias sret(%struct.agg_v4i8) align 4 %{{.*}}, i32 %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_agg_v4i8(%struct.agg_v4i8* noalias sret(%struct.agg_v4i8) align 4 %{{.*}}, i32 noext %{{.*}})
// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v4i8(%struct.agg_v4i8* noalias sret(%struct.agg_v4i8) align 4 %{{.*}}, <4 x i8> %{{.*}}) // CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v4i8(%struct.agg_v4i8* noalias sret(%struct.agg_v4i8) align 4 %{{.*}}, <4 x i8> %{{.*}})
struct agg_v8i8 { v8i8 a; }; struct agg_v8i8 { v8i8 a; };
struct agg_v8i8 pass_agg_v8i8(struct agg_v8i8 arg) { return arg; } struct agg_v8i8 pass_agg_v8i8(struct agg_v8i8 arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @pass_agg_v8i8(%struct.agg_v8i8* noalias sret(%struct.agg_v8i8) align 8 %{{.*}}, i64 %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_agg_v8i8(%struct.agg_v8i8* noalias sret(%struct.agg_v8i8) align 8 %{{.*}}, i64 %{{.*}})
// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v8i8(%struct.agg_v8i8* noalias sret(%struct.agg_v8i8) align 8 %{{.*}}, <8 x i8> %{{.*}}) // CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_v8i8(%struct.agg_v8i8* noalias sret(%struct.agg_v8i8) align 8 %{{.*}}, <8 x i8> %{{.*}})
struct agg_v16i8 { v16i8 a; }; struct agg_v16i8 { v16i8 a; };
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struct agg_novector2 { v4i8 a; float b; }; struct agg_novector2 { v4i8 a; float b; };
struct agg_novector2 pass_agg_novector2(struct agg_novector2 arg) { return arg; } struct agg_novector2 pass_agg_novector2(struct agg_novector2 arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @pass_agg_novector2(%struct.agg_novector2* noalias sret(%struct.agg_novector2) align 4 %{{.*}}, i64 %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_agg_novector2(%struct.agg_novector2* noalias sret(%struct.agg_novector2) align 4 %{{.*}}, i64 %{{.*}})
// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_novector2(%struct.agg_novector2* noalias sret(%struct.agg_novector2) align 4 %{{.*}}, i64 %{{.*}}) // CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_novector2(%struct.agg_novector2* noalias sret(%struct.agg_novector2) align 4 %{{.*}}, i64 %{{.*}})
struct agg_novector3 { v4i8 a; int : 0; }; struct agg_novector3 { v4i8 a; int : 0; };
struct agg_novector3 pass_agg_novector3(struct agg_novector3 arg) { return arg; } struct agg_novector3 pass_agg_novector3(struct agg_novector3 arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @pass_agg_novector3(%struct.agg_novector3* noalias sret(%struct.agg_novector3) align 4 %{{.*}}, i32 %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_agg_novector3(%struct.agg_novector3* noalias sret(%struct.agg_novector3) align 4 %{{.*}}, i32 noext %{{.*}})
// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_novector3(%struct.agg_novector3* noalias sret(%struct.agg_novector3) align 4 %{{.*}}, i32 %{{.*}}) // CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_novector3(%struct.agg_novector3* noalias sret(%struct.agg_novector3) align 4 %{{.*}}, i32 noext %{{.*}})
struct agg_novector4 { v4i8 a __attribute__((aligned (8))); }; struct agg_novector4 { v4i8 a __attribute__((aligned (8))); };
struct agg_novector4 pass_agg_novector4(struct agg_novector4 arg) { return arg; } struct agg_novector4 pass_agg_novector4(struct agg_novector4 arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @pass_agg_novector4(%struct.agg_novector4* noalias sret(%struct.agg_novector4) align 8 %{{.*}}, i64 %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_agg_novector4(%struct.agg_novector4* noalias sret(%struct.agg_novector4) align 8 %{{.*}}, i64 %{{.*}})
// CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_novector4(%struct.agg_novector4* noalias sret(%struct.agg_novector4) align 8 %{{.*}}, i64 %{{.*}}) // CHECK-VECTOR-LABEL: define{{.*}} void @pass_agg_novector4(%struct.agg_novector4* noalias sret(%struct.agg_novector4) align 8 %{{.*}}, i64 %{{.*}})
// Accessing variable argument lists // Accessing variable argument lists
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clang/test/CodeGen/SystemZ/systemz-abi.c

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
_Complex long double pass_complex_longdouble(_Complex long double arg) { return arg; } _Complex long double pass_complex_longdouble(_Complex long double arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @pass_complex_longdouble({ fp128, fp128 }* noalias sret({ fp128, fp128 }) align 8 %{{.*}}, { fp128, fp128 }* %{{.*}}arg) // CHECK-LABEL: define{{.*}} void @pass_complex_longdouble({ fp128, fp128 }* noalias sret({ fp128, fp128 }) align 8 %{{.*}}, { fp128, fp128 }* %{{.*}}arg)
// Aggregate types // Aggregate types
struct agg_1byte { char a[1]; }; struct agg_1byte { char a[1]; };
struct agg_1byte pass_agg_1byte(struct agg_1byte arg) { return arg; } struct agg_1byte pass_agg_1byte(struct agg_1byte arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @pass_agg_1byte(%struct.agg_1byte* noalias sret(%struct.agg_1byte) align 1 %{{.*}}, i8 %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_agg_1byte(%struct.agg_1byte* noalias sret(%struct.agg_1byte) align 1 %{{.*}}, i8 noext %{{.*}})
struct agg_2byte { char a[2]; }; struct agg_2byte { char a[2]; };
struct agg_2byte pass_agg_2byte(struct agg_2byte arg) { return arg; } struct agg_2byte pass_agg_2byte(struct agg_2byte arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @pass_agg_2byte(%struct.agg_2byte* noalias sret(%struct.agg_2byte) align 1 %{{.*}}, i16 %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_agg_2byte(%struct.agg_2byte* noalias sret(%struct.agg_2byte) align 1 %{{.*}}, i16 noext %{{.*}})
struct agg_3byte { char a[3]; }; struct agg_3byte { char a[3]; };
struct agg_3byte pass_agg_3byte(struct agg_3byte arg) { return arg; } struct agg_3byte pass_agg_3byte(struct agg_3byte arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @pass_agg_3byte(%struct.agg_3byte* noalias sret(%struct.agg_3byte) align 1 %{{.*}}, %struct.agg_3byte* %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_agg_3byte(%struct.agg_3byte* noalias sret(%struct.agg_3byte) align 1 %{{.*}}, %struct.agg_3byte* %{{.*}})
struct agg_4byte { char a[4]; }; struct agg_4byte { char a[4]; };
struct agg_4byte pass_agg_4byte(struct agg_4byte arg) { return arg; } struct agg_4byte pass_agg_4byte(struct agg_4byte arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @pass_agg_4byte(%struct.agg_4byte* noalias sret(%struct.agg_4byte) align 1 %{{.*}}, i32 %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_agg_4byte(%struct.agg_4byte* noalias sret(%struct.agg_4byte) align 1 %{{.*}}, i32 noext %{{.*}})
struct agg_5byte { char a[5]; }; struct agg_5byte { char a[5]; };
struct agg_5byte pass_agg_5byte(struct agg_5byte arg) { return arg; } struct agg_5byte pass_agg_5byte(struct agg_5byte arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @pass_agg_5byte(%struct.agg_5byte* noalias sret(%struct.agg_5byte) align 1 %{{.*}}, %struct.agg_5byte* %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_agg_5byte(%struct.agg_5byte* noalias sret(%struct.agg_5byte) align 1 %{{.*}}, %struct.agg_5byte* %{{.*}})
struct agg_6byte { char a[6]; }; struct agg_6byte { char a[6]; };
struct agg_6byte pass_agg_6byte(struct agg_6byte arg) { return arg; } struct agg_6byte pass_agg_6byte(struct agg_6byte arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @pass_agg_6byte(%struct.agg_6byte* noalias sret(%struct.agg_6byte) align 1 %{{.*}}, %struct.agg_6byte* %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_agg_6byte(%struct.agg_6byte* noalias sret(%struct.agg_6byte) align 1 %{{.*}}, %struct.agg_6byte* %{{.*}})
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// CHECK-LABEL: define{{.*}} void @pass_agg_16byte(%struct.agg_16byte* noalias sret(%struct.agg_16byte) align 1 %{{.*}}, %struct.agg_16byte* %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_agg_16byte(%struct.agg_16byte* noalias sret(%struct.agg_16byte) align 1 %{{.*}}, %struct.agg_16byte* %{{.*}})
// Float-like aggregate types // Float-like aggregate types
struct agg_float { float a; }; struct agg_float { float a; };
struct agg_float pass_agg_float(struct agg_float arg) { return arg; } struct agg_float pass_agg_float(struct agg_float arg) { return arg; }
// HARD-FLOAT-LABEL: define{{.*}} void @pass_agg_float(%struct.agg_float* noalias sret(%struct.agg_float) align 4 %{{.*}}, float %{{.*}}) // HARD-FLOAT-LABEL: define{{.*}} void @pass_agg_float(%struct.agg_float* noalias sret(%struct.agg_float) align 4 %{{.*}}, float %{{.*}})
// SOFT-FLOAT-LABEL: define{{.*}} void @pass_agg_float(%struct.agg_float* noalias sret(%struct.agg_float) align 4 %{{.*}}, i32 %{{.*}}) // SOFT-FLOAT-LABEL: define{{.*}} void @pass_agg_float(%struct.agg_float* noalias sret(%struct.agg_float) align 4 %{{.*}}, i32 noext %{{.*}})
struct agg_double { double a; }; struct agg_double { double a; };
struct agg_double pass_agg_double(struct agg_double arg) { return arg; } struct agg_double pass_agg_double(struct agg_double arg) { return arg; }
// HARD-FLOAT-LABEL: define{{.*}} void @pass_agg_double(%struct.agg_double* noalias sret(%struct.agg_double) align 8 %{{.*}}, double %{{.*}}) // HARD-FLOAT-LABEL: define{{.*}} void @pass_agg_double(%struct.agg_double* noalias sret(%struct.agg_double) align 8 %{{.*}}, double %{{.*}})
// SOFT-FLOAT-LABEL: define{{.*}} void @pass_agg_double(%struct.agg_double* noalias sret(%struct.agg_double) align 8 %{{.*}}, i64 %{{.*}}) // SOFT-FLOAT-LABEL: define{{.*}} void @pass_agg_double(%struct.agg_double* noalias sret(%struct.agg_double) align 8 %{{.*}}, i64 %{{.*}})
struct agg_longdouble { long double a; }; struct agg_longdouble { long double a; };
struct agg_longdouble pass_agg_longdouble(struct agg_longdouble arg) { return arg; } struct agg_longdouble pass_agg_longdouble(struct agg_longdouble arg) { return arg; }
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// CHECK-LABEL: define{{.*}} void @pass_agg_nofloat1(%struct.agg_nofloat1* noalias sret(%struct.agg_nofloat1) align 4 %{{.*}}, i64 %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_agg_nofloat1(%struct.agg_nofloat1* noalias sret(%struct.agg_nofloat1) align 4 %{{.*}}, i64 %{{.*}})
struct agg_nofloat2 { float a; int b; }; struct agg_nofloat2 { float a; int b; };
struct agg_nofloat2 pass_agg_nofloat2(struct agg_nofloat2 arg) { return arg; } struct agg_nofloat2 pass_agg_nofloat2(struct agg_nofloat2 arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @pass_agg_nofloat2(%struct.agg_nofloat2* noalias sret(%struct.agg_nofloat2) align 4 %{{.*}}, i64 %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_agg_nofloat2(%struct.agg_nofloat2* noalias sret(%struct.agg_nofloat2) align 4 %{{.*}}, i64 %{{.*}})
struct agg_nofloat3 { float a; int : 0; }; struct agg_nofloat3 { float a; int : 0; };
struct agg_nofloat3 pass_agg_nofloat3(struct agg_nofloat3 arg) { return arg; } struct agg_nofloat3 pass_agg_nofloat3(struct agg_nofloat3 arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @pass_agg_nofloat3(%struct.agg_nofloat3* noalias sret(%struct.agg_nofloat3) align 4 %{{.*}}, i32 %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_agg_nofloat3(%struct.agg_nofloat3* noalias sret(%struct.agg_nofloat3) align 4 %{{.*}}, i32 noext %{{.*}})
// Union types likewise are *not* float-like aggregate types // Union types likewise are *not* float-like aggregate types
union union_float { float a; }; union union_float { float a; };
union union_float pass_union_float(union union_float arg) { return arg; } union union_float pass_union_float(union union_float arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @pass_union_float(%union.union_float* noalias sret(%union.union_float) align 4 %{{.*}}, i32 %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_union_float(%union.union_float* noalias sret(%union.union_float) align 4 %{{.*}}, i32 noext %{{.*}})
union union_double { double a; }; union union_double { double a; };
union union_double pass_union_double(union union_double arg) { return arg; } union union_double pass_union_double(union union_double arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @pass_union_double(%union.union_double* noalias sret(%union.union_double) align 8 %{{.*}}, i64 %{{.*}}) // CHECK-LABEL: define{{.*}} void @pass_union_double(%union.union_double* noalias sret(%union.union_double) align 8 %{{.*}}, i64 %{{.*}})
// Accessing variable argument lists // Accessing variable argument lists
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clang/test/CodeGen/SystemZ/systemz-abi.cpp

// RUN: %clang_cc1 -triple s390x-linux-gnu -emit-llvm -x c++ -o - %s | FileCheck %s // RUN: %clang_cc1 -triple s390x-linux-gnu -emit-llvm -x c++ -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple s390x-linux-gnu -emit-llvm -x c++ -o - %s -mfloat-abi soft \ // RUN: %clang_cc1 -triple s390x-linux-gnu -emit-llvm -x c++ -o - %s -mfloat-abi soft \
// RUN: | FileCheck %s --check-prefix=SOFT-FLOAT // RUN: | FileCheck %s --check-prefix=SOFT-FLOAT
// Verify that class types are also recognized as float-like aggregate types // Verify that class types are also recognized as float-like aggregate types
class agg_float_class { float a; }; class agg_float_class { float a; };
class agg_float_class pass_agg_float_class(class agg_float_class arg) { return arg; } class agg_float_class pass_agg_float_class(class agg_float_class arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @_Z20pass_agg_float_class15agg_float_class(%class.agg_float_class* noalias sret(%class.agg_float_class) align 4 %{{.*}}, float %{{.*}}) // CHECK-LABEL: define{{.*}} void @_Z20pass_agg_float_class15agg_float_class(%class.agg_float_class* noalias sret(%class.agg_float_class) align 4 %{{.*}}, float %{{.*}})
// SOFT-FLOAT-LABEL: define{{.*}} void @_Z20pass_agg_float_class15agg_float_class(%class.agg_float_class* noalias sret(%class.agg_float_class) align 4 %{{.*}}, i32 %{{.*}}) // SOFT-FLOAT-LABEL: define{{.*}} void @_Z20pass_agg_float_class15agg_float_class(%class.agg_float_class* noalias sret(%class.agg_float_class) align 4 %{{.*}}, i32 noext %{{.*}})
class agg_double_class { double a; }; class agg_double_class { double a; };
class agg_double_class pass_agg_double_class(class agg_double_class arg) { return arg; } class agg_double_class pass_agg_double_class(class agg_double_class arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @_Z21pass_agg_double_class16agg_double_class(%class.agg_double_class* noalias sret(%class.agg_double_class) align 8 %{{.*}}, double %{{.*}}) // CHECK-LABEL: define{{.*}} void @_Z21pass_agg_double_class16agg_double_class(%class.agg_double_class* noalias sret(%class.agg_double_class) align 8 %{{.*}}, double %{{.*}})
// SOFT-FLOAT-LABEL: define{{.*}} void @_Z21pass_agg_double_class16agg_double_class(%class.agg_double_class* noalias sret(%class.agg_double_class) align 8 %{{.*}}, i64 %{{.*}}) // SOFT-FLOAT-LABEL: define{{.*}} void @_Z21pass_agg_double_class16agg_double_class(%class.agg_double_class* noalias sret(%class.agg_double_class) align 8 %{{.*}}, i64 %{{.*}})
// For compatibility with GCC, this structure is passed in an FPR in C++, // For compatibility with GCC, this structure is passed in an FPR in C++,
// but passed in a GPR in C (checked in systemz-abi.c). // but passed in a GPR in C (checked in systemz-abi.c).
struct agg_float_cpp { float a; int : 0; }; struct agg_float_cpp { float a; int : 0; };
struct agg_float_cpp pass_agg_float_cpp(struct agg_float_cpp arg) { return arg; } struct agg_float_cpp pass_agg_float_cpp(struct agg_float_cpp arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @_Z18pass_agg_float_cpp13agg_float_cpp(%struct.agg_float_cpp* noalias sret(%struct.agg_float_cpp) align 4 %{{.*}}, float %{{.*}}) // CHECK-LABEL: define{{.*}} void @_Z18pass_agg_float_cpp13agg_float_cpp(%struct.agg_float_cpp* noalias sret(%struct.agg_float_cpp) align 4 %{{.*}}, float %{{.*}})
// SOFT-FLOAT-LABEL: define{{.*}} void @_Z18pass_agg_float_cpp13agg_float_cpp(%struct.agg_float_cpp* noalias sret(%struct.agg_float_cpp) align 4 %{{.*}}, i32 %{{.*}}) // SOFT-FLOAT-LABEL: define{{.*}} void @_Z18pass_agg_float_cpp13agg_float_cpp(%struct.agg_float_cpp* noalias sret(%struct.agg_float_cpp) align 4 %{{.*}}, i32 noext %{{.*}})
// A field member of empty class type in C++ makes the record nonhomogeneous, // A field member of empty class type in C++ makes the record nonhomogeneous,
// unless it is marked as [[no_unique_address]]. This does not apply to arrays. // unless it is marked as [[no_unique_address]]. This does not apply to arrays.
struct empty { }; struct empty { };
struct agg_nofloat_empty { float a; empty dummy; }; struct agg_nofloat_empty { float a; empty dummy; };
struct agg_nofloat_empty pass_agg_nofloat_empty(struct agg_nofloat_empty arg) { return arg; } struct agg_nofloat_empty pass_agg_nofloat_empty(struct agg_nofloat_empty arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @_Z22pass_agg_nofloat_empty17agg_nofloat_empty(%struct.agg_nofloat_empty* noalias sret(%struct.agg_nofloat_empty) align 4 %{{.*}}, i64 %{{.*}}) // CHECK-LABEL: define{{.*}} void @_Z22pass_agg_nofloat_empty17agg_nofloat_empty(%struct.agg_nofloat_empty* noalias sret(%struct.agg_nofloat_empty) align 4 %{{.*}}, i64 %{{.*}})
// SOFT-FLOAT-LABEL: define{{.*}} void @_Z22pass_agg_nofloat_empty17agg_nofloat_empty(%struct.agg_nofloat_empty* noalias sret(%struct.agg_nofloat_empty) align 4 %{{.*}}, i64 %{{.*}}) // SOFT-FLOAT-LABEL: define{{.*}} void @_Z22pass_agg_nofloat_empty17agg_nofloat_empty(%struct.agg_nofloat_empty* noalias sret(%struct.agg_nofloat_empty) align 4 %{{.*}}, i64 %{{.*}})
struct agg_float_empty { float a; [[no_unique_address]] empty dummy; }; struct agg_float_empty { float a; [[no_unique_address]] empty dummy; };
struct agg_float_empty pass_agg_float_empty(struct agg_float_empty arg) { return arg; } struct agg_float_empty pass_agg_float_empty(struct agg_float_empty arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @_Z20pass_agg_float_empty15agg_float_empty(%struct.agg_float_empty* noalias sret(%struct.agg_float_empty) align 4 %{{.*}}, float %{{.*}}) // CHECK-LABEL: define{{.*}} void @_Z20pass_agg_float_empty15agg_float_empty(%struct.agg_float_empty* noalias sret(%struct.agg_float_empty) align 4 %{{.*}}, float %{{.*}})
// SOFT-FLOAT-LABEL: define{{.*}} void @_Z20pass_agg_float_empty15agg_float_empty(%struct.agg_float_empty* noalias sret(%struct.agg_float_empty) align 4 %{{.*}}, i32 %{{.*}}) // SOFT-FLOAT-LABEL: define{{.*}} void @_Z20pass_agg_float_empty15agg_float_empty(%struct.agg_float_empty* noalias sret(%struct.agg_float_empty) align 4 %{{.*}}, i32 noext %{{.*}})
struct agg_nofloat_emptyarray { float a; [[no_unique_address]] empty dummy[3]; }; struct agg_nofloat_emptyarray { float a; [[no_unique_address]] empty dummy[3]; };
struct agg_nofloat_emptyarray pass_agg_nofloat_emptyarray(struct agg_nofloat_emptyarray arg) { return arg; } struct agg_nofloat_emptyarray pass_agg_nofloat_emptyarray(struct agg_nofloat_emptyarray arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @_Z27pass_agg_nofloat_emptyarray22agg_nofloat_emptyarray(%struct.agg_nofloat_emptyarray* noalias sret(%struct.agg_nofloat_emptyarray) align 4 %{{.*}}, i64 %{{.*}}) // CHECK-LABEL: define{{.*}} void @_Z27pass_agg_nofloat_emptyarray22agg_nofloat_emptyarray(%struct.agg_nofloat_emptyarray* noalias sret(%struct.agg_nofloat_emptyarray) align 4 %{{.*}}, i64 %{{.*}})
// SOFT-FLOAT-LABEL: define{{.*}} void @_Z27pass_agg_nofloat_emptyarray22agg_nofloat_emptyarray(%struct.agg_nofloat_emptyarray* noalias sret(%struct.agg_nofloat_emptyarray) align 4 %{{.*}}, i64 %{{.*}}) // SOFT-FLOAT-LABEL: define{{.*}} void @_Z27pass_agg_nofloat_emptyarray22agg_nofloat_emptyarray(%struct.agg_nofloat_emptyarray* noalias sret(%struct.agg_nofloat_emptyarray) align 4 %{{.*}}, i64 %{{.*}})
// And likewise for members of base classes. // And likewise for members of base classes.
struct noemptybase { empty dummy; }; struct noemptybase { empty dummy; };
struct agg_nofloat_emptybase : noemptybase { float a; }; struct agg_nofloat_emptybase : noemptybase { float a; };
struct agg_nofloat_emptybase pass_agg_nofloat_emptybase(struct agg_nofloat_emptybase arg) { return arg; } struct agg_nofloat_emptybase pass_agg_nofloat_emptybase(struct agg_nofloat_emptybase arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @_Z26pass_agg_nofloat_emptybase21agg_nofloat_emptybase(%struct.agg_nofloat_emptybase* noalias sret(%struct.agg_nofloat_emptybase) align 4 %{{.*}}, i64 %{{.*}}) // CHECK-LABEL: define{{.*}} void @_Z26pass_agg_nofloat_emptybase21agg_nofloat_emptybase(%struct.agg_nofloat_emptybase* noalias sret(%struct.agg_nofloat_emptybase) align 4 %{{.*}}, i64 %{{.*}})
// SOFT-FLOAT-LABEL: define{{.*}} void @_Z26pass_agg_nofloat_emptybase21agg_nofloat_emptybase(%struct.agg_nofloat_emptybase* noalias sret(%struct.agg_nofloat_emptybase) align 4 %{{.*}}, i64 %{{.*}}) // SOFT-FLOAT-LABEL: define{{.*}} void @_Z26pass_agg_nofloat_emptybase21agg_nofloat_emptybase(%struct.agg_nofloat_emptybase* noalias sret(%struct.agg_nofloat_emptybase) align 4 %{{.*}}, i64 %{{.*}})
struct emptybase { [[no_unique_address]] empty dummy; }; struct emptybase { [[no_unique_address]] empty dummy; };
struct agg_float_emptybase : emptybase { float a; }; struct agg_float_emptybase : emptybase { float a; };
struct agg_float_emptybase pass_agg_float_emptybase(struct agg_float_emptybase arg) { return arg; } struct agg_float_emptybase pass_agg_float_emptybase(struct agg_float_emptybase arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @_Z24pass_agg_float_emptybase19agg_float_emptybase(%struct.agg_float_emptybase* noalias sret(%struct.agg_float_emptybase) align 4 %{{.*}}, float %{{.*}}) // CHECK-LABEL: define{{.*}} void @_Z24pass_agg_float_emptybase19agg_float_emptybase(%struct.agg_float_emptybase* noalias sret(%struct.agg_float_emptybase) align 4 %{{.*}}, float %{{.*}})
// SOFT-FLOAT-LABEL: define{{.*}} void @_Z24pass_agg_float_emptybase19agg_float_emptybase(%struct.agg_float_emptybase* noalias sret(%struct.agg_float_emptybase) align 4 %{{.*}}, i32 %{{.*}}) // SOFT-FLOAT-LABEL: define{{.*}} void @_Z24pass_agg_float_emptybase19agg_float_emptybase(%struct.agg_float_emptybase* noalias sret(%struct.agg_float_emptybase) align 4 %{{.*}}, i32 noext %{{.*}})
struct noemptybasearray { [[no_unique_address]] empty dummy[3]; }; struct noemptybasearray { [[no_unique_address]] empty dummy[3]; };
struct agg_nofloat_emptybasearray : noemptybasearray { float a; }; struct agg_nofloat_emptybasearray : noemptybasearray { float a; };
struct agg_nofloat_emptybasearray pass_agg_nofloat_emptybasearray(struct agg_nofloat_emptybasearray arg) { return arg; } struct agg_nofloat_emptybasearray pass_agg_nofloat_emptybasearray(struct agg_nofloat_emptybasearray arg) { return arg; }
// CHECK-LABEL: define{{.*}} void @_Z31pass_agg_nofloat_emptybasearray26agg_nofloat_emptybasearray(%struct.agg_nofloat_emptybasearray* noalias sret(%struct.agg_nofloat_emptybasearray) align 4 %{{.*}}, i64 %{{.*}}) // CHECK-LABEL: define{{.*}} void @_Z31pass_agg_nofloat_emptybasearray26agg_nofloat_emptybasearray(%struct.agg_nofloat_emptybasearray* noalias sret(%struct.agg_nofloat_emptybasearray) align 4 %{{.*}}, i64 %{{.*}})
// SOFT-FLOAT-LABEL: define{{.*}} void @_Z31pass_agg_nofloat_emptybasearray26agg_nofloat_emptybasearray(%struct.agg_nofloat_emptybasearray* noalias sret(%struct.agg_nofloat_emptybasearray) align 4 %{{.*}}, i64 %{{.*}}) // SOFT-FLOAT-LABEL: define{{.*}} void @_Z31pass_agg_nofloat_emptybasearray26agg_nofloat_emptybasearray(%struct.agg_nofloat_emptybasearray* noalias sret(%struct.agg_nofloat_emptybasearray) align 4 %{{.*}}, i64 %{{.*}})

llvm/docs/LangRef.rst

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,052 Lines • ▼ Show 20 Lines.. code-block:: llvm
declare i32 @printf(i8* noalias nocapture, ...) declare i32 @printf(i8* noalias nocapture, ...)
declare i32 @atoi(i8 zeroext) declare i32 @atoi(i8 zeroext)
declare signext i8 @returns_signed_char() declare signext i8 @returns_signed_char()
Note that any attributes for the function result (``nounwind``, Note that any attributes for the function result (``nounwind``,
``readonly``) come immediately after the argument list. ``readonly``) come immediately after the argument list.
For an integer argument, it is mandatory to specify either zeroext, signext
or noext. Although this is not significant for all targets, some depend on
this for correctness entirely. For example, the SystemZ ABI dictates that any
passed integer that is 32 bits or less is either sign or zero extended to 64
bits by the caller.
Currently, only the following parameter attributes are defined: Currently, only the following parameter attributes are defined:
``zeroext`` ``zeroext``
This indicates to the code generator that the parameter or return This indicates to the code generator that the parameter or return
value should be zero-extended to the extent required by the target's value should be zero-extended to the extent required by the target's
ABI by the caller (for a parameter) or the callee (for a return value). ABI by the caller (for a parameter) or the callee (for a return value).
``signext`` ``signext``
This indicates to the code generator that the parameter or return This indicates to the code generator that the parameter or return
value should be sign-extended to the extent required by the target's value should be sign-extended to the extent required by the target's
ABI (which is usually 32-bits) by the caller (for a parameter) or ABI (which is usually 32-bits) by the caller (for a parameter) or
the callee (for a return value). the callee (for a return value).
``noext`` This indicates to the code generator that the parameter or return
value contains a struct in a register, and therefore does not need to be
sign or zero extended.
``inreg`` ``inreg``
This indicates that this parameter or return value should be treated This indicates that this parameter or return value should be treated
in a special target-dependent fashion while emitting code for in a special target-dependent fashion while emitting code for
a function call or return (usually, by putting it in a register as a function call or return (usually, by putting it in a register as
opposed to memory, though some targets use it to distinguish between opposed to memory, though some targets use it to distinguish between
two different kinds of registers). Use of this attribute is two different kinds of registers). Use of this attribute is
target-specific. target-specific.
``byval(<ty>)`` ``byval(<ty>)``
▲ Show 20 Lines • Show All 22,536 Lines • Show Last 20 Lines

llvm/include/llvm/AsmParser/LLToken.h

Show First 20 Lines • Show All 200 Lines • ▼ Show 20 Linesenum Kind {
kw_naked, kw_naked,
kw_nest, kw_nest,
kw_noalias, kw_noalias,
kw_noundef, kw_noundef,
kw_nobuiltin, kw_nobuiltin,
kw_nocallback, kw_nocallback,
kw_nocapture, kw_nocapture,
kw_noduplicate, kw_noduplicate,
kw_noext,
kw_nofree, kw_nofree,
kw_noimplicitfloat, kw_noimplicitfloat,
kw_noinline, kw_noinline,
kw_norecurse, kw_norecurse,
kw_nonlazybind, kw_nonlazybind,
kw_nomerge, kw_nomerge,
kw_nonnull, kw_nonnull,
kw_noprofile, kw_noprofile,
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llvm/include/llvm/Bitcode/LLVMBitCodes.h

Show First 20 Lines • Show All 666 Lines • ▼ Show 20 Linesenum AttributeKindCodes {
ATTR_KIND_NO_CALLBACK = 71, ATTR_KIND_NO_CALLBACK = 71,
ATTR_KIND_HOT = 72, ATTR_KIND_HOT = 72,
ATTR_KIND_NO_PROFILE = 73, ATTR_KIND_NO_PROFILE = 73,
ATTR_KIND_VSCALE_RANGE = 74, ATTR_KIND_VSCALE_RANGE = 74,
ATTR_KIND_SWIFT_ASYNC = 75, ATTR_KIND_SWIFT_ASYNC = 75,
ATTR_KIND_NO_SANITIZE_COVERAGE = 76, ATTR_KIND_NO_SANITIZE_COVERAGE = 76,
ATTR_KIND_ELEMENTTYPE = 77, ATTR_KIND_ELEMENTTYPE = 77,
ATTR_KIND_DISABLE_SANITIZER_INSTRUMENTATION = 78, ATTR_KIND_DISABLE_SANITIZER_INSTRUMENTATION = 78,
ATTR_KIND_NO_EXT = 79,
}; };
enum ComdatSelectionKindCodes { enum ComdatSelectionKindCodes {
COMDAT_SELECTION_KIND_ANY = 1, COMDAT_SELECTION_KIND_ANY = 1,
COMDAT_SELECTION_KIND_EXACT_MATCH = 2, COMDAT_SELECTION_KIND_EXACT_MATCH = 2,
COMDAT_SELECTION_KIND_LARGEST = 3, COMDAT_SELECTION_KIND_LARGEST = 3,
COMDAT_SELECTION_KIND_NO_DUPLICATES = 4, COMDAT_SELECTION_KIND_NO_DUPLICATES = 4,
COMDAT_SELECTION_KIND_SAME_SIZE = 5, COMDAT_SELECTION_KIND_SAME_SIZE = 5,
Show All 14 Lines

llvm/include/llvm/CodeGen/TargetCallingConv.h

Show All 22 Lines
namespace llvm { namespace llvm {
namespace ISD { namespace ISD {
struct ArgFlagsTy { struct ArgFlagsTy {
private: private:
unsigned IsZExt : 1; ///< Zero extended unsigned IsZExt : 1; ///< Zero extended
unsigned IsSExt : 1; ///< Sign extended unsigned IsSExt : 1; ///< Sign extended
unsigned IsNoExt : 1; ///< No extension (struct in reg)
unsigned IsInReg : 1; ///< Passed in register unsigned IsInReg : 1; ///< Passed in register
unsigned IsSRet : 1; ///< Hidden struct-ret ptr unsigned IsSRet : 1; ///< Hidden struct-ret ptr
unsigned IsByVal : 1; ///< Struct passed by value unsigned IsByVal : 1; ///< Struct passed by value
unsigned IsByRef : 1; ///< Passed in memory unsigned IsByRef : 1; ///< Passed in memory
unsigned IsNest : 1; ///< Nested fn static chain unsigned IsNest : 1; ///< Nested fn static chain
unsigned IsReturned : 1; ///< Always returned unsigned IsReturned : 1; ///< Always returned
unsigned IsSplit : 1; unsigned IsSplit : 1;
unsigned IsInAlloca : 1; ///< Passed with inalloca unsigned IsInAlloca : 1; ///< Passed with inalloca
Show All 15 Lines private:
unsigned IsPointer : 1; unsigned IsPointer : 1;
unsigned ByValOrByRefSize; ///< Byval or byref struct size unsigned ByValOrByRefSize; ///< Byval or byref struct size
unsigned PointerAddrSpace; ///< Address space of pointer argument unsigned PointerAddrSpace; ///< Address space of pointer argument
public: public:
ArgFlagsTy() ArgFlagsTy()
: IsZExt(0), IsSExt(0), IsInReg(0), IsSRet(0), IsByVal(0), IsByRef(0), : IsZExt(0), IsSExt(0), IsNoExt(0), IsInReg(0), IsSRet(0), IsByVal(0),
IsNest(0), IsReturned(0), IsSplit(0), IsInAlloca(0), IsByRef(0), IsNest(0), IsReturned(0), IsSplit(0), IsInAlloca(0),
IsPreallocated(0), IsSplitEnd(0), IsSwiftSelf(0), IsSwiftAsync(0), IsPreallocated(0), IsSplitEnd(0), IsSwiftSelf(0), IsSwiftAsync(0),
IsSwiftError(0), IsCFGuardTarget(0), IsHva(0), IsHvaStart(0), IsSwiftError(0), IsCFGuardTarget(0), IsHva(0), IsHvaStart(0),
IsSecArgPass(0), MemAlign(0), OrigAlign(0), IsSecArgPass(0), MemAlign(0), OrigAlign(0),
IsInConsecutiveRegsLast(0), IsInConsecutiveRegs(0), IsInConsecutiveRegsLast(0), IsInConsecutiveRegs(0),
IsCopyElisionCandidate(0), IsPointer(0), ByValOrByRefSize(0), IsCopyElisionCandidate(0), IsPointer(0), ByValOrByRefSize(0),
PointerAddrSpace(0) { PointerAddrSpace(0) {
static_assert(sizeof(*this) == 3 * sizeof(unsigned), "flags are too big"); static_assert(sizeof(*this) == 4 * sizeof(unsigned), "flags are too big");
} }
bool isZExt() const { return IsZExt; } bool isZExt() const { return IsZExt; }
void setZExt() { IsZExt = 1; } void setZExt() { IsZExt = 1; }
bool isSExt() const { return IsSExt; } bool isSExt() const { return IsSExt; }
void setSExt() { IsSExt = 1; } void setSExt() { IsSExt = 1; }
bool isNoExt() const { return IsNoExt; }
void setNoExt() { IsNoExt = 1; }
bool isInReg() const { return IsInReg; } bool isInReg() const { return IsInReg; }
void setInReg() { IsInReg = 1; } void setInReg() { IsInReg = 1; }
bool isSRet() const { return IsSRet; } bool isSRet() const { return IsSRet; }
void setSRet() { IsSRet = 1; } void setSRet() { IsSRet = 1; }
bool isByVal() const { return IsByVal; } bool isByVal() const { return IsByVal; }
void setByVal() { IsByVal = 1; } void setByVal() { IsByVal = 1; }
▲ Show 20 Lines • Show All 176 Lines • Show Last 20 Lines

llvm/include/llvm/CodeGen/TargetLowering.h

Show First 20 Lines • Show All 272 Lines • ▼ Show 20 Linespublic:
class ArgListEntry { class ArgListEntry {
public: public:
Value *Val = nullptr; Value *Val = nullptr;
SDValue Node = SDValue(); SDValue Node = SDValue();
Type *Ty = nullptr; Type *Ty = nullptr;
bool IsSExt : 1; bool IsSExt : 1;
bool IsZExt : 1; bool IsZExt : 1;
bool IsNoExt : 1;
bool IsInReg : 1; bool IsInReg : 1;
bool IsSRet : 1; bool IsSRet : 1;
bool IsNest : 1; bool IsNest : 1;
bool IsByVal : 1; bool IsByVal : 1;
bool IsByRef : 1; bool IsByRef : 1;
bool IsInAlloca : 1; bool IsInAlloca : 1;
bool IsPreallocated : 1; bool IsPreallocated : 1;
bool IsReturned : 1; bool IsReturned : 1;
bool IsSwiftSelf : 1; bool IsSwiftSelf : 1;
bool IsSwiftAsync : 1; bool IsSwiftAsync : 1;
bool IsSwiftError : 1; bool IsSwiftError : 1;
bool IsCFGuardTarget : 1; bool IsCFGuardTarget : 1;
MaybeAlign Alignment = None; MaybeAlign Alignment = None;
Type *IndirectType = nullptr; Type *IndirectType = nullptr;
ArgListEntry() ArgListEntry()
: IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false), : IsSExt(false), IsZExt(false), IsNoExt(false), IsInReg(false),
IsNest(false), IsByVal(false), IsByRef(false), IsInAlloca(false), IsSRet(false), IsNest(false), IsByVal(false), IsByRef(false),
IsPreallocated(false), IsReturned(false), IsSwiftSelf(false), IsInAlloca(false), IsPreallocated(false), IsReturned(false),
IsSwiftAsync(false), IsSwiftError(false), IsCFGuardTarget(false) {} IsSwiftSelf(false), IsSwiftAsync(false), IsSwiftError(false),
IsCFGuardTarget(false) {}
void setAttributes(const CallBase *Call, unsigned ArgIdx); void setAttributes(const CallBase *Call, unsigned ArgIdx);
}; };
using ArgListTy = std::vector<ArgListEntry>; using ArgListTy = std::vector<ArgListEntry>;
virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC, virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
ArgListTy &Args) const {}; ArgListTy &Args) const {};
▲ Show 20 Lines • Show All 4,404 Lines • Show Last 20 Lines

llvm/include/llvm/IR/Attributes.td

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
def NoCallback : EnumAttr<"nocallback", [FnAttr]>; def NoCallback : EnumAttr<"nocallback", [FnAttr]>;
/// Function creates no aliases of pointer. /// Function creates no aliases of pointer.
def NoCapture : EnumAttr<"nocapture", [ParamAttr]>; def NoCapture : EnumAttr<"nocapture", [ParamAttr]>;
/// Call cannot be duplicated. /// Call cannot be duplicated.
def NoDuplicate : EnumAttr<"noduplicate", [FnAttr]>; def NoDuplicate : EnumAttr<"noduplicate", [FnAttr]>;
/// No extension needed before/after call (struct in reg).
rnkUnsubmitted
Done
ReplyInline Actions

This is not SystemZ-specific, so instead of "struct in reg" I suggest "high bits are undefined". That should be accurate when this attribute is used on any target.

rnk: This is not SystemZ-specific, so instead of "struct in reg" I suggest "high bits are undefined".
def NoExt : EnumAttr<"noext", [ParamAttr, RetAttr]>;
/// Function does not deallocate memory. /// Function does not deallocate memory.
def NoFree : EnumAttr<"nofree", [FnAttr, ParamAttr]>; def NoFree : EnumAttr<"nofree", [FnAttr, ParamAttr]>;
/// Disable implicit floating point insts. /// Disable implicit floating point insts.
def NoImplicitFloat : EnumAttr<"noimplicitfloat", [FnAttr]>; def NoImplicitFloat : EnumAttr<"noimplicitfloat", [FnAttr]>;
/// inline=never. /// inline=never.
def NoInline : EnumAttr<"noinline", [FnAttr]>; def NoInline : EnumAttr<"noinline", [FnAttr]>;
▲ Show 20 Lines • Show All 201 Lines • Show Last 20 Lines

llvm/lib/AsmParser/LLLexer.cpp

Show First 20 Lines • Show All 652 Lines • ▼ Show 20 Lines#define KEYWORD(STR) \
KEYWORD(minsize); KEYWORD(minsize);
KEYWORD(naked); KEYWORD(naked);
KEYWORD(nest); KEYWORD(nest);
KEYWORD(noalias); KEYWORD(noalias);
KEYWORD(nobuiltin); KEYWORD(nobuiltin);
KEYWORD(nocallback); KEYWORD(nocallback);
KEYWORD(nocapture); KEYWORD(nocapture);
KEYWORD(noduplicate); KEYWORD(noduplicate);
KEYWORD(noext);
KEYWORD(nofree); KEYWORD(nofree);
KEYWORD(noimplicitfloat); KEYWORD(noimplicitfloat);
KEYWORD(noinline); KEYWORD(noinline);
KEYWORD(norecurse); KEYWORD(norecurse);
KEYWORD(nonlazybind); KEYWORD(nonlazybind);
KEYWORD(nomerge); KEYWORD(nomerge);
KEYWORD(nonnull); KEYWORD(nonnull);
KEYWORD(noprofile); KEYWORD(noprofile);
▲ Show 20 Lines • Show All 523 Lines • Show Last 20 Lines

llvm/lib/Bitcode/Reader/BitcodeReader.cpp

Show First 20 Lines • Show All 1,519 Lines • ▼ Show 20 Linesstatic Attribute::AttrKind getAttrFromCode(uint64_t Code) {
case bitc::ATTR_KIND_PREALLOCATED: case bitc::ATTR_KIND_PREALLOCATED:
return Attribute::Preallocated; return Attribute::Preallocated;
case bitc::ATTR_KIND_NOUNDEF: case bitc::ATTR_KIND_NOUNDEF:
return Attribute::NoUndef; return Attribute::NoUndef;
case bitc::ATTR_KIND_BYREF: case bitc::ATTR_KIND_BYREF:
return Attribute::ByRef; return Attribute::ByRef;
case bitc::ATTR_KIND_MUSTPROGRESS: case bitc::ATTR_KIND_MUSTPROGRESS:
return Attribute::MustProgress; return Attribute::MustProgress;
case bitc::ATTR_KIND_NO_EXT:
return Attribute::NoExt;
case bitc::ATTR_KIND_HOT: case bitc::ATTR_KIND_HOT:
return Attribute::Hot; return Attribute::Hot;
} }
} }
Error BitcodeReader::parseAlignmentValue(uint64_t Exponent, Error BitcodeReader::parseAlignmentValue(uint64_t Exponent,
MaybeAlign &Alignment) { MaybeAlign &Alignment) {
// Note: Alignment in bitcode files is incremented by 1, so that zero // Note: Alignment in bitcode files is incremented by 1, so that zero
▲ Show 20 Lines • Show All 5,540 Lines • Show Last 20 Lines

llvm/lib/Bitcode/Writer/BitcodeWriter.cpp

Show First 20 Lines • Show All 758 Lines • ▼ Show 20 Linesstatic uint64_t getAttrKindEncoding(Attribute::AttrKind Kind) {
case Attribute::Preallocated: case Attribute::Preallocated:
return bitc::ATTR_KIND_PREALLOCATED; return bitc::ATTR_KIND_PREALLOCATED;
case Attribute::NoUndef: case Attribute::NoUndef:
return bitc::ATTR_KIND_NOUNDEF; return bitc::ATTR_KIND_NOUNDEF;
case Attribute::ByRef: case Attribute::ByRef:
return bitc::ATTR_KIND_BYREF; return bitc::ATTR_KIND_BYREF;
case Attribute::MustProgress: case Attribute::MustProgress:
return bitc::ATTR_KIND_MUSTPROGRESS; return bitc::ATTR_KIND_MUSTPROGRESS;
case Attribute::NoExt:
return bitc::ATTR_KIND_NO_EXT;
case Attribute::EndAttrKinds: case Attribute::EndAttrKinds:
llvm_unreachable("Can not encode end-attribute kinds marker."); llvm_unreachable("Can not encode end-attribute kinds marker.");
case Attribute::None: case Attribute::None:
llvm_unreachable("Can not encode none-attribute."); llvm_unreachable("Can not encode none-attribute.");
case Attribute::EmptyKey: case Attribute::EmptyKey:
case Attribute::TombstoneKey: case Attribute::TombstoneKey:
llvm_unreachable("Trying to encode EmptyKey/TombstoneKey"); llvm_unreachable("Trying to encode EmptyKey/TombstoneKey");
} }
▲ Show 20 Lines • Show All 4,198 Lines • Show Last 20 Lines

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 9,688 Lines • ▼ Show 20 Lines for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
Flags.setPointer(); Flags.setPointer();
Flags.setPointerAddrSpace( Flags.setPointerAddrSpace(
cast<PointerType>(Args[i].Ty)->getAddressSpace()); cast<PointerType>(Args[i].Ty)->getAddressSpace());
} }
if (Args[i].IsZExt) if (Args[i].IsZExt)
Flags.setZExt(); Flags.setZExt();
if (Args[i].IsSExt) if (Args[i].IsSExt)
Flags.setSExt(); Flags.setSExt();
if (Args[i].IsNoExt)
Flags.setNoExt();
if (Args[i].IsInReg) { if (Args[i].IsInReg) {
// If we are using vectorcall calling convention, a structure that is // If we are using vectorcall calling convention, a structure that is
// passed InReg - is surely an HVA // passed InReg - is surely an HVA
if (CLI.CallConv == CallingConv::X86_VectorCall && if (CLI.CallConv == CallingConv::X86_VectorCall &&
isa<StructType>(FinalType)) { isa<StructType>(FinalType)) {
// The first value of a structure is marked // The first value of a structure is marked
if (0 == Value) if (0 == Value)
Flags.setHvaStart(); Flags.setHvaStart();
▲ Show 20 Lines • Show All 1,558 Lines • Show Last 20 Lines

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 103 Lines • ▼ Show 20 Lines
} }
/// Set CallLoweringInfo attribute flags based on a call instruction /// Set CallLoweringInfo attribute flags based on a call instruction
/// and called function attributes. /// and called function attributes.
void TargetLoweringBase::ArgListEntry::setAttributes(const CallBase *Call, void TargetLoweringBase::ArgListEntry::setAttributes(const CallBase *Call,
unsigned ArgIdx) { unsigned ArgIdx) {
IsSExt = Call->paramHasAttr(ArgIdx, Attribute::SExt); IsSExt = Call->paramHasAttr(ArgIdx, Attribute::SExt);
IsZExt = Call->paramHasAttr(ArgIdx, Attribute::ZExt); IsZExt = Call->paramHasAttr(ArgIdx, Attribute::ZExt);
IsNoExt = Call->paramHasAttr(ArgIdx, Attribute::NoExt);
IsInReg = Call->paramHasAttr(ArgIdx, Attribute::InReg); IsInReg = Call->paramHasAttr(ArgIdx, Attribute::InReg);
IsSRet = Call->paramHasAttr(ArgIdx, Attribute::StructRet); IsSRet = Call->paramHasAttr(ArgIdx, Attribute::StructRet);
IsNest = Call->paramHasAttr(ArgIdx, Attribute::Nest); IsNest = Call->paramHasAttr(ArgIdx, Attribute::Nest);
IsByVal = Call->paramHasAttr(ArgIdx, Attribute::ByVal); IsByVal = Call->paramHasAttr(ArgIdx, Attribute::ByVal);
IsPreallocated = Call->paramHasAttr(ArgIdx, Attribute::Preallocated); IsPreallocated = Call->paramHasAttr(ArgIdx, Attribute::Preallocated);
IsInAlloca = Call->paramHasAttr(ArgIdx, Attribute::InAlloca); IsInAlloca = Call->paramHasAttr(ArgIdx, Attribute::InAlloca);
IsReturned = Call->paramHasAttr(ArgIdx, Attribute::Returned); IsReturned = Call->paramHasAttr(ArgIdx, Attribute::Returned);
IsSwiftSelf = Call->paramHasAttr(ArgIdx, Attribute::SwiftSelf); IsSwiftSelf = Call->paramHasAttr(ArgIdx, Attribute::SwiftSelf);
▲ Show 20 Lines • Show All 8,843 Lines • Show Last 20 Lines

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show All 24 Lines
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/Support/KnownBits.h" #include "llvm/Support/KnownBits.h"
#include <cctype> #include <cctype>
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "systemz-lower" #define DEBUG_TYPE "systemz-lower"
static cl::opt<bool> VerifyIntArgExtensions(
"verify-int-arg-exts",
cl::desc("Verify that narrow int args are properly extended per the ABI."),
cl::Hidden);
static cl::opt<bool> DisableIntArgExtensions(
"no-arg-exts", cl::desc("Disable the default int args extensions."),
cl::Hidden);
namespace { namespace {
// Represents information about a comparison. // Represents information about a comparison.
struct Comparison { struct Comparison {
Comparison(SDValue Op0In, SDValue Op1In, SDValue ChainIn) Comparison(SDValue Op0In, SDValue Op1In, SDValue ChainIn)
: Op0(Op0In), Op1(Op1In), Chain(ChainIn), : Op0(Op0In), Op1(Op1In), Chain(ChainIn),
Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {} Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
// The operands to the comparison. // The operands to the comparison.
▲ Show 20 Lines • Show All 1,271 Lines • ▼ Show 20 Lines for (unsigned i = 0; i < Ins.size(); ++i)
VerifyVectorType(Ins[i].VT, Ins[i].ArgVT); VerifyVectorType(Ins[i].VT, Ins[i].ArgVT);
} }
static void VerifyVectorTypes(const SmallVectorImpl<ISD::OutputArg> &Outs) { static void VerifyVectorTypes(const SmallVectorImpl<ISD::OutputArg> &Outs) {
for (unsigned i = 0; i < Outs.size(); ++i) for (unsigned i = 0; i < Outs.size(); ++i)
VerifyVectorType(Outs[i].VT, Outs[i].ArgVT); VerifyVectorType(Outs[i].VT, Outs[i].ArgVT);
} }
// Verify that narrow integer args are extended to 64 bits as required by the
// ABI. An ingoing integer argument may contain a struct, in which case it
// should be marked with 'noext'.
static void VerifyIntegerArg(MVT VT, ISD::ArgFlagsTy Flags, bool IsRetVal) {
if (VT.isInteger()) {
assert((VT == MVT::i32 || VT.getSizeInBits() >= 64) &&
"Unexpected integer argument VT.");
assert((VT != MVT::i32 || (Flags.isSExt() || Flags.isZExt() ||
(!IsRetVal && Flags.isNoExt()))) &&
"Narrow integer argument must have a valid extension type!");
}
}
// Optionally either verify that all narrow integer arguments have an
// extension attribute, or add sign extension by default in case of no
// attribute.
static void CheckNarrowIntegerArgs(SmallVectorImpl<ISD::OutputArg> &Outs,
bool IsRetVal) {
// Verify that narrow integer args are extended as required by the ABI.
if (VerifyIntArgExtensions) {
for (unsigned i = 0; i < Outs.size(); ++i)
VerifyIntegerArg(Outs[i].VT, Outs[i].Flags, IsRetVal);
return;
}
if (DisableIntArgExtensions)
return;
// Add sign extension by default if no extension attribute has been
// given. FIXME: This should not really be handled this way, but is "better
// than nothing". Hopefully the above verification can become the default
// instead.
for (unsigned i = 0; i != Outs.size(); ++i)
if (Outs[i].VT == MVT::i32) {
ISD::ArgFlagsTy &ArgFlags = Outs[i].Flags;
if (!ArgFlags.isSExt() && !ArgFlags.isZExt() &&
(IsRetVal || !ArgFlags.isNoExt()))
ArgFlags.setSExt();
}
}
// Value is a value that has been passed to us in the location described by VA // Value is a value that has been passed to us in the location described by VA
// (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
// any loads onto Chain. // any loads onto Chain.
static SDValue convertLocVTToValVT(SelectionDAG &DAG, const SDLoc &DL, static SDValue convertLocVTToValVT(SelectionDAG &DAG, const SDLoc &DL,
CCValAssign &VA, SDValue Chain, CCValAssign &VA, SDValue Chain,
SDValue Value) { SDValue Value) {
// If the argument has been promoted from a smaller type, insert an // If the argument has been promoted from a smaller type, insert an
// assertion to capture this. // assertion to capture this.
▲ Show 20 Lines • Show All 297 Lines • ▼ Show 20 Lines if (Subtarget.isTargetXPLINK64())
IsTailCall = false; IsTailCall = false;
// Detect unsupported vector argument and return types. // Detect unsupported vector argument and return types.
if (Subtarget.hasVector()) { if (Subtarget.hasVector()) {
VerifyVectorTypes(Outs); VerifyVectorTypes(Outs);
VerifyVectorTypes(Ins); VerifyVectorTypes(Ins);
} }
// Integer args <=32 bits should have an extension attribute.
CheckNarrowIntegerArgs(Outs, false/*IsRetVal*/);
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  CheckNarrowIntegerArgs(Outs, false/*IsRetVal*/);
+  CheckNarrowIntegerArgs(Outs, false /*IsRetVal*/);
Lint: Pre-merge checks: clang-format: please reformat the code ``` - CheckNarrowIntegerArgs(Outs, false/*IsRetVal*/)…
// Analyze the operands of the call, assigning locations to each operand. // Analyze the operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs; SmallVector<CCValAssign, 16> ArgLocs;
SystemZCCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, Ctx); SystemZCCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, Ctx);
ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ); ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
// We don't support GuaranteedTailCallOpt, only automatically-detected // We don't support GuaranteedTailCallOpt, only automatically-detected
// sibling calls. // sibling calls.
if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs, Outs)) if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs, Outs))
▲ Show 20 Lines • Show All 213 Lines • ▼ Show 20 LinesSystemZTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<SDValue> &OutVals,
const SDLoc &DL, SelectionDAG &DAG) const { const SDLoc &DL, SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
// Detect unsupported vector return types. // Detect unsupported vector return types.
if (Subtarget.hasVector()) if (Subtarget.hasVector())
VerifyVectorTypes(Outs); VerifyVectorTypes(Outs);
// Integer args <=32 bits should have an extension attribute.
CheckNarrowIntegerArgs(const_cast<SmallVectorImpl<ISD::OutputArg> &>(Outs),
true/*IsRetVal*/);
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-                         true/*IsRetVal*/);
+                         true /*IsRetVal*/);
Lint: Pre-merge checks: clang-format: please reformat the code ``` - true/*IsRetVal*/); +…
// Assign locations to each returned value. // Assign locations to each returned value.
SmallVector<CCValAssign, 16> RetLocs; SmallVector<CCValAssign, 16> RetLocs;
CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext()); CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ); RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
// Quick exit for void returns // Quick exit for void returns
if (RetLocs.empty()) if (RetLocs.empty())
return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain); return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
▲ Show 20 Lines • Show All 6,805 Lines • Show Last 20 Lines

llvm/test/Bitcode/attributes.ll

Show First 20 Lines • Show All 472 Lines • ▼ Show 20 Lines
} }
; CHECK: define void @f80() #50 ; CHECK: define void @f80() #50
define void @f80() disable_sanitizer_instrumentation define void @f80() disable_sanitizer_instrumentation
{ {
ret void; ret void;
} }
define void @f81(i32 noext %0)
; CHECK: define void @f81(i32 noext %0)
{
ret void;
}
; CHECK: attributes #0 = { noreturn } ; CHECK: attributes #0 = { noreturn }
; CHECK: attributes #1 = { nounwind } ; CHECK: attributes #1 = { nounwind }
; CHECK: attributes #2 = { readnone } ; CHECK: attributes #2 = { readnone }
; CHECK: attributes #3 = { readonly } ; CHECK: attributes #3 = { readonly }
; CHECK: attributes #4 = { noinline } ; CHECK: attributes #4 = { noinline }
; CHECK: attributes #5 = { alwaysinline } ; CHECK: attributes #5 = { alwaysinline }
; CHECK: attributes #6 = { optsize } ; CHECK: attributes #6 = { optsize }
; CHECK: attributes #7 = { ssp } ; CHECK: attributes #7 = { ssp }
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llvm/test/CodeGen/SystemZ/and-02.ll

; Test 32-bit ANDs in which the second operand is constant. ; Test 32-bit ANDs in which the second operand is constant.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
; ANDs with 1 can use NILF. ; ANDs with 1 can use NILF.
define i32 @f1(i32 %a) { define i32 @f1(i32 %a) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: nilf %r2, 1 ; CHECK: nilf %r2, 1
; CHECK: br %r14 ; CHECK: br %r14
%and = and i32 %a, 1 %and = and i32 %a, 1
ret i32 %and ret i32 %and
▲ Show 20 Lines • Show All 215 Lines • Show Last 20 Lines

llvm/test/CodeGen/SystemZ/and-07.ll

; Test the three-operand forms of AND. ; Test the three-operand forms of AND.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
; Check NRK. ; Check NRK.
define i32 @f1(i32 %a, i32 %b, i32 %c) { define i32 @f1(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: nrk %r2, %r3, %r4 ; CHECK: nrk %r2, %r3, %r4
; CHECK: br %r14 ; CHECK: br %r14
%and = and i32 %b, %c %and = and i32 %b, %c
ret i32 %and ret i32 %and
Show All 28 Lines

llvm/test/CodeGen/SystemZ/args-01.ll

; Test the handling of GPR, FPR and stack arguments when no extension ; Test the handling of GPR, FPR and stack arguments with the noext attribute.
; type is given. This type of argument is used for passing structures, etc. ; This type of argument is used for passing structures, etc.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-INT ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-INT
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FLOAT ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FLOAT
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-DOUBLE ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-DOUBLE
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FP128-1 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FP128-1
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FP128-2 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FP128-2
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-STACK ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-STACK
declare void @bar(i8, i16, i32, i64, float, double, fp128, i64, declare void @bar(i8 noext, i16 noext, i32 noext, i64, float, double, fp128, i64,
float, double, i8, i16, i32, i64, float, double, fp128) float, double, i8 noext, i16 noext, i32 noext, i64, float,
double, fp128)
; There are two indirect fp128 slots, one at offset 224 (the first available ; There are two indirect fp128 slots, one at offset 224 (the first available
; byte after the outgoing arguments) and one immediately after it at 240. ; byte after the outgoing arguments) and one immediately after it at 240.
; These slots should be set up outside the glued call sequence, so would ; These slots should be set up outside the glued call sequence, so would
; normally use %f0/%f2 as the first available 128-bit pair. This choice ; normally use %f0/%f2 as the first available 128-bit pair. This choice
; is hard-coded in the FP128 tests. ; is hard-coded in the FP128 tests.
; ;
; The order of the CHECK-STACK stores doesn't matter. It would be OK to reorder ; The order of the CHECK-STACK stores doesn't matter. It would be OK to reorder
▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines

llvm/test/CodeGen/SystemZ/args-04.ll

; Test incoming GPR, FPR and stack arguments when no extension type is given. ; Test incoming GPR, FPR and stack arguments when no extension type is given.
; This type of argument is used for passing structures, etc. ; This type of argument is used for passing structures, etc.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -verify-machineinstrs -no-arg-exts \
; RUN: | FileCheck %s
; Do some arithmetic so that we can see the register being used. ; Do some arithmetic so that we can see the register being used.
define i8 @f1(i8 %r2) { define i8 @f1(i8 %r2) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: ahi %r2, 1 ; CHECK: ahi %r2, 1
; CHECK: br %r14 ; CHECK: br %r14
%y = add i8 %r2, 1 %y = add i8 %r2, 1
ret i8 %y ret i8 %y
▲ Show 20 Lines • Show All 128 Lines • Show Last 20 Lines

llvm/test/CodeGen/SystemZ/args-11.ll

Show All 12 Lines
; CHECK-NEXT: .cfi_offset %r15, -40 ; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -184 ; CHECK-NEXT: aghi %r15, -184
; CHECK-NEXT: .cfi_def_cfa_offset 344 ; CHECK-NEXT: .cfi_def_cfa_offset 344
; CHECK-NEXT: mvhi 180(%r15), -1 ; CHECK-NEXT: mvhi 180(%r15), -1
; CHECK-NEXT: mvghi 168(%r15), 0 ; CHECK-NEXT: mvghi 168(%r15), 0
; CHECK-NEXT: la %r2, 160(%r15) ; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: mvghi 160(%r15), 0 ; CHECK-NEXT: mvghi 160(%r15), 0
; CHECK-NEXT: brasl %r14, fn1@PLT ; CHECK-NEXT: brasl %r14, fn1@PLT
; CHECK-NEXT: l %r2, 180(%r15) ; CHECK-NEXT: lgf %r2, 180(%r15)
; CHECK-NEXT: lmg %r14, %r15, 296(%r15) ; CHECK-NEXT: lmg %r14, %r15, 296(%r15)
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%1 = alloca i32 %1 = alloca i32
store i32 -1, i32* %1 store i32 -1, i32* %1
call void @fn1(i96 0) call void @fn1(i96 0)
%2 = load i32, i32* %1 %2 = load i32, i32* %1
ret i32 %2 ret i32 %2
} }
declare void @fn3(i136) declare void @fn3(i136)
define i32 @fn4() { define i32 @fn4() {
; CHECK-LABEL: fn4: ; CHECK-LABEL: fn4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48 ; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40 ; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192 ; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352 ; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: mvhi 188(%r15), -1 ; CHECK-NEXT: mvhi 188(%r15), -1
; CHECK-NEXT: mvghi 176(%r15), 0 ; CHECK-NEXT: mvghi 176(%r15), 0
; CHECK-NEXT: mvghi 168(%r15), 0 ; CHECK-NEXT: mvghi 168(%r15), 0
; CHECK-NEXT: la %r2, 160(%r15) ; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: mvghi 160(%r15), 0 ; CHECK-NEXT: mvghi 160(%r15), 0
; CHECK-NEXT: brasl %r14, fn3@PLT ; CHECK-NEXT: brasl %r14, fn3@PLT
; CHECK-NEXT: l %r2, 188(%r15) ; CHECK-NEXT: lgf %r2, 188(%r15)
; CHECK-NEXT: lmg %r14, %r15, 304(%r15) ; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%1 = alloca i32 %1 = alloca i32
store i32 -1, i32* %1 store i32 -1, i32* %1
call void @fn3(i136 0) call void @fn3(i136 0)
%2 = load i32, i32* %1 %2 = load i32, i32* %1
ret i32 %2 ret i32 %2
} }

llvm/test/CodeGen/SystemZ/args-12.ll

  • This file was added.
; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -verify-int-arg-exts 2>&1 \
; RUN: | FileCheck %s
; REQUIRES: asserts
;
; Test detection of missing extension of an i32 return value.
define i32 @callee_MissingRetAttr() {
ret i32 -1
}
; CHECK: Narrow integer argument must have a valid extension type

llvm/test/CodeGen/SystemZ/args-13.ll

  • This file was added.
; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -verify-int-arg-exts 2>&1 \
; RUN: | FileCheck %s
; REQUIRES: asserts
;
; Test detection of missing extension of an i16 return value.
define i16 @callee_MissingRetAttr() {
ret i16 -1
}
; CHECK: Narrow integer argument must have a valid extension type

llvm/test/CodeGen/SystemZ/args-14.ll

  • This file was added.
; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -verify-int-arg-exts 2>&1 \
; RUN: | FileCheck %s
; REQUIRES: asserts
; Test detection of missing extension of an i8 return value. NoExt should be
; accepted by parser here but the test should still fail as structs are
; always returned via memory.
define noext i8 @callee_MissingRetAttr() {
ret i8 -1
}
; CHECK: Narrow integer argument must have a valid extension type

llvm/test/CodeGen/SystemZ/args-15.ll

  • This file was added.
; RUN: llc < %s -mtriple=s390x-linux-gnu -verify-int-arg-exts
;
; Test that it works to pass structs as outgoing call arguments when the
; NoExt attribute is given, either in the call instruction or in the
; prototype of the called function.
define void @caller() {
call void @bar_Struct_32(i32 noext 123)
call void @bar_Struct_16(i16 123)
call void @bar_Struct_8(i8 noext 123)
ret void
}
declare void @bar_Struct_32(i32 %Arg)
declare void @bar_Struct_16(i16 noext %Arg)
declare void @bar_Struct_8(i8 %Arg)

llvm/test/CodeGen/SystemZ/args-16.ll

  • This file was added.
; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -verify-int-arg-exts 2>&1 \
; RUN: | FileCheck %s
; REQUIRES: asserts
;
; Test detection of missing extension of an outgoing i32 call argument.
define void @caller() {
call void @bar_Struct(i32 123)
ret void
}
declare void @bar_Struct(i32 %Arg)
; CHECK: Narrow integer argument must have a valid extension type

llvm/test/CodeGen/SystemZ/args-17.ll

  • This file was added.
; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -verify-int-arg-exts 2>&1 \
; RUN: | FileCheck %s
; REQUIRES: asserts
;
; Test detection of missing extension of an outgoing i16 call argument.
define void @caller() {
call void @bar_Struct(i16 123)
ret void
}
declare void @bar_Struct(i16 %Arg)
; CHECK: Narrow integer argument must have a valid extension type

llvm/test/CodeGen/SystemZ/args-18.ll

  • This file was added.
; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -verify-int-arg-exts 2>&1 \
; RUN: | FileCheck %s
; REQUIRES: asserts
;
; Test detection of missing extension of an outgoing i8 call argument.
define void @caller() {
call void @bar_Struct(i8 123)
ret void
}
declare void @bar_Struct(i8 %Arg)
; CHECK: Narrow integer argument must have a valid extension type

llvm/test/CodeGen/SystemZ/args-19.ll

  • This file was added.
; RUN: llc < %s -mtriple=s390x-linux-gnu
; Test that passed outgoing integer arguments are sign-extended by default if
; the extension attribute is missing.
define void @caller() {
; CHECK-LABEL: caller:
; CHECK: lghi %r2, 132
; CHECK-NEXT: brasl %r14, bar_Struct_32@PLT
; CHECK-NEXT: lghi %r2, 116
; CHECK-NEXT: brasl %r14, bar_Struct_16@PLT
; CHECK-NEXT: lghi %r2, 108
; CHECK-NEXT: brasl %r14, bar_Struct_8@PLT
call void @bar_Struct_32(i32 132)
call void @bar_Struct_16(i16 116)
call void @bar_Struct_8(i8 108)
ret void
}
; Test default sign extension of returned values.
define i32 @callee_1(i32 %Arg) {
; CHECK-LABEL: callee_1:
; CHECK: ahi %r2, 1
; CHECK-NEXT: lgfr %r2, %r2
; CHECK-NEXT: br %r14
%A = add i32 %Arg, 1
ret i32 %A
}
define i16 @callee_2(i16 %Arg) {
; CHECK-LABEL: callee_2:
; CHECK: ahi %r2, 1
; CHECK-NEXT: lghr %r2, %r2
; CHECK-NEXT: br %r14
%A = add i16 %Arg, 1
ret i16 %A
}
define i8 @callee_3(i8 %Arg) {
; CHECK-LABEL: callee_3:
; CHECK: ahi %r2, 1
; CHECK-NEXT: lgbr %r2, %r2
; CHECK-NEXT: br %r14
%A = add i8 %Arg, 1
ret i8 %A
}
declare void @bar_Struct_32(i32 %Arg)
declare void @bar_Struct_16(i16 %Arg)
declare void @bar_Struct_8(i8 %Arg)

llvm/test/CodeGen/SystemZ/asm-11.ll

; Test the "I" constraint (8-bit unsigned constants). ; Test the "I" constraint (8-bit unsigned constants).
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as -no-arg-exts \
; RUN: | FileCheck %s
; Test 1 below the first valid value. ; Test 1 below the first valid value.
define i32 @f1() { define i32 @f1() {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lhi [[REG:%r[0-5]]], -1 ; CHECK: lhi [[REG:%r[0-5]]], -1
; CHECK: blah %r2 [[REG]] ; CHECK: blah %r2 [[REG]]
; CHECK: br %r14 ; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rI" (i32 -1) %val = call i32 asm "blah $0 $1", "=&r,rI" (i32 -1)
Show All 30 Lines

llvm/test/CodeGen/SystemZ/asm-12.ll

; Test the "J" constraint (12-bit unsigned constants). ; Test the "J" constraint (12-bit unsigned constants).
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as -no-arg-exts \
; RUN: | FileCheck %s
; Test 1 below the first valid value. ; Test 1 below the first valid value.
define i32 @f1() { define i32 @f1() {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lhi [[REG:%r[0-5]]], -1 ; CHECK: lhi [[REG:%r[0-5]]], -1
; CHECK: blah %r2 [[REG]] ; CHECK: blah %r2 [[REG]]
; CHECK: br %r14 ; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rJ" (i32 -1) %val = call i32 asm "blah $0 $1", "=&r,rJ" (i32 -1)
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llvm/test/CodeGen/SystemZ/asm-13.ll

; Test the "K" constraint (16-bit signed constants). ; Test the "K" constraint (16-bit signed constants).
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as -no-arg-exts \
; RUN: | FileCheck %s
; Test 1 below the first valid value. ; Test 1 below the first valid value.
define i32 @f1() { define i32 @f1() {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: iilf [[REG:%r[0-5]]], 4294934527 ; CHECK: iilf [[REG:%r[0-5]]], 4294934527
; CHECK: blah %r2 [[REG]] ; CHECK: blah %r2 [[REG]]
; CHECK: br %r14 ; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rK" (i32 -32769) %val = call i32 asm "blah $0 $1", "=&r,rK" (i32 -32769)
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llvm/test/CodeGen/SystemZ/asm-14.ll

; Test the "L" constraint (20-bit signed constants). ; Test the "L" constraint (20-bit signed constants).
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as -no-arg-exts \
; RUN: | FileCheck %s
; Test 1 below the first valid value. ; Test 1 below the first valid value.
define i32 @f1() { define i32 @f1() {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: iilf [[REG:%r[0-5]]], 4294443007 ; CHECK: iilf [[REG:%r[0-5]]], 4294443007
; CHECK: blah %r2 [[REG]] ; CHECK: blah %r2 [[REG]]
; CHECK: br %r14 ; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rL" (i32 -524289) %val = call i32 asm "blah $0 $1", "=&r,rL" (i32 -524289)
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llvm/test/CodeGen/SystemZ/asm-15.ll

; Test the "M" constraint (0x7fffffff) ; Test the "M" constraint (0x7fffffff)
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as -no-arg-exts \
; RUN: | FileCheck %s
; Test 1 below the valid value. ; Test 1 below the valid value.
define i32 @f1() { define i32 @f1() {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: iilf [[REG:%r[0-5]]], 2147483646 ; CHECK: iilf [[REG:%r[0-5]]], 2147483646
; CHECK: blah %r2 [[REG]] ; CHECK: blah %r2 [[REG]]
; CHECK: br %r14 ; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483646) %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483646)
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llvm/test/CodeGen/SystemZ/asm-16.ll

; Test the "M" constraint (0x7fffffff) ; Test the "M" constraint (0x7fffffff)
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as -no-arg-exts \
; RUN: | FileCheck %s
; Test 1 below the valid value. ; Test 1 below the valid value.
define i32 @f1() { define i32 @f1() {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: iilf [[REG:%r[0-5]]], 2147483646 ; CHECK: iilf [[REG:%r[0-5]]], 2147483646
; CHECK: blah %r2 [[REG]] ; CHECK: blah %r2 [[REG]]
; CHECK: br %r14 ; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483646) %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483646)
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llvm/test/CodeGen/SystemZ/asm-17.ll

; Test explicit register names. ; Test explicit register names.
; ;
; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -no-integrated-as \ ; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -no-integrated-as \
; RUN: | FileCheck %s ; RUN: | FileCheck %s
; Test i32 GPRs. ; Test i32 GPRs.
define i32 @f1() { define i32 @f1() {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lhi %r4, 1 ; CHECK: lhi %r4, 1
; CHECK: blah %r4 ; CHECK: blah %r4
; CHECK: lr %r2, %r4 ; CHECK: lgfr %r2, %r4
; CHECK: br %r14 ; CHECK: br %r14
%ret = call i32 asm "blah $0", "={r4},0" (i32 1) %ret = call i32 asm "blah $0", "={r4},0" (i32 1)
ret i32 %ret ret i32 %ret
} }
; Test i64 GPRs. ; Test i64 GPRs.
define i64 @f2() { define i64 @f2() {
; CHECK-LABEL: f2: ; CHECK-LABEL: f2:
Show All 40 Lines; CHECK: br %r14
ret void ret void
} }
; Test clobbers of GPRs and CC. ; Test clobbers of GPRs and CC.
define i32 @f6(i32 %in) { define i32 @f6(i32 %in) {
; CHECK-LABEL: f6: ; CHECK-LABEL: f6:
; CHECK: lr [[REG:%r[01345]]], %r2 ; CHECK: lr [[REG:%r[01345]]], %r2
; CHECK: blah ; CHECK: blah
; CHECK: lr %r2, [[REG]] ; CHECK: lgfr %r2, [[REG]]
; CHECK: br %r14 ; CHECK: br %r14
call void asm sideeffect "blah", "~{r2},~{cc}"() call void asm sideeffect "blah", "~{r2},~{cc}"()
ret i32 %in ret i32 %in
} }
; Test clobbers of FPRs and CC. ; Test clobbers of FPRs and CC.
define float @f7(float %in) { define float @f7(float %in) {
; CHECK-LABEL: f7: ; CHECK-LABEL: f7:
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llvm/test/CodeGen/SystemZ/asm-18.ll

; Test high-word operations, using "h" constraints to force a high ; Test high-word operations, using "h" constraints to force a high
; register and "r" constraints to force a low register. ; register and "r" constraints to force a low register.
; ;
; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z196 \ ; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z196 \
; RUN: -no-integrated-as | FileCheck %s ; RUN: -no-integrated-as -no-arg-exts | FileCheck %s
; Test loads and stores involving mixtures of high and low registers. ; Test loads and stores involving mixtures of high and low registers.
define void @f1(i32 *%ptr1, i32 *%ptr2) { define void @f1(i32 *%ptr1, i32 *%ptr2) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK-DAG: lfh [[REG1:%r[0-5]]], 0(%r2) ; CHECK-DAG: lfh [[REG1:%r[0-5]]], 0(%r2)
; CHECK-DAG: l [[REG2:%r[0-5]]], 0(%r3) ; CHECK-DAG: l [[REG2:%r[0-5]]], 0(%r3)
; CHECK-DAG: lfh [[REG3:%r[0-5]]], 4096(%r2) ; CHECK-DAG: lfh [[REG3:%r[0-5]]], 4096(%r2)
; CHECK-DAG: ly [[REG4:%r[0-5]]], 524284(%r3) ; CHECK-DAG: ly [[REG4:%r[0-5]]], 524284(%r3)
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llvm/test/CodeGen/SystemZ/atomic-load-01.ll

; Test 8-bit atomic loads. ; Test 8-bit atomic loads.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
define i8 @f1(i8 *%src) { define i8 @f1(i8 *%src) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lb %r2, 0(%r2) ; CHECK: lb %r2, 0(%r2)
; CHECK: br %r14 ; CHECK: br %r14
%val = load atomic i8, i8 *%src seq_cst, align 1 %val = load atomic i8, i8 *%src seq_cst, align 1
ret i8 %val ret i8 %val
} }

llvm/test/CodeGen/SystemZ/atomic-load-02.ll

; Test 16-bit atomic loads. ; Test 16-bit atomic loads.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
define i16 @f1(i16 *%src) { define i16 @f1(i16 *%src) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lh %r2, 0(%r2) ; CHECK: lh %r2, 0(%r2)
; CHECK: br %r14 ; CHECK: br %r14
%val = load atomic i16, i16 *%src seq_cst, align 2 %val = load atomic i16, i16 *%src seq_cst, align 2
ret i16 %val ret i16 %val
} }

llvm/test/CodeGen/SystemZ/atomic-load-03.ll

; Test 32-bit atomic loads. ; Test 32-bit atomic loads.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
define i32 @f1(i32 *%src) { define i32 @f1(i32 *%src) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r2) ; CHECK: l %r2, 0(%r2)
; CHECK: br %r14 ; CHECK: br %r14
%val = load atomic i32, i32 *%src seq_cst, align 4 %val = load atomic i32, i32 *%src seq_cst, align 4
ret i32 %val ret i32 %val
} }

llvm/test/CodeGen/SystemZ/atomicrmw-add-01.ll

; Test 8-bit atomic additions. ; Test 8-bit atomic additions.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 ; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2
; Check addition of a variable. ; Check addition of a variable.
; - CHECK is for the main loop. ; - CHECK is for the main loop.
; - CHECK-SHIFT1 makes sure that the negated shift count used by the second ; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
; RLL is set up correctly. The negation is independent of the NILL and L ; RLL is set up correctly. The negation is independent of the NILL and L
; tested in CHECK. ; tested in CHECK.
; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
; before being used. This shift is independent of the other loop prologue ; before being used. This shift is independent of the other loop prologue
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llvm/test/CodeGen/SystemZ/atomicrmw-add-02.ll

; Test 16-bit atomic additions. ; Test 16-bit atomic additions.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 ; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2
; Check addition of a variable. ; Check addition of a variable.
; - CHECK is for the main loop. ; - CHECK is for the main loop.
; - CHECK-SHIFT1 makes sure that the negated shift count used by the second ; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
; RLL is set up correctly. The negation is independent of the NILL and L ; RLL is set up correctly. The negation is independent of the NILL and L
; tested in CHECK. ; tested in CHECK.
; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
; before being used. This shift is independent of the other loop prologue ; before being used. This shift is independent of the other loop prologue
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llvm/test/CodeGen/SystemZ/atomicrmw-add-03.ll

; Test 32-bit atomic additions. ; Test 32-bit atomic additions.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s
; Check addition of a variable. ; Check addition of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3) ; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]: ; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lr %r0, %r2 ; CHECK: lr %r0, %r2
; CHECK: ar %r0, %r4 ; CHECK: ar %r0, %r4
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llvm/test/CodeGen/SystemZ/atomicrmw-add-05.ll

; Test 32-bit atomic additions, z196 version. ; Test 32-bit atomic additions, z196 version.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
; Check addition of a variable. ; Check addition of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: laa %r2, %r4, 0(%r3) ; CHECK: laa %r2, %r4, 0(%r3)
; CHECK: br %r14 ; CHECK: br %r14
%res = atomicrmw add i32 *%src, i32 %b seq_cst %res = atomicrmw add i32 *%src, i32 %b seq_cst
ret i32 %res ret i32 %res
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llvm/test/CodeGen/SystemZ/atomicrmw-and-01.ll

; Test 8-bit atomic ANDs. ; Test 8-bit atomic ANDs.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 ; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2
; Check AND of a variable. ; Check AND of a variable.
; - CHECK is for the main loop. ; - CHECK is for the main loop.
; - CHECK-SHIFT1 makes sure that the negated shift count used by the second ; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
; RLL is set up correctly. The negation is independent of the NILL and L ; RLL is set up correctly. The negation is independent of the NILL and L
; tested in CHECK. ; tested in CHECK.
; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
; before being used, and that the low bits are set to 1. This sequence is ; before being used, and that the low bits are set to 1. This sequence is
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llvm/test/CodeGen/SystemZ/atomicrmw-and-02.ll

; Test 16-bit atomic ANDs. ; Test 16-bit atomic ANDs.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 ; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2
; Check AND of a variable. ; Check AND of a variable.
; - CHECK is for the main loop. ; - CHECK is for the main loop.
; - CHECK-SHIFT1 makes sure that the negated shift count used by the second ; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
; RLL is set up correctly. The negation is independent of the NILL and L ; RLL is set up correctly. The negation is independent of the NILL and L
; tested in CHECK. ; tested in CHECK.
; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
; before being used, and that the low bits are set to 1. This sequence is ; before being used, and that the low bits are set to 1. This sequence is
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llvm/test/CodeGen/SystemZ/atomicrmw-and-03.ll

; Test 32-bit atomic ANDs. ; Test 32-bit atomic ANDs.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s
; Check ANDs of a variable. ; Check ANDs of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3) ; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]: ; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2 ; CHECK: lr %r0, %r2
; CHECK: nr %r0, %r4 ; CHECK: nr %r0, %r4
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llvm/test/CodeGen/SystemZ/atomicrmw-and-05.ll

; Test 32-bit atomic ANDs, z196 version. ; Test 32-bit atomic ANDs, z196 version.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
; Check AND of a variable. ; Check AND of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lan %r2, %r4, 0(%r3) ; CHECK: lan %r2, %r4, 0(%r3)
; CHECK: br %r14 ; CHECK: br %r14
%res = atomicrmw and i32 *%src, i32 %b seq_cst %res = atomicrmw and i32 *%src, i32 %b seq_cst
ret i32 %res ret i32 %res
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llvm/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll

; Test 8-bit atomic min/max operations. ; Test 8-bit atomic min/max operations.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement -no-arg-exts \
; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement | FileCheck %s -check-prefix=CHECK-SHIFT2 ; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement -no-arg-exts \
; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1
; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement -no-arg-exts \
; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2
; Check signed minimum. ; Check signed minimum.
; - CHECK is for the main loop. ; - CHECK is for the main loop.
; - CHECK-SHIFT1 makes sure that the negated shift count used by the second ; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
; RLL is set up correctly. The negation is independent of the NILL and L ; RLL is set up correctly. The negation is independent of the NILL and L
; tested in CHECK. ; tested in CHECK.
; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
; before being used, and that the low bits are set to 1. This sequence is ; before being used, and that the low bits are set to 1. This sequence is
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llvm/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll

; Test 8-bit atomic min/max operations. ; Test 8-bit atomic min/max operations.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement -no-arg-exts \
; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement | FileCheck %s -check-prefix=CHECK-SHIFT2 ; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement -no-arg-exts \
; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1
; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-block-placement -no-arg-exts \
; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2
; Check signed minimum. ; Check signed minimum.
; - CHECK is for the main loop. ; - CHECK is for the main loop.
; - CHECK-SHIFT1 makes sure that the negated shift count used by the second ; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
; RLL is set up correctly. The negation is independent of the NILL and L ; RLL is set up correctly. The negation is independent of the NILL and L
; tested in CHECK. ; tested in CHECK.
; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
; before being used, and that the low bits are set to 1. This sequence is ; before being used, and that the low bits are set to 1. This sequence is
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llvm/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll

; Test 32-bit atomic minimum and maximum. Here we match the z10 versions, ; Test 32-bit atomic minimum and maximum. Here we match the z10 versions,
; which can't use LOCR. ; which can't use LOCR.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s
; Check signed minium. ; Check signed minium.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3) ; CHECK: l %r2, 0(%r3)
; CHECK: j [[LOOP:\.[^:]*]] ; CHECK: j [[LOOP:\.[^:]*]]
; CHECK: [[BB1:\.[^:]*]]: ; CHECK: [[BB1:\.[^:]*]]:
; CHECK: cs %r2, [[NEW:%r[0-9]+]], 0(%r3) ; CHECK: cs %r2, [[NEW:%r[0-9]+]], 0(%r3)
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llvm/test/CodeGen/SystemZ/atomicrmw-nand-01.ll

; Test 8-bit atomic NANDs. ; Test 8-bit atomic NANDs.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 ; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2
; Check NAND of a variable. ; Check NAND of a variable.
; - CHECK is for the main loop. ; - CHECK is for the main loop.
; - CHECK-SHIFT1 makes sure that the negated shift count used by the second ; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
; RLL is set up correctly. The negation is independent of the NILL and L ; RLL is set up correctly. The negation is independent of the NILL and L
; tested in CHECK. ; tested in CHECK.
; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
; before being used, and that the low bits are set to 1. This sequence is ; before being used, and that the low bits are set to 1. This sequence is
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llvm/test/CodeGen/SystemZ/atomicrmw-nand-02.ll

; Test 16-bit atomic NANDs. ; Test 16-bit atomic NANDs.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 ; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2
; Check NAND of a variable. ; Check NAND of a variable.
; - CHECK is for the main loop. ; - CHECK is for the main loop.
; - CHECK-SHIFT1 makes sure that the negated shift count used by the second ; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
; RLL is set up correctly. The negation is independent of the NILL and L ; RLL is set up correctly. The negation is independent of the NILL and L
; tested in CHECK. ; tested in CHECK.
; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
; before being used, and that the low bits are set to 1. This sequence is ; before being used, and that the low bits are set to 1. This sequence is
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llvm/test/CodeGen/SystemZ/atomicrmw-nand-03.ll

; Test 32-bit atomic NANDs. ; Test 32-bit atomic NANDs.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s
; Check NANDs of a variable. ; Check NANDs of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3) ; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]: ; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2 ; CHECK: lr %r0, %r2
; CHECK: nr %r0, %r4 ; CHECK: nr %r0, %r4
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llvm/test/CodeGen/SystemZ/atomicrmw-or-01.ll

; Test 8-bit atomic ORs. ; Test 8-bit atomic ORs.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 ; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2
; Check OR of a variable. ; Check OR of a variable.
; - CHECK is for the main loop. ; - CHECK is for the main loop.
; - CHECK-SHIFT1 makes sure that the negated shift count used by the second ; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
; RLL is set up correctly. The negation is independent of the NILL and L ; RLL is set up correctly. The negation is independent of the NILL and L
; tested in CHECK. ; tested in CHECK.
; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
; before being used. This shift is independent of the other loop prologue ; before being used. This shift is independent of the other loop prologue
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llvm/test/CodeGen/SystemZ/atomicrmw-or-02.ll

; Test 16-bit atomic ORs. ; Test 16-bit atomic ORs.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 ; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2
; Check OR of a variable. ; Check OR of a variable.
; - CHECK is for the main loop. ; - CHECK is for the main loop.
; - CHECK-SHIFT1 makes sure that the negated shift count used by the second ; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
; RLL is set up correctly. The negation is independent of the NILL and L ; RLL is set up correctly. The negation is independent of the NILL and L
; tested in CHECK. ; tested in CHECK.
; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
; before being used. This shift is independent of the other loop prologue ; before being used. This shift is independent of the other loop prologue
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llvm/test/CodeGen/SystemZ/atomicrmw-or-03.ll

; Test 32-bit atomic ORs. ; Test 32-bit atomic ORs.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s
; Check ORs of a variable. ; Check ORs of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3) ; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]: ; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2 ; CHECK: lr %r0, %r2
; CHECK: or %r0, %r4 ; CHECK: or %r0, %r4
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llvm/test/CodeGen/SystemZ/atomicrmw-or-05.ll

; Test 32-bit atomic ORs, z196 version. ; Test 32-bit atomic ORs, z196 version.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
; Check OR of a variable. ; Check OR of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lao %r2, %r4, 0(%r3) ; CHECK: lao %r2, %r4, 0(%r3)
; CHECK: br %r14 ; CHECK: br %r14
%res = atomicrmw or i32 *%src, i32 %b seq_cst %res = atomicrmw or i32 *%src, i32 %b seq_cst
ret i32 %res ret i32 %res
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llvm/test/CodeGen/SystemZ/atomicrmw-sub-01.ll

; Test 8-bit atomic subtractions. ; Test 8-bit atomic subtractions.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 ; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2
; Check subtraction of a variable. ; Check subtraction of a variable.
; - CHECK is for the main loop. ; - CHECK is for the main loop.
; - CHECK-SHIFT1 makes sure that the negated shift count used by the second ; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
; RLL is set up correctly. The negation is independent of the NILL and L ; RLL is set up correctly. The negation is independent of the NILL and L
; tested in CHECK. ; tested in CHECK.
; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
; before being used. This shift is independent of the other loop prologue ; before being used. This shift is independent of the other loop prologue
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llvm/test/CodeGen/SystemZ/atomicrmw-sub-02.ll

; Test 16-bit atomic subtractions. ; Test 16-bit atomic subtractions.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 ; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2
; Check subtraction of a variable. ; Check subtraction of a variable.
; - CHECK is for the main loop. ; - CHECK is for the main loop.
; - CHECK-SHIFT1 makes sure that the negated shift count used by the second ; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
; RLL is set up correctly. The negation is independent of the NILL and L ; RLL is set up correctly. The negation is independent of the NILL and L
; tested in CHECK. ; tested in CHECK.
; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
; before being used. This shift is independent of the other loop prologue ; before being used. This shift is independent of the other loop prologue
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llvm/test/CodeGen/SystemZ/atomicrmw-sub-03.ll

; Test 32-bit atomic subtractions. ; Test 32-bit atomic subtractions.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s
; Check subtraction of a variable. ; Check subtraction of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3) ; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]: ; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lr %r0, %r2 ; CHECK: lr %r0, %r2
; CHECK: sr %r0, %r4 ; CHECK: sr %r0, %r4
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llvm/test/CodeGen/SystemZ/atomicrmw-sub-05.ll

; Test 32-bit atomic subtractions, z196 version. ; Test 32-bit atomic subtractions, z196 version.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
; Check addition of a variable. ; Check addition of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lcr [[NEG:%r[0-5]]], %r4 ; CHECK: lcr [[NEG:%r[0-5]]], %r4
; CHECK: laa %r2, [[NEG]], 0(%r3) ; CHECK: laa %r2, [[NEG]], 0(%r3)
; CHECK: br %r14 ; CHECK: br %r14
%res = atomicrmw sub i32 *%src, i32 %b seq_cst %res = atomicrmw sub i32 *%src, i32 %b seq_cst
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llvm/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll

Show All 15 Lines
; CHECK-DAG: sll %r2, 3 ; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]: ; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: risbg [[ROT]], %r3, 32, 39, 24 ; CHECK: risbg [[ROT]], %r3, 32, 39, 24
; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
; CHECK: jl [[LABEL]] ; CHECK: jl [[LABEL]]
; CHECK: rll %r2, [[OLD]], 8(%r2) ; CHECK: rll %r0, [[OLD]], 8(%r2)
; CHECK: lgbr %r2, %r0
; CHECK: br %r14 ; CHECK: br %r14
; ;
; CHECK-SHIFT-LABEL: f1: ; CHECK-SHIFT-LABEL: f1:
; CHECK-SHIFT-NOT: %r3 ; CHECK-SHIFT-NOT: %r3
; CHECK-SHIFT: sll %r2, 3 ; CHECK-SHIFT: sll %r2, 3
; CHECK-SHIFT-NOT: %r3 ; CHECK-SHIFT-NOT: %r3
; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], %r2
; CHECK-SHIFT-NOT: %r3 ; CHECK-SHIFT-NOT: %r3
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llvm/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll

Show All 15 Lines
; CHECK-DAG: sll %r2, 3 ; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]: ; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: risbg [[ROT]], %r3, 32, 47, 16 ; CHECK: risbg [[ROT]], %r3, 32, 47, 16
; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
; CHECK: jl [[LABEL]] ; CHECK: jl [[LABEL]]
; CHECK: rll %r2, [[OLD]], 16(%r2) ; CHECK: rll %r0, [[OLD]], 16(%r2)
; CHECK: lghr %r2, %r0
; CHECK: br %r14 ; CHECK: br %r14
; ;
; CHECK-SHIFT-LABEL: f1: ; CHECK-SHIFT-LABEL: f1:
; CHECK-SHIFT-NOT: %r3 ; CHECK-SHIFT-NOT: %r3
; CHECK-SHIFT: sll %r2, 3 ; CHECK-SHIFT: sll %r2, 3
; CHECK-SHIFT-NOT: %r3 ; CHECK-SHIFT-NOT: %r3
; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], %r2
; CHECK-SHIFT-NOT: %r3 ; CHECK-SHIFT-NOT: %r3
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llvm/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll

; Test 32-bit atomic exchange. ; Test 32-bit atomic exchange.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; Check register exchange. ; Check register exchange.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3) ; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]: ; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: cs %r2, %r4, 0(%r3) ; CHECK: cs %r2, %r4, 0(%r3)
; CHECK: jl [[LABEL]] ; CHECK: jl [[LABEL]]
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llvm/test/CodeGen/SystemZ/atomicrmw-xor-01.ll

; Test 8-bit atomic XORs. ; Test 8-bit atomic XORs.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 ; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2
; Check XOR of a variable. ; Check XOR of a variable.
; - CHECK is for the main loop. ; - CHECK is for the main loop.
; - CHECK-SHIFT1 makes sure that the negated shift count used by the second ; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
; RLL is set up correctly. The negation is independent of the NILL and L ; RLL is set up correctly. The negation is independent of the NILL and L
; tested in CHECK. ; tested in CHECK.
; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
; before being used. This shift is independent of the other loop prologue ; before being used. This shift is independent of the other loop prologue
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llvm/test/CodeGen/SystemZ/atomicrmw-xor-02.ll

; Test 16-bit atomic XORs. ; Test 16-bit atomic XORs.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 ; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT1
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT2
; Check XOR of a variable. ; Check XOR of a variable.
; - CHECK is for the main loop. ; - CHECK is for the main loop.
; - CHECK-SHIFT1 makes sure that the negated shift count used by the second ; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
; RLL is set up correctly. The negation is independent of the NILL and L ; RLL is set up correctly. The negation is independent of the NILL and L
; tested in CHECK. ; tested in CHECK.
; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word ; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
; before being used. This shift is independent of the other loop prologue ; before being used. This shift is independent of the other loop prologue
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llvm/test/CodeGen/SystemZ/atomicrmw-xor-03.ll

; Test 32-bit atomic XORs. ; Test 32-bit atomic XORs.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s
; Check XORs of a variable. ; Check XORs of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3) ; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]: ; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2 ; CHECK: lr %r0, %r2
; CHECK: xr %r0, %r4 ; CHECK: xr %r0, %r4
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llvm/test/CodeGen/SystemZ/atomicrmw-xor-05.ll

; Test 32-bit atomic ORs, z196 version. ; Test 32-bit atomic ORs, z196 version.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
; Check OR of a variable. ; Check OR of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lax %r2, %r4, 0(%r3) ; CHECK: lax %r2, %r4, 0(%r3)
; CHECK: br %r14 ; CHECK: br %r14
%res = atomicrmw xor i32 *%src, i32 %b seq_cst %res = atomicrmw xor i32 *%src, i32 %b seq_cst
ret i32 %res ret i32 %res
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llvm/test/CodeGen/SystemZ/branch-05.ll

; Test indirect jumps. ; Test indirect jumps.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
define i32 @f1(i32 %x, i32 %y, i32 %op) { define i32 @f1(i32 %x, i32 %y, i32 %op) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: ahi %r4, -1 ; CHECK: ahi %r4, -1
; CHECK: clibh %r4, 5, 0(%r14) ; CHECK: clibh %r4, 5, 0(%r14)
; CHECK: llgfr [[OP64:%r[0-5]]], %r4 ; CHECK: llgfr [[OP64:%r[0-5]]], %r4
; CHECK: sllg [[INDEX:%r[1-5]]], [[OP64]], 3 ; CHECK: sllg [[INDEX:%r[1-5]]], [[OP64]], 3
; CHECK: larl [[BASE:%r[1-5]]] ; CHECK: larl [[BASE:%r[1-5]]]
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llvm/test/CodeGen/SystemZ/branch-11.ll

; Test indirect jumps on z14. ; Test indirect jumps on z14.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -no-arg-exts | FileCheck %s
define i32 @f1(i32 %x, i32 %y, i32 %op) { define i32 @f1(i32 %x, i32 %y, i32 %op) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: ahi %r4, -1 ; CHECK: ahi %r4, -1
; CHECK: clibh %r4, 5, 0(%r14) ; CHECK: clibh %r4, 5, 0(%r14)
; CHECK: llgfr [[OP64:%r[0-5]]], %r4 ; CHECK: llgfr [[OP64:%r[0-5]]], %r4
; CHECK: sllg [[INDEX:%r[1-5]]], [[OP64]], 3 ; CHECK: sllg [[INDEX:%r[1-5]]], [[OP64]], 3
; CHECK: larl [[BASE:%r[1-5]]] ; CHECK: larl [[BASE:%r[1-5]]]
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llvm/test/CodeGen/SystemZ/bswap-02.ll

; Test 32-bit byteswaps from memory to registers. ; Test 32-bit byteswaps from memory to registers.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
declare i32 @llvm.bswap.i32(i32 %a) declare i32 @llvm.bswap.i32(i32 %a)
; Check LRV with no displacement. ; Check LRV with no displacement.
define i32 @f1(i32 *%src) { define i32 @f1(i32 *%src) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lrv %r2, 0(%r2) ; CHECK: lrv %r2, 0(%r2)
; CHECK: br %r14 ; CHECK: br %r14
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llvm/test/CodeGen/SystemZ/bswap-06.ll

; Test 16-bit byteswaps from memory to registers. ; Test 16-bit byteswaps from memory to registers.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
declare i16 @llvm.bswap.i16(i16 %a) declare i16 @llvm.bswap.i16(i16 %a)
; Check LRVH with no displacement. ; Check LRVH with no displacement.
define i16 @f1(i16 *%src) { define i16 @f1(i16 *%src) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lrvh %r2, 0(%r2) ; CHECK: lrvh %r2, 0(%r2)
; CHECK: br %r14 ; CHECK: br %r14
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llvm/test/CodeGen/SystemZ/call-03.ll

Show All 11 Lines
declare i64 @returns_i64() declare i64 @returns_i64()
; Check the maximum number of arguments that we can pass and still use ; Check the maximum number of arguments that we can pass and still use
; a sibling call. ; a sibling call.
define void @f1() { define void @f1() {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK-DAG: lzer %f0 ; CHECK-DAG: lzer %f0
; CHECK-DAG: lzdr %f2 ; CHECK-DAG: lzdr %f2
; CHECK-DAG: lhi %r2, 1 ; CHECK-DAG: lghi %r2, 1
; CHECK-DAG: lhi %r3, 2 ; CHECK-DAG: lghi %r3, 2
; CHECK-DAG: lhi %r4, 3 ; CHECK-DAG: lghi %r4, 3
; CHECK-DAG: lghi %r5, 4 ; CHECK-DAG: lghi %r5, 4
; CHECK-DAG: {{ler %f4, %f0|lzer %f4}} ; CHECK-DAG: {{ler %f4, %f0|lzer %f4}}
; CHECK-DAG: {{ldr %f6, %f2|lzdr %f6}} ; CHECK-DAG: {{ldr %f6, %f2|lzdr %f6}}
; CHECK: jg ok@PLT ; CHECK: jg ok@PLT
tail call void @ok(i8 1, i16 2, i32 3, i64 4, float 0.0, double 0.0, tail call void @ok(i8 1, i16 2, i32 3, i64 4, float 0.0, double 0.0,
float 0.0, double 0.0) float 0.0, double 0.0)
ret void ret void
} }
Show All 29 Lines; CHECK: br %r14
ret void ret void
} }
; Check an indirect call. In this case the only acceptable choice for ; Check an indirect call. In this case the only acceptable choice for
; the target register is %r1. ; the target register is %r1.
define void @f5(void(i32, i32, i32, i32) *%foo) { define void @f5(void(i32, i32, i32, i32) *%foo) {
; CHECK-LABEL: f5: ; CHECK-LABEL: f5:
; CHECK: lgr %r1, %r2 ; CHECK: lgr %r1, %r2
; CHECK-DAG: lhi %r2, 1 ; CHECK-DAG: lghi %r2, 1
; CHECK-DAG: lhi %r3, 2 ; CHECK-DAG: lghi %r3, 2
; CHECK-DAG: lhi %r4, 3 ; CHECK-DAG: lghi %r4, 3
; CHECK-DAG: lhi %r5, 4 ; CHECK-DAG: lghi %r5, 4
; CHECK: br %r1 ; CHECK: br %r1
tail call void %foo(i32 1, i32 2, i32 3, i32 4) tail call void %foo(i32 1, i32 2, i32 3, i32 4)
ret void ret void
} }
; Check an indirect call that will be forced into a call-saved GPR ; Check an indirect call that will be forced into a call-saved GPR
; (which should be %r13, the highest GPR not used for anything else). ; (which should be %r13, the highest GPR not used for anything else).
define void @f6(void(i32) *%foo) { define void @f6(void(i32) *%foo) {
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llvm/test/CodeGen/SystemZ/cmpxchg-01.ll

; Test 8-bit compare and swap. ; Test 8-bit compare and swap.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-MAIN ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT ; RUN: | FileCheck %s -check-prefix=CHECK-MAIN
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT
; Check compare and swap with a variable. ; Check compare and swap with a variable.
; - CHECK is for the main loop. ; - CHECK is for the main loop.
; - CHECK-SHIFT makes sure that the negated shift count used by the second ; - CHECK-SHIFT makes sure that the negated shift count used by the second
; RLL is set up correctly. The negation is independent of the NILL and L ; RLL is set up correctly. The negation is independent of the NILL and L
; tested in CHECK. CHECK-SHIFT also checks that %r3 is not modified before ; tested in CHECK. CHECK-SHIFT also checks that %r3 is not modified before
; being used in the RISBG (in contrast to things like atomic addition, ; being used in the RISBG (in contrast to things like atomic addition,
; which shift %r3 left so that %b is at the high end of the word). ; which shift %r3 left so that %b is at the high end of the word).
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llvm/test/CodeGen/SystemZ/cmpxchg-02.ll

; Test 16-bit compare and swap. ; Test 16-bit compare and swap.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-MAIN ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT ; RUN: | FileCheck %s -check-prefix=CHECK-MAIN
; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts \
; RUN: | FileCheck %s -check-prefix=CHECK-SHIFT
; Check compare and swap with a variable. ; Check compare and swap with a variable.
; - CHECK is for the main loop. ; - CHECK is for the main loop.
; - CHECK-SHIFT makes sure that the negated shift count used by the second ; - CHECK-SHIFT makes sure that the negated shift count used by the second
; RLL is set up correctly. The negation is independent of the NILL and L ; RLL is set up correctly. The negation is independent of the NILL and L
; tested in CHECK. CHECK-SHIFT also checks that %r3 is not modified before ; tested in CHECK. CHECK-SHIFT also checks that %r3 is not modified before
; being used in the RISBG (in contrast to things like atomic addition, ; being used in the RISBG (in contrast to things like atomic addition,
; which shift %r3 left so that %b is at the high end of the word). ; which shift %r3 left so that %b is at the high end of the word).
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llvm/test/CodeGen/SystemZ/cmpxchg-03.ll

; Test 32-bit compare and swap. ; Test 32-bit compare and swap.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; Check the low end of the CS range. ; Check the low end of the CS range.
define i32 @f1(i32 %cmp, i32 %swap, i32 *%src) { define i32 @f1(i32 %cmp, i32 %swap, i32 *%src) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: cs %r2, %r3, 0(%r4) ; CHECK: cs %r2, %r3, 0(%r4)
; CHECK: br %r14 ; CHECK: br %r14
%pair = cmpxchg i32 *%src, i32 %cmp, i32 %swap seq_cst seq_cst %pair = cmpxchg i32 *%src, i32 %cmp, i32 %swap seq_cst seq_cst
%val = extractvalue { i32, i1 } %pair, 0 %val = extractvalue { i32, i1 } %pair, 0
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llvm/test/CodeGen/SystemZ/cmpxchg-04.ll

; Test 64-bit compare and swap. ; Test 64-bit compare and swap.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; Check CSG without a displacement. ; Check CSG without a displacement.
define i64 @f1(i64 %cmp, i64 %swap, i64 *%src) { define i64 @f1(i64 %cmp, i64 %swap, i64 *%src) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: csg %r2, %r3, 0(%r4) ; CHECK: csg %r2, %r3, 0(%r4)
; CHECK: br %r14 ; CHECK: br %r14
%pairval = cmpxchg i64 *%src, i64 %cmp, i64 %swap seq_cst seq_cst %pairval = cmpxchg i64 *%src, i64 %cmp, i64 %swap seq_cst seq_cst
%val = extractvalue { i64, i1 } %pairval, 0 %val = extractvalue { i64, i1 } %pairval, 0
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llvm/test/CodeGen/SystemZ/cmpxchg-06.ll

; Test 64-bit compare and swap. ; Test 64-bit compare and swap.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; Check CDSG without a displacement. ; Check CDSG without a displacement.
define i128 @f1(i128 %cmp, i128 %swap, i128 *%src) { define i128 @f1(i128 %cmp, i128 %swap, i128 *%src) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK-DAG: lg %r1, 8(%r4) ; CHECK-DAG: lg %r1, 8(%r4)
; CHECK-DAG: lg %r0, 0(%r4) ; CHECK-DAG: lg %r0, 0(%r4)
; CHECK-DAG: lg %r13, 8(%r3) ; CHECK-DAG: lg %r13, 8(%r3)
; CHECK-DAG: lg %r12, 0(%r3) ; CHECK-DAG: lg %r12, 0(%r3)
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llvm/test/CodeGen/SystemZ/codegenprepare-form-OF-ops.ll

; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -O3 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -O3 -no-arg-exts \
; RUN: | FileCheck %s
; ;
; Check that CodeGenPrepare transforms these functions to use ; Check that CodeGenPrepare transforms these functions to use
; uadd.with.overflow / usub.with.overflow intrinsics so that the compare ; uadd.with.overflow / usub.with.overflow intrinsics so that the compare
; instruction is eliminated. ; instruction is eliminated.
define i32 @uaddo_32(i32 %arg) { define i32 @uaddo_32(i32 %arg) {
; CHECK-LABEL: uaddo_32: ; CHECK-LABEL: uaddo_32:
; CHECK: alhsik %r0, %r2, -1 ; CHECK: alhsik %r0, %r2, -1
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llvm/test/CodeGen/SystemZ/cond-move-02.ll

; Test LOCHI and LOCGHI. ; Test LOCHI and LOCGHI.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs \
; RUN: -no-arg-exts | FileCheck %s
; ;
; Run the test again to make sure it still works the same even ; Run the test again to make sure it still works the same even
; in the presence of the select instructions. ; in the presence of the select instructions.
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 -verify-machineinstrs \
; RUN: -no-arg-exts | FileCheck %s
define i32 @f1(i32 %x) { define i32 @f1(i32 %x) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: chi %r2, 0 ; CHECK: chi %r2, 0
; CHECK: lhi %r2, 0 ; CHECK: lhi %r2, 0
; CHECK: lochilh %r2, 42 ; CHECK: lochilh %r2, 42
; CHECK: br %r14 ; CHECK: br %r14
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llvm/test/CodeGen/SystemZ/cond-move-06.ll

; Test SELR and SELGR. ; Test SELR and SELGR.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 -verify-machineinstrs \
; RUN: -no-arg-exts | FileCheck %s
; Test SELR. ; Test SELR.
define i32 @f1(i32 %limit, i32 %a, i32 %b) { define i32 @f1(i32 %limit, i32 %a, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: clfi %r2, 42 ; CHECK: clfi %r2, 42
; CHECK: selrl %r2, %r3, %r4 ; CHECK: selrl %r2, %r3, %r4
; CHECK: br %r14 ; CHECK: br %r14
%cond = icmp ult i32 %limit, 42 %cond = icmp ult i32 %limit, 42
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llvm/test/CodeGen/SystemZ/ctpop-01.ll

; Test population-count instruction ; Test population-count instruction
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
declare i32 @llvm.ctpop.i32(i32 %a) declare i32 @llvm.ctpop.i32(i32 %a)
declare i64 @llvm.ctpop.i64(i64 %a) declare i64 @llvm.ctpop.i64(i64 %a)
define i32 @f1(i32 %a) { define i32 @f1(i32 %a) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: popcnt %r0, %r2 ; CHECK: popcnt %r0, %r2
; CHECK: sllk %r1, %r0, 16 ; CHECK: sllk %r1, %r0, 16
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llvm/test/CodeGen/SystemZ/fp-conv-09.ll

; Test conversion of floating-point values to signed i32s. ; Test conversion of floating-point values to signed i32s.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; Test f32->i32. ; Test f32->i32.
define i32 @f1(float %f) { define i32 @f1(float %f) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: cfebr %r2, 5, %f0 ; CHECK: cfebr %r2, 5, %f0
; CHECK: br %r14 ; CHECK: br %r14
%conv = fptosi float %f to i32 %conv = fptosi float %f to i32
ret i32 %conv ret i32 %conv
Show All 22 Lines

llvm/test/CodeGen/SystemZ/fp-conv-10.ll

Show All 11 Lines
define i32 @f1(float %f) { define i32 @f1(float %f) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: larl %r1, .LCPI0_0 ; CHECK-NEXT: larl %r1, .LCPI0_0
; CHECK-NEXT: le %f1, 0(%r1) ; CHECK-NEXT: le %f1, 0(%r1)
; CHECK-NEXT: cebr %f0, %f1 ; CHECK-NEXT: cebr %f0, %f1
; CHECK-NEXT: jnl .LBB0_2 ; CHECK-NEXT: jnl .LBB0_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: cfebr %r2, 5, %f0 ; CHECK-NEXT: cfebr %r0, 5, %f0
; CHECK-NEXT: lgfr %r2, %r0
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: sebr %f0, %f1 ; CHECK-NEXT: sebr %f0, %f1
; CHECK-NEXT: cfebr %r2, 5, %f0 ; CHECK-NEXT: cfebr %r0, 5, %f0
; CHECK-NEXT: xilf %r2, 2147483648 ; CHECK-NEXT: xilf %r0, 2147483648
; CHECK-NEXT: lgfr %r2, %r0
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%conv = fptoui float %f to i32 %conv = fptoui float %f to i32
ret i32 %conv ret i32 %conv
} }
; Test f64->i32. ; Test f64->i32.
define i32 @f2(double %f) { define i32 @f2(double %f) {
; CHECK-LABEL: f2: ; CHECK-LABEL: f2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: larl %r1, .LCPI1_0 ; CHECK-NEXT: larl %r1, .LCPI1_0
; CHECK-NEXT: ldeb %f1, 0(%r1) ; CHECK-NEXT: ldeb %f1, 0(%r1)
; CHECK-NEXT: cdbr %f0, %f1 ; CHECK-NEXT: cdbr %f0, %f1
; CHECK-NEXT: jnl .LBB1_2 ; CHECK-NEXT: jnl .LBB1_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: cfdbr %r2, 5, %f0 ; CHECK-NEXT: cfdbr %r0, 5, %f0
; CHECK-NEXT: lgfr %r2, %r0
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
; CHECK-NEXT: .LBB1_2: ; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: sdbr %f0, %f1 ; CHECK-NEXT: sdbr %f0, %f1
; CHECK-NEXT: cfdbr %r2, 5, %f0 ; CHECK-NEXT: cfdbr %r0, 5, %f0
; CHECK-NEXT: xilf %r2, 2147483648 ; CHECK-NEXT: xilf %r0, 2147483648
; CHECK-NEXT: lgfr %r2, %r0
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%conv = fptoui double %f to i32 %conv = fptoui double %f to i32
ret i32 %conv ret i32 %conv
} }
; Test f128->i32. ; Test f128->i32.
define i32 @f3(fp128 *%src) { define i32 @f3(fp128 *%src) {
; CHECK-LABEL: f3: ; CHECK-LABEL: f3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ld %f0, 0(%r2) ; CHECK-NEXT: ld %f0, 0(%r2)
; CHECK-NEXT: ld %f2, 8(%r2) ; CHECK-NEXT: ld %f2, 8(%r2)
; CHECK-NEXT: larl %r1, .LCPI2_0 ; CHECK-NEXT: larl %r1, .LCPI2_0
; CHECK-NEXT: lxeb %f1, 0(%r1) ; CHECK-NEXT: lxeb %f1, 0(%r1)
; CHECK-NEXT: cxbr %f0, %f1 ; CHECK-NEXT: cxbr %f0, %f1
; CHECK-NEXT: jnl .LBB2_2 ; CHECK-NEXT: jnl .LBB2_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: cfxbr %r2, 5, %f0 ; CHECK-NEXT: cfxbr %r0, 5, %f0
; CHECK-NEXT: lgfr %r2, %r0
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
; CHECK-NEXT: .LBB2_2: ; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: sxbr %f0, %f1 ; CHECK-NEXT: sxbr %f0, %f1
; CHECK-NEXT: cfxbr %r2, 5, %f0 ; CHECK-NEXT: cfxbr %r0, 5, %f0
; CHECK-NEXT: xilf %r2, 2147483648 ; CHECK-NEXT: xilf %r0, 2147483648
; CHECK-NEXT: lgfr %r2, %r0
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%f = load fp128, fp128 *%src %f = load fp128, fp128 *%src
%conv = fptoui fp128 %f to i32 %conv = fptoui fp128 %f to i32
ret i32 %conv ret i32 %conv
} }

llvm/test/CodeGen/SystemZ/fp-conv-14.ll

; Test conversion of floating-point values to unsigned integers. ; Test conversion of floating-point values to unsigned integers.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
; Test f32->i32. ; Test f32->i32.
define i32 @f1(float %f) { define i32 @f1(float %f) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: clfebr %r2, 5, %f0, 0 ; CHECK: clfebr %r2, 5, %f0, 0
; CHECK: br %r14 ; CHECK: br %r14
%conv = fptoui float %f to i32 %conv = fptoui float %f to i32
ret i32 %conv ret i32 %conv
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llvm/test/CodeGen/SystemZ/fp-conv-16.ll

; Test f128 floating-point conversion to/from integers on z14. ; Test f128 floating-point conversion to/from integers on z14.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -no-arg-exts | FileCheck %s
; Test signed i32->f128. ; Test signed i32->f128.
define void @f1(i32 %i, fp128 *%dst) { define void @f1(i32 %i, fp128 *%dst) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: cxfbr %f0, %r2 ; CHECK: cxfbr %f0, %r2
; CHECK: vmrhg %v0, %v0, %v2 ; CHECK: vmrhg %v0, %v0, %v2
; CHECK: vst %v0, 0(%r3) ; CHECK: vst %v0, 0(%r3)
; CHECK: br %r14 ; CHECK: br %r14
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llvm/test/CodeGen/SystemZ/fp-move-02.ll

; Test moves between FPRs and GPRs. The 32-bit cases test the z10 ; Test moves between FPRs and GPRs. The 32-bit cases test the z10
; implementation, which has no high-word support. ; implementation, which has no high-word support.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s
declare i64 @foo() declare i64 @foo()
declare double @bar() declare double @bar()
@dptr = external global double @dptr = external global double
@iptr = external global i64 @iptr = external global i64
; Test 32-bit moves from GPRs to FPRs. The GPR must be moved into the high ; Test 32-bit moves from GPRs to FPRs. The GPR must be moved into the high
; 32 bits of the FPR. ; 32 bits of the FPR.
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llvm/test/CodeGen/SystemZ/fp-strict-conv-09.ll

; Test strict conversion of floating-point values to signed i32s. ; Test strict conversion of floating-point values to signed i32s.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata) declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata)
declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata) declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
declare i32 @llvm.experimental.constrained.fptosi.i32.f128(fp128, metadata) declare i32 @llvm.experimental.constrained.fptosi.i32.f128(fp128, metadata)
; Test f32->i32. ; Test f32->i32.
define i32 @f1(float %f) #0 { define i32 @f1(float %f) #0 {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
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llvm/test/CodeGen/SystemZ/fp-strict-conv-10.ll

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; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lhi %r0, 0 ; CHECK-NEXT: lhi %r0, 0
; CHECK-NEXT: lzer %f1 ; CHECK-NEXT: lzer %f1
; CHECK-NEXT: j .LBB0_3 ; CHECK-NEXT: j .LBB0_3
; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: llilh %r0, 32768 ; CHECK-NEXT: llilh %r0, 32768
; CHECK-NEXT: .LBB0_3: ; CHECK-NEXT: .LBB0_3:
; CHECK-NEXT: sebr %f0, %f1 ; CHECK-NEXT: sebr %f0, %f1
; CHECK-NEXT: cfebr %r2, 5, %f0 ; CHECK-NEXT: cfebr %r1, 5, %f0
; CHECK-NEXT: xr %r2, %r0 ; CHECK-NEXT: xr %r1, %r0
; CHECK-NEXT: lgfr %r2, %r1
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%conv = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %f, %conv = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %f,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret i32 %conv ret i32 %conv
} }
; Test f64->i32. ; Test f64->i32.
define i32 @f2(double %f) #0 { define i32 @f2(double %f) #0 {
; CHECK-LABEL: f2: ; CHECK-LABEL: f2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: larl %r1, .LCPI1_0 ; CHECK-NEXT: larl %r1, .LCPI1_0
; CHECK-NEXT: ldeb %f1, 0(%r1) ; CHECK-NEXT: ldeb %f1, 0(%r1)
; CHECK-NEXT: kdbr %f0, %f1 ; CHECK-NEXT: kdbr %f0, %f1
; CHECK-NEXT: jnl .LBB1_2 ; CHECK-NEXT: jnl .LBB1_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lhi %r0, 0 ; CHECK-NEXT: lhi %r0, 0
; CHECK-NEXT: lzdr %f1 ; CHECK-NEXT: lzdr %f1
; CHECK-NEXT: j .LBB1_3 ; CHECK-NEXT: j .LBB1_3
; CHECK-NEXT: .LBB1_2: ; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: llilh %r0, 32768 ; CHECK-NEXT: llilh %r0, 32768
; CHECK-NEXT: .LBB1_3: ; CHECK-NEXT: .LBB1_3:
; CHECK-NEXT: sdbr %f0, %f1 ; CHECK-NEXT: sdbr %f0, %f1
; CHECK-NEXT: cfdbr %r2, 5, %f0 ; CHECK-NEXT: cfdbr %r1, 5, %f0
; CHECK-NEXT: xr %r2, %r0 ; CHECK-NEXT: xr %r1, %r0
; CHECK-NEXT: lgfr %r2, %r1
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%conv = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %f, %conv = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %f,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret i32 %conv ret i32 %conv
} }
; Test f128->i32. ; Test f128->i32.
define i32 @f3(fp128 *%src) #0 { define i32 @f3(fp128 *%src) #0 {
; CHECK-LABEL: f3: ; CHECK-LABEL: f3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ld %f0, 0(%r2) ; CHECK-NEXT: ld %f0, 0(%r2)
; CHECK-NEXT: ld %f2, 8(%r2) ; CHECK-NEXT: ld %f2, 8(%r2)
; CHECK-NEXT: larl %r1, .LCPI2_0 ; CHECK-NEXT: larl %r1, .LCPI2_0
; CHECK-NEXT: lxeb %f1, 0(%r1) ; CHECK-NEXT: lxeb %f1, 0(%r1)
; CHECK-NEXT: kxbr %f0, %f1 ; CHECK-NEXT: kxbr %f0, %f1
; CHECK-NEXT: jnl .LBB2_2 ; CHECK-NEXT: jnl .LBB2_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lhi %r0, 0 ; CHECK-NEXT: lhi %r0, 0
; CHECK-NEXT: lzxr %f1 ; CHECK-NEXT: lzxr %f1
; CHECK-NEXT: j .LBB2_3 ; CHECK-NEXT: j .LBB2_3
; CHECK-NEXT: .LBB2_2: ; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: llilh %r0, 32768 ; CHECK-NEXT: llilh %r0, 32768
; CHECK-NEXT: .LBB2_3: ; CHECK-NEXT: .LBB2_3:
; CHECK-NEXT: sxbr %f0, %f1 ; CHECK-NEXT: sxbr %f0, %f1
; CHECK-NEXT: cfxbr %r2, 5, %f0 ; CHECK-NEXT: cfxbr %r1, 5, %f0
; CHECK-NEXT: xr %r2, %r0 ; CHECK-NEXT: xr %r1, %r0
; CHECK-NEXT: lgfr %r2, %r1
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%f = load fp128, fp128 *%src %f = load fp128, fp128 *%src
%conv = call i32 @llvm.experimental.constrained.fptoui.i32.f128(fp128 %f, %conv = call i32 @llvm.experimental.constrained.fptoui.i32.f128(fp128 %f,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret i32 %conv ret i32 %conv
} }
attributes #0 = { strictfp } attributes #0 = { strictfp }

llvm/test/CodeGen/SystemZ/fp-strict-conv-14.ll

; Test strict conversion of floating-point values to unsigned integers. ; Test strict conversion of floating-point values to unsigned integers.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata) declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)
declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata) declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)
declare i32 @llvm.experimental.constrained.fptoui.i32.f128(fp128, metadata) declare i32 @llvm.experimental.constrained.fptoui.i32.f128(fp128, metadata)
declare i64 @llvm.experimental.constrained.fptoui.i64.f32(float, metadata) declare i64 @llvm.experimental.constrained.fptoui.i64.f32(float, metadata)
declare i64 @llvm.experimental.constrained.fptoui.i64.f64(double, metadata) declare i64 @llvm.experimental.constrained.fptoui.i64.f64(double, metadata)
declare i64 @llvm.experimental.constrained.fptoui.i64.f128(fp128, metadata) declare i64 @llvm.experimental.constrained.fptoui.i64.f128(fp128, metadata)
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llvm/test/CodeGen/SystemZ/fp-strict-conv-16.ll

; Test f128 floating-point strict conversion to/from integers on z14. ; Test f128 floating-point strict conversion to/from integers on z14.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -no-arg-exts | FileCheck %s
declare fp128 @llvm.experimental.constrained.sitofp.f128.i32(i32, metadata, metadata) declare fp128 @llvm.experimental.constrained.sitofp.f128.i32(i32, metadata, metadata)
declare fp128 @llvm.experimental.constrained.sitofp.f128.i64(i64, metadata, metadata) declare fp128 @llvm.experimental.constrained.sitofp.f128.i64(i64, metadata, metadata)
declare fp128 @llvm.experimental.constrained.uitofp.f128.i32(i32, metadata, metadata) declare fp128 @llvm.experimental.constrained.uitofp.f128.i32(i32, metadata, metadata)
declare fp128 @llvm.experimental.constrained.uitofp.f128.i64(i64, metadata, metadata) declare fp128 @llvm.experimental.constrained.uitofp.f128.i64(i64, metadata, metadata)
declare i32 @llvm.experimental.constrained.fptosi.i32.f128(fp128, metadata) declare i32 @llvm.experimental.constrained.fptosi.i32.f128(fp128, metadata)
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llvm/test/CodeGen/SystemZ/fpc-intrinsics.ll

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; CHECK: br %r14 ; CHECK: br %r14
call void @llvm.s390.sfpc(i32 %fpc) call void @llvm.s390.sfpc(i32 %fpc)
ret void ret void
} }
; EFPC. ; EFPC.
define i32 @test_efpc() { define i32 @test_efpc() {
; CHECK-LABEL: test_efpc: ; CHECK-LABEL: test_efpc:
; CHECK: efpc %r2 ; CHECK: efpc %r0
; CHECK: lgfr %r2, %r0
; CHECK: br %r14 ; CHECK: br %r14
%res = call i32 @llvm.s390.efpc() %res = call i32 @llvm.s390.efpc()
ret i32 %res ret i32 %res
} }
; LFPC. ; LFPC.
define void @test_lfpc1(i32 *%ptr) { define void @test_lfpc1(i32 *%ptr) {
; CHECK-LABEL: test_lfpc1: ; CHECK-LABEL: test_lfpc1:
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llvm/test/CodeGen/SystemZ/htm-intrinsics.ll

; Test transactional-execution intrinsics. ; Test transactional-execution intrinsics.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 -no-arg-exts | FileCheck %s
declare i32 @llvm.s390.tbegin(i8 *, i32) declare i32 @llvm.s390.tbegin(i8 *, i32)
declare i32 @llvm.s390.tbegin.nofloat(i8 *, i32) declare i32 @llvm.s390.tbegin.nofloat(i8 *, i32)
declare void @llvm.s390.tbeginc(i8 *, i32) declare void @llvm.s390.tbeginc(i8 *, i32)
declare i32 @llvm.s390.tend() declare i32 @llvm.s390.tend()
declare void @llvm.s390.tabort(i64) declare void @llvm.s390.tabort(i64)
declare void @llvm.s390.ntstg(i64, i64 *) declare void @llvm.s390.ntstg(i64, i64 *)
declare i32 @llvm.s390.etnd() declare i32 @llvm.s390.etnd()
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llvm/test/CodeGen/SystemZ/inline-asm-i128.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=s390x-linux-gnu -no-integrated-as < %s | FileCheck %s ; RUN: llc -mtriple=s390x-linux-gnu -no-integrated-as -no-arg-exts < %s \
; RUN: | FileCheck %s
; ;
; Test i128 (tied) operands. ; Test i128 (tied) operands.
define i32 @fun0(i8* %p1, i32 signext %l1, i8* %p2, i32 signext %l2, i8 zeroext %pad) { define i32 @fun0(i8* %p1, i32 signext %l1, i8* %p2, i32 signext %l2, i8 zeroext %pad) {
; CHECK-LABEL: fun0: ; CHECK-LABEL: fun0:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgr %r0, %r5 ; CHECK-NEXT: lgr %r0, %r5
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llvm/test/CodeGen/SystemZ/insert-01.ll

; Test insertions of memory into the low byte of an i32. ; Test insertions of memory into the low byte of an i32.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; Check a plain insertion with (or (and ... -0xff) (zext (load ....))). ; Check a plain insertion with (or (and ... -0xff) (zext (load ....))).
; The whole sequence can be performed by IC. ; The whole sequence can be performed by IC.
define i32 @f1(i32 %orig, i8 *%ptr) { define i32 @f1(i32 %orig, i8 *%ptr) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK-NOT: ni ; CHECK-NOT: ni
; CHECK: ic %r2, 0(%r3) ; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14 ; CHECK: br %r14
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llvm/test/CodeGen/SystemZ/int-abs-01.ll

; Test integer absolute. ; Test integer absolute.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; Test i32->i32 absolute using slt. ; Test i32->i32 absolute using slt.
define i32 @f1(i32 %val) { define i32 @f1(i32 %val) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lpr %r2, %r2 ; CHECK: lpr %r2, %r2
; CHECK: br %r14 ; CHECK: br %r14
%cmp = icmp slt i32 %val, 0 %cmp = icmp slt i32 %val, 0
%neg = sub i32 0, %val %neg = sub i32 0, %val
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llvm/test/CodeGen/SystemZ/int-add-13.ll

; Test the three-operand forms of addition. ; Test the three-operand forms of addition.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
; Check ARK. ; Check ARK.
define i32 @f1(i32 %a, i32 %b, i32 %c) { define i32 @f1(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: ark %r2, %r3, %r4 ; CHECK: ark %r2, %r3, %r4
; CHECK: br %r14 ; CHECK: br %r14
%add = add i32 %b, %c %add = add i32 %b, %c
ret i32 %add ret i32 %add
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llvm/test/CodeGen/SystemZ/int-add-14.ll

; Test 32-bit addition in which the second operand is constant and in which ; Test 32-bit addition in which the second operand is constant and in which
; three-operand forms are available. ; three-operand forms are available.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
; Check additions of 1. ; Check additions of 1.
define i32 @f1(i32 %a, i32 %b) { define i32 @f1(i32 %a, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: ahik %r2, %r3, 1 ; CHECK: ahik %r2, %r3, 1
; CHECK: br %r14 ; CHECK: br %r14
%add = add i32 %b, 1 %add = add i32 %b, 1
ret i32 %add ret i32 %add
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llvm/test/CodeGen/SystemZ/int-cmp-36.ll

; Test 32-bit comparisons in which the second operand is sign-extended ; Test 32-bit comparisons in which the second operand is sign-extended
; from a PC-relative i16. ; from a PC-relative i16.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
@g = dso_local global i16 1 @g = dso_local global i16 1
@h = dso_local global i16 1, align 1, section "foo" @h = dso_local global i16 1, align 1, section "foo"
; Check signed comparison. ; Check signed comparison.
define dso_local i32 @f1(i32 %src1) { define dso_local i32 @f1(i32 %src1) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: chrl %r2, g ; CHECK: chrl %r2, g
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llvm/test/CodeGen/SystemZ/int-cmp-38.ll

; Test 32-bit comparisons in which the second operand is a PC-relative ; Test 32-bit comparisons in which the second operand is a PC-relative
; variable. ; variable.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
@g = dso_local global i32 1 @g = dso_local global i32 1
@h = dso_local global i32 1, align 2, section "foo" @h = dso_local global i32 1, align 2, section "foo"
; Check signed comparisons. ; Check signed comparisons.
define dso_local i32 @f1(i32 %src1) { define dso_local i32 @f1(i32 %src1) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: crl %r2, g ; CHECK: crl %r2, g
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llvm/test/CodeGen/SystemZ/int-cmp-44.ll

; Test that compares are omitted if CC already has the right value ; Test that compares are omitted if CC already has the right value
; (z10 version). ; (z10 version).
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-integrated-as \ ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-integrated-as \
; RUN: -verify-machineinstrs| FileCheck %s ; RUN: -verify-machineinstrs -no-arg-exts | FileCheck %s
declare void @foo() declare void @foo()
; Addition provides enough for comparisons with zero if we know no ; Addition provides enough for comparisons with zero if we know no
; signed overflow happens, which is when the "nsw" flag is set. ; signed overflow happens, which is when the "nsw" flag is set.
; First test the EQ case. ; First test the EQ case.
define i32 @f1(i32 %a, i32 %b, i32 *%dest) { define i32 @f1(i32 %a, i32 %b, i32 *%dest) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
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llvm/test/CodeGen/SystemZ/int-cmp-45.ll

; Test that compares are omitted if CC already has the right value ; Test that compares are omitted if CC already has the right value
; (z196 version). ; (z196 version).
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-integrated-as | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-integrated-as \
; RUN: -no-arg-exts | FileCheck %s
; Addition provides enough for comparisons with zero if we know no ; Addition provides enough for comparisons with zero if we know no
; signed overflow happens, which is when the "nsw" flag is set. ; signed overflow happens, which is when the "nsw" flag is set.
; First test the EQ case with LOC. ; First test the EQ case with LOC.
define i32 @f1(i32 %a, i32 %b, i32 *%cptr) { define i32 @f1(i32 %a, i32 %b, i32 *%cptr) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: afi %r2, 1000000 ; CHECK: afi %r2, 1000000
; CHECK-NEXT: loce %r3, 0(%r4) ; CHECK-NEXT: loce %r3, 0(%r4)
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llvm/test/CodeGen/SystemZ/int-cmp-57.ll

; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -disable-cgp | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -disable-cgp -no-arg-exts \
; RUN: | FileCheck %s
; ;
; Check that signed comparisons against 0 are eliminated if the defining ; Check that signed comparisons against 0 are eliminated if the defining
; instruction is an add with immediate. ; instruction is an add with immediate.
; ;
; Addition of an immediate does not depend on the "nsw" flag, since the ; Addition of an immediate does not depend on the "nsw" flag, since the
; result can be predicted in case of overflow. For example, if adding a ; result can be predicted in case of overflow. For example, if adding a
; positive immediate gives overflow, the result must be negative. ; positive immediate gives overflow, the result must be negative.
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llvm/test/CodeGen/SystemZ/int-cmp-61.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
; ;
; Test using bitwise logic on icmp operands instead of i1 logic when ; Test using bitwise logic on icmp operands instead of i1 logic when
; possible. ; possible.
define i32 @fun(i32* %Src) { define i32 @fun(i32* %Src) {
; CHECK-LABEL: fun: ; CHECK-LABEL: fun:
; CHECK: # %bb.0: # %bb ; CHECK: # %bb.0: # %bb
; CHECK-NEXT: lhi %r0, -2 ; CHECK-NEXT: lhi %r0, -2
; CHECK-NEXT: s %r0, 0(%r2) ; CHECK-NEXT: s %r0, 0(%r2)
; CHECK-NEXT: nill %r0, 65533 ; CHECK-NEXT: nill %r0, 65533
; CHECK-NEXT: chi %r0, 0 ; CHECK-NEXT: chi %r0, 0
; CHECK-NEXT: lhi %r2, 0 ; CHECK-NEXT: lghi %r2, 0
; CHECK-NEXT: lochilh %r2, 1 ; CHECK-NEXT: locghilh %r2, 1
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
bb: bb:
%i = load i32, i32* %Src %i = load i32, i32* %Src
%i3 = sub nsw i32 0, %i %i3 = sub nsw i32 0, %i
%i4 = icmp ne i32 %i3, 2 %i4 = icmp ne i32 %i3, 2
%i5 = icmp ne i32 %i3, 4 %i5 = icmp ne i32 %i3, 4
%i6 = and i1 %i4, %i5 %i6 = and i1 %i4, %i5
%i7 = zext i1 %i6 to i32 %i7 = zext i1 %i6 to i32
ret i32 %i7 ret i32 %i7
} }

llvm/test/CodeGen/SystemZ/int-const-01.ll

; Test loading of 32-bit constants. ; Test loading of 32-bit constants.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
declare void @foo(i32, i32, i32, i32) declare void @foo(i32, i32, i32, i32)
; Check 0. ; Check 0.
define i32 @f1() { define i32 @f1() {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lhi %r2, 0 ; CHECK: lhi %r2, 0
; CHECK: br %r14 ; CHECK: br %r14
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llvm/test/CodeGen/SystemZ/int-conv-01.ll

; Test sign extensions from a byte to an i32. ; Test sign extensions from a byte to an i32.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; Test register extension, starting with an i32. ; Test register extension, starting with an i32.
define i32 @f1(i32 %a) { define i32 @f1(i32 %a) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lbr %r2, %r2 ; CHECK: lbr %r2, %r2
; CHECK: br %r14 ; CHECK: br %r14
%byte = trunc i32 %a to i8 %byte = trunc i32 %a to i8
%ext = sext i8 %byte to i32 %ext = sext i8 %byte to i32
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llvm/test/CodeGen/SystemZ/int-conv-02.ll

; Test zero extensions from a byte to an i32. The tests here ; Test zero extensions from a byte to an i32. The tests here
; assume z10 register pressure, without the high words being available. ; assume z10 register pressure, without the high words being available.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s
; Test register extension, starting with an i32. ; Test register extension, starting with an i32.
define i32 @f1(i32 %a) { define i32 @f1(i32 %a) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: llcr %r2, %r2 ; CHECK: llcr %r2, %r2
; CHECK: br %r14 ; CHECK: br %r14
%byte = trunc i32 %a to i8 %byte = trunc i32 %a to i8
%ext = zext i8 %byte to i32 %ext = zext i8 %byte to i32
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llvm/test/CodeGen/SystemZ/int-conv-05.ll

; Test sign extensions from a halfword to an i32. ; Test sign extensions from a halfword to an i32.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; Test register extension, starting with an i32. ; Test register extension, starting with an i32.
define i32 @f1(i32 %a) { define i32 @f1(i32 %a) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lhr %r2, %r2 ; CHECK: lhr %r2, %r2
; CHECK: br %r14 ; CHECK: br %r14
%half = trunc i32 %a to i16 %half = trunc i32 %a to i16
%ext = sext i16 %half to i32 %ext = sext i16 %half to i32
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llvm/test/CodeGen/SystemZ/int-conv-06.ll

; Test zero extensions from a halfword to an i32. The tests here ; Test zero extensions from a halfword to an i32. The tests here
; assume z10 register pressure, without the high words being available. ; assume z10 register pressure, without the high words being available.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s
; Test register extension, starting with an i32. ; Test register extension, starting with an i32.
define i32 @f1(i32 %a) { define i32 @f1(i32 %a) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: llhr %r2, %r2 ; CHECK: llhr %r2, %r2
; CHECK: br %r14 ; CHECK: br %r14
%half = trunc i32 %a to i16 %half = trunc i32 %a to i16
%ext = zext i16 %half to i32 %ext = zext i16 %half to i32
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llvm/test/CodeGen/SystemZ/int-conv-13.ll

; Test load and zero rightmost byte. ; Test load and zero rightmost byte.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -no-arg-exts | FileCheck %s
; Check LZRF with no displacement. ; Check LZRF with no displacement.
define i32 @f1(i32 *%src) { define i32 @f1(i32 *%src) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lzrf %r2, 0(%r2) ; CHECK: lzrf %r2, 0(%r2)
; CHECK: br %r14 ; CHECK: br %r14
%val = load i32, i32 *%src %val = load i32, i32 *%src
%and = and i32 %val, 4294967040 %and = and i32 %val, 4294967040
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llvm/test/CodeGen/SystemZ/int-div-01.ll

; Test 32-bit signed division and remainder. ; Test 32-bit signed division and remainder.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 -no-arg-exts \
; RUN: | FileCheck %s
declare i32 @foo() declare i32 @foo()
; Test register division. The result is in the second of the two registers. ; Test register division. The result is in the second of the two registers.
define void @f1(i32 *%dest, i32 %a, i32 %b) { define void @f1(i32 *%dest, i32 %a, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lgfr %r1, %r3 ; CHECK: lgfr %r1, %r3
; CHECK: dsgfr %r0, %r4 ; CHECK: dsgfr %r0, %r4
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llvm/test/CodeGen/SystemZ/int-div-06.ll

; Test that divisions by constants are implemented as multiplications. ; Test that divisions by constants are implemented as multiplications.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s
; Check signed 32-bit division. ; Check signed 32-bit division.
define i32 @f1(i32 %a) { define i32 @f1(i32 %a) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lgfr [[REG:%r[0-5]]], %r2 ; CHECK: lgfr [[REG:%r[0-5]]], %r2
; CHECK: msgfi [[REG]], 502748801 ; CHECK: msgfi [[REG]], 502748801
; CHECK-DAG: srlg [[RES1:%r[0-5]]], [[REG]], 63 ; CHECK-DAG: srlg [[RES1:%r[0-5]]], [[REG]], 63
; CHECK-DAG: srag %r2, [[REG]], 46 ; CHECK-DAG: srag %r0, [[REG]], 46
; CHECK: ar %r2, [[RES1]] ; CHECK: ar %r0, [[RES1]]
; CHECK: lgfr %r2, %r0
; CHECK: br %r14 ; CHECK: br %r14
%b = sdiv i32 %a, 139968 %b = sdiv i32 %a, 139968
ret i32 %b ret i32 %b
} }
; Check unsigned 32-bit division. ; Check unsigned 32-bit division.
define i32 @f2(i32 %a) { define i32 @f2(i32 %a) {
; CHECK-LABEL: f2: ; CHECK-LABEL: f2:
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llvm/test/CodeGen/SystemZ/int-move-01.ll

; Test moves between GPRs. ; Test moves between GPRs.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; Test 8-bit moves, which should get promoted to i32. ; Test 8-bit moves, which should get promoted to i32.
define i8 @f1(i8 %a, i8 %b) { define i8 @f1(i8 %a, i8 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lr %r2, %r3 ; CHECK: lr %r2, %r3
; CHECK: br %r14 ; CHECK: br %r14
ret i8 %b ret i8 %b
} }
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llvm/test/CodeGen/SystemZ/int-move-02.ll

; Test 32-bit GPR loads. ; Test 32-bit GPR loads.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; Check the low end of the L range. ; Check the low end of the L range.
define i32 @f1(i32 *%src) { define i32 @f1(i32 *%src) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r2) ; CHECK: l %r2, 0(%r2)
; CHECK: br %r14 ; CHECK: br %r14
%val = load i32, i32 *%src %val = load i32, i32 *%src
ret i32 %val ret i32 %val
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llvm/test/CodeGen/SystemZ/int-move-08.ll

; Test 32-bit GPR accesses to a PC-relative location. ; Test 32-bit GPR accesses to a PC-relative location.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
@gsrc16 = dso_local global i16 1 @gsrc16 = dso_local global i16 1
@gsrc32 = dso_local global i32 1 @gsrc32 = dso_local global i32 1
@gdst16 = dso_local global i16 2 @gdst16 = dso_local global i16 2
@gdst32 = dso_local global i32 2 @gdst32 = dso_local global i32 2
@gsrc16u = dso_local global i16 1, align 1, section "foo" @gsrc16u = dso_local global i16 1, align 1, section "foo"
@gsrc32u = dso_local global i32 1, align 2, section "foo" @gsrc32u = dso_local global i32 1, align 2, section "foo"
@gdst16u = dso_local global i16 2, align 1, section "foo" @gdst16u = dso_local global i16 2, align 1, section "foo"
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llvm/test/CodeGen/SystemZ/int-move-10.ll

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} }
;;; Loads ;;; Loads
; unaligned packed struct + 2 -> unaligned address ; unaligned packed struct + 2 -> unaligned address
define dso_local i32 @f9() { define dso_local i32 @f9() {
; CHECK-LABEL: f9: ; CHECK-LABEL: f9:
; CHECK: larl %r1, A_align2 ; CHECK: larl %r1, A_align2
; CHECK: l %r2, 2(%r1) ; CHECK: lgf %r2, 2(%r1)
; CHECK: br %r14 ; CHECK: br %r14
%L = load i32, i32* getelementptr inbounds (%packed.i16i32, %packed.i16i32* @A_align2, i64 0, i32 1), align 4 %L = load i32, i32* getelementptr inbounds (%packed.i16i32, %packed.i16i32* @A_align2, i64 0, i32 1), align 4
ret i32 %L ret i32 %L
} }
; unaligned packed struct + 8 -> unaligned address ; unaligned packed struct + 8 -> unaligned address
define dso_local i32 @f10() { define dso_local i32 @f10() {
; CHECK-LABEL: f10: ; CHECK-LABEL: f10:
; CHECK: larl %r1, B_align2 ; CHECK: larl %r1, B_align2
; CHECK: l %r2, 8(%r1) ; CHECK: lgf %r2, 8(%r1)
; CHECK: br %r14 ; CHECK: br %r14
%L = load i32, i32* getelementptr inbounds (%packed.i16i32i16i32, %packed.i16i32i16i32* @B_align2, i64 0, i32 3), align 4 %L = load i32, i32* getelementptr inbounds (%packed.i16i32i16i32, %packed.i16i32i16i32* @B_align2, i64 0, i32 3), align 4
ret i32 %L ret i32 %L
} }
; aligned packed struct + 2 -> unaligned address ; aligned packed struct + 2 -> unaligned address
define dso_local i32 @f11() { define dso_local i32 @f11() {
; CHECK-LABEL: f11: ; CHECK-LABEL: f11:
; CHECK: larl %r1, D_align4 ; CHECK: larl %r1, D_align4
; CHECK: l %r2, 2(%r1) ; CHECK: lgf %r2, 2(%r1)
; CHECK: br %r14 ; CHECK: br %r14
%L = load i32, i32* getelementptr inbounds (%packed.i16i32, %packed.i16i32* @D_align4, i64 0, i32 1), align 4 %L = load i32, i32* getelementptr inbounds (%packed.i16i32, %packed.i16i32* @D_align4, i64 0, i32 1), align 4
ret i32 %L ret i32 %L
} }
; aligned packed struct + 8 -> aligned address ; aligned packed struct + 8 -> aligned address
define dso_local i32 @f12() { define dso_local i32 @f12() {
; CHECK-LABEL: f12: ; CHECK-LABEL: f12:
; CHECK: lrl %r2, E_align4+8 ; CHECK: lgfrl %r2, E_align4+8
; CHECK: br %r14 ; CHECK: br %r14
%L = load i32, i32* getelementptr inbounds (%packed.i16i32i16i32, %packed.i16i32i16i32* @E_align4, i64 0, i32 3), align 4 %L = load i32, i32* getelementptr inbounds (%packed.i16i32i16i32, %packed.i16i32i16i32* @E_align4, i64 0, i32 3), align 4
ret i32 %L ret i32 %L
} }
define dso_local i64 @f13() { define dso_local i64 @f13() {
; CHECK-LABEL: f13: ; CHECK-LABEL: f13:
; CHECK: larl %r1, C_align2 ; CHECK: larl %r1, C_align2
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llvm/test/CodeGen/SystemZ/int-mul-05.ll

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; CHECK: br %r14 ; CHECK: br %r14
%mul = mul i32 %a, 2147483649 %mul = mul i32 %a, 2147483649
ret i32 %mul ret i32 %mul
} }
; Check multiplication by -1, which is a negation. ; Check multiplication by -1, which is a negation.
define i32 @f9(i32 %a, i32 *%dest) { define i32 @f9(i32 %a, i32 *%dest) {
; CHECK-LABEL: f9: ; CHECK-LABEL: f9:
; CHECK: lcr %r2, %r2 ; CHECK: lcr %r0, %r2
; CHECK: lgfr %r2, %r0
; CHECK: br %r14 ; CHECK: br %r14
%mul = mul i32 %a, -1 %mul = mul i32 %a, -1
ret i32 %mul ret i32 %mul
} }
; Check multiplication by -2, which should use shifts. ; Check multiplication by -2, which should use shifts.
define i32 @f10(i32 %a, i32 *%dest) { define i32 @f10(i32 %a, i32 *%dest) {
; CHECK-LABEL: f10: ; CHECK-LABEL: f10:
; CHECK: sll %r2, 1 ; CHECK: sll %r2, 1
; CHECK: lcr %r2, %r2 ; CHECK: lcr %r0, %r2
; CHECK: lgfr %r2, %r0
; CHECK: br %r14 ; CHECK: br %r14
%mul = mul i32 %a, -2 %mul = mul i32 %a, -2
ret i32 %mul ret i32 %mul
} }
; Check multiplication by -3. ; Check multiplication by -3.
define i32 @f11(i32 %a, i32 *%dest) { define i32 @f11(i32 %a, i32 *%dest) {
; CHECK-LABEL: f11: ; CHECK-LABEL: f11:
Show All 11 Lines; CHECK: br %r14
%mul = mul i32 %a, -32767 %mul = mul i32 %a, -32767
ret i32 %mul ret i32 %mul
} }
; Check the next value down, which should use shifts. ; Check the next value down, which should use shifts.
define i32 @f13(i32 %a, i32 *%dest) { define i32 @f13(i32 %a, i32 *%dest) {
; CHECK-LABEL: f13: ; CHECK-LABEL: f13:
; CHECK: sll %r2, 15 ; CHECK: sll %r2, 15
; CHECK: lcr %r2, %r2 ; CHECK: lcr %r0, %r2
; CHECK: lgfr %r2, %r0
; CHECK: br %r14 ; CHECK: br %r14
%mul = mul i32 %a, -32768 %mul = mul i32 %a, -32768
ret i32 %mul ret i32 %mul
} }
; Check the next value down again, which can use MSFI. ; Check the next value down again, which can use MSFI.
define i32 @f14(i32 %a, i32 *%dest) { define i32 @f14(i32 %a, i32 *%dest) {
; CHECK-LABEL: f14: ; CHECK-LABEL: f14:
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llvm/test/CodeGen/SystemZ/int-mul-11.ll

; Test three-operand multiplication instructions on z14. ; Test three-operand multiplication instructions on z14.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
; Check MSRKC. ; Check MSRKC.
define i32 @f1(i32 %dummy, i32 %a, i32 %b) { define i32 @f1(i32 %dummy, i32 %a, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: msrkc %r2, %r3, %r4 ; CHECK: msrkc %r0, %r3, %r4
; CHECK: lgfr %r2, %r0
; CHECK: br %r14 ; CHECK: br %r14
%mul = mul i32 %a, %b %mul = mul i32 %a, %b
ret i32 %mul ret i32 %mul
} }
; Check MSGRKC. ; Check MSGRKC.
define i64 @f2(i64 %dummy, i64 %a, i64 %b) { define i64 @f2(i64 %dummy, i64 %a, i64 %b) {
; CHECK-LABEL: f2: ; CHECK-LABEL: f2:
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llvm/test/CodeGen/SystemZ/int-neg-01.ll

; Test integer negation. ; Test integer negation.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; Test i32->i32 negation. ; Test i32->i32 negation.
define i32 @f1(i32 %val) { define i32 @f1(i32 %val) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lcr %r2, %r2 ; CHECK: lcr %r0, %r2
; CHECK: lgfr %r2, %r0
; CHECK: br %r14 ; CHECK: br %r14
%neg = sub i32 0, %val %neg = sub i32 0, %val
ret i32 %neg ret i32 %neg
} }
; Test i32->i64 negation. ; Test i32->i64 negation.
define i64 @f2(i32 %val) { define i64 @f2(i32 %val) {
; CHECK-LABEL: f2: ; CHECK-LABEL: f2:
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llvm/test/CodeGen/SystemZ/int-neg-02.ll

; Test negative integer absolute. ; Test negative integer absolute.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; Test i32->i32 negative absolute using slt. ; Test i32->i32 negative absolute using slt.
define i32 @f1(i32 %val) { define i32 @f1(i32 %val) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lnr %r2, %r2 ; CHECK: lnr %r0, %r2
; CHECK: lgfr %r2, %r0
; CHECK: br %r14 ; CHECK: br %r14
%cmp = icmp slt i32 %val, 0 %cmp = icmp slt i32 %val, 0
%neg = sub i32 0, %val %neg = sub i32 0, %val
%abs = select i1 %cmp, i32 %neg, i32 %val %abs = select i1 %cmp, i32 %neg, i32 %val
%res = sub i32 0, %abs %res = sub i32 0, %abs
ret i32 %res ret i32 %res
} }
; Test i32->i32 negative absolute using sle. ; Test i32->i32 negative absolute using sle.
define i32 @f2(i32 %val) { define i32 @f2(i32 %val) {
; CHECK-LABEL: f2: ; CHECK-LABEL: f2:
; CHECK: lnr %r2, %r2 ; CHECK: lnr %r0, %r2
; CHECK: lgfr %r2, %r0
; CHECK: br %r14 ; CHECK: br %r14
%cmp = icmp sle i32 %val, 0 %cmp = icmp sle i32 %val, 0
%neg = sub i32 0, %val %neg = sub i32 0, %val
%abs = select i1 %cmp, i32 %neg, i32 %val %abs = select i1 %cmp, i32 %neg, i32 %val
%res = sub i32 0, %abs %res = sub i32 0, %abs
ret i32 %res ret i32 %res
} }
; Test i32->i32 negative absolute using sgt. ; Test i32->i32 negative absolute using sgt.
define i32 @f3(i32 %val) { define i32 @f3(i32 %val) {
; CHECK-LABEL: f3: ; CHECK-LABEL: f3:
; CHECK: lnr %r2, %r2 ; CHECK: lnr %r0, %r2
; CHECK: lgfr %r2, %r0
; CHECK: br %r14 ; CHECK: br %r14
%cmp = icmp sgt i32 %val, 0 %cmp = icmp sgt i32 %val, 0
%neg = sub i32 0, %val %neg = sub i32 0, %val
%abs = select i1 %cmp, i32 %val, i32 %neg %abs = select i1 %cmp, i32 %val, i32 %neg
%res = sub i32 0, %abs %res = sub i32 0, %abs
ret i32 %res ret i32 %res
} }
; Test i32->i32 negative absolute using sge. ; Test i32->i32 negative absolute using sge.
define i32 @f4(i32 %val) { define i32 @f4(i32 %val) {
; CHECK-LABEL: f4: ; CHECK-LABEL: f4:
; CHECK: lnr %r2, %r2 ; CHECK: lnr %r0, %r2
; CHECK: lgfr %r2, %r0
; CHECK: br %r14 ; CHECK: br %r14
%cmp = icmp sge i32 %val, 0 %cmp = icmp sge i32 %val, 0
%neg = sub i32 0, %val %neg = sub i32 0, %val
%abs = select i1 %cmp, i32 %val, i32 %neg %abs = select i1 %cmp, i32 %val, i32 %neg
%res = sub i32 0, %abs %res = sub i32 0, %abs
ret i32 %res ret i32 %res
} }
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llvm/test/CodeGen/SystemZ/int-sub-08.ll

; Test the three-operand forms of subtraction. ; Test the three-operand forms of subtraction.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
; Check SRK. ; Check SRK.
define i32 @f1(i32 %a, i32 %b, i32 %c) { define i32 @f1(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: srk %r2, %r3, %r4 ; CHECK: srk %r2, %r3, %r4
; CHECK: br %r14 ; CHECK: br %r14
%sub = sub i32 %b, %c %sub = sub i32 %b, %c
ret i32 %sub ret i32 %sub
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llvm/test/CodeGen/SystemZ/int-uadd-06.ll

; Test the three-operand form of 32-bit addition. ; Test the three-operand form of 32-bit addition.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
declare i32 @foo(i32, i32, i32) declare i32 @foo(i32, i32, i32)
; Check ALRK. ; Check ALRK.
define i32 @f1(i32 %dummy, i32 %a, i32 %b, i32 *%flag) { define i32 @f1(i32 %dummy, i32 %a, i32 %b, i32 *%flag) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: alrk %r2, %r3, %r4 ; CHECK: alrk %r2, %r3, %r4
; CHECK: ipm [[REG1:%r[0-5]]] ; CHECK: ipm [[REG1:%r[0-5]]]
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llvm/test/CodeGen/SystemZ/int-usub-06.ll

; Test the three-operand form of 32-bit subtraction. ; Test the three-operand form of 32-bit subtraction.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
declare i32 @foo(i32, i32, i32) declare i32 @foo(i32, i32, i32)
; Check SLRK. ; Check SLRK.
define i32 @f1(i32 %dummy, i32 %a, i32 %b, i32 *%flag) { define i32 @f1(i32 %dummy, i32 %a, i32 %b, i32 *%flag) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: slrk %r2, %r3, %r4 ; CHECK: slrk %r2, %r3, %r4
; CHECK: ipm [[REG:%r[0-5]]] ; CHECK: ipm [[REG:%r[0-5]]]
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llvm/test/CodeGen/SystemZ/knownbits-intrinsics-binop.ll

Show First 20 Lines • Show All 405 Lines • ▼ Show 20 Lines %res = and <16 x i8> %shfd, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,
i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <16 x i8> %res ret <16 x i8> %res
} }
; Test that intrinsic CC result is recognized. ; Test that intrinsic CC result is recognized.
define i32 @f28(<4 x i32> %a, <4 x i32> %b) { define i32 @f28(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: f28: ; CHECK-LABEL: f28:
; CHECK-LABEL: # %bb.0: ; CHECK-LABEL: # %bb.0:
; CHECK-NEXT: lhi %r2, 0 ; CHECK-NEXT: lghi %r2, 0
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32> %a, <4 x i32> %b) %call = call {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32> %a, <4 x i32> %b)
%cc = extractvalue {<8 x i16>, i32} %call, 1 %cc = extractvalue {<8 x i16>, i32} %call, 1
%res = and i32 %cc, -4 %res = and i32 %cc, -4
ret i32 %res ret i32 %res
} }
declare <16 x i8> @llvm.s390.vperm(<16 x i8>, <16 x i8>, <16 x i8>) declare <16 x i8> @llvm.s390.vperm(<16 x i8>, <16 x i8>, <16 x i8>)
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llvm/test/CodeGen/SystemZ/knownbits.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s ; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s
; Test that DAGCombiner gets helped by computeKnownBitsForTargetNode(). ; Test that DAGCombiner gets helped by computeKnownBitsForTargetNode().
; SystemZISD::REPLICATE ; SystemZISD::REPLICATE
define i32 @f0(<4 x i32> *%p0) { define i32 @f0(<4 x i32> *%p0) {
; CHECK-LABEL: f0: ; CHECK-LABEL: f0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vl %v0, 0(%r2), 3 ; CHECK-NEXT: vl %v0, 0(%r2), 3
; CHECK-NEXT: vgbm %v1, 0 ; CHECK-NEXT: vgbm %v1, 0
; CHECK-NEXT: vceqf %v0, %v0, %v1 ; CHECK-NEXT: vceqf %v0, %v0, %v1
; CHECK-NEXT: vrepif %v1, 1 ; CHECK-NEXT: vrepif %v1, 1
; CHECK-NEXT: vnc %v0, %v1, %v0 ; CHECK-NEXT: vnc %v0, %v1, %v0
; CHECK-NEXT: vlgvf %r0, %v0, 3
; CHECK-NEXT: vst %v0, 0(%r2), 3 ; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: vlgvf %r2, %v0, 3 ; CHECK-NEXT: llgfr %r2, %r0
; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%a0 = load <4 x i32>, <4 x i32>* %p0, align 8 %a0 = load <4 x i32>, <4 x i32>* %p0, align 8
%cmp0 = icmp ne <4 x i32> %a0, zeroinitializer %cmp0 = icmp ne <4 x i32> %a0, zeroinitializer
%zxt0 = zext <4 x i1> %cmp0 to <4 x i32> %zxt0 = zext <4 x i1> %cmp0 to <4 x i32>
store <4 x i32> %zxt0, <4 x i32>* %p0, align 8 store <4 x i32> %zxt0, <4 x i32>* %p0, align 8
%ext0 = extractelement <4 x i32> %zxt0, i32 3 %ext0 = extractelement <4 x i32> %zxt0, i32 3
br label %exit br label %exit
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llvm/test/CodeGen/SystemZ/memcmp-01.ll

; Test memcmp using CLC, with i32 results. ; Test memcmp using CLC, with i32 results.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
declare signext i32 @memcmp(i8 *%src1, i8 *%src2, i64 %size) declare signext i32 @memcmp(i8 *%src1, i8 *%src2, i64 %size)
; Zero-length comparisons should be optimized away. ; Zero-length comparisons should be optimized away.
define i32 @f1(i8 *%src1, i8 *%src2) { define i32 @f1(i8 *%src1, i8 *%src2) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lhi %r2, 0 ; CHECK: lhi %r2, 0
; CHECK: br %r14 ; CHECK: br %r14
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llvm/test/CodeGen/SystemZ/not-01.ll

; Combined logical operations involving complement on z15 ; Combined logical operations involving complement on z15
; ;
; RUN: llc -mcpu=z15 < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc -mcpu=z15 < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; And-with-complement 32-bit. ; And-with-complement 32-bit.
define i32 @f1(i32 %dummy, i32 %a, i32 %b) { define i32 @f1(i32 %dummy, i32 %a, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: ncrk %r2, %r3, %r4 ; CHECK: ncrk %r2, %r3, %r4
; CHECK: br %r14 ; CHECK: br %r14
%neg = xor i32 %b, -1 %neg = xor i32 %b, -1
%ret = and i32 %neg, %a %ret = and i32 %neg, %a
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llvm/test/CodeGen/SystemZ/or-07.ll

; Test the three-operand forms of OR. ; Test the three-operand forms of OR.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
; Check XRK. ; Check XRK.
define i32 @f1(i32 %a, i32 %b, i32 %c) { define i32 @f1(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: ork %r2, %r3, %r4 ; CHECK: ork %r2, %r3, %r4
; CHECK: br %r14 ; CHECK: br %r14
%or = or i32 %b, %c %or = or i32 %b, %c
ret i32 %or ret i32 %or
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llvm/test/CodeGen/SystemZ/pr42512.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i8 @test(i8 %x) { define i8 @test(i8 %x) {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: slgfi %r0, 1 ; CHECK-NEXT: slgfi %r0, 1
; CHECK-NEXT: ipm %r0 ; CHECK-NEXT: ipm %r0
; CHECK-NEXT: afi %r0, -536870912 ; CHECK-NEXT: afi %r0, -536870912
; CHECK-NEXT: srl %r0, 31 ; CHECK-NEXT: srl %r0, 31
; CHECK-NEXT: ar %r2, %r0 ; CHECK-NEXT: ar %r0, %r2
; CHECK-NEXT: lgbr %r2, %r0
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%usubo = tail call { i64, i1 } @llvm.usub.with.overflow.i64(i64 undef, i64 1) %usubo = tail call { i64, i1 } @llvm.usub.with.overflow.i64(i64 undef, i64 1)
%ov = extractvalue { i64, i1 } %usubo, 1 %ov = extractvalue { i64, i1 } %usubo, 1
%ovext = zext i1 %ov to i8 %ovext = zext i1 %ov to i8
%ret = add i8 %x, %ovext %ret = add i8 %x, %ovext
ret i8 %ret ret i8 %ret
} }
; Function Attrs: nounwind readnone speculatable ; Function Attrs: nounwind readnone speculatable
declare { i64, i1 } @llvm.usub.with.overflow.i64(i64, i64) #0 declare { i64, i1 } @llvm.usub.with.overflow.i64(i64, i64) #0
attributes #0 = { nounwind readnone speculatable } attributes #0 = { nounwind readnone speculatable }

llvm/test/CodeGen/SystemZ/risbg-01.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test sequences that can use RISBG with a zeroed first operand. ; Test sequences that can use RISBG with a zeroed first operand.
; The tests here assume that RISBLG isn't available. ; The tests here assume that RISBLG isn't available.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s
; Test an extraction of bit 0 from a right-shifted value. ; Test an extraction of bit 0 from a right-shifted value.
define i32 @f1(i32 %foo) { define i32 @f1(i32 %foo) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d ; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
; CHECK-NEXT: risbg %r2, %r2, 63, 191, 54 ; CHECK-NEXT: risbg %r2, %r2, 63, 191, 54
; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d ; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
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llvm/test/CodeGen/SystemZ/risbg-02.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test sequences that can use RISBG with a normal first operand. ; Test sequences that can use RISBG with a normal first operand.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; Test a case with two ANDs. ; Test a case with two ANDs.
define i32 @f1(i32 %a, i32 %b) { define i32 @f1(i32 %a, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d ; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d
; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d ; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
; CHECK-NEXT: risbg %r2, %r3, 60, 62, 0 ; CHECK-NEXT: risbg %r2, %r3, 60, 62, 0
; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d ; CHECK-NEXT: lgfr %r2, %r2
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%anda = and i32 %a, -15 %anda = and i32 %a, -15
%andb = and i32 %b, 14 %andb = and i32 %b, 14
%or = or i32 %anda, %andb %or = or i32 %anda, %andb
ret i32 %or ret i32 %or
} }
; ...and again with i64. ; ...and again with i64.
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; Test a case with two ANDs and a shift. ; Test a case with two ANDs and a shift.
define i32 @f3(i32 %a, i32 %b) { define i32 @f3(i32 %a, i32 %b) {
; CHECK-LABEL: f3: ; CHECK-LABEL: f3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d ; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d
; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d ; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
; CHECK-NEXT: risbg %r2, %r3, 60, 63, 56 ; CHECK-NEXT: risbg %r2, %r3, 60, 63, 56
; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d ; CHECK-NEXT: lgfr %r2, %r2
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%anda = and i32 %a, -16 %anda = and i32 %a, -16
%shr = lshr i32 %b, 8 %shr = lshr i32 %b, 8
%andb = and i32 %shr, 15 %andb = and i32 %shr, 15
%or = or i32 %anda, %andb %or = or i32 %anda, %andb
ret i32 %or ret i32 %or
} }
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; Test a case with a single AND and a left shift. ; Test a case with a single AND and a left shift.
define i32 @f5(i32 %a, i32 %b) { define i32 @f5(i32 %a, i32 %b) {
; CHECK-LABEL: f5: ; CHECK-LABEL: f5:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d ; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d
; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d ; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
; CHECK-NEXT: risbg %r2, %r3, 32, 53, 10 ; CHECK-NEXT: risbg %r2, %r3, 32, 53, 10
; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d ; CHECK-NEXT: lgfr %r2, %r2
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%anda = and i32 %a, 1023 %anda = and i32 %a, 1023
%shlb = shl i32 %b, 10 %shlb = shl i32 %b, 10
%or = or i32 %anda, %shlb %or = or i32 %anda, %shlb
ret i32 %or ret i32 %or
} }
; ...and again with i64. ; ...and again with i64.
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; Test a case with a single AND and a right shift. ; Test a case with a single AND and a right shift.
define i32 @f7(i32 %a, i32 %b) { define i32 @f7(i32 %a, i32 %b) {
; CHECK-LABEL: f7: ; CHECK-LABEL: f7:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d ; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d
; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d ; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
; CHECK-NEXT: risbg %r2, %r3, 40, 63, 56 ; CHECK-NEXT: risbg %r2, %r3, 40, 63, 56
; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d ; CHECK-NEXT: lgfr %r2, %r2
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%anda = and i32 %a, -16777216 %anda = and i32 %a, -16777216
%shrb = lshr i32 %b, 8 %shrb = lshr i32 %b, 8
%or = or i32 %anda, %shrb %or = or i32 %anda, %shrb
ret i32 %or ret i32 %or
} }
; ...and again with i64. ; ...and again with i64.
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llvm/test/CodeGen/SystemZ/risbg-04.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test sequences that can use RISBG with a zeroed first operand. ; Test sequences that can use RISBG with a zeroed first operand.
; The tests here assume that RISBLG is available. ; The tests here assume that RISBLG is available.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
; Test an extraction of bit 0 from a right-shifted value. ; Test an extraction of bit 0 from a right-shifted value.
define i32 @f1(i32 %foo) { define i32 @f1(i32 %foo) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: risblg %r2, %r2, 31, 159, 54 ; CHECK-NEXT: risblg %r2, %r2, 31, 159, 54
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%shr = lshr i32 %foo, 10 %shr = lshr i32 %foo, 10
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llvm/test/CodeGen/SystemZ/rot-01.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test shortening of NILL to NILF when the result is used as a rotate amount. ; Test shortening of NILL to NILF when the result is used as a rotate amount.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; Test 32-bit rotate. ; Test 32-bit rotate.
define i32 @f1(i32 %val, i32 %amt) { define i32 @f1(i32 %val, i32 %amt) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: nill %r3, 15 ; CHECK-NEXT: nill %r3, 15
; CHECK-NEXT: rll %r2, %r2, 0(%r3) ; CHECK-NEXT: rll %r0, %r2, 0(%r3)
; CHECK-NEXT: lgfr %r2, %r0
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%mod = urem i32 %amt, 16 %mod = urem i32 %amt, 16
%inv = sub i32 32, %mod %inv = sub i32 32, %mod
%parta = shl i32 %val, %mod %parta = shl i32 %val, %mod
%partb = lshr i32 %val, %inv %partb = lshr i32 %val, %inv
%rotl = or i32 %parta, %partb %rotl = or i32 %parta, %partb
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llvm/test/CodeGen/SystemZ/rot-02.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test removal of AND operations that don't affect last 6 bits of rotate amount ; Test removal of AND operations that don't affect last 6 bits of rotate amount
; operand. ; operand.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; Test that AND is not removed when some lower 5 bits are not set. ; Test that AND is not removed when some lower 5 bits are not set.
define i32 @f1(i32 %val, i32 %amt) { define i32 @f1(i32 %val, i32 %amt) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: nill %r3, 15 ; CHECK-NEXT: nill %r3, 15
; CHECK-NEXT: rll %r2, %r2, 0(%r3) ; CHECK-NEXT: rll %r0, %r2, 0(%r3)
; CHECK-NEXT: lgfr %r2, %r0
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%and = and i32 %amt, 15 %and = and i32 %amt, 15
%inv = sub i32 32, %and %inv = sub i32 32, %and
%parta = shl i32 %val, %and %parta = shl i32 %val, %and
%partb = lshr i32 %val, %inv %partb = lshr i32 %val, %inv
%rotl = or i32 %parta, %partb %rotl = or i32 %parta, %partb
ret i32 %rotl ret i32 %rotl
} }
; Test removal of AND mask with only bottom 6 bits set. ; Test removal of AND mask with only bottom 6 bits set.
define i32 @f2(i32 %val, i32 %amt) { define i32 @f2(i32 %val, i32 %amt) {
; CHECK-LABEL: f2: ; CHECK-LABEL: f2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rll %r2, %r2, 0(%r3) ; CHECK-NEXT: rll %r0, %r2, 0(%r3)
; CHECK-NEXT: lgfr %r2, %r0
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%and = and i32 %amt, 63 %and = and i32 %amt, 63
%inv = sub i32 32, %and %inv = sub i32 32, %and
%parta = shl i32 %val, %and %parta = shl i32 %val, %and
%partb = lshr i32 %val, %inv %partb = lshr i32 %val, %inv
%rotl = or i32 %parta, %partb %rotl = or i32 %parta, %partb
ret i32 %rotl ret i32 %rotl
} }
; Test removal of AND mask including but not limited to bottom 6 bits. ; Test removal of AND mask including but not limited to bottom 6 bits.
define i32 @f3(i32 %val, i32 %amt) { define i32 @f3(i32 %val, i32 %amt) {
; CHECK-LABEL: f3: ; CHECK-LABEL: f3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rll %r2, %r2, 0(%r3) ; CHECK-NEXT: rll %r0, %r2, 0(%r3)
; CHECK-NEXT: lgfr %r2, %r0
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%and = and i32 %amt, 255 %and = and i32 %amt, 255
%inv = sub i32 32, %and %inv = sub i32 32, %and
%parta = shl i32 %val, %and %parta = shl i32 %val, %and
%partb = lshr i32 %val, %inv %partb = lshr i32 %val, %inv
%rotl = or i32 %parta, %partb %rotl = or i32 %parta, %partb
Show All 17 Lines; CHECK-NEXT: br %r14
ret i64 %rotl ret i64 %rotl
} }
; Test that AND is not entirely removed if the result is reused. ; Test that AND is not entirely removed if the result is reused.
define i32 @f5(i32 %val, i32 %amt) { define i32 @f5(i32 %val, i32 %amt) {
; CHECK-LABEL: f5: ; CHECK-LABEL: f5:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rll %r2, %r2, 0(%r3) ; CHECK-NEXT: rll %r0, %r2, 0(%r3)
; CHECK-NEXT: nilf %r3, 63 ; CHECK-NEXT: nilf %r3, 63
; CHECK-NEXT: ar %r2, %r3 ; CHECK-NEXT: ar %r3, %r0
; CHECK-NEXT: lgfr %r2, %r3
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%and = and i32 %amt, 63 %and = and i32 %amt, 63
%inv = sub i32 32, %and %inv = sub i32 32, %and
%parta = shl i32 %val, %and %parta = shl i32 %val, %and
%partb = lshr i32 %val, %inv %partb = lshr i32 %val, %inv
%rotl = or i32 %parta, %partb %rotl = or i32 %parta, %partb
%reuse = add i32 %and, %rotl %reuse = add i32 %and, %rotl
ret i32 %reuse ret i32 %reuse
} }

llvm/test/CodeGen/SystemZ/scalar-ctlz.ll

; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -no-arg-exts | FileCheck %s
; ;
; FIXME: two consecutive immediate adds not fused in i16/i8 functions. ; FIXME: two consecutive immediate adds not fused in i16/i8 functions.
declare i64 @llvm.ctlz.i64(i64, i1) declare i64 @llvm.ctlz.i64(i64, i1)
declare i32 @llvm.ctlz.i32(i32, i1) declare i32 @llvm.ctlz.i32(i32, i1)
declare i16 @llvm.ctlz.i16(i16, i1) declare i16 @llvm.ctlz.i16(i16, i1)
declare i8 @llvm.ctlz.i8(i8, i1) declare i8 @llvm.ctlz.i8(i8, i1)
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llvm/test/CodeGen/SystemZ/selectcc-01.ll

; Test an i32 0/-1 SELECTCCC for every floating-point condition. ; Test an i32 0/-1 SELECTCCC for every floating-point condition.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; Test CC in { 0 } ; Test CC in { 0 }
define i32 @f1(float %a, float %b) { define i32 @f1(float %a, float %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: ipm %r2 ; CHECK: ipm %r2
; CHECK-NEXT: afi %r2, -268435456 ; CHECK-NEXT: afi %r2, -268435456
; CHECK-NEXT: sra %r2, 31 ; CHECK-NEXT: sra %r2, 31
; CHECK: br %r14 ; CHECK: br %r14
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llvm/test/CodeGen/SystemZ/selectcc-02.ll

; Test an i32 0/-1 SELECTCCC for every floating-point condition. ; Test an i32 0/-1 SELECTCCC for every floating-point condition.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; Test CC in { 1, 2, 3 } ; Test CC in { 1, 2, 3 }
define i32 @f1(float %a, float %b) { define i32 @f1(float %a, float %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: ipm %r2 ; CHECK: ipm %r2
; CHECK-NEXT: afi %r2, 1879048192 ; CHECK-NEXT: afi %r2, 1879048192
; CHECK-NEXT: sra %r2, 31 ; CHECK-NEXT: sra %r2, 31
; CHECK: br %r14 ; CHECK: br %r14
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llvm/test/CodeGen/SystemZ/setcc-01.ll

; Test SETCC for every integer condition. The tests here assume that ; Test SETCC for every integer condition. The tests here assume that
; RISBLG isn't available. ; RISBLG isn't available.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s
; Test CC in { 0 }, with 3 don't care. ; Test CC in { 0 }, with 3 don't care.
define i32 @f1(i32 %a, i32 %b) { define i32 @f1(i32 %a, i32 %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: ipm %r2 ; CHECK: ipm %r2
; CHECK-NEXT: afi %r2, -268435456 ; CHECK-NEXT: afi %r2, -268435456
; CHECK-NEXT: srl %r2, 31 ; CHECK-NEXT: srl %r2, 31
; CHECK: br %r14 ; CHECK: br %r14
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llvm/test/CodeGen/SystemZ/setcc-02.ll

; Test SETCC for every floating-point condition. The tests here assume that ; Test SETCC for every floating-point condition. The tests here assume that
; RISBLG isn't available. ; RISBLG isn't available.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-arg-exts | FileCheck %s
; Test CC in { 0 } ; Test CC in { 0 }
define i32 @f1(float %a, float %b) { define i32 @f1(float %a, float %b) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: ipm %r2 ; CHECK: ipm %r2
; CHECK-NEXT: afi %r2, -268435456 ; CHECK-NEXT: afi %r2, -268435456
; CHECK-NEXT: srl %r2, 31 ; CHECK-NEXT: srl %r2, 31
; CHECK: br %r14 ; CHECK: br %r14
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llvm/test/CodeGen/SystemZ/sext-zext.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
;; fold (sext (not x)) -> (add (zext x) -1) ;; fold (sext (not x)) -> (add (zext x) -1)
define i32 @sext_of_not(i1 %x) { define i32 @sext_of_not(i1 %x) {
; CHECK-LABEL: sext_of_not: ; CHECK-LABEL: sext_of_not:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: nilf %r2, 1 ; CHECK-NEXT: nilf %r2, 1
; CHECK-NEXT: ahi %r2, -1 ; CHECK-NEXT: ahi %r2, -1
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
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llvm/test/CodeGen/SystemZ/shift-01.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test 32-bit shifts left. ; Test 32-bit shifts left.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; Check the low end of the SLL range. ; Check the low end of the SLL range.
define i32 @f1(i32 %a) { define i32 @f1(i32 %a) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %r2, 1 ; CHECK-NEXT: sll %r2, 1
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%shift = shl i32 %a, 1 %shift = shl i32 %a, 1
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llvm/test/CodeGen/SystemZ/shift-02.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test 32-bit logical shifts right. ; Test 32-bit logical shifts right.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; Check the low end of the SRL range. ; Check the low end of the SRL range.
define i32 @f1(i32 %a) { define i32 @f1(i32 %a) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: srl %r2, 1 ; CHECK-NEXT: srl %r2, 1
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%shift = lshr i32 %a, 1 %shift = lshr i32 %a, 1
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llvm/test/CodeGen/SystemZ/shift-03.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test 32-bit arithmetic shifts right. ; Test 32-bit arithmetic shifts right.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; Check the low end of the SRA range. ; Check the low end of the SRA range.
define i32 @f1(i32 %a) { define i32 @f1(i32 %a) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: sra %r2, 1 ; CHECK-NEXT: sra %r2, 1
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%shift = ashr i32 %a, 1 %shift = ashr i32 %a, 1
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llvm/test/CodeGen/SystemZ/shift-04.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test 32-bit rotates left. ; Test 32-bit rotates left.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; Check the low end of the RLL range. ; Check the low end of the RLL range.
define i32 @f1(i32 %a) { define i32 @f1(i32 %a) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rll %r2, %r2, 1 ; CHECK-NEXT: rll %r2, %r2, 1
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%parta = shl i32 %a, 1 %parta = shl i32 %a, 1
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llvm/test/CodeGen/SystemZ/shift-09.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test three-operand shifts. ; Test three-operand shifts.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
; Check that we use SLLK over SLL where useful. ; Check that we use SLLK over SLL where useful.
define i32 @f1(i32 %a, i32 %b, i32 %amt) { define i32 @f1(i32 %a, i32 %b, i32 %amt) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: sllk %r2, %r3, 15(%r4) ; CHECK-NEXT: sllk %r2, %r3, 15(%r4)
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%add = add i32 %amt, 15 %add = add i32 %amt, 15
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llvm/test/CodeGen/SystemZ/shift-11.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test shortening of NILL to NILF when the result is used as a shift amount. ; Test shortening of NILL to NILF when the result is used as a shift amount.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; Test logical shift right. ; Test logical shift right.
define i32 @f1(i32 %a, i32 %sh) { define i32 @f1(i32 %a, i32 %sh) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: nill %r3, 31 ; CHECK-NEXT: nill %r3, 31
; CHECK-NEXT: srl %r2, 0(%r3) ; CHECK-NEXT: srl %r2, 0(%r3)
; CHECK-NEXT: lgfr %r2, %r2
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%and = and i32 %sh, 31 %and = and i32 %sh, 31
%shift = lshr i32 %a, %and %shift = lshr i32 %a, %and
ret i32 %shift ret i32 %shift
} }
; Test arithmetic shift right. ; Test arithmetic shift right.
define i32 @f2(i32 %a, i32 %sh) { define i32 @f2(i32 %a, i32 %sh) {
; CHECK-LABEL: f2: ; CHECK-LABEL: f2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: nill %r3, 31 ; CHECK-NEXT: nill %r3, 31
; CHECK-NEXT: sra %r2, 0(%r3) ; CHECK-NEXT: sra %r2, 0(%r3)
; CHECK-NEXT: lgfr %r2, %r2
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%and = and i32 %sh, 31 %and = and i32 %sh, 31
%shift = ashr i32 %a, %and %shift = ashr i32 %a, %and
ret i32 %shift ret i32 %shift
} }
; Test shift left. ; Test shift left.
define i32 @f3(i32 %a, i32 %sh) { define i32 @f3(i32 %a, i32 %sh) {
; CHECK-LABEL: f3: ; CHECK-LABEL: f3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: nill %r3, 31 ; CHECK-NEXT: nill %r3, 31
; CHECK-NEXT: sll %r2, 0(%r3) ; CHECK-NEXT: sll %r2, 0(%r3)
; CHECK-NEXT: lgfr %r2, %r2
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%and = and i32 %sh, 31 %and = and i32 %sh, 31
%shift = shl i32 %a, %and %shift = shl i32 %a, %and
ret i32 %shift ret i32 %shift
} }
; Test 64-bit logical shift right. ; Test 64-bit logical shift right.
define i64 @f4(i64 %a, i64 %sh) { define i64 @f4(i64 %a, i64 %sh) {
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} }
; Test shift with negative 32-bit value. ; Test shift with negative 32-bit value.
define i32 @f8(i32 %a, i32 %sh, i32 %test) { define i32 @f8(i32 %a, i32 %sh, i32 %test) {
; CHECK-LABEL: f8: ; CHECK-LABEL: f8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: nill %r3, 65529 ; CHECK-NEXT: nill %r3, 65529
; CHECK-NEXT: sll %r2, 0(%r3) ; CHECK-NEXT: sll %r2, 0(%r3)
; CHECK-NEXT: lgfr %r2, %r2
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%and = and i32 %sh, -7 %and = and i32 %sh, -7
%shift = shl i32 %a, %and %shift = shl i32 %a, %and
ret i32 %shift ret i32 %shift
} }
; Test shift with negative 64-bit value. ; Test shift with negative 64-bit value.
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llvm/test/CodeGen/SystemZ/shift-12.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Test removal of AND operations that don't affect last 6 bits of shift amount ; Test removal of AND operations that don't affect last 6 bits of shift amount
; operand. ; operand.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
; Test that AND is not removed when some lower 6 bits are not set. ; Test that AND is not removed when some lower 6 bits are not set.
define i32 @f1(i32 %a, i32 %sh) { define i32 @f1(i32 %a, i32 %sh) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: nill %r3, 31 ; CHECK-NEXT: nill %r3, 31
; CHECK-NEXT: sll %r2, 0(%r3) ; CHECK-NEXT: sll %r2, 0(%r3)
; CHECK-NEXT: lgfr %r2, %r2
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%and = and i32 %sh, 31 %and = and i32 %sh, 31
%shift = shl i32 %a, %and %shift = shl i32 %a, %and
ret i32 %shift ret i32 %shift
} }
; Test removal of AND mask with only bottom 6 bits set. ; Test removal of AND mask with only bottom 6 bits set.
define i32 @f2(i32 %a, i32 %sh) { define i32 @f2(i32 %a, i32 %sh) {
; CHECK-LABEL: f2: ; CHECK-LABEL: f2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %r2, 0(%r3) ; CHECK-NEXT: sll %r2, 0(%r3)
; CHECK-NEXT: lgfr %r2, %r2
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%and = and i32 %sh, 63 %and = and i32 %sh, 63
%shift = shl i32 %a, %and %shift = shl i32 %a, %and
ret i32 %shift ret i32 %shift
} }
; Test removal of AND mask including but not limited to bottom 6 bits. ; Test removal of AND mask including but not limited to bottom 6 bits.
define i32 @f3(i32 %a, i32 %sh) { define i32 @f3(i32 %a, i32 %sh) {
; CHECK-LABEL: f3: ; CHECK-LABEL: f3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %r2, 0(%r3) ; CHECK-NEXT: sll %r2, 0(%r3)
; CHECK-NEXT: lgfr %r2, %r2
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%and = and i32 %sh, 255 %and = and i32 %sh, 255
%shift = shl i32 %a, %and %shift = shl i32 %a, %and
ret i32 %shift ret i32 %shift
} }
; Test removal of AND mask from SRA. ; Test removal of AND mask from SRA.
define i32 @f4(i32 %a, i32 %sh) { define i32 @f4(i32 %a, i32 %sh) {
; CHECK-LABEL: f4: ; CHECK-LABEL: f4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: sra %r2, 0(%r3) ; CHECK-NEXT: sra %r2, 0(%r3)
; CHECK-NEXT: lgfr %r2, %r2
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%and = and i32 %sh, 63 %and = and i32 %sh, 63
%shift = ashr i32 %a, %and %shift = ashr i32 %a, %and
ret i32 %shift ret i32 %shift
} }
; Test removal of AND mask from SRL. ; Test removal of AND mask from SRL.
define i32 @f5(i32 %a, i32 %sh) { define i32 @f5(i32 %a, i32 %sh) {
; CHECK-LABEL: f5: ; CHECK-LABEL: f5:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: srl %r2, 0(%r3) ; CHECK-NEXT: srl %r2, 0(%r3)
; CHECK-NEXT: lgfr %r2, %r2
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%and = and i32 %sh, 63 %and = and i32 %sh, 63
%shift = lshr i32 %a, %and %shift = lshr i32 %a, %and
ret i32 %shift ret i32 %shift
} }
; Test removal of AND mask from SLLG. ; Test removal of AND mask from SLLG.
define i64 @f6(i64 %a, i64 %sh) { define i64 @f6(i64 %a, i64 %sh) {
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} }
; Test that AND with two register operands is not affected. ; Test that AND with two register operands is not affected.
define i32 @f9(i32 %a, i32 %b, i32 %sh) { define i32 @f9(i32 %a, i32 %b, i32 %sh) {
; CHECK-LABEL: f9: ; CHECK-LABEL: f9:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: nr %r3, %r4 ; CHECK-NEXT: nr %r3, %r4
; CHECK-NEXT: sll %r2, 0(%r3) ; CHECK-NEXT: sll %r2, 0(%r3)
; CHECK-NEXT: lgfr %r2, %r2
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%and = and i32 %sh, %b %and = and i32 %sh, %b
%shift = shl i32 %a, %and %shift = shl i32 %a, %and
ret i32 %shift ret i32 %shift
} }
; Test that AND is not entirely removed if the result is reused. ; Test that AND is not entirely removed if the result is reused.
define i32 @f10(i32 %a, i32 %sh) { define i32 @f10(i32 %a, i32 %sh) {
; CHECK-LABEL: f10: ; CHECK-LABEL: f10:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: sll %r2, 0(%r3) ; CHECK-NEXT: sll %r2, 0(%r3)
; CHECK-NEXT: nilf %r3, 63 ; CHECK-NEXT: nilf %r3, 63
; CHECK-NEXT: ar %r2, %r3 ; CHECK-NEXT: ar %r2, %r3
; CHECK-NEXT: lgfr %r2, %r2
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%and = and i32 %sh, 63 %and = and i32 %sh, 63
%shift = shl i32 %a, %and %shift = shl i32 %a, %and
%reuse = add i32 %and, %shift %reuse = add i32 %and, %shift
ret i32 %reuse ret i32 %reuse
} }
define i128 @f11(i128 %a, i32 %sh) { define i128 @f11(i128 %a, i32 %sh) {
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llvm/test/CodeGen/SystemZ/soft-float-args.ll

; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -mattr=soft-float -O3 < %s | FileCheck %s ; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -mattr=soft-float -O3 \
; RUN: -no-arg-exts < %s | FileCheck %s
; ;
; Test that arguments and return values of fp/vector types are always handled ; Test that arguments and return values of fp/vector types are always handled
; with gprs with soft-float. ; with gprs with soft-float.
define double @f1(double %arg) { define double @f1(double %arg) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK-NOT: %r2 ; CHECK-NOT: %r2
; CHECK-NOT: %{{[fv]}} ; CHECK-NOT: %{{[fv]}}
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llvm/test/CodeGen/SystemZ/stack-clash-dynamic-alloca.ll

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; CHECK-NEXT: cgije %r1, 0, .LBB0_4 ; CHECK-NEXT: cgije %r1, 0, .LBB0_4
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: slgr %r15, %r1 ; CHECK-NEXT: slgr %r15, %r1
; CHECK-NEXT: cg %r15, -8(%r1,%r15) ; CHECK-NEXT: cg %r15, -8(%r1,%r15)
; CHECK-NEXT: .LBB0_4: ; CHECK-NEXT: .LBB0_4:
; CHECK-NEXT: la %r1, 160(%r15) ; CHECK-NEXT: la %r1, 160(%r15)
; CHECK-NEXT: lhi %r0, 1 ; CHECK-NEXT: lhi %r0, 1
; CHECK-NEXT: sty %r0, 4792(%r1) ; CHECK-NEXT: sty %r0, 4792(%r1)
; CHECK-NEXT: l %r2, 0(%r1) ; CHECK-NEXT: lgf %r2, 0(%r1)
; CHECK-NEXT: lmg %r11, %r15, 248(%r11) ; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%a = alloca i32, i32 %n %a = alloca i32, i32 %n
%b = getelementptr inbounds i32, i32* %a, i64 1198 %b = getelementptr inbounds i32, i32* %a, i64 1198
store volatile i32 1, i32* %b store volatile i32 1, i32* %b
%c = load volatile i32, i32* %a %c = load volatile i32, i32* %a
ret i32 %c ret i32 %c
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; CHECK-NEXT: cgije %r1, 0, .LBB1_4 ; CHECK-NEXT: cgije %r1, 0, .LBB1_4
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: slgr %r15, %r1 ; CHECK-NEXT: slgr %r15, %r1
; CHECK-NEXT: cg %r15, -8(%r1,%r15) ; CHECK-NEXT: cg %r15, -8(%r1,%r15)
; CHECK-NEXT: .LBB1_4: ; CHECK-NEXT: .LBB1_4:
; CHECK-NEXT: la %r1, 160(%r15) ; CHECK-NEXT: la %r1, 160(%r15)
; CHECK-NEXT: lhi %r0, 1 ; CHECK-NEXT: lhi %r0, 1
; CHECK-NEXT: sty %r0, 4792(%r1) ; CHECK-NEXT: sty %r0, 4792(%r1)
; CHECK-NEXT: l %r2, 0(%r1) ; CHECK-NEXT: lgf %r2, 0(%r1)
; CHECK-NEXT: lmg %r11, %r15, 248(%r11) ; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%a = alloca i32, i32 %n %a = alloca i32, i32 %n
%b = getelementptr inbounds i32, i32* %a, i64 1198 %b = getelementptr inbounds i32, i32* %a, i64 1198
store volatile i32 1, i32* %b store volatile i32 1, i32* %b
%c = load volatile i32, i32* %a %c = load volatile i32, i32* %a
ret i32 %c ret i32 %c
} }
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; CHECK-NEXT: cgije %r1, 0, .LBB2_6 ; CHECK-NEXT: cgije %r1, 0, .LBB2_6
; CHECK-NEXT: # %bb.5: ; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: slgr %r15, %r1 ; CHECK-NEXT: slgr %r15, %r1
; CHECK-NEXT: cg %r15, -8(%r1,%r15) ; CHECK-NEXT: cg %r15, -8(%r1,%r15)
; CHECK-NEXT: .LBB2_6: ; CHECK-NEXT: .LBB2_6:
; CHECK-NEXT: la %r1, 160(%r15) ; CHECK-NEXT: la %r1, 160(%r15)
; CHECK-NEXT: lhi %r0, 1 ; CHECK-NEXT: lhi %r0, 1
; CHECK-NEXT: sty %r0, 4792(%r1) ; CHECK-NEXT: sty %r0, 4792(%r1)
; CHECK-NEXT: l %r2, 0(%r1) ; CHECK-NEXT: lgf %r2, 0(%r1)
; CHECK-NEXT: lmg %r11, %r15, 248(%r11) ; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%a = alloca i32, i32 %n %a = alloca i32, i32 %n
%b = getelementptr inbounds i32, i32* %a, i64 1198 %b = getelementptr inbounds i32, i32* %a, i64 1198
store volatile i32 1, i32* %b store volatile i32 1, i32* %b
%c = load volatile i32, i32* %a %c = load volatile i32, i32* %a
ret i32 %c ret i32 %c
} }
attributes #0 = {"probe-stack"="inline-asm"} attributes #0 = {"probe-stack"="inline-asm"}

llvm/test/CodeGen/SystemZ/stack-clash-protection.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -O3 -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -O3 -verify-machineinstrs | FileCheck %s
; ;
; Test stack clash protection probing for static allocas. ; Test stack clash protection probing for static allocas.
; Small: one probe. ; Small: one probe.
define i32 @fun0() #0 { define i32 @fun0() #0 {
; CHECK-LABEL: fun0: ; CHECK-LABEL: fun0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: aghi %r15, -560 ; CHECK-NEXT: aghi %r15, -560
; CHECK-NEXT: .cfi_def_cfa_offset 720 ; CHECK-NEXT: .cfi_def_cfa_offset 720
; CHECK-NEXT: cg %r0, 552(%r15) ; CHECK-NEXT: cg %r0, 552(%r15)
; CHECK-NEXT: mvhi 552(%r15), 1 ; CHECK-NEXT: mvhi 552(%r15), 1
; CHECK-NEXT: l %r2, 160(%r15) ; CHECK-NEXT: lgf %r2, 160(%r15)
; CHECK-NEXT: aghi %r15, 560 ; CHECK-NEXT: aghi %r15, 560
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%a = alloca i32, i64 100 %a = alloca i32, i64 100
%b = getelementptr inbounds i32, i32* %a, i64 98 %b = getelementptr inbounds i32, i32* %a, i64 98
store volatile i32 1, i32* %b store volatile i32 1, i32* %b
%c = load volatile i32, i32* %a %c = load volatile i32, i32* %a
ret i32 %c ret i32 %c
} }
; Medium: two probes. ; Medium: two probes.
define i32 @fun1() #0 { define i32 @fun1() #0 {
; CHECK-LABEL: fun1: ; CHECK-LABEL: fun1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: aghi %r15, -4096 ; CHECK-NEXT: aghi %r15, -4096
; CHECK-NEXT: .cfi_def_cfa_offset 4256 ; CHECK-NEXT: .cfi_def_cfa_offset 4256
; CHECK-NEXT: cg %r0, 4088(%r15) ; CHECK-NEXT: cg %r0, 4088(%r15)
; CHECK-NEXT: aghi %r15, -4080 ; CHECK-NEXT: aghi %r15, -4080
; CHECK-NEXT: .cfi_def_cfa_offset 8336 ; CHECK-NEXT: .cfi_def_cfa_offset 8336
; CHECK-NEXT: cg %r0, 4072(%r15) ; CHECK-NEXT: cg %r0, 4072(%r15)
; CHECK-NEXT: mvhi 976(%r15), 1 ; CHECK-NEXT: mvhi 976(%r15), 1
; CHECK-NEXT: l %r2, 176(%r15) ; CHECK-NEXT: lgf %r2, 176(%r15)
; CHECK-NEXT: aghi %r15, 8176 ; CHECK-NEXT: aghi %r15, 8176
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%a = alloca i32, i64 2000 %a = alloca i32, i64 2000
%b = getelementptr inbounds i32, i32* %a, i64 200 %b = getelementptr inbounds i32, i32* %a, i64 200
store volatile i32 1, i32* %b store volatile i32 1, i32* %b
%c = load volatile i32, i32* %a %c = load volatile i32, i32* %a
ret i32 %c ret i32 %c
Show All 14 Lines
; CHECK-NEXT: # %bb.2: ; CHECK-NEXT: # %bb.2:
; CHECK-NEXT: .cfi_def_cfa_register %r15 ; CHECK-NEXT: .cfi_def_cfa_register %r15
; CHECK-NEXT: aghi %r15, -2544 ; CHECK-NEXT: aghi %r15, -2544
; CHECK-NEXT: .cfi_def_cfa_offset 72336 ; CHECK-NEXT: .cfi_def_cfa_offset 72336
; CHECK-NEXT: cg %r0, 2536(%r15) ; CHECK-NEXT: cg %r0, 2536(%r15)
; CHECK-NEXT: lhi %r0, 1 ; CHECK-NEXT: lhi %r0, 1
; CHECK-NEXT: mvhi 568(%r15), 1 ; CHECK-NEXT: mvhi 568(%r15), 1
; CHECK-NEXT: sty %r0, 28968(%r15) ; CHECK-NEXT: sty %r0, 28968(%r15)
; CHECK-NEXT: l %r2, 176(%r15) ; CHECK-NEXT: lgf %r2, 176(%r15)
; CHECK-NEXT: agfi %r15, 72176 ; CHECK-NEXT: agfi %r15, 72176
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%a = alloca i32, i64 18000 %a = alloca i32, i64 18000
%b0 = getelementptr inbounds i32, i32* %a, i64 98 %b0 = getelementptr inbounds i32, i32* %a, i64 98
%b1 = getelementptr inbounds i32, i32* %a, i64 7198 %b1 = getelementptr inbounds i32, i32* %a, i64 7198
store volatile i32 1, i32* %b0 store volatile i32 1, i32* %b0
store volatile i32 1, i32* %b1 store volatile i32 1, i32* %b1
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48 ; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40 ; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -3976 ; CHECK-NEXT: aghi %r15, -3976
; CHECK-NEXT: .cfi_def_cfa_offset 4136 ; CHECK-NEXT: .cfi_def_cfa_offset 4136
; CHECK-NEXT: brasl %r14, foo@PLT ; CHECK-NEXT: brasl %r14, foo@PLT
; CHECK-NEXT: st %r2, 568(%r15) ; CHECK-NEXT: st %r2, 568(%r15)
; CHECK-NEXT: l %r2, 176(%r15) ; CHECK-NEXT: lgf %r2, 176(%r15)
; CHECK-NEXT: lmg %r14, %r15, 4088(%r15) ; CHECK-NEXT: lmg %r14, %r15, 4088(%r15)
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%v = call i32 @foo() %v = call i32 @foo()
%a = alloca i32, i64 950 %a = alloca i32, i64 950
%b = getelementptr inbounds i32, i32* %a, i64 98 %b = getelementptr inbounds i32, i32* %a, i64 98
store volatile i32 %v, i32* %b store volatile i32 %v, i32* %b
%c = load volatile i32, i32* %a %c = load volatile i32, i32* %a
ret i32 %c ret i32 %c
} }
; Medium with an STMG - still needs probing. ; Medium with an STMG - still needs probing.
define i32 @fun8() #0 { define i32 @fun8() #0 {
; CHECK-LABEL: fun8: ; CHECK-LABEL: fun8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48 ; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40 ; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -3984 ; CHECK-NEXT: aghi %r15, -3984
; CHECK-NEXT: .cfi_def_cfa_offset 4144 ; CHECK-NEXT: .cfi_def_cfa_offset 4144
; CHECK-NEXT: cg %r0, 3976(%r15) ; CHECK-NEXT: cg %r0, 3976(%r15)
; CHECK-NEXT: brasl %r14, foo@PLT ; CHECK-NEXT: brasl %r14, foo@PLT
; CHECK-NEXT: st %r2, 976(%r15) ; CHECK-NEXT: st %r2, 976(%r15)
; CHECK-NEXT: l %r2, 176(%r15) ; CHECK-NEXT: lgf %r2, 176(%r15)
; CHECK-NEXT: lmg %r14, %r15, 4096(%r15) ; CHECK-NEXT: lmg %r14, %r15, 4096(%r15)
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
%v = call i32 @foo() %v = call i32 @foo()
%a = alloca i32, i64 952 %a = alloca i32, i64 952
%b = getelementptr inbounds i32, i32* %a, i64 200 %b = getelementptr inbounds i32, i32* %a, i64 200
store volatile i32 %v, i32* %b store volatile i32 %v, i32* %b
%c = load volatile i32, i32* %a %c = load volatile i32, i32* %a
Show All 37 Lines

llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s ; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -no-arg-exts < %s | FileCheck %s
; Store a <4 x i31> vector. ; Store a <4 x i31> vector.
define void @fun0(<4 x i31> %src, <4 x i31>* %p) define void @fun0(<4 x i31> %src, <4 x i31>* %p)
; CHECK-LABEL: fun0: ; CHECK-LABEL: fun0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vlgvf %r1, %v24, 0 ; CHECK-NEXT: vlgvf %r1, %v24, 0
; CHECK-NEXT: vlgvf %r0, %v24, 1 ; CHECK-NEXT: vlgvf %r0, %v24, 1
; CHECK-NEXT: sllg %r1, %r1, 29 ; CHECK-NEXT: sllg %r1, %r1, 29
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llvm/test/CodeGen/SystemZ/strcmp-01.ll

; Test strcmp using CLST, i32 version. ; Test strcmp using CLST, i32 version.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
declare signext i32 @strcmp(i8 *%src1, i8 *%src2) declare signext i32 @strcmp(i8 *%src1, i8 *%src2)
; Check a case where the result is used as an integer. ; Check a case where the result is used as an integer.
define i32 @f1(i8 *%src1, i8 *%src2) { define i32 @f1(i8 *%src1, i8 *%src2) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lhi %r0, 0 ; CHECK: lhi %r0, 0
; CHECK: [[LABEL:\.[^:]*]]: ; CHECK: [[LABEL:\.[^:]*]]:
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llvm/test/CodeGen/SystemZ/strcpy-01.ll

Show All 31 Lines; CHECK: br %r14
ret i8 *%res ret i8 *%res
} }
; Check correct operation with other loads and stores. The load must ; Check correct operation with other loads and stores. The load must
; come before the loop and the store afterwards. ; come before the loop and the store afterwards.
define i32 @f3(i32 %dummy, i8 *%dest, i8 *%src, i32 *%resptr, i32 *%storeptr) { define i32 @f3(i32 %dummy, i8 *%dest, i8 *%src, i32 *%resptr, i32 *%storeptr) {
; CHECK-LABEL: f3: ; CHECK-LABEL: f3:
; CHECK-DAG: lhi %r0, 0 ; CHECK-DAG: lhi %r0, 0
; CHECK-DAG: l %r2, 0(%r5) ; CHECK-DAG: lgf %r2, 0(%r5)
; CHECK: [[LABEL:\.[^:]*]]: ; CHECK: [[LABEL:\.[^:]*]]:
; CHECK-NEXT: mvst %r3, %r4 ; CHECK-NEXT: mvst %r3, %r4
; CHECK-NEXT: jo [[LABEL]] ; CHECK-NEXT: jo [[LABEL]]
; CHECK: mvhi 0(%r6), 0 ; CHECK: mvhi 0(%r6), 0
; CHECK: br %r14 ; CHECK: br %r14
%res = load i32, i32 *%resptr %res = load i32, i32 *%resptr
%unused = call i8 *@strcpy(i8 *%dest, i8 *%src) %unused = call i8 *@strcpy(i8 *%dest, i8 *%src)
store i32 0, i32 *%storeptr store i32 0, i32 *%storeptr
ret i32 %res ret i32 %res
} }

llvm/test/CodeGen/SystemZ/strcpy-nobuiltin.ll

Show All 24 Lines; CHECK: br %r14
%res = call i8 *@stpcpy(i8 *%dest, i8 *%src) nobuiltin %res = call i8 *@stpcpy(i8 *%dest, i8 *%src) nobuiltin
ret i8 *%res ret i8 *%res
} }
; Check correct operation with other loads and stores. The load must ; Check correct operation with other loads and stores. The load must
; come before the loop and the store afterwards. ; come before the loop and the store afterwards.
define i32 @f3(i32 %dummy, i8 *%dest, i8 *%src, i32 *%resptr, i32 *%storeptr) { define i32 @f3(i32 %dummy, i8 *%dest, i8 *%src, i32 *%resptr, i32 *%storeptr) {
; CHECK-LABEL: f3: ; CHECK-LABEL: f3:
; CHECK-DAG: l [[REG1:%r[0-9]+]], 0(%r5) ; CHECK-DAG: lgf [[REG1:%r[0-9]+]], 0(%r5)
; CHECK-NOT: mvst ; CHECK-NOT: mvst
; CHECK: brasl %r14, strcpy ; CHECK: brasl %r14, strcpy
; CHECK: mvhi 0(%r6), 0 ; CHECK: mvhi 0(%r6), 0
; CHECK: br %r14 ; CHECK: br %r14
%res = load i32, i32 *%resptr %res = load i32, i32 *%resptr
%unused = call i8 *@strcpy(i8 *%dest, i8 *%src) nobuiltin %unused = call i8 *@strcpy(i8 *%dest, i8 *%src) nobuiltin
store i32 0, i32 *%storeptr store i32 0, i32 *%storeptr
ret i32 %res ret i32 %res
} }

llvm/test/CodeGen/SystemZ/swift-return.ll

; RUN: llc < %s -mtriple=s390x-linux-gnu -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -verify-machineinstrs -no-arg-exts \
; RUN: llc < %s -mtriple=s390x-linux-gnu -O0 -verify-machineinstrs | FileCheck --check-prefix=CHECK-O0 %s ; RUN: | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -O0 -verify-machineinstrs -no-arg-exts \
; RUN: | FileCheck --check-prefix=CHECK-O0 %s
@var = global i32 0 @var = global i32 0
; Test how llvm handles return type of {i16, i8}. The return value will be ; Test how llvm handles return type of {i16, i8}. The return value will be
; passed in %r2 and %r3. ; passed in %r2 and %r3.
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: st %r2 ; CHECK: st %r2
; CHECK: brasl %r14, gen ; CHECK: brasl %r14, gen
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llvm/test/CodeGen/SystemZ/swifterror.ll

Show First 20 Lines • Show All 233 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; "caller3" calls "foo_sret" that takes a swifterror parameter. ; "caller3" calls "foo_sret" that takes a swifterror parameter.
define float @caller3(i8* %error_ref) { define float @caller3(i8* %error_ref) {
; CHECK-LABEL: caller3: ; CHECK-LABEL: caller3:
; Make a copy of error_ref because r2 is getting clobbered ; Make a copy of error_ref because r2 is getting clobbered
; CHECK: lgr %r[[REG1:[0-9]+]], %r2 ; CHECK: lgr %r[[REG1:[0-9]+]], %r2
; CHECK: lhi %r3, 1 ; CHECK: lghi %r3, 1
; CHECK: lghi %r9, 0 ; CHECK: lghi %r9, 0
; CHECK: brasl %r14, foo_sret ; CHECK: brasl %r14, foo_sret
; CHECK: jlh ; CHECK: jlh
; Access part of the error object and save it to error_ref ; Access part of the error object and save it to error_ref
; CHECK: lb %r0, 8(%r2) ; CHECK: lb %r0, 8(%r2)
; CHECK: stc %r0, 0(%r[[REG1]]) ; CHECK: stc %r0, 0(%r[[REG1]])
; CHECK: brasl %r14, free ; CHECK: brasl %r14, free
; CHECK-O0-LABEL: caller3: ; CHECK-O0-LABEL: caller3:
; CHECK-O0: lghi %r9, 0 ; CHECK-O0: lghi %r9, 0
; CHECK-O0: lhi %r3, 1 ; CHECK-O0: lghi %r3, 1
; CHECK-O0: brasl %r14, foo_sret ; CHECK-O0: brasl %r14, foo_sret
; CHECK-O0: lgr {{.*}}, %r9 ; CHECK-O0: lgr {{.*}}, %r9
; CHECK-O0: cghi %r9, 0 ; CHECK-O0: cghi %r9, 0
; CHECK-O0: jlh ; CHECK-O0: jlh
; Access part of the error object and save it to error_ref ; Access part of the error object and save it to error_ref
; CHECK-O0: lb %r0, 8(%r{{.*}}) ; CHECK-O0: lb %r0, 8(%r{{.*}})
; CHECK-O0: stc %r0, 0(%r{{.*}}) ; CHECK-O0: stc %r0, 0(%r{{.*}})
; reload from stack ; reload from stack
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llvm/test/CodeGen/SystemZ/tdc-01.ll

; Test the Test Data Class instruction, selected manually via the intrinsic. ; Test the Test Data Class instruction, selected manually via the intrinsic.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
declare i32 @llvm.s390.tdc.f32(float, i64) declare i32 @llvm.s390.tdc.f32(float, i64)
declare i32 @llvm.s390.tdc.f64(double, i64) declare i32 @llvm.s390.tdc.f64(double, i64)
declare i32 @llvm.s390.tdc.f128(fp128, i64) declare i32 @llvm.s390.tdc.f128(fp128, i64)
; Check using as i32 - f32 ; Check using as i32 - f32
define i32 @f1(float %x) { define i32 @f1(float %x) {
; CHECK-LABEL: f1 ; CHECK-LABEL: f1
▲ Show 20 Lines • Show All 84 Lines • Show Last 20 Lines

llvm/test/CodeGen/SystemZ/tdc-06.ll

; Test the Test Data Class instruction, as used by fpclassify. ; Test the Test Data Class instruction, as used by fpclassify.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; ;
declare float @llvm.fabs.f32(float) declare float @llvm.fabs.f32(float)
declare double @llvm.fabs.f64(double) declare double @llvm.fabs.f64(double)
declare fp128 @llvm.fabs.f128(fp128) declare fp128 @llvm.fabs.f128(fp128)
define i32 @fpc(double %x) { define i32 @fpc(double %x) {
entry: entry:
Show All 39 Lines

llvm/test/CodeGen/SystemZ/tdc-07.ll

; Test the Test Data Class instruction on z14 ; Test the Test Data Class instruction on z14
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
declare i32 @llvm.s390.tdc.f128(fp128, i64) declare i32 @llvm.s390.tdc.f128(fp128, i64)
; Check using as i32 - f128 ; Check using as i32 - f128
define i32 @f3(fp128 %x) { define i32 @f3(fp128 %x) {
; CHECK-LABEL: f3 ; CHECK-LABEL: f3
; CHECK: vl %v0, 0(%r2) ; CHECK: vl %v0, 0(%r2)
; CHECK: vrepg %v2, %v0, 1 ; CHECK: vrepg %v2, %v0, 1
; CHECK: tcxb %f0, 123 ; CHECK: tcxb %f0, 123
; CHECK: ipm %r2 ; CHECK: ipm %r0
; CHECK: srl %r2, 28 ; CHECK: risbgn %r2, %r0, 60, 191, 36
%res = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 123) %res = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 123)
ret i32 %res ret i32 %res
} }

llvm/test/CodeGen/SystemZ/trap-01.ll

Show All 12 Linesentry:
tail call void @llvm.trap() tail call void @llvm.trap()
ret i32 0 ret i32 0
} }
; Check conditional compare immediate and trap ; Check conditional compare immediate and trap
define i32 @f1(i32 signext %a) { define i32 @f1(i32 signext %a) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: cithe %r2, 15 ; CHECK: cithe %r2, 15
; CHECK: lhi %r2, 0 ; CHECK: lghi %r2, 0
; CHECK: br %r14 ; CHECK: br %r14
entry: entry:
%cmp = icmp sgt i32 %a, 14 %cmp = icmp sgt i32 %a, 14
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry if.then: ; preds = %entry
tail call void @llvm.trap() tail call void @llvm.trap()
unreachable unreachable
Show All 19 Lines
if.end: ; preds = %entry if.end: ; preds = %entry
ret i64 0 ret i64 0
} }
; Check conditional compare logical immediate and trap ; Check conditional compare logical immediate and trap
define i32 @f3(i32 zeroext %a) { define i32 @f3(i32 zeroext %a) {
; CHECK-LABEL: f3: ; CHECK-LABEL: f3:
; CHECK: clfithe %r2, 15 ; CHECK: clfithe %r2, 15
; CHECK: lhi %r2, 0 ; CHECK: lghi %r2, 0
; CHECK: br %r14 ; CHECK: br %r14
entry: entry:
%cmp = icmp ugt i32 %a, 14 %cmp = icmp ugt i32 %a, 14
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry if.then: ; preds = %entry
tail call void @llvm.trap() tail call void @llvm.trap()
unreachable unreachable
Show All 19 Lines
if.end: ; preds = %entry if.end: ; preds = %entry
ret i64 0 ret i64 0
} }
; Check conditional compare and trap ; Check conditional compare and trap
define i32 @f5(i32 signext %a, i32 signext %b) { define i32 @f5(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: f5: ; CHECK-LABEL: f5:
; CHECK: crte %r2, %r3 ; CHECK: crte %r2, %r3
; CHECK: lhi %r2, 0 ; CHECK: lghi %r2, 0
; CHECK: br %r14 ; CHECK: br %r14
entry: entry:
%cmp = icmp eq i32 %a, %b %cmp = icmp eq i32 %a, %b
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry if.then: ; preds = %entry
tail call void @llvm.trap() tail call void @llvm.trap()
unreachable unreachable
Show All 19 Lines
if.end: ; preds = %entry if.end: ; preds = %entry
ret i64 0 ret i64 0
} }
; Check conditional compare logical and trap ; Check conditional compare logical and trap
define i32 @f7(i32 zeroext %a, i32 zeroext %b) { define i32 @f7(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: f7: ; CHECK-LABEL: f7:
; CHECK: clrth %r2, %r3 ; CHECK: clrth %r2, %r3
; CHECK: lhi %r2, 0 ; CHECK: lghi %r2, 0
; CHECK: br %r14 ; CHECK: br %r14
entry: entry:
%cmp = icmp ugt i32 %a, %b %cmp = icmp ugt i32 %a, %b
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry if.then: ; preds = %entry
tail call void @llvm.trap() tail call void @llvm.trap()
unreachable unreachable
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llvm/test/CodeGen/SystemZ/trap-02.ll

; Test zE12 conditional traps ; Test zE12 conditional traps
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
declare void @llvm.trap() declare void @llvm.trap()
; Check conditional compare logical and trap ; Check conditional compare logical and trap
define i32 @f1(i32 zeroext %a, i32 *%ptr) { define i32 @f1(i32 zeroext %a, i32 *%ptr) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: clth %r2, 0(%r3) ; CHECK: clth %r2, 0(%r3)
; CHECK: lhi %r2, 0 ; CHECK: lghi %r2, 0
; CHECK: br %r14 ; CHECK: br %r14
entry: entry:
%b = load i32, i32 *%ptr %b = load i32, i32 *%ptr
%cmp = icmp ugt i32 %a, %b %cmp = icmp ugt i32 %a, %b
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry if.then: ; preds = %entry
tail call void @llvm.trap() tail call void @llvm.trap()
Show All 22 Linesif.end: ; preds = %entry
ret i64 0 ret i64 0
} }
; Verify that we don't attempt to use the compare and trap ; Verify that we don't attempt to use the compare and trap
; instruction with an index operand. ; instruction with an index operand.
define i32 @f3(i32 zeroext %a, i32 *%base, i64 %offset) { define i32 @f3(i32 zeroext %a, i32 *%base, i64 %offset) {
; CHECK-LABEL: f3: ; CHECK-LABEL: f3:
; CHECK: cl %r2, 0(%r{{[0-5]}},%r3) ; CHECK: cl %r2, 0(%r{{[0-5]}},%r3)
; CHECK: lhi %r2, 0 ; CHECK: lghi %r2, 0
; CHECK-LABEL: .Ltmp0 ; CHECK-LABEL: .Ltmp0
; CHECK: jh .Ltmp0+2 ; CHECK: jh .Ltmp0+2
; CHECK: br %r14 ; CHECK: br %r14
entry: entry:
%ptr = getelementptr i32, i32 *%base, i64 %offset %ptr = getelementptr i32, i32 *%base, i64 %offset
%b = load i32, i32 *%ptr %b = load i32, i32 *%ptr
%cmp = icmp ugt i32 %a, %b %cmp = icmp ugt i32 %a, %b
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
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llvm/test/CodeGen/SystemZ/trap-03.ll

; Test load-and-trap instructions (LAT/LGAT) ; Test load-and-trap instructions (LAT/LGAT)
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 -no-arg-exts | FileCheck %s
declare void @llvm.trap() declare void @llvm.trap()
; Check LAT with no displacement. ; Check LAT with no displacement.
define i32 @f1(i32 *%ptr) { define i32 @f1(i32 *%ptr) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: lat %r2, 0(%r2) ; CHECK: lat %r2, 0(%r2)
; CHECK: br %r14 ; CHECK: br %r14
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llvm/test/CodeGen/SystemZ/unaligned-01.ll

; Check that unaligned accesses are allowed in general. We check the ; Check that unaligned accesses are allowed in general. We check the
; few exceptions (like CRL) in their respective test files. ; few exceptions (like CRL) in their respective test files.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-arg-exts | FileCheck %s
; Check that these four byte stores become a single word store. ; Check that these four byte stores become a single word store.
define void @f1(i8 *%ptr) { define void @f1(i8 *%ptr) {
; CHECK: f1 ; CHECK: f1
; CHECK: iilf [[REG:%r[0-5]]], 66051 ; CHECK: iilf [[REG:%r[0-5]]], 66051
; CHECK: st [[REG]], 0(%r2) ; CHECK: st [[REG]], 0(%r2)
; CHECK: br %r14 ; CHECK: br %r14
%off1 = getelementptr i8, i8 *%ptr, i64 1 %off1 = getelementptr i8, i8 *%ptr, i64 1
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llvm/test/CodeGen/SystemZ/vec-combine-02.ll

Show First 20 Lines • Show All 402 Lines • ▼ Show 20 Lines
define i32 @f9(double %scalar0, double %scalar1, double %scalar2, define i32 @f9(double %scalar0, double %scalar1, double %scalar2,
double %scalar3) { double %scalar3) {
; CHECK-LABEL: f9: ; CHECK-LABEL: f9:
; CHECK-NOT: vperm ; CHECK-NOT: vperm
; CHECK-NOT: vpk ; CHECK-NOT: vpk
; CHECK-NOT: vmrh ; CHECK-NOT: vmrh
; CHECK: ar {{%r[0-5]}}, ; CHECK: ar {{%r[0-5]}},
; CHECK: ar {{%r[0-5]}}, ; CHECK: ar {{%r[0-5]}},
; CHECK: ork %r2, ; CHECK: or %r0,
; CHECK: lgfr %r2, %r0
; CHECK: br %r14 ; CHECK: br %r14
%vec0 = insertelement <2 x double> undef, double %scalar0, i32 0 %vec0 = insertelement <2 x double> undef, double %scalar0, i32 0
%vec1 = insertelement <2 x double> undef, double %scalar1, i32 0 %vec1 = insertelement <2 x double> undef, double %scalar1, i32 0
%vec2 = insertelement <2 x double> undef, double %scalar2, i32 0 %vec2 = insertelement <2 x double> undef, double %scalar2, i32 0
%vec3 = insertelement <2 x double> undef, double %scalar3, i32 0 %vec3 = insertelement <2 x double> undef, double %scalar3, i32 0
%join0 = shufflevector <2 x double> %vec0, <2 x double> %vec1, %join0 = shufflevector <2 x double> %vec0, <2 x double> %vec1,
<2 x i32> <i32 0, i32 2> <2 x i32> <i32 0, i32 2>
%join1 = shufflevector <2 x double> %vec2, <2 x double> %vec3, %join1 = shufflevector <2 x double> %vec2, <2 x double> %vec3,
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llvm/test/CodeGen/SystemZ/vec-extract-02.ll

; Verify ReplaceExtractVectorEltOfLoadWithNarrowedLoad fixes ; Verify ReplaceExtractVectorEltOfLoadWithNarrowedLoad fixes
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
; Test a case where a vector extraction can be simplified to a scalar load. ; Test a case where a vector extraction can be simplified to a scalar load.
; The index must be extended from i32 to i64. ; The index must be extended from i32 to i64.
define i32 @f1(<4 x i32> *%ptr, i32 %index) { define i32 @f1(<4 x i32> *%ptr, i32 %index) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: risbgn {{%r[0-5]}}, %r3, 60, 189, 2 ; CHECK: risbgn {{%r[0-5]}}, %r3, 60, 189, 2
; CHECK: l %r2, ; CHECK: lgf %r2,
; CHECK: br %r14 ; CHECK: br %r14
%vec = load <4 x i32>, <4 x i32> *%ptr %vec = load <4 x i32>, <4 x i32> *%ptr
%res = extractelement <4 x i32> %vec, i32 %index %res = extractelement <4 x i32> %vec, i32 %index
ret i32 %res ret i32 %res
} }

llvm/test/CodeGen/SystemZ/vec-intrinsics-01.ll

; Test vector intrinsics. ; Test vector intrinsics.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -no-arg-exts | FileCheck %s
declare i32 @llvm.s390.lcbb(i8 *, i32) declare i32 @llvm.s390.lcbb(i8 *, i32)
declare <16 x i8> @llvm.s390.vlbb(i8 *, i32) declare <16 x i8> @llvm.s390.vlbb(i8 *, i32)
declare <16 x i8> @llvm.s390.vll(i32, i8 *) declare <16 x i8> @llvm.s390.vll(i32, i8 *)
declare <2 x i64> @llvm.s390.vpdi(<2 x i64>, <2 x i64>, i32) declare <2 x i64> @llvm.s390.vpdi(<2 x i64>, <2 x i64>, i32)
declare <16 x i8> @llvm.s390.vperm(<16 x i8>, <16 x i8>, <16 x i8>) declare <16 x i8> @llvm.s390.vperm(<16 x i8>, <16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.s390.vpksh(<8 x i16>, <8 x i16>) declare <16 x i8> @llvm.s390.vpksh(<8 x i16>, <8 x i16>)
declare <8 x i16> @llvm.s390.vpksf(<4 x i32>, <4 x i32>) declare <8 x i16> @llvm.s390.vpksf(<4 x i32>, <4 x i32>)
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llvm/test/CodeGen/SystemZ/vec-intrinsics-02.ll

; Test vector intrinsics added with z14. ; Test vector intrinsics added with z14.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -no-arg-exts | FileCheck %s
declare <2 x i64> @llvm.s390.vbperm(<16 x i8>, <16 x i8>) declare <2 x i64> @llvm.s390.vbperm(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.s390.vmslg(<2 x i64>, <2 x i64>, <16 x i8>, i32) declare <16 x i8> @llvm.s390.vmslg(<2 x i64>, <2 x i64>, <16 x i8>, i32)
declare <16 x i8> @llvm.s390.vlrl(i32, i8 *) declare <16 x i8> @llvm.s390.vlrl(i32, i8 *)
declare void @llvm.s390.vstrl(<16 x i8>, i32, i8 *) declare void @llvm.s390.vstrl(<16 x i8>, i32, i8 *)
declare {<4 x i32>, i32} @llvm.s390.vfcesbs(<4 x float>, <4 x float>) declare {<4 x i32>, i32} @llvm.s390.vfcesbs(<4 x float>, <4 x float>)
declare {<4 x i32>, i32} @llvm.s390.vfchsbs(<4 x float>, <4 x float>) declare {<4 x i32>, i32} @llvm.s390.vfchsbs(<4 x float>, <4 x float>)
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llvm/test/CodeGen/SystemZ/vec-move-05.ll

; Test vector extraction. ; Test vector extraction.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -no-arg-exts | FileCheck %s
; Test v16i8 extraction of the first element. ; Test v16i8 extraction of the first element.
define i8 @f1(<16 x i8> %val) { define i8 @f1(<16 x i8> %val) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: vlgvb %r2, %v24, 0 ; CHECK: vlgvb %r2, %v24, 0
; CHECK: br %r14 ; CHECK: br %r14
%ret = extractelement <16 x i8> %val, i32 0 %ret = extractelement <16 x i8> %val, i32 0
ret i8 %ret ret i8 %ret
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llvm/test/CodeGen/SystemZ/xor-07.ll

; Test the three-operand forms of XOR. ; Test the three-operand forms of XOR.
; ;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-arg-exts | FileCheck %s
; Check XRK. ; Check XRK.
define i32 @f1(i32 %a, i32 %b, i32 %c) { define i32 @f1(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: f1: ; CHECK-LABEL: f1:
; CHECK: xrk %r2, %r3, %r4 ; CHECK: xrk %r2, %r3, %r4
; CHECK: br %r14 ; CHECK: br %r14
%xor = xor i32 %b, %c %xor = xor i32 %b, %c
ret i32 %xor ret i32 %xor
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llvm/test/DebugInfo/Generic/missing-abstract-variable.ll

; RUN: %llc_dwarf -O0 -filetype=obj < %s | llvm-dwarfdump -v -debug-info - | FileCheck %s ; RUN: %llc_dwarf -O0 -filetype=obj < %s | llvm-dwarfdump -v -debug-info - | FileCheck %s
; The formal parameter 'b' for Function 'x' when inlined within 'a' is lost on ; The formal parameter 'b' for Function 'x' when inlined within 'a' is lost on
; powerpc64 (and on x86_64 at at least -O2). Presumably this is a SelectionDAG ; powerpc64 (and on x86_64 at at least -O2). Presumably this is a SelectionDAG
; issue. ; issue.
; FIXME: arm64 is an alias for aarch64 on macs, apparently? ; FIXME: arm64 is an alias for aarch64 on macs, apparently?
; XFAIL: powerpc64, aarch64, arm64, hexagon, riscv ; FIXME: Fails on s390x (with default arg extension) due to DAGCombiner bug,
; see https://bugs.llvm.org/show_bug.cgi?id=52373.
; XFAIL: powerpc64, aarch64, arm64, hexagon, riscv, s390x
; Build from the following source with clang -O2. ; Build from the following source with clang -O2.
; The important details are that 'x's abstract definition is first built during ; The important details are that 'x's abstract definition is first built during
; the definition of 'b', where the parameter to 'x' is constant and so 'x's 's' ; the definition of 'b', where the parameter to 'x' is constant and so 'x's 's'
; variable is optimized away. No abstract definition DIE for 's' is constructed. ; variable is optimized away. No abstract definition DIE for 's' is constructed.
; Then, during 'a' emission, the abstract DbgVariable for 's' is created, but ; Then, during 'a' emission, the abstract DbgVariable for 's' is created, but
; the abstract DIE isn't (since the abstract definition for 'b' is already ; the abstract DIE isn't (since the abstract definition for 'b' is already
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llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_function_name.ll

; Check that we accept functions with '$' in the name. ; Check that we accept functions with '$' in the name.
; ;
; RUN: llc -mtriple=s390x-unknown-linux < %s | FileCheck %s ; RUN: llc -mtriple=s390x-unknown-linux < %s | FileCheck %s
; ;
define hidden i32 @"_Z54bar$ompvariant$bar"() { define hidden signext i32 @"_Z54bar$ompvariant$bar"() {
entry: entry:
ret i32 2 ret i32 2
} }

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_function_name.ll.expected

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Check that we accept functions with '$' in the name. ; Check that we accept functions with '$' in the name.
; ;
; RUN: llc -mtriple=s390x-unknown-linux < %s | FileCheck %s ; RUN: llc -mtriple=s390x-unknown-linux < %s | FileCheck %s
; ;
define hidden i32 @"_Z54bar$ompvariant$bar"() { define hidden signext i32 @"_Z54bar$ompvariant$bar"() {
; CHECK-LABEL: _Z54bar$ompvariant$bar: ; CHECK-LABEL: _Z54bar$ompvariant$bar:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhi %r2, 2 ; CHECK-NEXT: lghi %r2, 2
; CHECK-NEXT: br %r14 ; CHECK-NEXT: br %r14
entry: entry:
ret i32 2 ret i32 2
} }

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll

; RUN: llc -enable-machine-outliner -mtriple=s390x-unknown-linux < %s | FileCheck %s ; RUN: llc -enable-machine-outliner -mtriple=s390x-unknown-linux -no-arg-exts < %s \
; RUN: | FileCheck %s
; ;
; NOTE: Machine outliner doesn't run. ; NOTE: Machine outliner doesn't run.
@x = dso_local global i32 0, align 4 @x = dso_local global i32 0, align 4
define dso_local i32 @check_boundaries() #0 { define dso_local i32 @check_boundaries() #0 {
%1 = alloca i32, align 4 %1 = alloca i32, align 4
%2 = alloca i32, align 4 %2 = alloca i32, align 4
%3 = alloca i32, align 4 %3 = alloca i32, align 4
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llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.generated.expected

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --include-generated-funcs ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --include-generated-funcs
; RUN: llc -enable-machine-outliner -mtriple=s390x-unknown-linux < %s | FileCheck %s ; RUN: llc -enable-machine-outliner -mtriple=s390x-unknown-linux -no-arg-exts < %s \
; RUN: | FileCheck %s
; NOTE: Machine outliner doesn't run. ; NOTE: Machine outliner doesn't run.
@x = dso_local global i32 0, align 4 @x = dso_local global i32 0, align 4
define dso_local i32 @check_boundaries() #0 { define dso_local i32 @check_boundaries() #0 {
%1 = alloca i32, align 4 %1 = alloca i32, align 4
%2 = alloca i32, align 4 %2 = alloca i32, align 4
%3 = alloca i32, align 4 %3 = alloca i32, align 4
%4 = alloca i32, align 4 %4 = alloca i32, align 4
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llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/systemz_generated_funcs.ll.nogenerated.expected

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -enable-machine-outliner -mtriple=s390x-unknown-linux < %s | FileCheck %s ; RUN: llc -enable-machine-outliner -mtriple=s390x-unknown-linux -no-arg-exts < %s \
; RUN: | FileCheck %s
; ;
; NOTE: Machine outliner doesn't run. ; NOTE: Machine outliner doesn't run.
@x = dso_local global i32 0, align 4 @x = dso_local global i32 0, align 4
define dso_local i32 @check_boundaries() #0 { define dso_local i32 @check_boundaries() #0 {
; CHECK-LABEL: check_boundaries: ; CHECK-LABEL: check_boundaries:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: stmg %r11, %r15, 88(%r15) ; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
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