[AArch64] Async unwind - helper functions to decide on CFI emission

[efriedma]

llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp

123

It's kind of confusing to have a method called needsUnwindInfo that always returns false on Windows. Maybe name it needsDWARFUnwindInfo or something like that?

[efriedma]

LGTM

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
   MachineBasicBlock::iterator MBBI = MBB.begin();
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   const Function &F = MF.getFunction();
   const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
   MachineModuleInfo &MMI = MF.getMMI();
   AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
-  bool needsFrameMoves =
-      MF.needsFrameMoves() && !MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
+  bool EmitCFI = AFI->needsDwarfUnwindInfo();
   bool HasFP = hasFP(MF);
   bool NeedsWinCFI = needsWinCFI(MF);
   bool HasWinCFI = false;
   auto Cleanup = make_scope_exit([&]() { MF.setHasWinCFI(HasWinCFI); });
 
   bool IsFunclet = MBB.isEHFuncletEntry();
 
   // At this point, we're going to decide whether or not the function uses a
if (MFnI.shouldSignReturnAddress()) {
     }
 
     auto MI = BuildMI(MBB, MBBI, DL, TII->get(PACI));
     if (Subtarget.hasPAuth())
       MI.addReg(AArch64::LR, RegState::Define)
           .addReg(AArch64::LR)
           .addReg(AArch64::SP, RegState::InternalRead);
     MI.setMIFlag(MachineInstr::FrameSetup);
-
+    if (EmitCFI) {
       unsigned CFIIndex =
           MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr));
       BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndex)
           .setMIFlags(MachineInstr::FrameSetup);
     }
+  }
 
   // We signal the presence of a Swift extended frame to external tools by
   // storing FP with 0b0001 in bits 63:60. In normal userland operation a simple
   // ORR is sufficient, it is assumed a Swift kernel would initialize the TBI
   // bits so that is still true.
   if (HasFP && AFI->hasSwiftAsyncContext()) {
     switch (MF.getTarget().Options.SwiftAsyncFramePointer) {
     case SwiftAsyncFramePointerMode::DeploymentBased:
if (!AFI->hasStackFrame() && !windowsRequiresStackProbe(MF, NumBytes)) {
     // to actually allocate.
     if (canUseRedZone(MF)) {
       AFI->setHasRedZone(true);
       ++NumRedZoneFunctions;
     } else {
       emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP,
                       StackOffset::getFixed(-NumBytes), TII,
                       MachineInstr::FrameSetup, false, NeedsWinCFI, &HasWinCFI);
-      if (needsFrameMoves) {
+      if (EmitCFI) {
         // Label used to tie together the PROLOG_LABEL and the MachineMoves.
         MCSymbol *FrameLabel = MMI.getContext().createTempSymbol();
           // Encode the stack size of the leaf function.
         unsigned CFIIndex = MF.addFrameInst(
             MCCFIInstruction::cfiDefCfaOffset(FrameLabel, NumBytes));
         BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
             .addCFIIndex(CFIIndex)
             .setMIFlags(MachineInstr::FrameSetup);
if (IsFunclet && F.hasPersonalityFn()) {
     if (isAsynchronousEHPersonality(Per)) {
       BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::COPY), AArch64::FP)
           .addReg(AArch64::X1)
           .setMIFlag(MachineInstr::FrameSetup);
       MBB.addLiveIn(AArch64::X1);
     }
   }
 
-  if (needsFrameMoves) {
+  if (EmitCFI) {
     // An example of the prologue:
     //
     //     .globl __foo
     //     .align 2
     //  __foo:
     // Ltmp0:
     //     .cfi_startproc
     //     .cfi_personality 155, ___gxx_personality_v0
if (NeedShadowCallStackProlog) {
     // Shadow call stack prolog: str x30, [x18], #8
     BuildMI(MBB, MI, DL, TII.get(AArch64::STRXpost))
         .addReg(AArch64::X18, RegState::Define)
         .addReg(AArch64::LR)
         .addReg(AArch64::X18)
         .addImm(8)
         .setMIFlag(MachineInstr::FrameSetup);
 
+    // This instruction also makes x18 live-in to the entry block.
+    MBB.addLiveIn(AArch64::X18);
+
     if (NeedsWinCFI)
       BuildMI(MBB, MI, DL, TII.get(AArch64::SEH_Nop))
           .setMIFlag(MachineInstr::FrameSetup);
 
+    if (MF.getInfo<AArch64FunctionInfo>()->needsDwarfUnwindInfo()) {
       // Emit a CFI instruction that causes 8 to be subtracted from the value of
       // x18 when unwinding past this frame.
       static const char CFIInst[] = {
           dwarf::DW_CFA_val_expression,
           18, // register
           2,  // length
           static_cast<char>(unsigned(dwarf::DW_OP_breg18)),
           static_cast<char>(-8) & 0x7f, // addend (sleb128)
       };
       unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createEscape(
           nullptr, StringRef(CFIInst, sizeof(CFIInst))));
       BuildMI(MBB, MI, DL, TII.get(AArch64::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndex)
           .setMIFlag(MachineInstr::FrameSetup);
-
-    // This instruction also makes x18 live-in to the entry block.
-    MBB.addLiveIn(AArch64::X18);
+    }
   }
 
   if (homogeneousPrologEpilog(MF)) {
     auto MIB = BuildMI(MBB, MI, DL, TII.get(AArch64::HOM_Prolog))
                    .setMIFlag(MachineInstr::FrameSetup);
 
     for (auto &RPI : RegPairs) {
       MIB.addReg(RPI.Reg1);

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

if (ShouldSignReturnAddr) {
 
     auto MI = BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(PACI));
     if (Subtarget.hasPAuth())
       MI.addReg(AArch64::LR, RegState::Define)
           .addReg(AArch64::LR)
           .addReg(AArch64::SP, RegState::InternalRead);
     MI.setMIFlag(MachineInstr::FrameSetup);
 
+    if (MF.getInfo<AArch64FunctionInfo>()->needsDwarfUnwindInfo()) {
       unsigned CFIIndex =
           MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr));
       BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndex)
           .setMIFlags(MachineInstr::FrameSetup);
+    }
 
     // If v8.3a features are available we can replace a RET instruction by
     // RETAA or RETAB and omit the AUT instructions
     if (Subtarget.hasPAuth() && MBBAUT != MBB.end() &&
         MBBAUT->getOpcode() == AArch64::RET) {
       BuildMI(MBB, MBBAUT, DL,
               TII->get(ShouldSignReturnAddrWithAKey ? AArch64::RETAA
                                                     : AArch64::RETAB))
if (llvm::any_of(MBB.instrs(), IsNonTailCall)) {
     // Insert a save before the outlined region
     MachineInstr *STRXpre = BuildMI(MF, DebugLoc(), get(AArch64::STRXpre))
                                 .addReg(AArch64::SP, RegState::Define)
                                 .addReg(AArch64::LR)
                                 .addReg(AArch64::SP)
                                 .addImm(-16);
     It = MBB.insert(It, STRXpre);
 
+    if (MF.getInfo<AArch64FunctionInfo>()->needsDwarfUnwindInfo()) {
       const TargetSubtargetInfo &STI = MF.getSubtarget();
       const MCRegisterInfo *MRI = STI.getRegisterInfo();
       unsigned DwarfReg = MRI->getDwarfRegNum(AArch64::LR, true);
 
       // Add a CFI saying the stack was moved 16 B down.
       int64_t StackPosEntry =
           MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 16));
       BuildMI(MBB, It, DebugLoc(), get(AArch64::CFI_INSTRUCTION))
           .addCFIIndex(StackPosEntry)
           .setMIFlags(MachineInstr::FrameSetup);
 
-    // Add a CFI saying that the LR that we want to find is now 16 B higher than
-    // before.
-    int64_t LRPosEntry =
-        MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, DwarfReg, -16));
+      // Add a CFI saying that the LR that we want to find is now 16 B higher
+      // than before.
+      int64_t LRPosEntry = MF.addFrameInst(
+          MCCFIInstruction::createOffset(nullptr, DwarfReg, -16));
       BuildMI(MBB, It, DebugLoc(), get(AArch64::CFI_INSTRUCTION))
           .addCFIIndex(LRPosEntry)
           .setMIFlags(MachineInstr::FrameSetup);
+    }
 
     // Insert a restore before the terminator for the function.
     MachineInstr *LDRXpost = BuildMI(MF, DebugLoc(), get(AArch64::LDRXpost))
                                  .addReg(AArch64::SP, RegState::Define)
                                  .addReg(AArch64::LR, RegState::Define)
                                  .addReg(AArch64::SP)
                                  .addImm(16);
     Et = MBB.insert(Et, LDRXpost);

llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h

class AArch64FunctionInfo final : public MachineFunctionInfo {
   /// Whether this function has an extended frame record [Ctx, FP, LR]. If so,
   /// bit 60 of the in-memory FP will be 1 to enable other tools to detect the
   /// extended record.
   bool HasSwiftAsyncContext = false;
 
   /// The stack slot where the Swift asynchronous context is stored.
   int SwiftAsyncContextFrameIdx = std::numeric_limits<int>::max();
 
+  /// True if the function need unwind information.
+  mutable Optional<bool> NeedsDwarfUnwindInfo;
+
+  /// True if the function need asynchronous unwind information.
+  mutable Optional<bool> NeedsDwarfAsyncUnwindInfo;
+
 public:
   explicit AArch64FunctionInfo(MachineFunction &MF);
 
   void initializeBaseYamlFields(const yaml::AArch64FunctionInfo &YamlMFI);
 
   unsigned getBytesInStackArgArea() const { return BytesInStackArgArea; }
   void setBytesInStackArgArea(unsigned bytes) { BytesInStackArgArea = bytes; }
 
#endif
   }
   bool hasSwiftAsyncContext() const { return HasSwiftAsyncContext; }
 
   void setSwiftAsyncContextFrameIdx(int FI) {
     SwiftAsyncContextFrameIdx = FI;
   }
   int getSwiftAsyncContextFrameIdx() const { return SwiftAsyncContextFrameIdx; }
 
+  bool needsDwarfUnwindInfo() const;
+  bool needsAsyncDwarfUnwindInfo() const;
+
 private:
   // Hold the lists of LOHs.
   MILOHContainer LOHContainerSet;
   SetOfInstructions LOHRelated;
 
   SmallVector<std::pair<unsigned, MCSymbol *>, 2> JumpTableEntryInfo;
 };
 

llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp

 /// \file
 /// This file implements AArch64-specific per-machine-function
 /// information.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "AArch64MachineFunctionInfo.h"
 #include "AArch64InstrInfo.h"
+#include "llvm/MC/MCAsmInfo.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/Metadata.h"
 #include "llvm/IR/Module.h"
 
 using namespace llvm;
 
 yaml::AArch64FunctionInfo::AArch64FunctionInfo(
     const llvm::AArch64FunctionInfo &MFI)
bool AArch64FunctionInfo::shouldSignReturnAddress(bool SpillsLR) const {
   return SpillsLR;
 }
 
 bool AArch64FunctionInfo::shouldSignReturnAddress() const {
   return shouldSignReturnAddress(llvm::any_of(
       MF.getFrameInfo().getCalleeSavedInfo(),
       [](const auto &Info) { return Info.getReg() == AArch64::LR; }));
 }
+
+bool AArch64FunctionInfo::needsDwarfUnwindInfo() const {
+  if (!NeedsDwarfUnwindInfo.hasValue())
+    NeedsDwarfUnwindInfo = MF.needsFrameMoves() &&
+                           !MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
+
+  return NeedsDwarfUnwindInfo.getValue();
+}
+
+bool AArch64FunctionInfo::needsAsyncDwarfUnwindInfo() const {
+  if (!NeedsDwarfAsyncUnwindInfo.hasValue())
+    NeedsDwarfAsyncUnwindInfo =
+        needsDwarfUnwindInfo() &&
+        MF.getFunction().getUWTableKind() == UWTableKind::Async;
+  return NeedsDwarfAsyncUnwindInfo.getValue();
+}

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir

 # RUN: llc -mtriple=aarch64-arm-none-eabi -run-pass=prologepilog \
 # RUN: -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s
 
 # Check that we save LR to a callee-saved register when possible.
 # foo() should use a callee-saved register. However, bar() should not.
 --- |
 
   define void @foo() #0 {
     ret void
   }
 
-  define void @bar() #0 {
+  define void @bar() #1 {
     ret void
   }
 
-  attributes #0 = { nounwind "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" minsize noinline noredzone "frame-pointer"="all" }
+  attributes #0 = { nounwind         "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" minsize noinline noredzone "frame-pointer"="all" }
+  attributes #1 = { nounwind uwtable "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" minsize noinline noredzone "frame-pointer"="all" }
 ...
 ---
 # CHECK-LABEL:   name:            foo
 # CHECK:         bb.0:
 # CHECK:            frame-setup EMITBKEY
 # CHECK-NEXT:       frame-setup PACIBSP
-# CHECK-NEXT:       frame-setup CFI_INSTRUCTION negate_ra_sign_state
+# CHECK-NOT:        frame-setup CFI_INSTRUCTION negate_ra_sign_state
 # CHECK:        bb.1:
 # CHECK:            BL @[[OUTLINED_FUNCTION:OUTLINED_FUNCTION_[0-9]+]]
 # CHECK:        bb.2:
 # CHECK:            BL @[[OUTLINED_FUNCTION]]
 # CHECK:        bb.3:
 # CHECK:            BL @[[OUTLINED_FUNCTION]]
 # CHECK:        bb.4:
 # CHECK:            BL @[[OUTLINED_FUNCTION]]
body:             |
   bb.5:
     liveins: $w9
     RET undef $lr
 
 ...
 ---
 # CHECK:         name:            bar
 # CHECK:          bb.0:
+# CHECK:            frame-setup EMITBKEY
+# CHECK-NEXT:       frame-setup PACIBSP implicit-def $lr, implicit $lr, implicit $sp
+# CHECK-NEXT:       frame-setup CFI_INSTRUCTION negate_ra_sign_state
 # CHECK-NOT:        OUTLINED_FUNCTION_
 # CHECK:          bb.1:
 # CHECK-NOT:        OUTLINED_FUNCTION_
 # CHECK:          bb.2:
 # CHECK-NOT:        OUTLINED_FUNCTION_
 # CHECK:          bb.3:
 # CHECK-NOT:        OUTLINED_FUNCTION_
 # CHECK:            RET

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.mir

define dso_local void @illegal1() #0 {
     store volatile i32* %1, i32** @v, align 8
     store volatile i32* %1, i32** @v, align 8
     store volatile i32* %1, i32** @v, align 8
     store volatile i32* %1, i32** @v, align 8
     store volatile i32* %1, i32** @v, align 8
     ret void
   }
 
-  attributes #0 = { nounwind "sign-return-address"="all" "sign-return-address-key"="a_key" noinline noredzone "frame-pointer"="all" }
+  attributes #0 = { nounwind uwtable "sign-return-address"="all" "sign-return-address-key"="a_key" noinline noredzone "frame-pointer"="all" }
 
 ...
 ---
 name:            legal0
 tracksRegLiveness: true
 body:             |
   bb.0 (%ir-block.0):
   liveins: $lr