[WebAssembly] Add prototype relaxed float to int trunc instructions

[ngzhian]

Summary

Add i32x4.relaxed_trunc_f32x4_s, i32x4.relaxed_trunc_f32x4_u,
i32x4.relaxed_trunc_f64x2_s_zero, i32x4.relaxed_trunc_f64x2_u_zero.

These are only exposed as builtins, and require user opt-in.

[ngzhian]

clang/lib/CodeGen/CGBuiltin.cpp

18260–18265

@tlively I'm having trouble with this, getting this stack trace

WidenVectorResult #0: t4: v2i32 = llvm.wasm.relaxed.trunc.zero.signed TargetConstant:i32<9112>, t2

Do not know how to widen the result of this operator!
UNREACHABLE executed at /usr/local/google/home/zhin/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:3035!
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0.      Program arguments: /usr/local/google/home/zhin/ssd2/llvm-project/build-wasm/bin/llc -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+relaxed-simd -debug
1.      Running pass 'Function Pass Manager' on module '<stdin>'.
2.      Running pass 'WebAssembly Instruction Selection' on function '@relaxed_trunc_zero_s_v4i32'
 #0 0x00007f3012db05bb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/Unix/Signals.inc:565:22
 #1 0x00007f3012db0672 PrintStackTraceSignalHandler(void*) /usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/Unix/Signals.inc:632:1
 #2 0x00007f3012dae668 llvm::sys::RunSignalHandlers() /usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/Signals.cpp:97:20
 #3 0x00007f3012db000e SignalHandler(int) /usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/Unix/Signals.inc:407:1
 #4 0x00007f301276fef0 (/lib/x86_64-linux-gnu/libc.so.6+0x3cef0)
 #5 0x00007f301276fe71 raise ./signal/../sysdeps/unix/sysv/linux/raise.c:50:1
 #6 0x00007f3012759536 abort ./stdlib/abort.c:81:7
 #7 0x00007f3012c5a974 bindingsErrorHandler(void*, char const*, bool) /usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/ErrorHandling.cpp:218:55
 #8 0x00007f3016e7856c llvm::DAGTypeLegalizer::WidenVectorResult(llvm::SDNode*, unsigned int) /usr/local/google/home/zhin/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:3037:71
 #9 0x00007f3016e4a338 llvm::DAGTypeLegalizer::run() /usr/local/google/home/zhin/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:280:17
#10 0x00007f3016e4e34f llvm::SelectionDAG::LegalizeTypes() /usr/local/google/home/zhin/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:1055:37

Do I need to add some stuff to LegalizeTypes?

[tlively]

clang/lib/CodeGen/CGBuiltin.cpp

18260–18265

Sorry for the delay in review! The issue is that the code below generates the intrinsic calls with return type <2 x i32>, which is not a legal type, as well as a shuffle to get back to <4 x i32>. For the existing builtins, we use target-independent LLVM intrinsics, so LLVM already knows how to expand them, but it doesn't know how to expand these new target-specific intrinsics. Rather than piggybacking on the existing logic here, it would be good to generate intrinsics that return the expected <4 x i32> type (and no shuffle) so there is nothing to expand.

[ngzhian]

No shuffles

[ngzhian]

clang/lib/CodeGen/CGBuiltin.cpp

18260–18265

Got it, thanks! Updated in the latest diff, ptal.

[tlively]

clang/lib/CodeGen/CGBuiltin.cpp

18373–18374

This can be ConvertType(E->getType()) to calculate the LLVM type from the clang type for the call. However, it would be even better to not make these intrinsics polymorphic.

llvm/include/llvm/IR/IntrinsicsWebAssembly.td

218–219

Since these intrinsics only need to work with a single set of types each, it would be simpler to specify those types rather than make the intrinsics polymorphic. See the definition of int_wasm_q15mulr_sat_signed for an example. That would allow you to drop the type arguments from CGM.getIntrinsic() in CGBuiltin.cpp.

[ngzhian]

Make intrinsics monomorphic

[ngzhian]

Good suggestion, done.

[tlively]

LGTM, thanks!

clang/include/clang/Basic/BuiltinsWebAssembly.def

 
 TARGET_BUILTIN(__builtin_wasm_relaxed_swizzle_i8x16, "V16ScV16ScV16Sc", "nc", "relaxed-simd")
 
 TARGET_BUILTIN(__builtin_wasm_relaxed_min_f32x4, "V4fV4fV4f", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_relaxed_max_f32x4, "V4fV4fV4f", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_relaxed_min_f64x2, "V2dV2dV2d", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_relaxed_max_f64x2, "V2dV2dV2d", "nc", "relaxed-simd")
 
+TARGET_BUILTIN(__builtin_wasm_relaxed_trunc_s_i32x4_f32x4, "V4iV4f", "nc", "relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_trunc_u_i32x4_f32x4, "V4UiV4f", "nc", "relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_trunc_zero_s_i32x4_f64x2, "V4iV2d", "nc", "relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_trunc_zero_u_i32x4_f64x2, "V4UiV2d", "nc", "relaxed-simd")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/lib/CodeGen/CGBuiltin.cpp

case WebAssembly::BI__builtin_wasm_trunc_sat_zero_u_f64x2_i32x4: {
     unsigned IntNo;
     switch (BuiltinID) {
     case WebAssembly::BI__builtin_wasm_trunc_sat_zero_s_f64x2_i32x4:
       IntNo = Intrinsic::fptosi_sat;
       break;
     case WebAssembly::BI__builtin_wasm_trunc_sat_zero_u_f64x2_i32x4:
       IntNo = Intrinsic::fptoui_sat;
       break;
     default:
       llvm_unreachable("unexpected builtin ID");
     }
     llvm::Type *SrcT = Vec->getType();
     llvm::Type *TruncT =
         SrcT->getWithNewType(llvm::IntegerType::get(getLLVMContext(), 32));
     Function *Callee = CGM.getIntrinsic(IntNo, {TruncT, SrcT});
     Value *Trunc = Builder.CreateCall(Callee, Vec);
     Value *Splat = Builder.CreateVectorSplat(2, Builder.getInt32(0));
     Value *ConcatMask =
         llvm::ConstantVector::get({Builder.getInt32(0), Builder.getInt32(1),
                                    Builder.getInt32(2), Builder.getInt32(3)});
     return Builder.CreateShuffleVector(Trunc, Splat, ConcatMask);
   }
case WebAssembly::BI__builtin_wasm_relaxed_max_f64x2:
       IntNo = Intrinsic::wasm_relaxed_max;
       break;
     default:
       llvm_unreachable("unexpected builtin ID");
     }
     Function *Callee = CGM.getIntrinsic(IntNo, LHS->getType());
     return Builder.CreateCall(Callee, {LHS, RHS});
   }
+  case WebAssembly::BI__builtin_wasm_relaxed_trunc_s_i32x4_f32x4:
+  case WebAssembly::BI__builtin_wasm_relaxed_trunc_u_i32x4_f32x4:
+  case WebAssembly::BI__builtin_wasm_relaxed_trunc_zero_s_i32x4_f64x2:
+  case WebAssembly::BI__builtin_wasm_relaxed_trunc_zero_u_i32x4_f64x2: {
+    Value *Vec = EmitScalarExpr(E->getArg(0));
+    unsigned IntNo;
+    switch (BuiltinID) {
+    case WebAssembly::BI__builtin_wasm_relaxed_trunc_s_i32x4_f32x4:
+      IntNo = Intrinsic::wasm_relaxed_trunc_signed;
+      break;
+    case WebAssembly::BI__builtin_wasm_relaxed_trunc_u_i32x4_f32x4:
+      IntNo = Intrinsic::wasm_relaxed_trunc_unsigned;
+      break;
+    case WebAssembly::BI__builtin_wasm_relaxed_trunc_zero_s_i32x4_f64x2:
+      IntNo = Intrinsic::wasm_relaxed_trunc_zero_signed;
+      break;
+    case WebAssembly::BI__builtin_wasm_relaxed_trunc_zero_u_i32x4_f64x2:
+      IntNo = Intrinsic::wasm_relaxed_trunc_zero_unsigned;
+      break;
+    default:
+      llvm_unreachable("unexpected builtin ID");
+    }
+    llvm::Type *SrcT = Vec->getType();
+    llvm::Type *TruncT =
+        FixedVectorType::get(llvm::IntegerType::get(getLLVMContext(), 32), 4);
+    Function *Callee = CGM.getIntrinsic(IntNo, {TruncT, SrcT});
+    return Builder.CreateCall(Callee, {Vec});
+  }
   default:
     return nullptr;
   }
 }
 
 static std::pair<Intrinsic::ID, unsigned>
 getIntrinsicForHexagonNonGCCBuiltin(unsigned BuiltinID) {
   struct Info {

clang/test/CodeGen/builtins-wasm.c

 }
 
 f64x2 relaxed_max_f64x2(f64x2 a, f64x2 b) {
   return __builtin_wasm_relaxed_max_f64x2(a, b);
   // WEBASSEMBLY: call <2 x double> @llvm.wasm.relaxed.max.v2f64(
   // WEBASSEMBLY-SAME: <2 x double> %a, <2 x double> %b)
   // WEBASSEMBLY-NEXT: ret
 }
+
+i32x4 relaxed_trunc_s_i32x4_f32x4(f32x4 f) {
+  return __builtin_wasm_relaxed_trunc_s_i32x4_f32x4(f);
+  // WEBASSEMBLY: call <4 x i32> @llvm.wasm.relaxed.trunc.signed.v4i32.v4f32(<4 x float> %f)
+  // WEBASSEMBLY-NEXT: ret
+}
+
+u32x4 relaxed_trunc_u_i32x4_f32x4(f32x4 f) {
+  return __builtin_wasm_relaxed_trunc_u_i32x4_f32x4(f);
+  // WEBASSEMBLY: call <4 x i32> @llvm.wasm.relaxed.trunc.unsigned.v4i32.v4f32(<4 x float> %f)
+  // WEBASSEMBLY-NEXT: ret
+}
+
+i32x4 relaxed_trunc_zero_s_i32x4_f64x2(f64x2 x) {
+  return __builtin_wasm_relaxed_trunc_zero_s_i32x4_f64x2(x);
+  // WEBASSEMBLY: call <4 x i32> @llvm.wasm.relaxed.trunc.zero.signed.v4i32.v2f64(<2 x double> %x)
+  // WEBASSEMBLY-NEXT: ret
+}
+
+u32x4 relaxed_trunc_zero_u_i32x4_f64x2(f64x2 x) {
+  return __builtin_wasm_relaxed_trunc_zero_u_i32x4_f64x2(x);
+  // WEBASSEMBLY: call <4 x i32> @llvm.wasm.relaxed.trunc.zero.unsigned.v4i32.v2f64(<2 x double> %x)
+  // WEBASSEMBLY-NEXT: ret
+}

llvm/include/llvm/IR/IntrinsicsWebAssembly.td

def int_wasm_relaxed_min :
   Intrinsic<[llvm_anyvector_ty],
             [LLVMMatchType<0>, LLVMMatchType<0>],
             [IntrNoMem, IntrSpeculatable]>;
 def int_wasm_relaxed_max :
   Intrinsic<[llvm_anyvector_ty],
             [LLVMMatchType<0>, LLVMMatchType<0>],
             [IntrNoMem, IntrSpeculatable]>;
 
+def int_wasm_relaxed_trunc_signed:
+  Intrinsic<[llvm_anyvector_ty],
+            [llvm_anyvector_ty],
+            [IntrNoMem, IntrSpeculatable]>;
+
+def int_wasm_relaxed_trunc_unsigned:
+  Intrinsic<[llvm_anyvector_ty],
+            [llvm_anyvector_ty],
+            [IntrNoMem, IntrSpeculatable]>;
+
+def int_wasm_relaxed_trunc_zero_signed:
+  Intrinsic<[llvm_anyvector_ty],
+            [llvm_anyvector_ty],
+            [IntrNoMem, IntrSpeculatable]>;
+
+def int_wasm_relaxed_trunc_zero_unsigned:
+  Intrinsic<[llvm_anyvector_ty],
+            [llvm_anyvector_ty],
+            [IntrNoMem, IntrSpeculatable]>;
+
+
 //===----------------------------------------------------------------------===//
 // Thread-local storage intrinsics
 //===----------------------------------------------------------------------===//
 
 def int_wasm_tls_size :
   Intrinsic<[llvm_anyint_ty],
             [],
             [IntrNoMem, IntrSpeculatable]>;

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

defm RELAXED_FMAX_#vec :
     RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b), (outs), (ins),
               [(set (vec.vt V128:$dst), (int_wasm_relaxed_max
                 (vec.vt V128:$a), (vec.vt V128:$b)))],
               vec.prefix#".relaxed_max\t$dst, $a, $b", vec.prefix#".relaxed_max", simdopMax>;
 }
 
 defm "" : SIMD_RELAXED_FMINMAX<F32x4, 0xb4, 0xe2>;
 defm "" : SIMD_RELAXED_FMINMAX<F64x2, 0xd4, 0xee>;
+
+//===----------------------------------------------------------------------===//
+// Relaxed floating-point to int conversions
+//===----------------------------------------------------------------------===//
+
+multiclass SIMD_RELAXED_CONVERT<Vec vec, Vec arg, SDPatternOperator op, string name, bits<32> simdop> {
+  defm op#_#vec :
+    RELAXED_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
+              [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))],
+              vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>;
+}
+
+defm "" : SIMD_RELAXED_CONVERT<I32x4, F32x4, int_wasm_relaxed_trunc_signed, "relaxed_trunc_f32x4_s", 0xa5>;
+defm "" : SIMD_RELAXED_CONVERT<I32x4, F32x4, int_wasm_relaxed_trunc_unsigned, "relaxed_trunc_f32x4_u", 0xa6>;
+
+defm "" : SIMD_RELAXED_CONVERT<I32x4, F64x2, int_wasm_relaxed_trunc_zero_signed, "relaxed_trunc_f64x2_s_zero", 0xc5>;
+defm "" : SIMD_RELAXED_CONVERT<I32x4, F64x2, int_wasm_relaxed_trunc_zero_unsigned, "relaxed_trunc_f64x2_u_zero", 0xc6>;

llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

 declare <4 x i32> @llvm.wasm.laneselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
 define <4 x i32> @laneselect_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
   %v = call <4 x i32> @llvm.wasm.laneselect.v4i32(
     <4 x i32> %a, <4 x i32> %b, <4 x i32> %c
   )
   ret <4 x i32> %v
 }
 
+; CHECK-LABEL: relaxed_trunc_s_v4i32:
+; NO-CHECK-NOT: f32x4
+; CHECK-NEXT: .functype relaxed_trunc_s_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.relaxed_trunc_f32x4_s $push[[R:[0-9]+]]=, $0
+; CHECK-NEXT: return $pop[[R]]
+declare <4 x i32> @llvm.wasm.relaxed.trunc.signed.v4i32.v4f32(<4 x float>)
+define <4 x i32> @relaxed_trunc_s_v4i32(<4 x float> %x) {
+  %a = call <4 x i32> @llvm.wasm.relaxed.trunc.signed.v4i32.v4f32(<4 x float> %x)
+  ret <4 x i32> %a
+}
+
+; CHECK-LABEL: relaxed_trunc_u_v4i32:
+; NO-CHECK-NOT: f32x4
+; CHECK-NEXT: .functype relaxed_trunc_u_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.relaxed_trunc_f32x4_u $push[[R:[0-9]+]]=, $0
+; CHECK-NEXT: return $pop[[R]]
+declare <4 x i32> @llvm.wasm.relaxed.trunc.unsigned.v4i32.v4f32(<4 x float>)
+define <4 x i32> @relaxed_trunc_u_v4i32(<4 x float> %x) {
+  %a = call <4 x i32> @llvm.wasm.relaxed.trunc.unsigned.v4i32.v4f32(<4 x float> %x)
+  ret <4 x i32> %a
+}
+
+; CHECK-LABEL: relaxed_trunc_zero_s_v4i32:
+; CHECK-NEXT: .functype relaxed_trunc_zero_s_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.relaxed_trunc_f64x2_s_zero $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <4 x i32> @llvm.wasm.relaxed.trunc.zero.signed.v4i32.v2f64(<2 x double>)
+define <4 x i32> @relaxed_trunc_zero_s_v4i32(<2 x double> %x) {
+  %a = call <4 x i32> @llvm.wasm.relaxed.trunc.zero.signed.v4i32.v2f64(<2 x double> %x)
+  ret <4 x i32> %a
+}
+
+; CHECK-LABEL: relaxed_trunc_zero_u_v4i32:
+; CHECK-NEXT: .functype relaxed_trunc_zero_u_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.relaxed_trunc_f64x2_u_zero $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <4 x i32> @llvm.wasm.relaxed.trunc.zero.unsigned.v4i32.v2f64(<2 x double>)
+define <4 x i32> @relaxed_trunc_zero_u_v4i32(<2 x double> %x) {
+  %a = call <4 x i32> @llvm.wasm.relaxed.trunc.zero.unsigned.v4i32.v2f64(<2 x double> %x)
+  ret <4 x i32> %a
+}
+
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 ; CHECK-LABEL: any_v2i64:
 ; CHECK-NEXT: .functype any_v2i64 (v128) -> (i32){{$}}
 ; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.anytrue.v2i64(<2 x i64>)

llvm/test/MC/WebAssembly/simd-encodings.s

main:
     f32x4.relaxed_max
 
     # CHECK: f64x2.relaxed_min # encoding: [0xfd,0xd4,0x01]
     f64x2.relaxed_min
 
     # CHECK: f64x2.relaxed_max # encoding: [0xfd,0xee,0x01]
     f64x2.relaxed_max
 
+    # CHECK: i32x4.relaxed_trunc_f32x4_s # encoding: [0xfd,0xa5,0x01]
+    i32x4.relaxed_trunc_f32x4_s
+
+    # CHECK: i32x4.relaxed_trunc_f32x4_u # encoding: [0xfd,0xa6,0x01]
+    i32x4.relaxed_trunc_f32x4_u
+
+    # CHECK: i32x4.relaxed_trunc_f64x2_s_zero # encoding: [0xfd,0xc5,0x01]
+    i32x4.relaxed_trunc_f64x2_s_zero
+
+    # CHECK: i32x4.relaxed_trunc_f64x2_u_zero # encoding: [0xfd,0xc6,0x01]
+    i32x4.relaxed_trunc_f64x2_u_zero
+
     end_function