[X86][ABI] Do not return float/double from x87 registers when x87 is disabled

[pengfei]

Summary

This is aligned with GCC's behavior.
Also, alias -mno-fp-ret-in-387 to -mno-x87, by which we can fix pr51498.

[pengfei]

Found a mistake, working on that.

[pengfei]

Fix bugs. Ready for review now.

[nickdesaulniers]

Fixes https://bugs.llvm.org/show_bug.cgi?id=51498?

[pengfei]

In D112143#3089072, @nickdesaulniers wrote:

Fixes https://bugs.llvm.org/show_bug.cgi?id=51498?

Yes. I mentioned pr51498 in commit message :)

[nickdesaulniers]

In D112143#3089072, @nickdesaulniers wrote:

Fixes https://bugs.llvm.org/show_bug.cgi?id=51498?

sorry, I missed the PR # in the description; my mistake.

[nickdesaulniers]

clang/test/Driver/x86-target-features.c

5

If you split this test and the above change to clang/include/clang/Driver/Options.td into a separate patch on Phab, I'd be happy to accept that!

Otherwise someone more familiar with x86 will have to take a look at the below changes.

[pengfei]

clang/test/Driver/x86-target-features.c

5

This is a simple alias. Spliting it doesn't solve the initial problem. I think it's better to commit it together with the backend change.

[nickdesaulniers]

Just a comment on the ECX bit, otherwise this patch looks fine to me. Someone with more x86 knowledge may want to take a look though. Thanks for the patch!

llvm/lib/Target/X86/X86CallingConv.td

279

Is there a test case that exercises the assignment to %ecx?

[pengfei]

1. Add support for f80.
2. Add test case for 3 return values.

[pengfei]

llvm/lib/Target/X86/X86CallingConv.td

279

Add one test case for it, though I don't believe we can really generate it from frontend.

[nickdesaulniers]

llvm/test/CodeGen/X86/no-ret-in-x87-reg.ll

147–150

:(

[pengfei]

Thanks for the review!

llvm/test/CodeGen/X86/no-ret-in-x87-reg.ll

147–150

Will fix it as a follow up. D100091 aims to fix these problems.

clang/include/clang/Driver/Options.td

foreach i = {0-7} in
   def ffixed_d#i : Flag<["-"], "ffixed-d"#i>, Group<m_m68k_Features_Group>,
     HelpText<"Reserve the d"#i#" register (M68k only)">;
 
 // X86 feature flags
 def mx87 : Flag<["-"], "mx87">, Group<m_x86_Features_Group>;
 def mno_x87 : Flag<["-"], "mno-x87">, Group<m_x86_Features_Group>;
 def m80387 : Flag<["-"], "m80387">, Alias<mx87>;
 def mno_80387 : Flag<["-"], "mno-80387">, Alias<mno_x87>;
+def mno_fp_ret_in_387 : Flag<["-"], "mno-fp-ret-in-387">, Alias<mno_x87>;
 def mmmx : Flag<["-"], "mmmx">, Group<m_x86_Features_Group>;
 def mno_mmx : Flag<["-"], "mno-mmx">, Group<m_x86_Features_Group>;
 def m3dnow : Flag<["-"], "m3dnow">, Group<m_x86_Features_Group>;
 def mno_3dnow : Flag<["-"], "mno-3dnow">, Group<m_x86_Features_Group>;
 def m3dnowa : Flag<["-"], "m3dnowa">, Group<m_x86_Features_Group>;
 def mno_3dnowa : Flag<["-"], "mno-3dnowa">, Group<m_x86_Features_Group>;
 def mamx_bf16 : Flag<["-"], "mamx-bf16">, Group<m_x86_Features_Group>;
 def mno_amx_bf16 : Flag<["-"], "mno-amx-bf16">, Group<m_x86_Features_Group>;

clang/test/Driver/x86-target-features.c

 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mx87 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=X87 %s
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-x87 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-X87 %s
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -m80387 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=X87 %s
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-80387 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-X87 %s
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-fp-ret-in-387 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-X87 %s
 // X87: "-target-feature" "+x87"
 // NO-X87: "-target-feature" "-x87"
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mmmx -m3dnow -m3dnowa %s -### -o %t.o 2>&1 | FileCheck -check-prefix=MMX %s
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-mmx -mno-3dnow -mno-3dnowa %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-MMX %s
 // MMX: "-target-feature" "+mmx" "-target-feature" "+3dnow" "-target-feature" "+3dnowa"
 // NO-MMX: "-target-feature" "-mmx" "-target-feature" "-3dnow" "-target-feature" "-3dnowa"
 

llvm/lib/Target/X86/X86CallingConv.td

 def RetCC_X86_32_C : CallingConv<[
   // The X86-32 calling convention returns FP values in FP0, unless marked
   // with "inreg" (used here to distinguish one kind of reg from another,
   // weirdly; this is really the sse-regparm calling convention) in which
   // case they use XMM0, otherwise it is the same as the common X86 calling
   // conv.
   CCIfInReg<CCIfSubtarget<"hasSSE2()",
     CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
-  CCIfType<[f32,f64], CCAssignToReg<[FP0, FP1]>>,
+  CCIfSubtarget<"hasX87()",
+    CCIfType<[f32, f64], CCAssignToReg<[FP0, FP1]>>>,
+  CCIfNotSubtarget<"hasX87()",
+    CCIfType<[f32], CCAssignToReg<[EAX, EDX, ECX]>>>,
   CCIfType<[f16], CCAssignToReg<[XMM0,XMM1,XMM2]>>,
   CCDelegateTo<RetCC_X86Common>
 ]>;
 
 // X86-32 FastCC return-value convention.
 def RetCC_X86_32_Fast : CallingConv<[
   // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
   // SSE2.

llvm/lib/Target/X86/X86ISelLowering.cpp

if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
       return RegisterVT;
   }
 
   // v3f16 will be widen to v4f16. But we don't assign register class for v4f16.
   // So its default register type is f16. We override the type to v8f16 here.
   if (VT == MVT::v3f16 && Subtarget.hasFP16())
     return MVT::v8f16;
 
+  // We will use more GPRs for f64 and f80 on 32 bits when x87 is disabled.
+  if ((VT == MVT::f64 || VT == MVT::f80) && !Subtarget.is64Bit() &&
+      !Subtarget.hasX87())
+    return MVT::i32;
+
   return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
 }
 
 unsigned X86TargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
                                                           CallingConv::ID CC,
                                                           EVT VT) const {
   if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
       Subtarget.hasAVX512()) {
     unsigned NumElts = VT.getVectorNumElements();
 
     MVT RegisterVT;
     unsigned NumRegisters;
     std::tie(RegisterVT, NumRegisters) =
         handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
     if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
       return NumRegisters;
   }
 
   // v3f16 will be widen to v4f16. But we don't assign register class for v4f16.
   // So its default register number is 3. We override the number to 1 here.
   if (VT == MVT::v3f16 && Subtarget.hasFP16())
     return 1;
 
+  // We have to split f64 to 2 registers and f80 to 3 registers on 32 bits if
+  // x87 is disabled.
+  if (!Subtarget.is64Bit() && !Subtarget.hasX87()) {
+    if (VT == MVT::f64)
+      return 2;
+    if (VT == MVT::f80)
+      return 3;
+  }
+
   return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
 }
 
 unsigned X86TargetLowering::getVectorTypeBreakdownForCallingConv(
     LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
     unsigned &NumIntermediates, MVT &RegisterVT) const {
   // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
   if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&

llvm/test/CodeGen/X86/no-ret-in-x87-reg.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s -check-prefix=X87
+; RUN: llc < %s -mtriple=i686-- -mattr=-x87 | FileCheck %s -check-prefixes=NOX87,NOSSE-NOX87
+; RUN: llc < %s -mtriple=i686-- -mattr=-x87,-sse2 | FileCheck %s -check-prefixes=NOX87,NOSSE-NOX87
+; RUN: llc < %s -mtriple=i686-- -mattr=-x87,+sse2 | FileCheck %s -check-prefixes=NOX87,SSE-NOX87
+
+define float @f1(float %a, float %b) nounwind {
+; X87-LABEL: f1:
+; X87:       # %bb.0: # %entry
+; X87-NEXT:    flds {{[0-9]+}}(%esp)
+; X87-NEXT:    retl
+;
+; NOSSE-NOX87-LABEL: f1:
+; NOSSE-NOX87:       # %bb.0: # %entry
+; NOSSE-NOX87-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; NOSSE-NOX87-NEXT:    retl
+;
+; SSE-NOX87-LABEL: f1:
+; SSE-NOX87:       # %bb.0: # %entry
+; SSE-NOX87-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE-NOX87-NEXT:    movd %xmm0, %eax
+; SSE-NOX87-NEXT:    retl
+entry:
+  ret float %b
+}
+
+define double @f2(double %a, double %b) nounwind {
+; X87-LABEL: f2:
+; X87:       # %bb.0: # %entry
+; X87-NEXT:    fldl {{[0-9]+}}(%esp)
+; X87-NEXT:    retl
+;
+; NOX87-LABEL: f2:
+; NOX87:       # %bb.0: # %entry
+; NOX87-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; NOX87-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; NOX87-NEXT:    retl
+entry:
+  ret double %b
+}
+
+define x86_fp80 @f3(x86_fp80 %a, x86_fp80 %b) nounwind {
+; X87-LABEL: f3:
+; X87:       # %bb.0: # %entry
+; X87-NEXT:    fldt {{[0-9]+}}(%esp)
+; X87-NEXT:    retl
+;
+; NOX87-LABEL: f3:
+; NOX87:       # %bb.0: # %entry
+; NOX87-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; NOX87-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; NOX87-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; NOX87-NEXT:    retl
+entry:
+  ret x86_fp80 %b
+}
+
+define float @f4(float %a, float %b) nounwind {
+; X87-LABEL: f4:
+; X87:       # %bb.0: # %entry
+; X87-NEXT:    flds {{[0-9]+}}(%esp)
+; X87-NEXT:    fadds {{[0-9]+}}(%esp)
+; X87-NEXT:    retl
+;
+; NOSSE-NOX87-LABEL: f4:
+; NOSSE-NOX87:       # %bb.0: # %entry
+; NOSSE-NOX87-NEXT:    pushl {{[0-9]+}}(%esp)
+; NOSSE-NOX87-NEXT:    pushl {{[0-9]+}}(%esp)
+; NOSSE-NOX87-NEXT:    calll __addsf3
+; NOSSE-NOX87-NEXT:    addl $8, %esp
+; NOSSE-NOX87-NEXT:    retl
+;
+; SSE-NOX87-LABEL: f4:
+; SSE-NOX87:       # %bb.0: # %entry
+; SSE-NOX87-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE-NOX87-NEXT:    addss {{[0-9]+}}(%esp), %xmm0
+; SSE-NOX87-NEXT:    movd %xmm0, %eax
+; SSE-NOX87-NEXT:    retl
+entry:
+  %0 = fadd float %a, %b
+  ret float %0
+}
+
+define double @f5(double %a, double %b) nounwind {
+; X87-LABEL: f5:
+; X87:       # %bb.0: # %entry
+; X87-NEXT:    fldl {{[0-9]+}}(%esp)
+; X87-NEXT:    faddl {{[0-9]+}}(%esp)
+; X87-NEXT:    retl
+;
+; NOSSE-NOX87-LABEL: f5:
+; NOSSE-NOX87:       # %bb.0: # %entry
+; NOSSE-NOX87-NEXT:    pushl {{[0-9]+}}(%esp)
+; NOSSE-NOX87-NEXT:    pushl {{[0-9]+}}(%esp)
+; NOSSE-NOX87-NEXT:    pushl {{[0-9]+}}(%esp)
+; NOSSE-NOX87-NEXT:    pushl {{[0-9]+}}(%esp)
+; NOSSE-NOX87-NEXT:    calll __adddf3
+; NOSSE-NOX87-NEXT:    addl $16, %esp
+; NOSSE-NOX87-NEXT:    retl
+;
+; SSE-NOX87-LABEL: f5:
+; SSE-NOX87:       # %bb.0: # %entry
+; SSE-NOX87-NEXT:    pushl %ebp
+; SSE-NOX87-NEXT:    movl %esp, %ebp
+; SSE-NOX87-NEXT:    andl $-8, %esp
+; SSE-NOX87-NEXT:    subl $8, %esp
+; SSE-NOX87-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; SSE-NOX87-NEXT:    addsd 16(%ebp), %xmm0
+; SSE-NOX87-NEXT:    movsd %xmm0, (%esp)
+; SSE-NOX87-NEXT:    movl (%esp), %eax
+; SSE-NOX87-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; SSE-NOX87-NEXT:    movl %ebp, %esp
+; SSE-NOX87-NEXT:    popl %ebp
+; SSE-NOX87-NEXT:    retl
+entry:
+  %0 = fadd double %a, %b
+  ret double %0
+}
+
+; FIXME: We should not generate x87 instructions when x87 is disabled.
+define x86_fp80 @f6(x86_fp80 %a, x86_fp80 %b) nounwind {
+; X87-LABEL: f6:
+; X87:       # %bb.0: # %entry
+; X87-NEXT:    fldt {{[0-9]+}}(%esp)
+; X87-NEXT:    fldt {{[0-9]+}}(%esp)
+; X87-NEXT:    faddp %st, %st(1)
+; X87-NEXT:    retl
+;
+; NOX87-LABEL: f6:
+; NOX87:       # %bb.0: # %entry
+; NOX87-NEXT:    pushl %ebp
+; NOX87-NEXT:    movl %esp, %ebp
+; NOX87-NEXT:    andl $-8, %esp
+; NOX87-NEXT:    subl $48, %esp
+; NOX87-NEXT:    movl 20(%ebp), %eax
+; NOX87-NEXT:    movl 24(%ebp), %ecx
+; NOX87-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; NOX87-NEXT:    movl %eax, {{[0-9]+}}(%esp)
+; NOX87-NEXT:    movl 28(%ebp), %eax
+; NOX87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
+; NOX87-NEXT:    movl 8(%ebp), %eax
+; NOX87-NEXT:    movl 12(%ebp), %ecx
+; NOX87-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; NOX87-NEXT:    movl %eax, {{[0-9]+}}(%esp)
+; NOX87-NEXT:    movl 16(%ebp), %eax
+; NOX87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
+; NOX87-NEXT:    fldt {{[0-9]+}}(%esp)
+; NOX87-NEXT:    fldt {{[0-9]+}}(%esp)
+; NOX87-NEXT:    faddp %st, %st(1)
+; NOX87-NEXT:    fstpt (%esp)
+; NOX87-NEXT:    movl (%esp), %eax
+; NOX87-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; NOX87-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
+; NOX87-NEXT:    movl %ebp, %esp
+; NOX87-NEXT:    popl %ebp
+; NOX87-NEXT:    retl
+entry:
+  %0 = fadd x86_fp80 %a, %b
+  ret x86_fp80 %0
+}
+
+define {float, float, float} @f7(float %a, float %b) nounwind {
+; X87-LABEL: f7:
+; X87:       # %bb.0: # %entry
+; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X87-NEXT:    flds {{[0-9]+}}(%esp)
+; X87-NEXT:    flds {{[0-9]+}}(%esp)
+; X87-NEXT:    fstps 8(%eax)
+; X87-NEXT:    fsts 4(%eax)
+; X87-NEXT:    fstps (%eax)
+; X87-NEXT:    retl $4
+;
+; NOSSE-NOX87-LABEL: f7:
+; NOSSE-NOX87:       # %bb.0: # %entry
+; NOSSE-NOX87-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; NOSSE-NOX87-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; NOSSE-NOX87-NEXT:    movl %eax, %edx
+; NOSSE-NOX87-NEXT:    retl
+;
+; SSE-NOX87-LABEL: f7:
+; SSE-NOX87:       # %bb.0: # %entry
+; SSE-NOX87-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE-NOX87-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE-NOX87-NEXT:    movd %xmm0, %eax
+; SSE-NOX87-NEXT:    movd %xmm0, %edx
+; SSE-NOX87-NEXT:    movd %xmm1, %ecx
+; SSE-NOX87-NEXT:    retl
+entry:
+  %0 = insertvalue {float, float, float} undef, float %a, 0
+  %1 = insertvalue {float, float, float} %0, float %a, 1
+  %2 = insertvalue {float, float, float} %1, float %b, 2
+  ret {float, float, float} %2
+}