[WebAssembly] Add prototype relaxed swizzle instructions

[ngzhian]

Summary

Add i8x16 relaxed_swizzle instructions. These are only
exposed as builtins, and require user opt-in.

[ngzhian]

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

1365

@tlively i'm not 100% sure if this is needed or the right thing to do, i looked at what i8x16.swizzle currently does and just replaced the name and opcode. LMK if this needs to be changed.

[ngzhian]

Add title for relaxed swizzle instruction

[ngzhian]

Wrong commits

[tlively]

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

1365

HANDLE_NODETYPE(RELAXED_SWIZZLE)

and

def wasm_relaxed_swizzle : SDNode<"WebAssemblyISD::RELAXED_SWIZZLE", wasm_swizzle_t>;

Are both necessary when we do more interesting codegen optimizations from the C++, but in this case we want to just directly select the intrinsic, so they aren't necessary. For the pattern inside the definition of RELAXED_SWIZZLE below, you can just use int_wasm_relaxed_swizzle rather than defining and using the separate wasm_relaxed_swizzle. That will let you get rid of the separate Pat below as well.

[ngzhian]

• Remove RELAXED_SWIZZLE sdnode

[tlively]

Thanks! I'll go ahead and land this.

clang/include/clang/Basic/BuiltinsWebAssembly.def

 TARGET_BUILTIN(__builtin_wasm_fma_f64x2, "V2dV2dV2dV2d", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_fms_f64x2, "V2dV2dV2dV2d", "nc", "relaxed-simd")
 
 TARGET_BUILTIN(__builtin_wasm_laneselect_i8x16, "V16ScV16ScV16ScV16Sc", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_laneselect_i16x8, "V8sV8sV8sV8s", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_laneselect_i32x4, "V4iV4iV4iV4i", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_laneselect_i64x2, "V2LLiV2LLiV2LLiV2LLi", "nc", "relaxed-simd")
 
+TARGET_BUILTIN(__builtin_wasm_relaxed_swizzle_i8x16, "V16ScV16ScV16Sc", "nc", "relaxed-simd")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/lib/CodeGen/CGBuiltin.cpp

Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
   case WebAssembly::BI__builtin_wasm_laneselect_i64x2: {
     Value *A = EmitScalarExpr(E->getArg(0));
     Value *B = EmitScalarExpr(E->getArg(1));
     Value *C = EmitScalarExpr(E->getArg(2));
     Function *Callee =
         CGM.getIntrinsic(Intrinsic::wasm_laneselect, A->getType());
     return Builder.CreateCall(Callee, {A, B, C});
   }
+  case WebAssembly::BI__builtin_wasm_relaxed_swizzle_i8x16: {
+    Value *Src = EmitScalarExpr(E->getArg(0));
+    Value *Indices = EmitScalarExpr(E->getArg(1));
+    Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_relaxed_swizzle);
+    return Builder.CreateCall(Callee, {Src, Indices});
+  }
   default:
     return nullptr;
   }
 }
 
 static std::pair<Intrinsic::ID, unsigned>
 getIntrinsicForHexagonNonGCCBuiltin(unsigned BuiltinID) {
   struct Info {

clang/test/CodeGen/builtins-wasm.c

 }
 
 i64x2 laneselect_i64x2(i64x2 a, i64x2 b, i64x2 c) {
   return __builtin_wasm_laneselect_i64x2(a, b, c);
   // WEBASSEMBLY: call <2 x i64> @llvm.wasm.laneselect.v2i64(
   // WEBASSEMBLY-SAME: <2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
   // WEBASSEMBLY-NEXT: ret
 }
+
+i8x16 relaxed_swizzle_i8x16(i8x16 x, i8x16 y) {
+  return __builtin_wasm_relaxed_swizzle_i8x16(x, y);
+  // WEBASSEMBLY: call <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8> %x, <16 x i8> %y)
+}

llvm/include/llvm/IR/IntrinsicsWebAssembly.td

Intrinsic<[llvm_anyvector_ty],
             [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
             [IntrNoMem, IntrSpeculatable]>;
 
 def int_wasm_laneselect :
   Intrinsic<[llvm_anyvector_ty],
             [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
             [IntrNoMem, IntrSpeculatable]>;
 
+def int_wasm_relaxed_swizzle :
+  Intrinsic<[llvm_v16i8_ty],
+            [llvm_v16i8_ty, llvm_v16i8_ty],
+            [IntrNoMem, IntrSpeculatable]>;
+
 //===----------------------------------------------------------------------===//
 // Thread-local storage intrinsics
 //===----------------------------------------------------------------------===//
 
 def int_wasm_tls_size :
   Intrinsic<[llvm_anyint_ty],
             [],
             [IntrNoMem, IntrSpeculatable]>;

llvm/lib/Target/WebAssembly/WebAssemblyISD.def

 HANDLE_NODETYPE(MEMORY_COPY)
 HANDLE_NODETYPE(MEMORY_FILL)
 
 // Memory intrinsics
 HANDLE_MEM_NODETYPE(LOAD_SPLAT)
 HANDLE_MEM_NODETYPE(GLOBAL_GET)
 HANDLE_MEM_NODETYPE(GLOBAL_SET)
 HANDLE_MEM_NODETYPE(TABLE_SET)
+
+// Relaxed SIMD proposal.
+HANDLE_NODETYPE(RELAXED_SWIZZLE)

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), (outs), (ins),
                 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
               vec.prefix#".laneselect\t$dst, $a, $b, $c", vec.prefix#".laneselect", op>;
 }
 
 defm "" : SIMDLANESELECT<I8x16, 0xb2>;
 defm "" : SIMDLANESELECT<I16x8, 0xb3>;
 defm "" : SIMDLANESELECT<I32x4, 0xd2>;
 defm "" : SIMDLANESELECT<I64x2, 0xd3>;
+
+def wasm_relaxed_swizzle : SDNode<"WebAssemblyISD::RELAXED_SWIZZLE", wasm_swizzle_t>;
+
+defm RELAXED_SWIZZLE :
+  RELAXED_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins),
+         [(set (v16i8 V128:$dst),
+           (wasm_relaxed_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))],
+         "i8x16.relaxed_swizzle\t$dst, $src, $mask", "i8x16.relaxed_swizzle", 162>;
+
+def : Pat<(int_wasm_relaxed_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)),
+          (RELAXED_SWIZZLE $src, $mask)>;

llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

 declare <16 x i8> @llvm.wasm.laneselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
 define <16 x i8> @laneselect_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
   %v = call <16 x i8> @llvm.wasm.laneselect.v16i8(
     <16 x i8> %a, <16 x i8> %b, <16 x i8> %c
   )
   ret <16 x i8> %v
 }
 
+; CHECK-LABEL: relaxed_swizzle_v16i8:
+; CHECK-NEXT: .functype relaxed_swizzle_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.relaxed_swizzle $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8>, <16 x i8>)
+define <16 x i8> @relaxed_swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) {
+  %a = call <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8> %x, <16 x i8> %y)
+  ret <16 x i8> %a
+}
+
 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
 ; CHECK-LABEL: add_sat_s_v8i16:
 ; CHECK-NEXT: .functype add_sat_s_v8i16 (v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i16x8.add_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)

llvm/test/MC/WebAssembly/simd-encodings.s

main:
     i16x8.laneselect
 
     # CHECK: i32x4.laneselect # encoding: [0xfd,0xd2,0x01]
     i32x4.laneselect
 
     # CHECK: i64x2.laneselect # encoding: [0xfd,0xd3,0x01]
     i64x2.laneselect
 
+    # CHECK: i8x16.relaxed_swizzle # encoding: [0xfd,0xa2,0x01]
+    i8x16.relaxed_swizzle
+
     end_function