This is an archive of the discontinued LLVM Phabricator instance.

Differential D110009

[asan] Changed ASan intrinsic to be X86 specific.
AbandonedPublic

Authored by kstoimenov on Sep 17 2021, 3:39 PM.

Details

Reviewers
eugenis
vitalybuka
Summary

Main reason for this change is to add this to the list of instructions which set hasCopyImplyingStackAdjustment to fix the redzone crash. The actual fix will come in the next patch.

Diff Detail

Revision Contents

PathSize
llvm/
include/
llvm/
IR/
3 lines
7 lines
lib/
Target/
X86/
2 lines
Transforms/
Instrumentation/
5 lines
test/
CodeGen/
X86/
37 lines
38 lines
Instrumentation/
AddressSanitizer/
40 lines

Diff 373354

llvm/include/llvm/IR/Intrinsics.td

Show First 20 Lines • Show All 1,629 Lines • ▼ Show 20 Lines
// Create a branch funnel that implements an indirect call to a limited set of // Create a branch funnel that implements an indirect call to a limited set of
// callees. This needs to be a musttail call. // callees. This needs to be a musttail call.
def int_icall_branch_funnel : DefaultAttrsIntrinsic<[], [llvm_vararg_ty], []>; def int_icall_branch_funnel : DefaultAttrsIntrinsic<[], [llvm_vararg_ty], []>;
def int_load_relative: DefaultAttrsIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_anyint_ty], def int_load_relative: DefaultAttrsIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_anyint_ty],
[IntrReadMem, IntrArgMemOnly]>; [IntrReadMem, IntrArgMemOnly]>;
def int_asan_check_memaccess :
Intrinsic<[],[llvm_ptr_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
def int_hwasan_check_memaccess : def int_hwasan_check_memaccess :
Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty],
[ImmArg<ArgIndex<2>>]>; [ImmArg<ArgIndex<2>>]>;
def int_hwasan_check_memaccess_shortgranules : def int_hwasan_check_memaccess_shortgranules :
Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty],
[ImmArg<ArgIndex<2>>]>; [ImmArg<ArgIndex<2>>]>;
// Xray intrinsics // Xray intrinsics
▲ Show 20 Lines • Show All 215 Lines • Show Last 20 Lines

llvm/include/llvm/IR/IntrinsicsX86.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
// Read processor ID. // Read processor ID.
let TargetPrefix = "x86" in { let TargetPrefix = "x86" in {
def int_x86_rdpid : GCCBuiltin<"__builtin_ia32_rdpid">, def int_x86_rdpid : GCCBuiltin<"__builtin_ia32_rdpid">,
Intrinsic<[llvm_i32_ty], [], []>; Intrinsic<[llvm_i32_ty], [], []>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Sanitizer support.
let TargetPrefix = "x86" in {
def int_x86_asan_check_memaccess :
Intrinsic<[],[llvm_ptr_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
}
//===----------------------------------------------------------------------===//
// CET SS // CET SS
let TargetPrefix = "x86" in { let TargetPrefix = "x86" in {
def int_x86_incsspd : GCCBuiltin<"__builtin_ia32_incsspd">, def int_x86_incsspd : GCCBuiltin<"__builtin_ia32_incsspd">,
Intrinsic<[], [llvm_i32_ty], []>; Intrinsic<[], [llvm_i32_ty], []>;
def int_x86_incsspq : GCCBuiltin<"__builtin_ia32_incsspq">, def int_x86_incsspq : GCCBuiltin<"__builtin_ia32_incsspq">,
Intrinsic<[], [llvm_i64_ty], []>; Intrinsic<[], [llvm_i64_ty], []>;
def int_x86_rdsspd : GCCBuiltin<"__builtin_ia32_rdsspd">, def int_x86_rdsspd : GCCBuiltin<"__builtin_ia32_rdsspd">,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty], []>; Intrinsic<[llvm_i32_ty], [llvm_i32_ty], []>;
▲ Show 20 Lines • Show All 5,795 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86InstrCompiler.td

Show First 20 Lines • Show All 261 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Pseudo instructions used by address sanitizer. // Pseudo instructions used by address sanitizer.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let let
Defs = [R8, EFLAGS] in { Defs = [R8, EFLAGS] in {
def ASAN_CHECK_MEMACCESS : PseudoI< def ASAN_CHECK_MEMACCESS : PseudoI<
(outs), (ins GR64NoR8:$addr, i32imm:$accessinfo), (outs), (ins GR64NoR8:$addr, i32imm:$accessinfo),
[(int_asan_check_memaccess GR64NoR8:$addr, (i32 timm:$accessinfo))]>, [(int_x86_asan_check_memaccess GR64NoR8:$addr, (i32 timm:$accessinfo))]>,
Sched<[]>; Sched<[]>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Pseudo instructions used by segmented stacks. // Pseudo instructions used by segmented stacks.
// //
// This is lowered into a RET instruction by MCInstLower. We need // This is lowered into a RET instruction by MCInstLower. We need
▲ Show 20 Lines • Show All 1,930 Lines • Show Last 20 Lines

llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
#include "llvm/IR/IRBuilder.h" #include "llvm/IR/IRBuilder.h"
#include "llvm/IR/InlineAsm.h" #include "llvm/IR/InlineAsm.h"
#include "llvm/IR/InstVisitor.h" #include "llvm/IR/InstVisitor.h"
#include "llvm/IR/InstrTypes.h" #include "llvm/IR/InstrTypes.h"
#include "llvm/IR/Instruction.h" #include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h" #include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h" #include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsX86.h"
#include "llvm/IR/LLVMContext.h" #include "llvm/IR/LLVMContext.h"
#include "llvm/IR/MDBuilder.h" #include "llvm/IR/MDBuilder.h"
#include "llvm/IR/Metadata.h" #include "llvm/IR/Metadata.h"
#include "llvm/IR/Module.h" #include "llvm/IR/Module.h"
#include "llvm/IR/Type.h" #include "llvm/IR/Type.h"
#include "llvm/IR/Use.h" #include "llvm/IR/Use.h"
#include "llvm/IR/Value.h" #include "llvm/IR/Value.h"
#include "llvm/InitializePasses.h" #include "llvm/InitializePasses.h"
▲ Show 20 Lines • Show All 1,729 Lines • ▼ Show 20 Lines if (!InsertBefore)
return; return;
} }
IRBuilder<> IRB(InsertBefore); IRBuilder<> IRB(InsertBefore);
size_t AccessSizeIndex = TypeSizeToSizeIndex(TypeSize); size_t AccessSizeIndex = TypeSizeToSizeIndex(TypeSize);
const ASanAccessInfo AccessInfo(IsWrite, CompileKernel, AccessSizeIndex); const ASanAccessInfo AccessInfo(IsWrite, CompileKernel, AccessSizeIndex);
if (UseCalls && ClOptimizeCallbacks) { if (UseCalls && ClOptimizeCallbacks) {
if (!TargetTriple.isX86())
llvm_unreachable("Flag -asan-optimize-callbacks is X86 only!");
const ASanAccessInfo AccessInfo(IsWrite, CompileKernel, AccessSizeIndex); const ASanAccessInfo AccessInfo(IsWrite, CompileKernel, AccessSizeIndex);
Module *M = IRB.GetInsertBlock()->getParent()->getParent(); Module *M = IRB.GetInsertBlock()->getParent()->getParent();
IRB.CreateCall( IRB.CreateCall(
Intrinsic::getDeclaration(M, Intrinsic::asan_check_memaccess), Intrinsic::getDeclaration(M, llvm::Intrinsic::x86_asan_check_memaccess),
{IRB.CreatePointerCast(Addr, Int8PtrTy), {IRB.CreatePointerCast(Addr, Int8PtrTy),
ConstantInt::get(Int32Ty, AccessInfo.Packed)}); ConstantInt::get(Int32Ty, AccessInfo.Packed)});
return; return;
} }
Value *AddrLong = IRB.CreatePointerCast(Addr, IntptrTy); Value *AddrLong = IRB.CreatePointerCast(Addr, IntptrTy);
if (UseCalls) { if (UseCalls) {
if (Exp == 0) if (Exp == 0)
▲ Show 20 Lines • Show All 1,842 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/asan-check-memaccess-add.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc < %s | FileCheck %s
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define void @load1(i8* nocapture readonly %x) { define void @load1(i8* nocapture readonly %x) {
; CHECK: callq __asan_check_load1_rn[[RN1:.*]] ; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
; CHECK: callq __asan_check_store1_rn[[RN1]] ; CHECK-NEXT: callq __asan_check_store1_rn[[RN1]]
; CHECK-NEXT: retq call void @llvm.x86.asan.check.memaccess(i8* %x, i32 0)
call void @llvm.asan.check.memaccess(i8* %x, i32 0) call void @llvm.x86.asan.check.memaccess(i8* %x, i32 32)
call void @llvm.asan.check.memaccess(i8* %x, i32 32)
ret void ret void
} }
define void @load2(i16* nocapture readonly %x) { define void @load2(i16* nocapture readonly %x) {
; CHECK: callq __asan_check_load2_rn[[RN2:.*]] ; CHECK: callq __asan_check_load2_rn[[RN2:.*]]
; CHECK: callq __asan_check_store2_rn[[RN2]] ; CHECK-NEXT: callq __asan_check_store2_rn[[RN2]]
; CHECK-NEXT: retq
%1 = ptrtoint i16* %x to i64 %1 = ptrtoint i16* %x to i64
%2 = bitcast i16* %x to i8* %2 = bitcast i16* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 2) call void @llvm.x86.asan.check.memaccess(i8* %2, i32 2)
call void @llvm.asan.check.memaccess(i8* %2, i32 34) call void @llvm.x86.asan.check.memaccess(i8* %2, i32 34)
ret void ret void
} }
define void @load4(i32* nocapture readonly %x) { define void @load4(i32* nocapture readonly %x) {
; CHECK: callq __asan_check_load4_rn[[RN4:.*]] ; CHECK: callq __asan_check_load4_rn[[RN4:.*]]
; CHECK: callq __asan_check_store4_rn[[RN4]] ; CHECK-NEXT: callq __asan_check_store4_rn[[RN4]]
; CHECK-NEXT: retq
%1 = ptrtoint i32* %x to i64 %1 = ptrtoint i32* %x to i64
%2 = bitcast i32* %x to i8* %2 = bitcast i32* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 4) call void @llvm.x86.asan.check.memaccess(i8* %2, i32 4)
call void @llvm.asan.check.memaccess(i8* %2, i32 36) call void @llvm.x86.asan.check.memaccess(i8* %2, i32 36)
ret void ret void
} }
define void @load8(i64* nocapture readonly %x) { define void @load8(i64* nocapture readonly %x) {
; CHECK: callq __asan_check_load8_rn[[RN8:.*]] ; CHECK: callq __asan_check_load8_rn[[RN8:.*]]
; CHECK: callq __asan_check_store8_rn[[RN8]] ; CHECK-NEXT: callq __asan_check_store8_rn[[RN8]]
; CHECK-NEXT: retq
%1 = ptrtoint i64* %x to i64 %1 = ptrtoint i64* %x to i64
%2 = bitcast i64* %x to i8* %2 = bitcast i64* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 6) call void @llvm.x86.asan.check.memaccess(i8* %2, i32 6)
call void @llvm.asan.check.memaccess(i8* %2, i32 38) call void @llvm.x86.asan.check.memaccess(i8* %2, i32 38)
ret void ret void
} }
define void @load16(i128* nocapture readonly %x) { define void @load16(i128* nocapture readonly %x) {
; CHECK: callq __asan_check_load16_rn[[RN16:.*]] ; CHECK: callq __asan_check_load16_rn[[RN16:.*]]
; CHECK: callq __asan_check_store16_rn[[RN16]] ; CHECK-NEXT: callq __asan_check_store16_rn[[RN16]]
; CHECK-NEXT: retq
%1 = ptrtoint i128* %x to i64 %1 = ptrtoint i128* %x to i64
%2 = bitcast i128* %x to i8* %2 = bitcast i128* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 8) call void @llvm.x86.asan.check.memaccess(i8* %2, i32 8)
call void @llvm.asan.check.memaccess(i8* %2, i32 40) call void @llvm.x86.asan.check.memaccess(i8* %2, i32 40)
ret void ret void
} }
; CHECK: .type __asan_check_load1_rn[[RN1]],@function ; CHECK: .type __asan_check_load1_rn[[RN1]],@function
; CHECK-NEXT: .weak __asan_check_load1_rn[[RN1]] ; CHECK-NEXT: .weak __asan_check_load1_rn[[RN1]]
; CHECK-NEXT: .hidden __asan_check_load1_rn[[RN1]] ; CHECK-NEXT: .hidden __asan_check_load1_rn[[RN1]]
; CHECK-NEXT: __asan_check_load1_rn[[RN1]]: ; CHECK-NEXT: __asan_check_load1_rn[[RN1]]:
; CHECK-NEXT: movq [[REG:.*]], %r8 ; CHECK-NEXT: movq [[REG:.*]], %r8
▲ Show 20 Lines • Show All 173 Lines • ▼ Show 20 Lines
; CHECK-NEXT: cmpw $0, 2147450880(%r8) ; CHECK-NEXT: cmpw $0, 2147450880(%r8)
; CHECK-NEXT: jne [[FAIL:.*]] ; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]: ; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]: ; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi ; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store16@PLT ; CHECK-NEXT: jmp __asan_report_store16@PLT
declare void @llvm.asan.check.memaccess(i8*, i32 immarg) declare void @llvm.x86.asan.check.memaccess(i8*, i32 immarg)

llvm/test/CodeGen/X86/asan-check-memaccess-or.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc < %s | FileCheck %s
target triple = "x86_64-pc-win" target triple = "x86_64-pc-win"
define void @load1(i8* nocapture readonly %x) { define void @load1(i8* nocapture readonly %x) {
; CHECK: callq __asan_check_load1_rn[[RN1:.*]] ; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
; CHECK: callq __asan_check_store1_rn[[RN1]] ; CHECK-NEXT: callq __asan_check_store1_rn[[RN1]]
; CHECK-NEXT: retq call void @llvm.x86.asan.check.memaccess(i8* %x, i32 0)
call void @llvm.asan.check.memaccess(i8* %x, i32 0) call void @llvm.x86.asan.check.memaccess(i8* %x, i32 32)
call void @llvm.asan.check.memaccess(i8* %x, i32 32)
ret void ret void
} }
define void @load2(i16* nocapture readonly %x) { define void @load2(i16* nocapture readonly %x) {
; CHECK: callq __asan_check_load2_rn[[RN2:.*]] ; CHECK: callq __asan_check_load2_rn[[RN2:.*]]
; CHECK: callq __asan_check_store2_rn[[RN2]] ; CHECK-NEXT: callq __asan_check_store2_rn[[RN2]]
; CHECK-NEXT: retq
%1 = ptrtoint i16* %x to i64 %1 = ptrtoint i16* %x to i64
%2 = bitcast i16* %x to i8* %2 = bitcast i16* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 2) call void @llvm.x86.asan.check.memaccess(i8* %2, i32 2)
call void @llvm.asan.check.memaccess(i8* %2, i32 34) call void @llvm.x86.asan.check.memaccess(i8* %2, i32 34)
ret void ret void
} }
define void @load4(i32* nocapture readonly %x) { define void @load4(i32* nocapture readonly %x) {
; CHECK: callq __asan_check_load4_rn[[RN4:.*]] ; CHECK: callq __asan_check_load4_rn[[RN4:.*]]
; CHECK: callq __asan_check_store4_rn[[RN4]] ; CHECK-NEXT: callq __asan_check_store4_rn[[RN4]]
; CHECK-NEXT: retq
%1 = ptrtoint i32* %x to i64 %1 = ptrtoint i32* %x to i64
%2 = bitcast i32* %x to i8* %2 = bitcast i32* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 4) call void @llvm.x86.asan.check.memaccess(i8* %2, i32 4)
call void @llvm.asan.check.memaccess(i8* %2, i32 36) call void @llvm.x86.asan.check.memaccess(i8* %2, i32 36)
ret void ret void
} }
define void @load8(i64* nocapture readonly %x) { define void @load8(i64* nocapture readonly %x) {
; CHECK: callq __asan_check_load8_rn[[RN8:.*]] ; CHECK: callq __asan_check_load8_rn[[RN8:.*]]
; CHECK: callq __asan_check_store8_rn[[RN8]] ; CHECK-NEXT: callq __asan_check_store8_rn[[RN8]]
; CHECK-NEXT: retq
%1 = ptrtoint i64* %x to i64 %1 = ptrtoint i64* %x to i64
%2 = bitcast i64* %x to i8* %2 = bitcast i64* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 6) call void @llvm.x86.asan.check.memaccess(i8* %2, i32 6)
call void @llvm.asan.check.memaccess(i8* %2, i32 38) call void @llvm.x86.asan.check.memaccess(i8* %2, i32 38)
ret void ret void
} }
define void @load16(i128* nocapture readonly %x) { define void @load16(i128* nocapture readonly %x) {
; CHECK: callq __asan_check_load16_rn[[RN16:.*]] ; CHECK: callq __asan_check_load16_rn[[RN16:.*]]
; CHECK: callq __asan_check_store16_rn[[RN16]] ; CHECK-NEXT: callq __asan_check_store16_rn[[RN16]]
; CHECK-NEXT: retq
%1 = ptrtoint i128* %x to i64 %1 = ptrtoint i128* %x to i64
%2 = bitcast i128* %x to i8* %2 = bitcast i128* %x to i8*
call void @llvm.asan.check.memaccess(i8* %2, i32 8) call void @llvm.x86.asan.check.memaccess(i8* %2, i32 8)
call void @llvm.asan.check.memaccess(i8* %2, i32 40) call void @llvm.x86.asan.check.memaccess(i8* %2, i32 40)
ret void ret void
} }
; CHECK: .type __asan_check_load1_rn[[RN1]],@function ; CHECK: .type __asan_check_load1_rn[[RN1]],@function
; CHECK-NEXT: .weak __asan_check_load1_rn[[RN1]] ; CHECK-NEXT: .weak __asan_check_load1_rn[[RN1]]
; CHECK-NEXT: .hidden __asan_check_load1_rn[[RN1]] ; CHECK-NEXT: .hidden __asan_check_load1_rn[[RN1]]
; CHECK-NEXT: __asan_check_load1_rn[[RN1]]: ; CHECK-NEXT: __asan_check_load1_rn[[RN1]]:
; CHECK-NEXT: movq [[REG:.*]], %r8 ; CHECK-NEXT: movq [[REG:.*]], %r8
; CHECK-NEXT: shrq $3, %r8 ; CHECK-NEXT: shrq $3, %r8
; CHECK-NEXT: orq $17592186044416, %r8{{.*}} ; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
; CHECK-NEXT: movb (%r8), %r8b ; CHECK-NEXT: movb (%r8), %r8b
▲ Show 20 Lines • Show All 180 Lines • ▼ Show 20 Lines
; CHECK-NEXT: cmpw $0, (%r8) ; CHECK-NEXT: cmpw $0, (%r8)
; CHECK-NEXT: jne [[FAIL:.*]] ; CHECK-NEXT: jne [[FAIL:.*]]
; CHECK-NEXT: [[RET:.*]]: ; CHECK-NEXT: [[RET:.*]]:
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: [[FAIL]]: ; CHECK-NEXT: [[FAIL]]:
; CHECK-NEXT: movq [[REG:.*]], %rdi ; CHECK-NEXT: movq [[REG:.*]], %rdi
; CHECK-NEXT: jmp __asan_report_store16@PLT ; CHECK-NEXT: jmp __asan_report_store16@PLT
declare void @llvm.asan.check.memaccess(i8*, i32 immarg) declare void @llvm.x86.asan.check.memaccess(i8*, i32 immarg)

llvm/test/Instrumentation/AddressSanitizer/asan-optimize-callbacks.ll

; RUN: opt < %s -passes=asan-pipeline -asan-instrumentation-with-call-threshold=0 \ ; RUN: opt < %s -passes=asan-pipeline -asan-instrumentation-with-call-threshold=0 \
; RUN: -asan-optimize-callbacks -S | FileCheck %s --check-prefixes=LOAD,STORE ; RUN: -asan-optimize-callbacks -S | FileCheck %s --check-prefixes=LOAD,STORE
; RUN: opt < %s -passes=asan-pipeline -asan-instrumentation-with-call-threshold=0 \ ; RUN: opt < %s -passes=asan-pipeline -asan-instrumentation-with-call-threshold=0 \
; RUN: -asan-optimize-callbacks --asan-kernel -S | \ ; RUN: -asan-optimize-callbacks --asan-kernel -S | \
; RUN: FileCheck %s --check-prefixes=LOAD-KERNEL,STORE-KERNEL ; RUN: FileCheck %s --check-prefixes=LOAD-KERNEL,STORE-KERNEL
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define void @load(i8* %p1, i16* %p2, i32* %p4, i64* %p8, i128* %p16) define void @load(i8* %p1, i16* %p2, i32* %p4, i64* %p8, i128* %p16)
sanitize_address { sanitize_address {
%n1 = load i8, i8* %p1, align 1 %n1 = load i8, i8* %p1, align 1
%n2 = load i16, i16* %p2, align 2 %n2 = load i16, i16* %p2, align 2
%n4 = load i32, i32* %p4, align 4 %n4 = load i32, i32* %p4, align 4
%n8 = load i64, i64* %p8, align 8 %n8 = load i64, i64* %p8, align 8
%n16 = load i128, i128* %p16, align 16 %n16 = load i128, i128* %p16, align 16
; LOAD: call void @llvm.asan.check.memaccess(i8* %p1, i32 0) ; LOAD: call void @llvm.x86.asan.check.memaccess(i8* %p1, i32 0)
; LOAD-NEXT: %n1 = load i8, i8* %p1, align 1 ; LOAD-NEXT: %n1 = load i8, i8* %p1, align 1
; LOAD-NEXT: %1 = bitcast i16* %p2 to i8* ; LOAD-NEXT: %1 = bitcast i16* %p2 to i8*
; LOAD-NEXT: call void @llvm.asan.check.memaccess(i8* %1, i32 2) ; LOAD-NEXT: call void @llvm.x86.asan.check.memaccess(i8* %1, i32 2)
; LOAD-NEXT: %n2 = load i16, i16* %p2, align 2 ; LOAD-NEXT: %n2 = load i16, i16* %p2, align 2
; LOAD-NEXT: %2 = bitcast i32* %p4 to i8* ; LOAD-NEXT: %2 = bitcast i32* %p4 to i8*
; LOAD-NEXT: call void @llvm.asan.check.memaccess(i8* %2, i32 4) ; LOAD-NEXT: call void @llvm.x86.asan.check.memaccess(i8* %2, i32 4)
; LOAD-NEXT: %n4 = load i32, i32* %p4, align 4 ; LOAD-NEXT: %n4 = load i32, i32* %p4, align 4
; LOAD-NEXT: %3 = bitcast i64* %p8 to i8* ; LOAD-NEXT: %3 = bitcast i64* %p8 to i8*
; LOAD-NEXT: call void @llvm.asan.check.memaccess(i8* %3, i32 6) ; LOAD-NEXT: call void @llvm.x86.asan.check.memaccess(i8* %3, i32 6)
; LOAD-NEXT: %n8 = load i64, i64* %p8, align 8 ; LOAD-NEXT: %n8 = load i64, i64* %p8, align 8
; LOAD-NEXT: %4 = bitcast i128* %p16 to i8* ; LOAD-NEXT: %4 = bitcast i128* %p16 to i8*
; LOAD-NEXT: call void @llvm.asan.check.memaccess(i8* %4, i32 8) ; LOAD-NEXT: call void @llvm.x86.asan.check.memaccess(i8* %4, i32 8)
; LOAD-NEXT: %n16 = load i128, i128* %p16, align 16 ; LOAD-NEXT: %n16 = load i128, i128* %p16, align 16
; LOAD-KERNEL: call void @llvm.asan.check.memaccess(i8* %p1, i32 1) ; LOAD-KERNEL: call void @llvm.x86.asan.check.memaccess(i8* %p1, i32 1)
; LOAD-KERNEL-NEXT: %n1 = load i8, i8* %p1, align 1 ; LOAD-KERNEL-NEXT: %n1 = load i8, i8* %p1, align 1
; LOAD-KERNEL-NEXT: %1 = bitcast i16* %p2 to i8* ; LOAD-KERNEL-NEXT: %1 = bitcast i16* %p2 to i8*
; LOAD-KERNEL-NEXT: call void @llvm.asan.check.memaccess(i8* %1, i32 3) ; LOAD-KERNEL-NEXT: call void @llvm.x86.asan.check.memaccess(i8* %1, i32 3)
; LOAD-KERNEL-NEXT: %n2 = load i16, i16* %p2, align 2 ; LOAD-KERNEL-NEXT: %n2 = load i16, i16* %p2, align 2
; LOAD-KERNEL-NEXT: %2 = bitcast i32* %p4 to i8* ; LOAD-KERNEL-NEXT: %2 = bitcast i32* %p4 to i8*
; LOAD-KERNEL-NEXT: call void @llvm.asan.check.memaccess(i8* %2, i32 5) ; LOAD-KERNEL-NEXT: call void @llvm.x86.asan.check.memaccess(i8* %2, i32 5)
; LOAD-KERNEL-NEXT: %n4 = load i32, i32* %p4, align 4 ; LOAD-KERNEL-NEXT: %n4 = load i32, i32* %p4, align 4
; LOAD-KERNEL-NEXT: %3 = bitcast i64* %p8 to i8* ; LOAD-KERNEL-NEXT: %3 = bitcast i64* %p8 to i8*
; LOAD-KERNEL-NEXT: call void @llvm.asan.check.memaccess(i8* %3, i32 7) ; LOAD-KERNEL-NEXT: call void @llvm.x86.asan.check.memaccess(i8* %3, i32 7)
; LOAD-KERNEL-NEXT: %n8 = load i64, i64* %p8, align 8 ; LOAD-KERNEL-NEXT: %n8 = load i64, i64* %p8, align 8
; LOAD-KERNEL-NEXT: %4 = bitcast i128* %p16 to i8* ; LOAD-KERNEL-NEXT: %4 = bitcast i128* %p16 to i8*
; LOAD-KERNEL-NEXT: call void @llvm.asan.check.memaccess(i8* %4, i32 9) ; LOAD-KERNEL-NEXT: call void @llvm.x86.asan.check.memaccess(i8* %4, i32 9)
; LOAD-KERNEL-NEXT: %n16 = load i128, i128* %p16, align 16 ; LOAD-KERNEL-NEXT: %n16 = load i128, i128* %p16, align 16
ret void ret void
} }
define void @store(i8* %p1, i16* %p2, i32* %p4, i64* %p8, i128* %p16) define void @store(i8* %p1, i16* %p2, i32* %p4, i64* %p8, i128* %p16)
sanitize_address { sanitize_address {
store i8 0, i8* %p1, align 1 store i8 0, i8* %p1, align 1
store i16 0, i16* %p2, align 2 store i16 0, i16* %p2, align 2
store i32 0, i32* %p4, align 4 store i32 0, i32* %p4, align 4
store i64 0, i64* %p8, align 8 store i64 0, i64* %p8, align 8
store i128 0, i128* %p16, align 16 store i128 0, i128* %p16, align 16
; STORE: call void @llvm.asan.check.memaccess(i8* %p1, i32 32) ; STORE: call void @llvm.x86.asan.check.memaccess(i8* %p1, i32 32)
; STORE-NEXT: store i8 0, i8* %p1, align 1 ; STORE-NEXT: store i8 0, i8* %p1, align 1
; STORE-NEXT: %1 = bitcast i16* %p2 to i8* ; STORE-NEXT: %1 = bitcast i16* %p2 to i8*
; STORE-NEXT: call void @llvm.asan.check.memaccess(i8* %1, i32 34) ; STORE-NEXT: call void @llvm.x86.asan.check.memaccess(i8* %1, i32 34)
; STORE-NEXT: store i16 0, i16* %p2, align 2 ; STORE-NEXT: store i16 0, i16* %p2, align 2
; STORE-NEXT: %2 = bitcast i32* %p4 to i8* ; STORE-NEXT: %2 = bitcast i32* %p4 to i8*
; STORE-NEXT: call void @llvm.asan.check.memaccess(i8* %2, i32 36) ; STORE-NEXT: call void @llvm.x86.asan.check.memaccess(i8* %2, i32 36)
; STORE-NEXT: store i32 0, i32* %p4, align 4 ; STORE-NEXT: store i32 0, i32* %p4, align 4
; STORE-NEXT: %3 = bitcast i64* %p8 to i8* ; STORE-NEXT: %3 = bitcast i64* %p8 to i8*
; STORE-NEXT: call void @llvm.asan.check.memaccess(i8* %3, i32 38) ; STORE-NEXT: call void @llvm.x86.asan.check.memaccess(i8* %3, i32 38)
; STORE-NEXT: store i64 0, i64* %p8, align 8 ; STORE-NEXT: store i64 0, i64* %p8, align 8
; STORE-NEXT: %4 = bitcast i128* %p16 to i8* ; STORE-NEXT: %4 = bitcast i128* %p16 to i8*
; STORE-NEXT: call void @llvm.asan.check.memaccess(i8* %4, i32 40) ; STORE-NEXT: call void @llvm.x86.asan.check.memaccess(i8* %4, i32 40)
; STORE-NEXT: store i128 0, i128* %p16, align 16 ; STORE-NEXT: store i128 0, i128* %p16, align 16
; STORE-KERNEL: call void @llvm.asan.check.memaccess(i8* %p1, i32 33) ; STORE-KERNEL: call void @llvm.x86.asan.check.memaccess(i8* %p1, i32 33)
; STORE-KERNEL-NEXT: store i8 0, i8* %p1, align 1 ; STORE-KERNEL-NEXT: store i8 0, i8* %p1, align 1
; STORE-KERNEL-NEXT: %1 = bitcast i16* %p2 to i8* ; STORE-KERNEL-NEXT: %1 = bitcast i16* %p2 to i8*
; STORE-KERNEL-NEXT: call void @llvm.asan.check.memaccess(i8* %1, i32 35) ; STORE-KERNEL-NEXT: call void @llvm.x86.asan.check.memaccess(i8* %1, i32 35)
; STORE-KERNEL-NEXT: store i16 0, i16* %p2, align 2 ; STORE-KERNEL-NEXT: store i16 0, i16* %p2, align 2
; STORE-KERNEL-NEXT: %2 = bitcast i32* %p4 to i8* ; STORE-KERNEL-NEXT: %2 = bitcast i32* %p4 to i8*
; STORE-KERNEL-NEXT: call void @llvm.asan.check.memaccess(i8* %2, i32 37) ; STORE-KERNEL-NEXT: call void @llvm.x86.asan.check.memaccess(i8* %2, i32 37)
; STORE-KERNEL-NEXT: store i32 0, i32* %p4, align 4 ; STORE-KERNEL-NEXT: store i32 0, i32* %p4, align 4
; STORE-KERNEL-NEXT: %3 = bitcast i64* %p8 to i8* ; STORE-KERNEL-NEXT: %3 = bitcast i64* %p8 to i8*
; STORE-KERNEL-NEXT: call void @llvm.asan.check.memaccess(i8* %3, i32 39) ; STORE-KERNEL-NEXT: call void @llvm.x86.asan.check.memaccess(i8* %3, i32 39)
; STORE-KERNEL-NEXT: store i64 0, i64* %p8, align 8 ; STORE-KERNEL-NEXT: store i64 0, i64* %p8, align 8
; STORE-KERNEL-NEXT: %4 = bitcast i128* %p16 to i8* ; STORE-KERNEL-NEXT: %4 = bitcast i128* %p16 to i8*
; STORE-KERNEL-NEXT: call void @llvm.asan.check.memaccess(i8* %4, i32 41) ; STORE-KERNEL-NEXT: call void @llvm.x86.asan.check.memaccess(i8* %4, i32 41)
; STORE-KERNEL-NEXT: store i128 0, i128* %p16, align 16 ; STORE-KERNEL-NEXT: store i128 0, i128* %p16, align 16
; STORE-KERNEL-NEXT: ret void ; STORE-KERNEL-NEXT: ret void
ret void ret void
} }