[AArch64]Enabling Cortex-A510 Support

[mubashar_]

Summary

This patch enables support for Cortex-A510 CPUs.

[MarkMurrayARM]

As I did the downstream work for this, I'm happy with it to go in in this form.

[dmgreen]

As I did the downstream work for this, I'm happy with it to go in in this form.

This doesn't seem.. wise. Please make sure the reviews you do are at a sufficient quality, and it is probably best not to review patches you write yourself.

llvm/include/llvm/Support/AArch64TargetParser.def

201

Why is this 8.3? The TRM (https://developer.arm.com/documentation/101604/0003/The-Cortex-A510--core) describes it as implementing the 9.0-A architecture.

llvm/lib/Target/AArch64/AArch64.td

1083

This should be in some sort of order, next to the Cortex-A55. It should probably be called ProcA510 for consistency too.

1223

Ordering. Please use the CortexA55Model. This is not an out of order core like the A57.

llvm/lib/Target/AArch64/AArch64Subtarget.cpp

196 ↗

(On Diff #372691)

This can be the same case block as the A53 and A55.

[mubashar_]

Updated release notes to solve a merge conflict.

[MarkMurrayARM]

In D109825#3001622, @dmgreen wrote:

As I did the downstream work for this, I'm happy with it to go in in this form.

This doesn't seem.. wise. Please make sure the reviews you do are at a sufficient quality, and it is probably best not to review patches you write yourself.

Very good point!

I reduce this to the claim that it has been stable downstream for a couple of weeks now.

[xgupta]

Where are the other patches? Or diff is not uploaded correctly.

[mubashar_]

@xgupta those would be under the history tab.

[xgupta]

Yeah, those changes are in history, But we need them in the present to commit :)

The patch is incorrectly updated, did you followed https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-command-line?

[mubashar_]

@xgupta I followed the request review via web interface section of that page. Let me look into it.

[mubashar_]

Added files that were missing from previous diff.

[xgupta]

It misses llvm/test/CodeGen/AArch64 and llvm/test/MC/AArch64 testcases changes, see for example https://reviews.llvm.org/D36667 (Cortex-A55 support).

[lenary]

In D109825#3055142, @xgupta wrote:

It misses llvm/test/CodeGen/AArch64 and llvm/test/MC/AArch64 testcases changes, see for example https://reviews.llvm.org/D36667 (Cortex-A55 support).

I'm not convinced this is required - those tests are to ensure that the extensions (rcpc, dotprod) can be enabled either from a -march, or from a -mcpu=<cpu> with a cpu that contains that extension -- they are not testing that the extension is enabled from *all* cpus that contain said extension.

[xgupta]

oh thanks for the clarification, I am not aware of it.

[dmgreen]

Thanks for the updates.

In D109825#3055264, @lenary wrote:

In D109825#3055142, @xgupta wrote:

It misses llvm/test/CodeGen/AArch64 and llvm/test/MC/AArch64 testcases changes, see for example https://reviews.llvm.org/D36667 (Cortex-A55 support).

I'm not convinced this is required - those tests are to ensure that the extensions (rcpc, dotprod) can be enabled either from a -march, or from a -mcpu=<cpu> with a cpu that contains that extension -- they are not testing that the extension is enabled from *all* cpus that contain said extension.

Yeah I agree. It would be useful to add some tests for -mcpu=cortex-a510+crypto and -mcpu=cortex-a510+nocrypto, to make sure they do what is expected.

clang/docs/ReleaseNotes.rst

86 ↗

(On Diff #378645)

Can you add an Arm section below and move this to it.

[mubashar_]

Added crypto and non-crypto related tests for mcpu in aarch64-cpus.c

[dmgreen]

In D109825#3060796, @mubashar_ wrote:

Added crypto and non-crypto related tests for mcpu in aarch64-cpus.c

Thanks, but did this change miss being updated in the review?

clang/docs/ReleaseNotes.rst

86 ↗

(On Diff #378645)

This still needs doing. Also please add a line to the arm section saying "Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures."

It looks like there are some llvm release notes in llvm/docs/ReleaseNotes.rst too, that could have a line added.

llvm/include/llvm/Support/AArch64TargetParser.def

149

AEK_PAUTH is twice here.

[mubashar_]

Added crypto and no-crypto tests for -mcpu and added new section for Arm and AArch64 support in release notes.

[mubashar_]

Corrected PAUTH duplication mistake.

[mubashar_]

clang/docs/ReleaseNotes.rst

86 ↗

(On Diff #378645)

I didn't add support for these architectures. This may already be in its own commit.

[dmgreen]

Thanks for the changes. Nice working pulling this into shape.

LGTM

llvm/include/llvm/Support/AArch64TargetParser.def

149

Can you make sure you remove the second PAUTH here before committing.

[lenary]

clang/docs/ReleaseNotes.rst

86 ↗

(On Diff #378645)

I'll do armv9 in a separate NFC commit

[jansvoboda11]

This seems to be breaking the macOS bot, can you take a look? https://green.lab.llvm.org/green/job/clang-stage1-RA/24735/

[lenary]

In D109825#3066853, @jansvoboda11 wrote:

This seems to be breaking the macOS bot, can you take a look? https://green.lab.llvm.org/green/job/clang-stage1-RA/24735/

Will do.

llvm/include/llvm/Support/AArch64TargetParser.def

 AARCH64_CPU_NAME("cortex-a34", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
                  (AArch64::AEK_CRC))
 AARCH64_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
                  (AArch64::AEK_CRC))
 AARCH64_CPU_NAME("cortex-a53", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, true,
                  (AArch64::AEK_CRC))
 AARCH64_CPU_NAME("cortex-a55", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
                  (AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC))
-AARCH64_CPU_NAME("cortex=a510", ARMV9A,FK_CRYPTO_NEON_FP_ARMV8, false,
-                 (AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_SIMD |
-                  AArch64::AEK_RAS | AArch64::AEK_I8MM | AArch64::AEK_BF16 |
-                  AArch64::AEK_SVE2 | AArch64::AEK_SVE | AArch64::AEK_SVE2BITPERM |
-                  AArch64::AEK_SSBS | AArch64::AEK_BT | AArch64::AEK_MTE))
+AARCH64_CPU_NAME("cortex-a510", ARMV9A, FK_NEON_FP_ARMV8, false,
+                 (AArch64::AEK_BF16 | AArch64::AEK_I8MM | AArch64::AEK_SVE2BITPERM |
+                  AArch64::AEK_PAUTH | AArch64::AEK_PAUTH | AArch64::AEK_MTE |
+                  AArch64::AEK_SSBS | AArch64::AEK_SB | AArch64::AEK_FP16FML))
 AARCH64_CPU_NAME("cortex-a57", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
                  (AArch64::AEK_CRC))
 AARCH64_CPU_NAME("cortex-a65", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
                  (AArch64::AEK_DOTPROD | AArch64::AEK_FP16 | AArch64::AEK_RAS |
                   AArch64::AEK_RCPC | AArch64::AEK_SSBS))
 AARCH64_CPU_NAME("cortex-a65ae", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
                  (AArch64::AEK_DOTPROD | AArch64::AEK_FP16 | AArch64::AEK_RAS |
                   AArch64::AEK_RCPC | AArch64::AEK_SSBS))
AARCH64_CPU_NAME("neoverse-n2", ARMV8_5A, FK_CRYPTO_NEON_FP_ARMV8, false,
                  (AArch64::AEK_BF16 | AArch64::AEK_DOTPROD | AArch64::AEK_FP16 |
                   AArch64::AEK_I8MM | AArch64::AEK_MTE | AArch64::AEK_RAS |
                   AArch64::AEK_RCPC | AArch64::AEK_SB | AArch64::AEK_SSBS |
                   AArch64::AEK_SVE | AArch64::AEK_SVE2 | AArch64::AEK_SVE2BITPERM))
 AARCH64_CPU_NAME("neoverse-v1", ARMV8_4A, FK_CRYPTO_NEON_FP_ARMV8, false,
                  (AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
                   AArch64::AEK_RCPC | AArch64::AEK_FP16 | AArch64::AEK_BF16 |
                   AArch64::AEK_DOTPROD ))
 AARCH64_CPU_NAME("cyclone", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
                  (AArch64::AEK_NONE))
 AARCH64_CPU_NAME("apple-a7", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
                  (AArch64::AEK_NONE))
 AARCH64_CPU_NAME("apple-a8", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
                  (AArch64::AEK_NONE))
 AARCH64_CPU_NAME("apple-a9", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
                  (AArch64::AEK_NONE))
 AARCH64_CPU_NAME("apple-a10", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,

llvm/lib/Target/AArch64/AArch64.td

def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
                                    FeatureRCPC,
                                    FeaturePerfMon,
                                    FeaturePostRAScheduler,
                                    FeatureFuseAddress,
                                    ]>;
 
 def ProcA510    : SubtargetFeature<"a510", "ARMProcFamily", "CortexA510",
                                    "Cortex-A510 ARM processors", [
-                                     HasV9aOps,
-                                     FeatureCrypto,
-                                     FeatureFPARMv8,
-                                     FeatureFuseAES,
-                                     FeatureNEON,
-                                     FeaturePerfMon,
-                                     FeaturePostRAScheduler,
-                                     FeatureSPE,
-                                     FeatureAM,
-                                     FeatureMPAM,
-                                     FeatureETE,
-                                     FeatureMTE,
-                                     FeatureSVE2,
-                                     FeatureSVE2BitPerm,
-                                     FeatureFullFP16,
-                                     FeatureFP16FML,
-                                     FeatureDotProd
+                                   HasV9_0aOps,
+                                   FeatureMatMulInt8,
+                                   FeatureBF16,
+                                   FeatureETE,
+                                   FeatureFuseAES,
+                                   FeaturePostRAScheduler
                                    ]>;
 
 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
                                    "Cortex-A57 ARM processors", [
                                    FeatureBalanceFPOps,
                                    FeatureCRC,
                                    FeatureCrypto,
                                    FeatureCustomCheapAsMoveHandling,
def ProcNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily",
                                       FeatureNEON,
                                       FeaturePerfMon,
                                       FeaturePostRAScheduler,
                                       FeatureRandGen,
                                       FeatureSPE,
                                       FeatureSSBS,
                                       FeatureSVE]>;
 
 def ProcSaphira  : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
                                    "Qualcomm Saphira processors", [
                                    FeatureCrypto,
                                    FeatureCustomCheapAsMoveHandling,
                                    FeatureFPARMv8,
                                    FeatureNEON,
                                    FeatureSPE,
                                    FeaturePerfMon,
                                    FeaturePostRAScheduler,

 def : ProcessorModel<"cortex-a78", CortexA57Model, [ProcA78]>;
 def : ProcessorModel<"cortex-a78c", CortexA57Model, [ProcA78C]>;
 def : ProcessorModel<"cortex-r82", CortexA55Model, [ProcR82]>;
 def : ProcessorModel<"cortex-x1", CortexA57Model, [ProcX1]>;
 def : ProcessorModel<"neoverse-e1", CortexA53Model, [ProcNeoverseE1]>;
 def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>;
 def : ProcessorModel<"neoverse-n2", CortexA57Model, [ProcNeoverseN2]>;
 def : ProcessorModel<"neoverse-v1", CortexA57Model, [ProcNeoverseV1]>;
 def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>;
 def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>;
 def : ProcessorModel<"exynos-m5", ExynosM5Model, [ProcExynosM4]>;
 def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
 def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>;
 def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
 // Cavium ThunderX/ThunderX T8X  Processors
 def : ProcessorModel<"thunderx", ThunderXT8XModel,  [ProcThunderX]>;
 def : ProcessorModel<"thunderxt88", ThunderXT8XModel,  [ProcThunderXT88]>;

llvm/unittests/Support/TargetParserTest.cpp

::testing::Values(
                          "8-A"),
         ARMCPUTestParams("cortex-a55", "armv8.2-a", "crypto-neon-fp-armv8",
                          AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
                              AArch64::AEK_FP | AArch64::AEK_SIMD |
                              AArch64::AEK_RAS | AArch64::AEK_LSE |
                              AArch64::AEK_RDM | AArch64::AEK_FP16 |
                              AArch64::AEK_DOTPROD | AArch64::AEK_RCPC,
                          "8.2-A"),
-        ARMCPUTestParams("cortex-a510", "armv9-a", "crypto-neon-fp-armv8",
+        ARMCPUTestParams("cortex-a510", "armv9-a", "neon-fp-armv8",
                          AArch64::AEK_CRC | AArch64::AEK_FP |
                              AArch64::AEK_SIMD | AArch64::AEK_RAS |
-                             AArch64::AEK_I8MM | AArch64::AEK_BF16 |
-                             AArch64::AEK_SVE2 | AArch64::AEK_SVE |
-                             AArch64::AEK_SVE2BITPERM | AArch64::AEK_SSBS |
-                             AArch64::AEK_BT | AArch64::AEK_MTE |
-                             AArch64::AEK_DOTPROD,
+                             AArch64::AEK_LSE | AArch64::AEK_RDM |
+                             AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+                             AArch64::AEK_SVE2 | AArch64::AEK_BF16 |
+                             AArch64::AEK_I8MM | AArch64::AEK_SVE2BITPERM |
+                             AArch64::AEK_PAUTH | AArch64::AEK_MTE |
+                             AArch64::AEK_SSBS | AArch64::AEK_FP16FML |
+                             AArch64::AEK_SB,
                          "9-A"),
         ARMCPUTestParams("cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
                          AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
                              AArch64::AEK_FP | AArch64::AEK_SIMD,
                          "8-A"),
         ARMCPUTestParams("cortex-a65", "armv8.2-a", "crypto-neon-fp-armv8",
                          AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
                              AArch64::AEK_DOTPROD | AArch64::AEK_FP |