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[ARM][AArch64] Cortex-A75 and Cortex-A55 support
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Authored by samparker on Aug 14 2017, 3:13 AM.

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Details

Reviewers

t.p.northover

Commits

rGb252ffd2cca9: [ARM][AArch64] Cortex-A75 and Cortex-A55 support
rL311316: [ARM][AArch64] Cortex-A75 and Cortex-A55 support

Summary

This patch introduces support for Cortex-A75 and Cortex-A55, Arm's latest big.LITTLE A-class cores. They implement the ARMv8.2-A architecture, including the cryptography and RAS extensions, plus the optional dot product extension. They also implement the RCpc AArch64 extension from ARMv8.3-A.

Cortex-A75:
https://developer.arm.com/products/processors/cortex-a/cortex-a75

Cortex-A55:
https://developer.arm.com/products/processors/cortex-a/cortex-a55

Diff Detail

Repository: rL LLVM

Event Timeline

samparker created this revision.Aug 14 2017, 3:13 AM

Herald added subscribers: kristof.beyls, javed.absar, rengolin, aemerson. · View Herald TranscriptAug 14 2017, 3:13 AM

Looks reasonable to me. Looking forward to the RCPC instructions!

This revision is now accepted and ready to land.Aug 14 2017, 7:45 AM

Hi Tim,

I've added dotprod and ras to the target parser and set the Cortex-A55 to be the default core for AArch32, not just AArch64.

cheers,
sam

samparker added a child revision: D36731: [ARM][AArch64] Cortex-A75 and Cortex-A55 tests.Aug 15 2017, 3:36 AM

Reverted back to using 'generic' as the default v8.2-a cpu.

Closed by commit rL311316: [ARM][AArch64] Cortex-A75 and Cortex-A55 support (authored by sam_parker). · Explain WhyAug 21 2017, 1:44 AM

This revision was automatically updated to reflect the committed changes.

xgupta mentioned this in D109825: [AArch64]Enabling Cortex-A510 Support.Oct 11 2021, 8:05 AM

Revision Contents

Path

Size

llvm/

trunk/

include/

llvm/

Support/

AArch64TargetParser.def

8 lines

ARMTargetParser.def

5 lines

TargetParser.h

56 lines

lib/

Support/

TargetParser.cpp

14 lines

Target/

AArch64/

30 lines

2 lines

2 lines

4 lines

ARM/

ARM.td

14 lines

ARMSubtarget.h

2 lines

ARMSubtarget.cpp

2 lines

test/

CodeGen/

AArch64/

cpus.ll

2 lines

remat.ll

4 lines

MC/

AArch64/

armv8.2a-dotprod.s

2 lines

armv8.3a-rcpc.s

3 lines

ARM/

armv8.2a-dotprod-a32.s

2 lines

armv8.2a-dotprod-t32.s

2 lines

Disassembler/

AArch64/

armv8.2a-dotprod.txt

2 lines

armv8.3a-rcpc.txt

3 lines

unittests/

Support/

TargetParserTest.cpp

36 lines

Diff 111937

llvm/trunk/include/llvm/Support/AArch64TargetParser.def

Show All 26 Lines	AARCH64_ARCH("armv8.1-a", ARMV8_1A, "8.1-A", "v8.1a",
AArch64::AEK_SIMD \| AArch64::AEK_LSE))		AArch64::AEK_SIMD \| AArch64::AEK_LSE))
AARCH64_ARCH("armv8.2-a", ARMV8_2A, "8.2-A", "v8.2a",		AARCH64_ARCH("armv8.2-a", ARMV8_2A, "8.2-A", "v8.2a",
ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,		ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
(AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \| AArch64::AEK_FP \|		(AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \| AArch64::AEK_FP \|
AArch64::AEK_SIMD \| AArch64::AEK_RAS \| AArch64::AEK_LSE))		AArch64::AEK_SIMD \| AArch64::AEK_RAS \| AArch64::AEK_LSE))
AARCH64_ARCH("armv8.3-a", ARMV8_3A, "8.3-A", "v8.3a",		AARCH64_ARCH("armv8.3-a", ARMV8_3A, "8.3-A", "v8.3a",
ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,		ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
(AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \| AArch64::AEK_FP \|		(AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \| AArch64::AEK_FP \|
AArch64::AEK_SIMD \| AArch64::AEK_RAS \| AArch64::AEK_LSE))		AArch64::AEK_SIMD \| AArch64::AEK_RAS \| AArch64::AEK_LSE \|
		AArch64::AEK_RCPC))
#undef AARCH64_ARCH		#undef AARCH64_ARCH

#ifndef AARCH64_ARCH_EXT_NAME		#ifndef AARCH64_ARCH_EXT_NAME
#define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)		#define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)
#endif		#endif
// FIXME: This would be nicer were it tablegen		// FIXME: This would be nicer were it tablegen
AARCH64_ARCH_EXT_NAME("invalid", AArch64::AEK_INVALID, nullptr, nullptr)		AARCH64_ARCH_EXT_NAME("invalid", AArch64::AEK_INVALID, nullptr, nullptr)
AARCH64_ARCH_EXT_NAME("none", AArch64::AEK_NONE, nullptr, nullptr)		AARCH64_ARCH_EXT_NAME("none", AArch64::AEK_NONE, nullptr, nullptr)
AARCH64_ARCH_EXT_NAME("crc", AArch64::AEK_CRC, "+crc", "-crc")		AARCH64_ARCH_EXT_NAME("crc", AArch64::AEK_CRC, "+crc", "-crc")
AARCH64_ARCH_EXT_NAME("lse", AArch64::AEK_LSE, "+lse", "-lse")		AARCH64_ARCH_EXT_NAME("lse", AArch64::AEK_LSE, "+lse", "-lse")
AARCH64_ARCH_EXT_NAME("crypto", AArch64::AEK_CRYPTO, "+crypto","-crypto")		AARCH64_ARCH_EXT_NAME("crypto", AArch64::AEK_CRYPTO, "+crypto","-crypto")
AARCH64_ARCH_EXT_NAME("dotprod", AArch64::AEK_DOTPROD, "+dotprod","-dotprod")		AARCH64_ARCH_EXT_NAME("dotprod", AArch64::AEK_DOTPROD, "+dotprod","-dotprod")
AARCH64_ARCH_EXT_NAME("fp", AArch64::AEK_FP, "+fp-armv8", "-fp-armv8")		AARCH64_ARCH_EXT_NAME("fp", AArch64::AEK_FP, "+fp-armv8", "-fp-armv8")
AARCH64_ARCH_EXT_NAME("simd", AArch64::AEK_SIMD, "+neon", "-neon")		AARCH64_ARCH_EXT_NAME("simd", AArch64::AEK_SIMD, "+neon", "-neon")
AARCH64_ARCH_EXT_NAME("fp16", AArch64::AEK_FP16, "+fullfp16", "-fullfp16")		AARCH64_ARCH_EXT_NAME("fp16", AArch64::AEK_FP16, "+fullfp16", "-fullfp16")
AARCH64_ARCH_EXT_NAME("profile", AArch64::AEK_PROFILE, "+spe", "-spe")		AARCH64_ARCH_EXT_NAME("profile", AArch64::AEK_PROFILE, "+spe", "-spe")
AARCH64_ARCH_EXT_NAME("ras", AArch64::AEK_RAS, "+ras", "-ras")		AARCH64_ARCH_EXT_NAME("ras", AArch64::AEK_RAS, "+ras", "-ras")
AARCH64_ARCH_EXT_NAME("sve", AArch64::AEK_SVE, "+sve", "-sve")		AARCH64_ARCH_EXT_NAME("sve", AArch64::AEK_SVE, "+sve", "-sve")
		AARCH64_ARCH_EXT_NAME("rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc")
#undef AARCH64_ARCH_EXT_NAME		#undef AARCH64_ARCH_EXT_NAME

#ifndef AARCH64_CPU_NAME		#ifndef AARCH64_CPU_NAME
#define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)		#define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)
#endif		#endif
AARCH64_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,		AARCH64_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC))		(AArch64::AEK_CRC))
AARCH64_CPU_NAME("cortex-a53", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, true,		AARCH64_CPU_NAME("cortex-a53", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, true,
(AArch64::AEK_CRC))		(AArch64::AEK_CRC))
		AARCH64_CPU_NAME("cortex-a55", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
		(AArch64::AEK_FP16 \| AArch64::AEK_DOTPROD \| AArch64::AEK_RCPC))
AARCH64_CPU_NAME("cortex-a57", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,		AARCH64_CPU_NAME("cortex-a57", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC))		(AArch64::AEK_CRC))
AARCH64_CPU_NAME("cortex-a72", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,		AARCH64_CPU_NAME("cortex-a72", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC))		(AArch64::AEK_CRC))
AARCH64_CPU_NAME("cortex-a73", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,		AARCH64_CPU_NAME("cortex-a73", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC))		(AArch64::AEK_CRC))
		AARCH64_CPU_NAME("cortex-a75", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
		(AArch64::AEK_FP16 \| AArch64::AEK_DOTPROD \| AArch64::AEK_RCPC))
AARCH64_CPU_NAME("cyclone", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,		AARCH64_CPU_NAME("cyclone", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_NONE))		(AArch64::AEK_NONE))
AARCH64_CPU_NAME("exynos-m1", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,		AARCH64_CPU_NAME("exynos-m1", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC))		(AArch64::AEK_CRC))
AARCH64_CPU_NAME("exynos-m2", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,		AARCH64_CPU_NAME("exynos-m2", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC))		(AArch64::AEK_CRC))
AARCH64_CPU_NAME("exynos-m3", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,		AARCH64_CPU_NAME("exynos-m3", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC))		(AArch64::AEK_CRC))
Show All 17 Lines

llvm/trunk/include/llvm/Support/ARMTargetParser.def

	Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
	#ifndef ARM_ARCH_EXT_NAME			#ifndef ARM_ARCH_EXT_NAME
	#define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)			#define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)
	#endif			#endif
	// FIXME: This would be nicer were it tablegen			// FIXME: This would be nicer were it tablegen
	ARM_ARCH_EXT_NAME("invalid", ARM::AEK_INVALID, nullptr, nullptr)			ARM_ARCH_EXT_NAME("invalid", ARM::AEK_INVALID, nullptr, nullptr)
	ARM_ARCH_EXT_NAME("none", ARM::AEK_NONE, nullptr, nullptr)			ARM_ARCH_EXT_NAME("none", ARM::AEK_NONE, nullptr, nullptr)
	ARM_ARCH_EXT_NAME("crc", ARM::AEK_CRC, "+crc", "-crc")			ARM_ARCH_EXT_NAME("crc", ARM::AEK_CRC, "+crc", "-crc")
	ARM_ARCH_EXT_NAME("crypto", ARM::AEK_CRYPTO, "+crypto","-crypto")			ARM_ARCH_EXT_NAME("crypto", ARM::AEK_CRYPTO, "+crypto","-crypto")
				ARM_ARCH_EXT_NAME("dotprod", ARM::AEK_DOTPROD, "+dotprod","-dotprod")
	ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp")			ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp")
	ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, nullptr, nullptr)			ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, nullptr, nullptr)
	ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM \| ARM::AEK_HWDIVTHUMB), nullptr, nullptr)			ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM \| ARM::AEK_HWDIVTHUMB), nullptr, nullptr)
	ARM_ARCH_EXT_NAME("mp", ARM::AEK_MP, nullptr, nullptr)			ARM_ARCH_EXT_NAME("mp", ARM::AEK_MP, nullptr, nullptr)
	ARM_ARCH_EXT_NAME("simd", ARM::AEK_SIMD, nullptr, nullptr)			ARM_ARCH_EXT_NAME("simd", ARM::AEK_SIMD, nullptr, nullptr)
	ARM_ARCH_EXT_NAME("sec", ARM::AEK_SEC, nullptr, nullptr)			ARM_ARCH_EXT_NAME("sec", ARM::AEK_SEC, nullptr, nullptr)
	ARM_ARCH_EXT_NAME("virt", ARM::AEK_VIRT, nullptr, nullptr)			ARM_ARCH_EXT_NAME("virt", ARM::AEK_VIRT, nullptr, nullptr)
	ARM_ARCH_EXT_NAME("fp16", ARM::AEK_FP16, "+fullfp16", "-fullfp16")			ARM_ARCH_EXT_NAME("fp16", ARM::AEK_FP16, "+fullfp16", "-fullfp16")
	▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
	ARM_CPU_NAME("cortex-m3", ARMV7M, FK_NONE, true, ARM::AEK_NONE)			ARM_CPU_NAME("cortex-m3", ARMV7M, FK_NONE, true, ARM::AEK_NONE)
	ARM_CPU_NAME("cortex-m4", ARMV7EM, FK_FPV4_SP_D16, true, ARM::AEK_NONE)			ARM_CPU_NAME("cortex-m4", ARMV7EM, FK_FPV4_SP_D16, true, ARM::AEK_NONE)
	ARM_CPU_NAME("cortex-m7", ARMV7EM, FK_FPV5_D16, false, ARM::AEK_NONE)			ARM_CPU_NAME("cortex-m7", ARMV7EM, FK_FPV5_D16, false, ARM::AEK_NONE)
	ARM_CPU_NAME("cortex-m23", ARMV8MBaseline, FK_NONE, false, ARM::AEK_NONE)			ARM_CPU_NAME("cortex-m23", ARMV8MBaseline, FK_NONE, false, ARM::AEK_NONE)
	ARM_CPU_NAME("cortex-m33", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)			ARM_CPU_NAME("cortex-m33", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
	ARM_CPU_NAME("cortex-a32", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)			ARM_CPU_NAME("cortex-a32", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
	ARM_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)			ARM_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
	ARM_CPU_NAME("cortex-a53", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)			ARM_CPU_NAME("cortex-a53", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
				ARM_CPU_NAME("cortex-a55", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
				(ARM::AEK_FP16 \| ARM::AEK_DOTPROD))
	ARM_CPU_NAME("cortex-a57", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)			ARM_CPU_NAME("cortex-a57", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
	ARM_CPU_NAME("cortex-a72", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)			ARM_CPU_NAME("cortex-a72", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
	ARM_CPU_NAME("cortex-a73", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)			ARM_CPU_NAME("cortex-a73", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
				ARM_CPU_NAME("cortex-a75", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
				(ARM::AEK_FP16 \| ARM::AEK_DOTPROD))
	ARM_CPU_NAME("cyclone", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)			ARM_CPU_NAME("cyclone", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
	ARM_CPU_NAME("exynos-m1", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)			ARM_CPU_NAME("exynos-m1", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
	ARM_CPU_NAME("exynos-m2", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)			ARM_CPU_NAME("exynos-m2", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
	ARM_CPU_NAME("exynos-m3", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)			ARM_CPU_NAME("exynos-m3", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
	ARM_CPU_NAME("kryo", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)			ARM_CPU_NAME("kryo", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
	// Non-standard Arch names.			// Non-standard Arch names.
	ARM_CPU_NAME("iwmmxt", IWMMXT, FK_NONE, true, ARM::AEK_NONE)			ARM_CPU_NAME("iwmmxt", IWMMXT, FK_NONE, true, ARM::AEK_NONE)
	ARM_CPU_NAME("xscale", XSCALE, FK_NONE, true, ARM::AEK_NONE)			ARM_CPU_NAME("xscale", XSCALE, FK_NONE, true, ARM::AEK_NONE)
	ARM_CPU_NAME("swift", ARMV7S, FK_NEON_VFPV4, true,			ARM_CPU_NAME("swift", ARMV7S, FK_NEON_VFPV4, true,
	(ARM::AEK_HWDIVARM \| ARM::AEK_HWDIVTHUMB))			(ARM::AEK_HWDIVARM \| ARM::AEK_HWDIVTHUMB))
	// Invalid CPU			// Invalid CPU
	ARM_CPU_NAME("invalid", INVALID, FK_INVALID, true, ARM::AEK_INVALID)			ARM_CPU_NAME("invalid", INVALID, FK_INVALID, true, ARM::AEK_INVALID)
	#undef ARM_CPU_NAME			#undef ARM_CPU_NAME

llvm/trunk/include/llvm/Support/TargetParser.h

	Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
	// Arch names.			// Arch names.
	enum class ArchKind {			enum class ArchKind {
	#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,			#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,
	#include "ARMTargetParser.def"			#include "ARMTargetParser.def"
	};			};

	// Arch extension modifiers for CPUs.			// Arch extension modifiers for CPUs.
	enum ArchExtKind : unsigned {			enum ArchExtKind : unsigned {
	AEK_INVALID = 0x0,			AEK_INVALID = 0,
	AEK_NONE = 0x1,			AEK_NONE = 1,
	AEK_CRC = 0x2,			AEK_CRC = 1 << 1,
	AEK_CRYPTO = 0x4,			AEK_CRYPTO = 1 << 2,
	AEK_FP = 0x8,			AEK_FP = 1 << 3,
	AEK_HWDIVTHUMB = 0x10,			AEK_HWDIVTHUMB = 1 << 4,
	AEK_HWDIVARM = 0x20,			AEK_HWDIVARM = 1 << 5,
	AEK_MP = 0x40,			AEK_MP = 1 << 6,
	AEK_SIMD = 0x80,			AEK_SIMD = 1 << 7,
	AEK_SEC = 0x100,			AEK_SEC = 1 << 8,
	AEK_VIRT = 0x200,			AEK_VIRT = 1 << 9,
	AEK_DSP = 0x400,			AEK_DSP = 1 << 10,
	AEK_FP16 = 0x800,			AEK_FP16 = 1 << 11,
	AEK_RAS = 0x1000,			AEK_RAS = 1 << 12,
	AEK_SVE = 0x2000,			AEK_SVE = 1 << 13,
				AEK_DOTPROD = 1 << 14,
	// Unsupported extensions.			// Unsupported extensions.
	AEK_OS = 0x8000000,			AEK_OS = 0x8000000,
	AEK_IWMMXT = 0x10000000,			AEK_IWMMXT = 0x10000000,
	AEK_IWMMXT2 = 0x20000000,			AEK_IWMMXT2 = 0x20000000,
	AEK_MAVERICK = 0x40000000,			AEK_MAVERICK = 0x40000000,
	AEK_XSCALE = 0x80000000,			AEK_XSCALE = 0x80000000,
	};			};

	▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
	// Arch names.			// Arch names.
	enum class ArchKind {			enum class ArchKind {
	#define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,			#define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,
	#include "AArch64TargetParser.def"			#include "AArch64TargetParser.def"
	};			};

	// Arch extension modifiers for CPUs.			// Arch extension modifiers for CPUs.
	enum ArchExtKind : unsigned {			enum ArchExtKind : unsigned {
	AEK_INVALID = 0x0,			AEK_INVALID = 0,
	AEK_NONE = 0x1,			AEK_NONE = 1,
	AEK_CRC = 0x2,			AEK_CRC = 1 << 1,
	AEK_CRYPTO = 0x4,			AEK_CRYPTO = 1 << 2,
	AEK_FP = 0x8,			AEK_FP = 1 << 3,
	AEK_SIMD = 0x10,			AEK_SIMD = 1 << 4,
	AEK_FP16 = 0x20,			AEK_FP16 = 1 << 5,
	AEK_PROFILE = 0x40,			AEK_PROFILE = 1 << 6,
	AEK_RAS = 0x80,			AEK_RAS = 1 << 7,
	AEK_LSE = 0x100,			AEK_LSE = 1 << 8,
	AEK_SVE = 0x200,			AEK_SVE = 1 << 9,
	AEK_DOTPROD = 0x400			AEK_DOTPROD = 1 << 10,
				AEK_RCPC = 1 << 11
	};			};

	StringRef getCanonicalArchName(StringRef Arch);			StringRef getCanonicalArchName(StringRef Arch);

	// Information by ID			// Information by ID
	StringRef getFPUName(unsigned FPUKind);			StringRef getFPUName(unsigned FPUKind);
	ARM::FPUVersion getFPUVersion(unsigned FPUKind);			ARM::FPUVersion getFPUVersion(unsigned FPUKind);
	ARM::NeonSupportLevel getFPUNeonSupportLevel(unsigned FPUKind);			ARM::NeonSupportLevel getFPUNeonSupportLevel(unsigned FPUKind);
	Show All 35 Lines

llvm/trunk/lib/Support/TargetParser.cpp

Show First 20 Lines • Show All 229 Lines • ▼ Show 20 Lines	bool llvm::ARM::getExtensionFeatures(unsigned Extensions,
else		else
Features.push_back("-crc");		Features.push_back("-crc");

if (Extensions & ARM::AEK_DSP)		if (Extensions & ARM::AEK_DSP)
Features.push_back("+dsp");		Features.push_back("+dsp");
else		else
Features.push_back("-dsp");		Features.push_back("-dsp");

		if (Extensions & ARM::AEK_RAS)
		Features.push_back("+ras");
		else
		Features.push_back("-ras");

		if (Extensions & ARM::AEK_DOTPROD)
		Features.push_back("+dotprod");
		else
		Features.push_back("-dotprod");

return getHWDivFeatures(Extensions, Features);		return getHWDivFeatures(Extensions, Features);
}		}

bool llvm::ARM::getFPUFeatures(unsigned FPUKind,		bool llvm::ARM::getFPUFeatures(unsigned FPUKind,
std::vector<StringRef> &Features) {		std::vector<StringRef> &Features) {

if (FPUKind >= ARM::FK_LAST \|\| FPUKind == ARM::FK_INVALID)		if (FPUKind >= ARM::FK_LAST \|\| FPUKind == ARM::FK_INVALID)
return false;		return false;
▲ Show 20 Lines • Show All 187 Lines • ▼ Show 20 Lines	bool llvm::AArch64::getExtensionFeatures(unsigned Extensions,
if (Extensions & AArch64::AEK_FP)		if (Extensions & AArch64::AEK_FP)
Features.push_back("+fp-armv8");		Features.push_back("+fp-armv8");
if (Extensions & AArch64::AEK_SIMD)		if (Extensions & AArch64::AEK_SIMD)
Features.push_back("+neon");		Features.push_back("+neon");
if (Extensions & AArch64::AEK_CRC)		if (Extensions & AArch64::AEK_CRC)
Features.push_back("+crc");		Features.push_back("+crc");
if (Extensions & AArch64::AEK_CRYPTO)		if (Extensions & AArch64::AEK_CRYPTO)
Features.push_back("+crypto");		Features.push_back("+crypto");
		if (Extensions & AArch64::AEK_DOTPROD)
		Features.push_back("+dotprod");
if (Extensions & AArch64::AEK_FP16)		if (Extensions & AArch64::AEK_FP16)
Features.push_back("+fullfp16");		Features.push_back("+fullfp16");
if (Extensions & AArch64::AEK_PROFILE)		if (Extensions & AArch64::AEK_PROFILE)
Features.push_back("+spe");		Features.push_back("+spe");
if (Extensions & AArch64::AEK_RAS)		if (Extensions & AArch64::AEK_RAS)
Features.push_back("+ras");		Features.push_back("+ras");
if (Extensions & AArch64::AEK_LSE)		if (Extensions & AArch64::AEK_LSE)
Features.push_back("+lse");		Features.push_back("+lse");
if (Extensions & AArch64::AEK_SVE)		if (Extensions & AArch64::AEK_SVE)
Features.push_back("+sve");		Features.push_back("+sve");
		if (Extensions & AArch64::AEK_RCPC)
		Features.push_back("+rcpc");

return true;		return true;
}		}

bool llvm::AArch64::getFPUFeatures(unsigned FPUKind,		bool llvm::AArch64::getFPUFeatures(unsigned FPUKind,
std::vector<StringRef> &Features) {		std::vector<StringRef> &Features) {
return ARM::getFPUFeatures(FPUKind, Features);		return ARM::getFPUFeatures(FPUKind, Features);
}		}
▲ Show 20 Lines • Show All 433 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64.td

Show First 20 Lines • Show All 204 Lines • ▼ Show 20 Lines	def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
FeatureFPARMv8,		FeatureFPARMv8,
FeatureFuseAES,		FeatureFuseAES,
FeatureNEON,		FeatureNEON,
FeaturePerfMon,		FeaturePerfMon,
FeaturePostRAScheduler,		FeaturePostRAScheduler,
FeatureUseAA		FeatureUseAA
]>;		]>;

		def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
		"Cortex-A55 ARM processors", [
		FeatureCrypto,
		FeatureFPARMv8,
		FeatureFuseAES,
		FeatureNEON,
		FeatureFullFP16,
		FeatureDotProd,
		FeatureRCPC,
		FeaturePerfMon
		]>;

def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",		def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
"Cortex-A57 ARM processors", [		"Cortex-A57 ARM processors", [
FeatureBalanceFPOps,		FeatureBalanceFPOps,
FeatureCRC,		FeatureCRC,
FeatureCrypto,		FeatureCrypto,
FeatureCustomCheapAsMoveHandling,		FeatureCustomCheapAsMoveHandling,
FeatureFPARMv8,		FeatureFPARMv8,
FeatureFuseAES,		FeatureFuseAES,
Show All 19 Lines	def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
FeatureCRC,		FeatureCRC,
FeatureCrypto,		FeatureCrypto,
FeatureFPARMv8,		FeatureFPARMv8,
FeatureFuseAES,		FeatureFuseAES,
FeatureNEON,		FeatureNEON,
FeaturePerfMon		FeaturePerfMon
]>;		]>;

		def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
		"Cortex-A75 ARM processors", [
		FeatureCrypto,
		FeatureFPARMv8,
		FeatureFuseAES,
		FeatureNEON,
		FeatureFullFP16,
		FeatureDotProd,
		FeatureRCPC,
		FeaturePerfMon
		]>;

def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",		def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
"Cyclone", [		"Cyclone", [
FeatureAlternateSExtLoadCVTF32Pattern,		FeatureAlternateSExtLoadCVTF32Pattern,
FeatureCrypto,		FeatureCrypto,
FeatureDisableLatencySchedHeuristic,		FeatureDisableLatencySchedHeuristic,
FeatureFPARMv8,		FeatureFPARMv8,
FeatureArithmeticBccFusion,		FeatureArithmeticBccFusion,
FeatureArithmeticCbzFusion,		FeatureArithmeticCbzFusion,
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines
def : ProcessorModel<"generic", NoSchedModel, [		def : ProcessorModel<"generic", NoSchedModel, [
FeatureFPARMv8,		FeatureFPARMv8,
FeatureFuseAES,		FeatureFuseAES,
FeatureNEON,		FeatureNEON,
FeaturePerfMon,		FeaturePerfMon,
FeaturePostRAScheduler		FeaturePostRAScheduler
]>;		]>;

// FIXME: Cortex-A35 is currently modeled as a Cortex-A53.		// FIXME: Cortex-A35 and Cortex-A55 are currently modeled as a Cortex-A53.
def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;		def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;		def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
		def : ProcessorModel<"cortex-a55", CortexA53Model, [ProcA55]>;
def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;		def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
// FIXME: Cortex-A72 and Cortex-A73 are currently modeled as a Cortex-A57.		// FIXME: Cortex-A72, Cortex-A73 and Cortex-A75 are currently modeled as a Cortex-A57.
def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;		def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;		def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
		def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>;
def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;		def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;		def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;		def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
def : ProcessorModel<"exynos-m3", ExynosM1Model, [ProcExynosM2]>;		def : ProcessorModel<"exynos-m3", ExynosM1Model, [ProcExynosM2]>;
def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;		def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;		def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
// Cavium ThunderX/ThunderX T8X Processors		// Cavium ThunderX/ThunderX T8X Processors
def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>;		def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>;
▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 445 Lines • ▼ Show 20 Lines
	def SDOT4S : BaseSIMDThreeSameVectorDot<1, 0, "sdot", ".4s", ".16b">;			def SDOT4S : BaseSIMDThreeSameVectorDot<1, 0, "sdot", ".4s", ".16b">;
	def UDOTIDX2S : BaseSIMDThreeSameVectorDotIndex<0, 1, "udot", ".2s", ".8b", ".4b">;			def UDOTIDX2S : BaseSIMDThreeSameVectorDotIndex<0, 1, "udot", ".2s", ".8b", ".4b">;
	def SDOTIDX2S : BaseSIMDThreeSameVectorDotIndex<0, 0, "sdot", ".2s", ".8b", ".4b">;			def SDOTIDX2S : BaseSIMDThreeSameVectorDotIndex<0, 0, "sdot", ".2s", ".8b", ".4b">;
	def UDOTIDX4S : BaseSIMDThreeSameVectorDotIndex<1, 1, "udot", ".4s", ".16b", ".4b">;			def UDOTIDX4S : BaseSIMDThreeSameVectorDotIndex<1, 1, "udot", ".4s", ".16b", ".4b">;
	def SDOTIDX4S : BaseSIMDThreeSameVectorDotIndex<1, 0, "sdot", ".4s", ".16b", ".4b">;			def SDOTIDX4S : BaseSIMDThreeSameVectorDotIndex<1, 0, "sdot", ".4s", ".16b", ".4b">;
	}			}

	let Predicates = [HasRCPC] in {			let Predicates = [HasRCPC] in {
	// v8.3 Release Consistent Processor Consistent support			// v8.3 Release Consistent Processor Consistent support, optional in v8.2.
	def LDAPRB : RCPCLoad<0b00, "ldaprb", GPR32>;			def LDAPRB : RCPCLoad<0b00, "ldaprb", GPR32>;
	def LDAPRH : RCPCLoad<0b01, "ldaprh", GPR32>;			def LDAPRH : RCPCLoad<0b01, "ldaprh", GPR32>;
	def LDAPRW : RCPCLoad<0b10, "ldapr", GPR32>;			def LDAPRW : RCPCLoad<0b10, "ldapr", GPR32>;
	def LDAPRX : RCPCLoad<0b11, "ldapr", GPR64>;			def LDAPRX : RCPCLoad<0b11, "ldapr", GPR64>;
	}			}

	let Predicates = [HasV8_3a] in {			let Predicates = [HasV8_3a] in {
	// v8.3a Pointer Authentication			// v8.3a Pointer Authentication
	▲ Show 20 Lines • Show All 5,784 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h

	Show All 35 Lines
	class Triple;			class Triple;

	class AArch64Subtarget final : public AArch64GenSubtargetInfo {			class AArch64Subtarget final : public AArch64GenSubtargetInfo {
	public:			public:
	enum ARMProcFamilyEnum : uint8_t {			enum ARMProcFamilyEnum : uint8_t {
	Others,			Others,
	CortexA35,			CortexA35,
	CortexA53,			CortexA53,
				CortexA55,
	CortexA57,			CortexA57,
	CortexA72,			CortexA72,
	CortexA73,			CortexA73,
				CortexA75,
	Cyclone,			Cyclone,
	ExynosM1,			ExynosM1,
	Falkor,			Falkor,
	Kryo,			Kryo,
	ThunderX2T99,			ThunderX2T99,
	ThunderX,			ThunderX,
	ThunderXT81,			ThunderXT81,
	ThunderXT83,			ThunderXT83,
	▲ Show 20 Lines • Show All 275 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Lines	case ThunderXT83:
PrefLoopAlignment = 2;		PrefLoopAlignment = 2;
// FIXME: remove this to enable 64-bit SLP if performance looks good.		// FIXME: remove this to enable 64-bit SLP if performance looks good.
MinVectorRegisterBitWidth = 128;		MinVectorRegisterBitWidth = 128;
break;		break;
case CortexA35: break;		case CortexA35: break;
case CortexA53:		case CortexA53:
PrefFunctionAlignment = 3;		PrefFunctionAlignment = 3;
break;		break;
		case CortexA55: break;
case CortexA72:		case CortexA72:
PrefFunctionAlignment = 4;
break;
case CortexA73:		case CortexA73:
		case CortexA75:
PrefFunctionAlignment = 4;		PrefFunctionAlignment = 4;
break;		break;
case Others: break;		case Others: break;
}		}
}		}

AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,		AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
const std::string &FS,		const std::string &FS,
▲ Show 20 Lines • Show All 120 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/ARM.td

	Show First 20 Lines • Show All 429 Lines • ▼ Show 20 Lines
	def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",			def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
	"Cortex-A17 ARM processors", []>;			"Cortex-A17 ARM processors", []>;
	def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",			def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",
	"Cortex-A32 ARM processors", []>;			"Cortex-A32 ARM processors", []>;
	def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",			def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
	"Cortex-A35 ARM processors", []>;			"Cortex-A35 ARM processors", []>;
	def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",			def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
	"Cortex-A53 ARM processors", []>;			"Cortex-A53 ARM processors", []>;
				def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
				"Cortex-A55 ARM processors", []>;
	def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",			def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
	"Cortex-A57 ARM processors", []>;			"Cortex-A57 ARM processors", []>;
	def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",			def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
	"Cortex-A72 ARM processors", []>;			"Cortex-A72 ARM processors", []>;
	def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",			def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
	"Cortex-A73 ARM processors", []>;			"Cortex-A73 ARM processors", []>;
				def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
				"Cortex-A75 ARM processors", []>;

	def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",			def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
	"Qualcomm Krait processors", []>;			"Qualcomm Krait processors", []>;
	def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",			def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
	"Qualcomm Kryo processors", []>;			"Qualcomm Kryo processors", []>;
	def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",			def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
	"Swift ARM processors", []>;			"Swift ARM processors", []>;

	▲ Show 20 Lines • Show All 464 Lines • ▼ Show 20 Lines

	def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,			def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
	FeatureHWDivThumb,			FeatureHWDivThumb,
	FeatureHWDivARM,			FeatureHWDivARM,
	FeatureCrypto,			FeatureCrypto,
	FeatureCRC,			FeatureCRC,
	FeatureFPAO]>;			FeatureFPAO]>;

				def : ProcNoItin<"cortex-a55", [ARMv82a, ProcA55,
				FeatureHWDivThumb,
				FeatureHWDivARM,
				FeatureDotProd]>;

	def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57,			def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57,
	FeatureHWDivThumb,			FeatureHWDivThumb,
	FeatureHWDivARM,			FeatureHWDivARM,
	FeatureCrypto,			FeatureCrypto,
	FeatureCRC,			FeatureCRC,
	FeatureFPAO,			FeatureFPAO,
	FeatureAvoidPartialCPSR,			FeatureAvoidPartialCPSR,
	FeatureCheapPredicableCPSR]>;			FeatureCheapPredicableCPSR]>;

	def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,			def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
	FeatureHWDivThumb,			FeatureHWDivThumb,
	FeatureHWDivARM,			FeatureHWDivARM,
	FeatureCrypto,			FeatureCrypto,
	FeatureCRC]>;			FeatureCRC]>;

	def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73,			def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73,
	FeatureHWDivThumb,			FeatureHWDivThumb,
	FeatureHWDivARM,			FeatureHWDivARM,
	FeatureCrypto,			FeatureCrypto,
	FeatureCRC]>;			FeatureCRC]>;

				def : ProcNoItin<"cortex-a75", [ARMv82a, ProcA75,
				FeatureHWDivThumb,
				FeatureHWDivARM,
				FeatureDotProd]>;

	def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,			def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
	FeatureHasRetAddrStack,			FeatureHasRetAddrStack,
	FeatureNEONForFP,			FeatureNEONForFP,
	FeatureVFP4,			FeatureVFP4,
	FeatureMP,			FeatureMP,
	FeatureHWDivThumb,			FeatureHWDivThumb,
	FeatureHWDivARM,			FeatureHWDivARM,
	FeatureAvoidPartialCPSR,			FeatureAvoidPartialCPSR,
	▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/ARMSubtarget.h

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines	enum ARMProcFamilyEnum {

CortexA12,		CortexA12,
CortexA15,		CortexA15,
CortexA17,		CortexA17,
CortexA32,		CortexA32,
CortexA35,		CortexA35,
CortexA5,		CortexA5,
CortexA53,		CortexA53,
		CortexA55,
CortexA57,		CortexA57,
CortexA7,		CortexA7,
CortexA72,		CortexA72,
CortexA73,		CortexA73,
		CortexA75,
CortexA8,		CortexA8,
CortexA9,		CortexA9,
CortexM3,		CortexM3,
CortexR4,		CortexR4,
CortexR4F,		CortexR4F,
CortexR5,		CortexR5,
CortexR52,		CortexR52,
CortexR7,		CortexR7,
▲ Show 20 Lines • Show All 690 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp

Show First 20 Lines • Show All 273 Lines • ▼ Show 20 Lines	case CortexA15:
MaxInterleaveFactor = 2;		MaxInterleaveFactor = 2;
PreISelOperandLatencyAdjustment = 1;		PreISelOperandLatencyAdjustment = 1;
PartialUpdateClearance = 12;		PartialUpdateClearance = 12;
break;		break;
case CortexA17:		case CortexA17:
case CortexA32:		case CortexA32:
case CortexA35:		case CortexA35:
case CortexA53:		case CortexA53:
		case CortexA55:
case CortexA57:		case CortexA57:
case CortexA72:		case CortexA72:
case CortexA73:		case CortexA73:
		case CortexA75:
case CortexR4:		case CortexR4:
case CortexR4F:		case CortexR4F:
case CortexR5:		case CortexR5:
case CortexR7:		case CortexR7:
case CortexM3:		case CortexM3:
case CortexR52:		case CortexR52:
case ExynosM1:		case ExynosM1:
case Kryo:		case Kryo:
▲ Show 20 Lines • Show All 109 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/cpus.ll

	; This tests that llc accepts all valid AArch64 CPUs			; This tests that llc accepts all valid AArch64 CPUs


	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=generic 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=generic 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a35 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a35 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 \| FileCheck %s
				; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a55 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a57 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a57 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a72 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a72 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a73 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a73 2>&1 \| FileCheck %s
				; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a75 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m1 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m1 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m2 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m2 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m3 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m3 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=falkor 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=falkor 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=kryo 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=kryo 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=thunderx2t99 2>&1 \| FileCheck %s			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=thunderx2t99 2>&1 \| FileCheck %s
	; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 \| FileCheck %s --check-prefix=INVALID			; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 \| FileCheck %s --check-prefix=INVALID

	; CHECK-NOT: {{.*}} is not a recognized processor for this target			; CHECK-NOT: {{.*}} is not a recognized processor for this target
	; INVALID: {{.*}} is not a recognized processor for this target			; INVALID: {{.*}} is not a recognized processor for this target

	define i32 @f(i64 %z) {			define i32 @f(i64 %z) {
	ret i32 0			ret i32 0
	}			}

llvm/trunk/test/CodeGen/AArch64/remat.ll

	; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a35 -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a35 -o - %s \| FileCheck %s
	; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s \| FileCheck %s
	; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s \| FileCheck %s
				; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a55 -o - %s \| FileCheck %s
				; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s \| FileCheck %s
	; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a72 -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a72 -o - %s \| FileCheck %s
	; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a73 -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a73 -o - %s \| FileCheck %s
				; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a75 -o - %s \| FileCheck %s
	; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m1 -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m1 -o - %s \| FileCheck %s
	; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m2 -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m2 -o - %s \| FileCheck %s
	; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m3 -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m3 -o - %s \| FileCheck %s
	; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=falkor -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=falkor -o - %s \| FileCheck %s
	; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=kryo -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=kryo -o - %s \| FileCheck %s
	; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s \| FileCheck %s
	; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s \| FileCheck %s			; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s \| FileCheck %s

	Show All 15 Lines

llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s

	// RUN: llvm-mc -triple aarch64 -mattr=+dotprod -show-encoding < %s \| FileCheck %s --check-prefix=CHECK-DOTPROD			// RUN: llvm-mc -triple aarch64 -mattr=+dotprod -show-encoding < %s \| FileCheck %s --check-prefix=CHECK-DOTPROD
				// RUN: llvm-mc -triple aarch64 -mcpu=cortex-a75 -show-encoding < %s \| FileCheck %s --check-prefix=CHECK-DOTPROD
				// RUN: llvm-mc -triple aarch64 -mcpu=cortex-a55 -show-encoding < %s \| FileCheck %s --check-prefix=CHECK-DOTPROD
	// RUN: not llvm-mc -triple aarch64 -mattr=+v8.2a -show-encoding < %s 2> %t			// RUN: not llvm-mc -triple aarch64 -mattr=+v8.2a -show-encoding < %s 2> %t
	// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s			// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s

	udot v0.2s, v1.8b, v2.8b			udot v0.2s, v1.8b, v2.8b
	sdot v0.2s, v1.8b, v2.8b			sdot v0.2s, v1.8b, v2.8b
	udot v0.4s, v1.16b, v2.16b			udot v0.4s, v1.16b, v2.16b
	sdot v0.4s, v1.16b, v2.16b			sdot v0.4s, v1.16b, v2.16b
	udot v0.2s, v1.8b, v2.4b[0]			udot v0.2s, v1.8b, v2.4b[0]
	▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/trunk/test/MC/AArch64/armv8.3a-rcpc.s

	// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 \| FileCheck %s			// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 \| FileCheck %s
				// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a75 < %s 2>&1 \| FileCheck %s
				// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a55 < %s 2>&1 \| FileCheck %s
				// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -mattr=+rcpc < %s 2>&1 \| FileCheck %s
	// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t			// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t
	// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t			// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t

	ldaprb w0, [x0, #0]			ldaprb w0, [x0, #0]
	ldaprh w0, [x17, #0]			ldaprh w0, [x17, #0]
	ldapr w0, [x1, #0]			ldapr w0, [x1, #0]
	ldapr x0, [x0, #0]			ldapr x0, [x0, #0]
	ldapr w18, [x0]			ldapr w18, [x0]
	Show All 14 Lines

llvm/trunk/test/MC/ARM/armv8.2a-dotprod-a32.s

	// RUN: llvm-mc -triple arm -mattr=+dotprod -show-encoding < %s \| FileCheck %s --check-prefix=CHECK			// RUN: llvm-mc -triple arm -mattr=+dotprod -show-encoding < %s \| FileCheck %s --check-prefix=CHECK
				// RUN: llvm-mc -triple arm -mcpu=cortex-a75 -show-encoding < %s \| FileCheck %s --check-prefix=CHECK
				// RUN: llvm-mc -triple arm -mcpu=cortex-a55 -show-encoding < %s \| FileCheck %s --check-prefix=CHECK

	// RUN: not llvm-mc -triple arm -mattr=-dotprod -show-encoding < %s 2> %t			// RUN: not llvm-mc -triple arm -mattr=-dotprod -show-encoding < %s 2> %t
	// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s			// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
	// RUN: not llvm-mc -triple arm -show-encoding < %s 2> %t			// RUN: not llvm-mc -triple arm -show-encoding < %s 2> %t
	// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s			// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
	// RUN: not llvm-mc -triple arm -mattr=+v8.1a -show-encoding < %s 2> %t			// RUN: not llvm-mc -triple arm -mattr=+v8.1a -show-encoding < %s 2> %t
	// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s			// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
	// RUN: not llvm-mc -triple arm -mattr=+v8.2a -show-encoding < %s 2> %t			// RUN: not llvm-mc -triple arm -mattr=+v8.2a -show-encoding < %s 2> %t
	Show All 28 Lines

llvm/trunk/test/MC/ARM/armv8.2a-dotprod-t32.s

	// RUN: llvm-mc -triple thumb -mattr=+dotprod -show-encoding < %s \| FileCheck %s --check-prefix=CHECK			// RUN: llvm-mc -triple thumb -mattr=+dotprod -show-encoding < %s \| FileCheck %s --check-prefix=CHECK
				// RUN: llvm-mc -triple thumb -mcpu=cortex-a75 -show-encoding < %s \| FileCheck %s --check-prefix=CHECK
				// RUN: llvm-mc -triple thumb -mcpu=cortex-a55 -show-encoding < %s \| FileCheck %s --check-prefix=CHECK

	// RUN: not llvm-mc -triple thumb -mattr=-dotprod -show-encoding < %s 2> %t			// RUN: not llvm-mc -triple thumb -mattr=-dotprod -show-encoding < %s 2> %t
	// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s			// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
	// RUN: not llvm-mc -triple thumb -show-encoding < %s 2> %t			// RUN: not llvm-mc -triple thumb -show-encoding < %s 2> %t
	// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s			// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
	// RUN: not llvm-mc -triple thumb -mattr=+v8.1a -show-encoding < %s 2> %t			// RUN: not llvm-mc -triple thumb -mattr=+v8.1a -show-encoding < %s 2> %t
	// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s			// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
	// RUN: not llvm-mc -triple thumb -mattr=+v8.2a -show-encoding < %s 2> %t			// RUN: not llvm-mc -triple thumb -mattr=+v8.2a -show-encoding < %s 2> %t
	Show All 29 Lines

llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt

	# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+dotprod --disassemble < %s \| FileCheck %s			# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+dotprod --disassemble < %s \| FileCheck %s
				# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a75 --disassemble < %s \| FileCheck %s
				# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a55 --disassemble < %s \| FileCheck %s
	# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-dotprod --disassemble < %s 2>&1 \| FileCheck %s --check-prefix=CHECK-ERROR			# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-dotprod --disassemble < %s 2>&1 \| FileCheck %s --check-prefix=CHECK-ERROR

	0x20,0x94,0x82,0x2e			0x20,0x94,0x82,0x2e
	0x20,0x94,0x82,0x0e			0x20,0x94,0x82,0x0e
	0x20,0x94,0x82,0x6e			0x20,0x94,0x82,0x6e
	0x20,0x94,0x82,0x4e			0x20,0x94,0x82,0x4e
	0x20,0xe0,0x82,0x2f			0x20,0xe0,0x82,0x2f
	0x20,0xe0,0xa2,0x0f			0x20,0xe0,0xa2,0x0f
	Show All 20 Lines

llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt

	# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s \| FileCheck %s			# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s \| FileCheck %s
				# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a75 --disassemble < %s \| FileCheck %s
				# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a55 --disassemble < %s \| FileCheck %s
				# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a -mattr=+rcpc --disassemble < %s \| FileCheck %s

	# CHECK: ldaprb w0, [x0]			# CHECK: ldaprb w0, [x0]
	# CHECK: ldaprh w0, [x0]			# CHECK: ldaprh w0, [x0]
	# CHECK: ldapr w0, [x0]			# CHECK: ldapr w0, [x0]
	# CHECK: ldapr x0, [x0]			# CHECK: ldapr x0, [x0]
	[0x00,0xc0,0xbf,0x38]			[0x00,0xc0,0xbf,0x38]
	[0x00,0xc0,0xbf,0x78]			[0x00,0xc0,0xbf,0x78]
	[0x00,0xc0,0xbf,0xb8]			[0x00,0xc0,0xbf,0xb8]
	Show All 17 Lines

llvm/trunk/unittests/Support/TargetParserTest.cpp

Show First 20 Lines • Show All 212 Lines • ▼ Show 20 Lines	EXPECT_TRUE(testARMCPU("cortex-a35", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_VIRT \| ARM::AEK_HWDIVARM \|		ARM::AEK_VIRT \| ARM::AEK_HWDIVARM \|
ARM::AEK_HWDIVTHUMB \| ARM::AEK_DSP,		ARM::AEK_HWDIVTHUMB \| ARM::AEK_DSP,
"8-A"));		"8-A"));
EXPECT_TRUE(testARMCPU("cortex-a53", "armv8-a", "crypto-neon-fp-armv8",		EXPECT_TRUE(testARMCPU("cortex-a53", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC \| ARM::AEK_SEC \| ARM::AEK_MP \|		ARM::AEK_CRC \| ARM::AEK_SEC \| ARM::AEK_MP \|
ARM::AEK_VIRT \| ARM::AEK_HWDIVARM \|		ARM::AEK_VIRT \| ARM::AEK_HWDIVARM \|
ARM::AEK_HWDIVTHUMB \| ARM::AEK_DSP,		ARM::AEK_HWDIVTHUMB \| ARM::AEK_DSP,
"8-A"));		"8-A"));
		EXPECT_TRUE(testARMCPU("cortex-a55", "armv8.2-a", "crypto-neon-fp-armv8",
		ARM::AEK_CRC \| ARM::AEK_SEC \| ARM::AEK_MP \|
		ARM::AEK_VIRT \| ARM::AEK_HWDIVARM \|
		ARM::AEK_HWDIVTHUMB \| ARM::AEK_DSP \| ARM::AEK_FP16 \|
		ARM::AEK_RAS \| ARM::AEK_DOTPROD,
		"8.2-A"));
EXPECT_TRUE(testARMCPU("cortex-a57", "armv8-a", "crypto-neon-fp-armv8",		EXPECT_TRUE(testARMCPU("cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC \| ARM::AEK_SEC \| ARM::AEK_MP \|		ARM::AEK_CRC \| ARM::AEK_SEC \| ARM::AEK_MP \|
ARM::AEK_VIRT \| ARM::AEK_HWDIVARM \|		ARM::AEK_VIRT \| ARM::AEK_HWDIVARM \|
ARM::AEK_HWDIVTHUMB \| ARM::AEK_DSP,		ARM::AEK_HWDIVTHUMB \| ARM::AEK_DSP,
"8-A"));		"8-A"));
EXPECT_TRUE(testARMCPU("cortex-a72", "armv8-a", "crypto-neon-fp-armv8",		EXPECT_TRUE(testARMCPU("cortex-a72", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC \| ARM::AEK_SEC \| ARM::AEK_MP \|		ARM::AEK_CRC \| ARM::AEK_SEC \| ARM::AEK_MP \|
ARM::AEK_VIRT \| ARM::AEK_HWDIVARM \|		ARM::AEK_VIRT \| ARM::AEK_HWDIVARM \|
ARM::AEK_HWDIVTHUMB \| ARM::AEK_DSP,		ARM::AEK_HWDIVTHUMB \| ARM::AEK_DSP,
"8-A"));		"8-A"));
EXPECT_TRUE(testARMCPU("cortex-a73", "armv8-a", "crypto-neon-fp-armv8",		EXPECT_TRUE(testARMCPU("cortex-a73", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC \| ARM::AEK_SEC \| ARM::AEK_MP \|		ARM::AEK_CRC \| ARM::AEK_SEC \| ARM::AEK_MP \|
ARM::AEK_VIRT \| ARM::AEK_HWDIVARM \|		ARM::AEK_VIRT \| ARM::AEK_HWDIVARM \|
ARM::AEK_HWDIVTHUMB \| ARM::AEK_DSP,		ARM::AEK_HWDIVTHUMB \| ARM::AEK_DSP,
"8-A"));		"8-A"));
		EXPECT_TRUE(testARMCPU("cortex-a75", "armv8.2-a", "crypto-neon-fp-armv8",
		ARM::AEK_CRC \| ARM::AEK_SEC \| ARM::AEK_MP \|
		ARM::AEK_VIRT \| ARM::AEK_HWDIVARM \|
		ARM::AEK_HWDIVTHUMB \| ARM::AEK_DSP \| ARM::AEK_FP16 \|
		ARM::AEK_RAS \| ARM::AEK_DOTPROD,
		"8.2-A"));
EXPECT_TRUE(testARMCPU("cyclone", "armv8-a", "crypto-neon-fp-armv8",		EXPECT_TRUE(testARMCPU("cyclone", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC \| ARM::AEK_SEC \| ARM::AEK_MP \|		ARM::AEK_CRC \| ARM::AEK_SEC \| ARM::AEK_MP \|
ARM::AEK_VIRT \| ARM::AEK_HWDIVARM \|		ARM::AEK_VIRT \| ARM::AEK_HWDIVARM \|
ARM::AEK_HWDIVTHUMB \| ARM::AEK_DSP,		ARM::AEK_HWDIVTHUMB \| ARM::AEK_DSP,
"8-A"));		"8-A"));
EXPECT_TRUE(testARMCPU("exynos-m1", "armv8-a", "crypto-neon-fp-armv8",		EXPECT_TRUE(testARMCPU("exynos-m1", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC \| ARM::AEK_SEC \| ARM::AEK_MP \|		ARM::AEK_CRC \| ARM::AEK_SEC \| ARM::AEK_MP \|
ARM::AEK_VIRT \| ARM::AEK_HWDIVARM \|		ARM::AEK_VIRT \| ARM::AEK_HWDIVARM \|
▲ Show 20 Lines • Show All 266 Lines • ▼ Show 20 Lines	const char *ArchExt[][4] = {{"crc", "nocrc", "+crc", "-crc"},
{"fp", "nofp", nullptr, nullptr},		{"fp", "nofp", nullptr, nullptr},
{"idiv", "noidiv", nullptr, nullptr},		{"idiv", "noidiv", nullptr, nullptr},
{"mp", "nomp", nullptr, nullptr},		{"mp", "nomp", nullptr, nullptr},
{"simd", "nosimd", nullptr, nullptr},		{"simd", "nosimd", nullptr, nullptr},
{"sec", "nosec", nullptr, nullptr},		{"sec", "nosec", nullptr, nullptr},
{"virt", "novirt", nullptr, nullptr},		{"virt", "novirt", nullptr, nullptr},
{"fp16", "nofp16", "+fullfp16", "-fullfp16"},		{"fp16", "nofp16", "+fullfp16", "-fullfp16"},
{"ras", "noras", "+ras", "-ras"},		{"ras", "noras", "+ras", "-ras"},
		{"dotprod", "nodotprod", "+dotprod", "-dotprod"},
{"os", "noos", nullptr, nullptr},		{"os", "noos", nullptr, nullptr},
{"iwmmxt", "noiwmmxt", nullptr, nullptr},		{"iwmmxt", "noiwmmxt", nullptr, nullptr},
{"iwmmxt2", "noiwmmxt2", nullptr, nullptr},		{"iwmmxt2", "noiwmmxt2", nullptr, nullptr},
{"maverick", "maverick", nullptr, nullptr},		{"maverick", "maverick", nullptr, nullptr},
{"xscale", "noxscale", nullptr, nullptr}};		{"xscale", "noxscale", nullptr, nullptr}};

for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {		for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
EXPECT_EQ(StringRef(ArchExt[i][2]), ARM::getArchExtFeature(ArchExt[i][0]));		EXPECT_EQ(StringRef(ArchExt[i][2]), ARM::getArchExtFeature(ArchExt[i][0]));
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines	EXPECT_TRUE(testAArch64CPU(
"cortex-a35", "armv8-a", "crypto-neon-fp-armv8",		"cortex-a35", "armv8-a", "crypto-neon-fp-armv8",
AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \| AArch64::AEK_FP \|		AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \| AArch64::AEK_FP \|
AArch64::AEK_SIMD, "8-A"));		AArch64::AEK_SIMD, "8-A"));
EXPECT_TRUE(testAArch64CPU(		EXPECT_TRUE(testAArch64CPU(
"cortex-a53", "armv8-a", "crypto-neon-fp-armv8",		"cortex-a53", "armv8-a", "crypto-neon-fp-armv8",
AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \| AArch64::AEK_FP \|		AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \| AArch64::AEK_FP \|
AArch64::AEK_SIMD, "8-A"));		AArch64::AEK_SIMD, "8-A"));
EXPECT_TRUE(testAArch64CPU(		EXPECT_TRUE(testAArch64CPU(
		"cortex-a55", "armv8.2-a", "crypto-neon-fp-armv8",
		AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \| AArch64::AEK_FP \|
		AArch64::AEK_SIMD \| AArch64::AEK_RAS \| AArch64::AEK_LSE \|
		AArch64::AEK_FP16 \| AArch64::AEK_DOTPROD \| AArch64::AEK_RCPC,
		"8.2-A"));
		EXPECT_TRUE(testAArch64CPU(
"cortex-a57", "armv8-a", "crypto-neon-fp-armv8",		"cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \| AArch64::AEK_FP \|		AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \| AArch64::AEK_FP \|
AArch64::AEK_SIMD, "8-A"));		AArch64::AEK_SIMD, "8-A"));
EXPECT_TRUE(testAArch64CPU(		EXPECT_TRUE(testAArch64CPU(
"cortex-a72", "armv8-a", "crypto-neon-fp-armv8",		"cortex-a72", "armv8-a", "crypto-neon-fp-armv8",
AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \| AArch64::AEK_FP \|		AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \| AArch64::AEK_FP \|
AArch64::AEK_SIMD, "8-A"));		AArch64::AEK_SIMD, "8-A"));
EXPECT_TRUE(testAArch64CPU(		EXPECT_TRUE(testAArch64CPU(
"cortex-a73", "armv8-a", "crypto-neon-fp-armv8",		"cortex-a73", "armv8-a", "crypto-neon-fp-armv8",
AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \| AArch64::AEK_FP \|		AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \| AArch64::AEK_FP \|
AArch64::AEK_SIMD, "8-A"));		AArch64::AEK_SIMD, "8-A"));
EXPECT_TRUE(testAArch64CPU(		EXPECT_TRUE(testAArch64CPU(
		"cortex-a75", "armv8.2-a", "crypto-neon-fp-armv8",
		AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \| AArch64::AEK_FP \|
		AArch64::AEK_SIMD \| AArch64::AEK_RAS \| AArch64::AEK_LSE \|
		AArch64::AEK_FP16 \| AArch64::AEK_DOTPROD \| AArch64::AEK_RCPC,
		"8.2-A"));
		EXPECT_TRUE(testAArch64CPU(
"cyclone", "armv8-a", "crypto-neon-fp-armv8",		"cyclone", "armv8-a", "crypto-neon-fp-armv8",
AArch64::AEK_CRYPTO \| AArch64::AEK_FP \| AArch64::AEK_SIMD, "8-A"));		AArch64::AEK_CRYPTO \| AArch64::AEK_FP \| AArch64::AEK_SIMD, "8-A"));
EXPECT_TRUE(testAArch64CPU(		EXPECT_TRUE(testAArch64CPU(
"exynos-m1", "armv8-a", "crypto-neon-fp-armv8",		"exynos-m1", "armv8-a", "crypto-neon-fp-armv8",
AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \| AArch64::AEK_FP \|		AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \| AArch64::AEK_FP \|
AArch64::AEK_SIMD, "8-A"));		AArch64::AEK_SIMD, "8-A"));
EXPECT_TRUE(testAArch64CPU(		EXPECT_TRUE(testAArch64CPU(
"exynos-m2", "armv8-a", "crypto-neon-fp-armv8",		"exynos-m2", "armv8-a", "crypto-neon-fp-armv8",
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines	return AArch64::getDefaultExtensions(CPUName, AK) &
AArch64::parseArchExt(ArchExt);		AArch64::parseArchExt(ArchExt);
}		}

TEST(TargetParserTest, testAArch64Extension) {		TEST(TargetParserTest, testAArch64Extension) {
EXPECT_FALSE(testAArch64Extension("cortex-a35",		EXPECT_FALSE(testAArch64Extension("cortex-a35",
AArch64::ArchKind::INVALID, "ras"));		AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("cortex-a53",		EXPECT_FALSE(testAArch64Extension("cortex-a53",
AArch64::ArchKind::INVALID, "ras"));		AArch64::ArchKind::INVALID, "ras"));
		EXPECT_TRUE(testAArch64Extension("cortex-a55",
		AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("cortex-a57",		EXPECT_FALSE(testAArch64Extension("cortex-a57",
AArch64::ArchKind::INVALID, "ras"));		AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("cortex-a72",		EXPECT_FALSE(testAArch64Extension("cortex-a72",
AArch64::ArchKind::INVALID, "ras"));		AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("cortex-a73",		EXPECT_FALSE(testAArch64Extension("cortex-a73",
AArch64::ArchKind::INVALID, "ras"));		AArch64::ArchKind::INVALID, "ras"));
		EXPECT_TRUE(testAArch64Extension("cortex-a75",
		AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("cyclone",		EXPECT_FALSE(testAArch64Extension("cyclone",
AArch64::ArchKind::INVALID, "ras"));		AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("exynos-m1",		EXPECT_FALSE(testAArch64Extension("exynos-m1",
AArch64::ArchKind::INVALID, "ras"));		AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("kryo",		EXPECT_FALSE(testAArch64Extension("kryo",
AArch64::ArchKind::INVALID, "ras"));		AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("thunderx2t99",		EXPECT_FALSE(testAArch64Extension("thunderx2t99",
AArch64::ArchKind::INVALID, "ras"));		AArch64::ArchKind::INVALID, "ras"));
Show All 14 Lines	EXPECT_FALSE(testAArch64Extension(
"generic", AArch64::ArchKind::ARMV8_2A, "spe"));		"generic", AArch64::ArchKind::ARMV8_2A, "spe"));
}		}

TEST(TargetParserTest, AArch64ExtensionFeatures) {		TEST(TargetParserTest, AArch64ExtensionFeatures) {
std::vector<StringRef> Features;		std::vector<StringRef> Features;
unsigned Extensions = AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \|		unsigned Extensions = AArch64::AEK_CRC \| AArch64::AEK_CRYPTO \|
AArch64::AEK_FP \| AArch64::AEK_SIMD \|		AArch64::AEK_FP \| AArch64::AEK_SIMD \|
AArch64::AEK_FP16 \| AArch64::AEK_PROFILE \|		AArch64::AEK_FP16 \| AArch64::AEK_PROFILE \|
AArch64::AEK_RAS \| AArch64::AEK_SVE;		AArch64::AEK_RAS \| AArch64::AEK_SVE \|
		AArch64::AEK_DOTPROD \| AArch64::AEK_RCPC;

for (unsigned i = 0; i <= Extensions; i++)		for (unsigned i = 0; i <= Extensions; i++)
EXPECT_TRUE(i == 0 ? !AArch64::getExtensionFeatures(i, Features)		EXPECT_TRUE(i == 0 ? !AArch64::getExtensionFeatures(i, Features)
: AArch64::getExtensionFeatures(i, Features));		: AArch64::getExtensionFeatures(i, Features));
}		}

TEST(TargetParserTest, AArch64ArchFeatures) {		TEST(TargetParserTest, AArch64ArchFeatures) {
std::vector<StringRef> Features;		std::vector<StringRef> Features;
Show All 12 Lines
TEST(TargetParserTest, AArch64ArchExtFeature) {		TEST(TargetParserTest, AArch64ArchExtFeature) {
const char *ArchExt[][4] = {{"crc", "nocrc", "+crc", "-crc"},		const char *ArchExt[][4] = {{"crc", "nocrc", "+crc", "-crc"},
{"crypto", "nocrypto", "+crypto", "-crypto"},		{"crypto", "nocrypto", "+crypto", "-crypto"},
{"fp", "nofp", "+fp-armv8", "-fp-armv8"},		{"fp", "nofp", "+fp-armv8", "-fp-armv8"},
{"simd", "nosimd", "+neon", "-neon"},		{"simd", "nosimd", "+neon", "-neon"},
{"fp16", "nofp16", "+fullfp16", "-fullfp16"},		{"fp16", "nofp16", "+fullfp16", "-fullfp16"},
{"profile", "noprofile", "+spe", "-spe"},		{"profile", "noprofile", "+spe", "-spe"},
{"ras", "noras", "+ras", "-ras"},		{"ras", "noras", "+ras", "-ras"},
{"sve", "nosve", "+sve", "-sve"}};		{"sve", "nosve", "+sve", "-sve"},
		{"dotprod", "nodotprod", "+dotprod", "-dotprod"},
		{"rcpc", "norcpc", "+rcpc", "-rcpc" }};

for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {		for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
EXPECT_EQ(StringRef(ArchExt[i][2]),		EXPECT_EQ(StringRef(ArchExt[i][2]),
AArch64::getArchExtFeature(ArchExt[i][0]));		AArch64::getArchExtFeature(ArchExt[i][0]));
EXPECT_EQ(StringRef(ArchExt[i][3]),		EXPECT_EQ(StringRef(ArchExt[i][3]),
AArch64::getArchExtFeature(ArchExt[i][1]));		AArch64::getArchExtFeature(ArchExt[i][1]));
}		}
}		}
}		}

This is an archive of the discontinued LLVM Phabricator instance.

[ARM][AArch64] Cortex-A75 and Cortex-A55 supportClosedPublic

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Revision Contents

Diff 111937

llvm/trunk/include/llvm/Support/AArch64TargetParser.def

llvm/trunk/include/llvm/Support/ARMTargetParser.def

llvm/trunk/include/llvm/Support/TargetParser.h

llvm/trunk/lib/Support/TargetParser.cpp

llvm/trunk/lib/Target/AArch64/AArch64.td

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp

llvm/trunk/lib/Target/ARM/ARM.td

llvm/trunk/lib/Target/ARM/ARMSubtarget.h

llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp

llvm/trunk/test/CodeGen/AArch64/cpus.ll

llvm/trunk/test/CodeGen/AArch64/remat.ll

llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s

llvm/trunk/test/MC/AArch64/armv8.3a-rcpc.s

llvm/trunk/test/MC/ARM/armv8.2a-dotprod-a32.s

llvm/trunk/test/MC/ARM/armv8.2a-dotprod-t32.s

llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt

llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt

llvm/trunk/unittests/Support/TargetParserTest.cpp

[ARM][AArch64] Cortex-A75 and Cortex-A55 support
ClosedPublic