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[RISCV] Use V0 instead of VMV0: for mask vectors in isel patterns.

Authored by craig.topper on Sep 3 2021, 9:38 AM.



This is consistent with the RVV intrinsic patterns. This has been
shown to prevent some "ran out of registers" errors in our internal

Unfortunately, there are some regressions on LMUL=8 tests in here.
I think the lack of registers with LMUL=8 just makes it very hard
to schedule correctly.

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craig.topper created this revision.Sep 3 2021, 9:38 AM
craig.topper requested review of this revision.Sep 3 2021, 9:38 AM
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frasercrmck accepted this revision.Sep 8 2021, 9:16 AM

Sorry for the delay - I'd been meaning to try out this patch with one of the "ran out of registers" issues I'd seen locally. Good news is that it fixes it too. Less good news is I'm not entirely sure why.

The closest I came to was that, in my case, we'd have ISel generate something like:

%1:vr = COPY $v8
%0:vr = COPY $v0
%3:vr = PseudoVMV_V_I_MF8 0, -1, 3
%5:vmv0 = COPY %1
%4:vrnov0 = PseudoVMERGE_VIM_MF8 %3, 1, %5, -1, 3

which eventually gets optimized to

	  liveins: $v0, $v8, $v9
16B	  %2:vmv0 = COPY $v9
64B	  dead %19:gpr = PseudoVSETVLIX0 $x0, 69, implicit-def $vl, implicit-def $vtype
80B	  %3:vr = PseudoVMV_V_I_MF8 0, -1, 3, implicit $vl, implicit $vtype
96B	  %10:vrnov0 = PseudoVMERGE_VIM_MF8 %3:vr, 1, %2:vmv0, -1, 3, implicit $vl, implicit $vtype
136B	  %0:vmv0 = COPY $v0 ; used by another VMERGE in a successor block

Where the first copy is now essentially to $v0 but it is interfered with by the livein $v0 which hasn't been moved out of a physical register yet. All I know is that RA doesn't know how to handle that. But I'm sure it could if we taught it?

Anyway, just jotting that down in case that helps. This change LGTM.

This revision is now accepted and ready to land.Sep 8 2021, 9:16 AM
This revision was landed with ongoing or failed builds.Sep 8 2021, 9:48 AM
This revision was automatically updated to reflect the committed changes.