[RISCV] Use GPRNoX0 for source register to WriteSysReg/SwapSysReg pseudo instructions.

[craig.topper]

Summary

Having X0 as a source of a CSRRW means don't write the register. To
write a 0, you should use CSRRWI instead. ISel normally takes care of
this. To further guarantee this I've merged the classes so we must
have isel patterns for imm 0 if we have the register operation.

It is possible that a X0 is an operand of a select that feeds the CSR
write pseudo instruction. The select will be expanded to control flow
and phis which later be turned into copies. This can allow register
coalescing to coalesce the X0 into a CSR write pseudo instruction. By
using GPRNoX0 the coalescing should be prevented.

We don't yet have any uses of these pseudo instructions that I know of
so I can't test this. I'm extrapolating from a similar issue we found
on vsetvli for vector instructions. That's a much larger bug to fix.

[jrtc27]

It's only CSRRS/CSRRC (and their immediate counterparts) that special-case a zero source (whereas it's only CSRRW (and its immediate counterpart) that special-cases a zero destination). So the existing code is fine AFAICT.

[craig.topper]

In D109076#2977435, @jrtc27 wrote:

It's only CSRRS/CSRRC (and their immediate counterparts) that special-case a zero source (whereas it's only CSRRW (and its immediate counterpart) that special-cases a zero destination). So the existing code is fine AFAICT.

Oops. You're right, I misread the table. Thanks. I'll go back to trying to fix vsetvli.

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 class ReadSysReg<SysReg SR, list<Register> Regs>
   : Pseudo<(outs GPR:$rd), (ins),
            [(set GPR:$rd, (riscv_read_csr (XLenVT SR.Encoding)))]>,
     PseudoInstExpansion<(CSRRS GPR:$rd, SR.Encoding, X0)> {
   let hasSideEffects = 0;
   let Uses = Regs;
 }
 
-class WriteSysReg<SysReg SR, list<Register> Regs>
-  : Pseudo<(outs), (ins GPR:$val),
-           [(riscv_write_csr (XLenVT SR.Encoding), GPR:$val)]>,
-    PseudoInstExpansion<(CSRRW X0, SR.Encoding, GPR:$val)> {
-  let hasSideEffects = 0;
-  let Defs = Regs;
-}
-
-class WriteSysRegImm<SysReg SR, list<Register> Regs>
-  : Pseudo<(outs), (ins uimm5:$val),
+// Need to use GPRNoX0 for $val to prevent X0 copies coalescing into this
+// causing it to become CSRRW x0, x0 which is a NOP.
+multiclass WriteSysReg<SysReg SR, list<Register> Regs> {
+  let hasSideEffects = 0, Defs = Regs in {
+    def NAME : Pseudo<(outs), (ins GPRNoX0:$val),
+                      [(riscv_write_csr (XLenVT SR.Encoding), GPRNoX0:$val)]>,
+               PseudoInstExpansion<(CSRRW X0, SR.Encoding, GPR:$val)>;
+    def Imm : Pseudo<(outs), (ins uimm5:$val),
                      [(riscv_write_csr (XLenVT SR.Encoding), uimm5:$val)]>,
-    PseudoInstExpansion<(CSRRWI X0, SR.Encoding, uimm5:$val)> {
-  let hasSideEffects = 0;
-  let Defs = Regs;
+              PseudoInstExpansion<(CSRRWI X0, SR.Encoding, uimm5:$val)>;
   }
-
-class SwapSysReg<SysReg SR, list<Register> Regs>
-  : Pseudo<(outs GPR:$rd), (ins GPR:$val),
-           [(set GPR:$rd, (riscv_swap_csr (XLenVT SR.Encoding), GPR:$val))]>,
-    PseudoInstExpansion<(CSRRW GPR:$rd, SR.Encoding, GPR:$val)> {
-  let hasSideEffects = 0;
-  let Uses = Regs;
-  let Defs = Regs;
 }
 
-class SwapSysRegImm<SysReg SR, list<Register> Regs>
-  : Pseudo<(outs GPR:$rd), (ins uimm5:$val),
-           [(set GPR:$rd, (riscv_swap_csr (XLenVT SR.Encoding), uimm5:$val))]>,
-    PseudoInstExpansion<(CSRRWI GPR:$rd, SR.Encoding, uimm5:$val)> {
-  let hasSideEffects = 0;
-  let Uses = Regs;
-  let Defs = Regs;
+// Need to use GPRNoX0 for $val to prevent copies from X0 coalescing into this
+// causing it to become CSRRW rd, x0 which will not write the CSR.
+multiclass SwapSysReg<SysReg SR, list<Register> Regs> {
+  let hasSideEffects = 0, Uses = Regs, Defs = Regs in {
+    def NAME : Pseudo<(outs GPR:$rd), (ins GPRNoX0:$val),
+                      [(set GPR:$rd,
+                        (riscv_swap_csr (XLenVT SR.Encoding), GPRNoX0:$val))]>,
+               PseudoInstExpansion<(CSRRW GPR:$rd, SR.Encoding, GPR:$val)>;
+    def Imm : Pseudo<(outs GPR:$rd), (ins uimm5:$val),
+                     [(set GPR:$rd,
+                       (riscv_swap_csr (XLenVT SR.Encoding), uimm5:$val))]>;
+  }
 }
 
 def ReadFRM : ReadSysReg<SysRegFRM, [FRM]>;
-def WriteFRM : WriteSysReg<SysRegFRM, [FRM]>;
-def WriteFRMImm : WriteSysRegImm<SysRegFRM, [FRM]>;
+defm WriteFRM : WriteSysReg<SysRegFRM, [FRM]>;
 
 /// Other pseudo-instructions
 
 // Pessimistically assume the stack pointer will be clobbered
 let Defs = [X2], Uses = [X2] in {
 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                               [(callseq_start timm:$amt1, timm:$amt2)]>;
 def ADJCALLSTACKUP   : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),