This is an archive of the discontinued LLVM Phabricator instance.

[LegalizeTypes][VP] Add promotion support for binary VP ops
ClosedPublic

Authored by frasercrmck on Aug 18 2021, 4:05 AM.

Details

Summary

This patch extends the preliminary support for vector-predicated (VP)
operation legalization to include promotion of illegal integer vector
types.

Integer promotion of binary VP operations is relatively simple and
piggy-backs on the non-VP logic, but passing the two extra mask and VP
operands through to the promoted operation.

Tests have been added to the RISC-V target to cover the basic scenarios
for integer promotion for both fixed- and scalable-vector types.

Diff Detail

Event Timeline

frasercrmck created this revision.Aug 18 2021, 4:05 AM
frasercrmck requested review of this revision.Aug 18 2021, 4:05 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 18 2021, 4:05 AM
craig.topper added inline comments.Aug 31 2021, 9:13 AM
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
259

Follow clang-format

  • rebase & clang-format
frasercrmck marked an inline comment as done.Sep 1 2021, 1:32 AM
frasercrmck added inline comments.
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
259

Ah yes, thanks - that's the one that my fingers' muscle memory hasn't yet gotten used to.

LGTM - but a RISCV specialist should do the official accept

simoll added a project: Restricted Project.Sep 1 2021, 5:33 AM
frasercrmck marked an inline comment as done.
  • rebase on main

LGTM - but a RISCV specialist should do the official accept

@craig.topper or @rogfer01 perhaps - could you be that specialist?

craig.topper accepted this revision.Sep 7 2021, 10:57 AM

LGTM

llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
15

We should use slli a0, a0, 1 followed by vmv.v.x here. Not something that needs to be fixed in this patch though.

This revision is now accepted and ready to land.Sep 7 2021, 10:57 AM
frasercrmck added inline comments.Sep 8 2021, 2:22 AM
llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
15

Ah yes that's an interesting observation. Presumably we also want to do the vsra.vi v26, v26, 1 in scalar before splatting?

frasercrmck added inline comments.Sep 8 2021, 2:32 AM
llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
15

That said, the ideal is surely just to do vdiv.vx with a0? The fixed vectors generate:

vsetivli        zero, 8, e8, mf2, ta, mu
vadd.vv v25, v8, v8
vsra.vi v25, v25, 1
vsetvli zero, a1, e8, mf2, ta, mu
vdiv.vx v8, v25, a0, v0.t

I'll look into what's going on.

This revision was landed with ongoing or failed builds.Sep 8 2021, 2:33 AM
This revision was automatically updated to reflect the committed changes.