[AArch64][SME] Fix v8.6a bf16 NEON instruction predication

[c-rhodes]

Summary

In streaming mode on SME targets only the scalar BFCVT armv8.6-a
instruction is legal, predicate the illegal instructions on NEON to
disable them in streaming mode (see D107902). BFCVT is predicated on
HasNEONorStreamingSVE.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06/SIMD-FP-Instructions

[paulwalker-arm]

llvm/test/MC/AArch64/SME/streaming-mode-neon-negative.s

2

Do you need another RUN line here? Given this file is all about verifying +neon isn't implicitly enabled, I would have assumed a single RUN line with all feature flags is sufficient.

[c-rhodes]

llvm/test/MC/AArch64/SME/streaming-mode-neon-negative.s

2

Do you need another RUN line here? Given this file is all about verifying +neon isn't implicitly enabled, I would have assumed a single RUN line with all feature flags is sufficient.

I suppose not, I'll remove it and and bf16 to the existing line before landing, cheers

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 let Predicates = [HasDotProd] in {
 defm SDOT : SIMDThreeSameVectorDot<0, 0, "sdot", AArch64sdot>;
 defm UDOT : SIMDThreeSameVectorDot<1, 0, "udot", AArch64udot>;
 defm SDOTlane : SIMDThreeSameVectorDotIndex<0, 0, 0b10, "sdot", AArch64sdot>;
 defm UDOTlane : SIMDThreeSameVectorDotIndex<1, 0, 0b10, "udot", AArch64udot>;
 }
 
 // ARMv8.6-A BFloat
-let Predicates = [HasBF16] in {
+let Predicates = [HasNEON, HasBF16] in {
 defm BFDOT       : SIMDThreeSameVectorBFDot<1, "bfdot">;
 defm BF16DOTlane : SIMDThreeSameVectorBF16DotI<0, "bfdot">;
 def BFMMLA       : SIMDThreeSameVectorBF16MatrixMul<"bfmmla">;
 def BFMLALB      : SIMDBF16MLAL<0, "bfmlalb", int_aarch64_neon_bfmlalb>;
 def BFMLALT      : SIMDBF16MLAL<1, "bfmlalt", int_aarch64_neon_bfmlalt>;
 def BFMLALBIdx   : SIMDBF16MLALIndex<0, "bfmlalb", int_aarch64_neon_bfmlalb>;
 def BFMLALTIdx   : SIMDBF16MLALIndex<1, "bfmlalt", int_aarch64_neon_bfmlalt>;
 def BFCVTN       : SIMD_BFCVTN;
 def BFCVTN2      : SIMD_BFCVTN2;
-def BFCVT        : BF16ToSinglePrecision<"bfcvt">;
 
 // Vector-scalar BFDOT:
 // The second source operand of the 64-bit variant of BF16DOTlane is a 128-bit
 // register (the instruction uses a single 32-bit lane from it), so the pattern
 // is a bit tricky.
 def : Pat<(v2f32 (int_aarch64_neon_bfdot
                     (v2f32 V64:$Rd), (v4bf16 V64:$Rn),
                     (v4bf16 (bitconvert
                       (v2i32 (AArch64duplane32
                         (v4i32 (bitconvert
                           (v8bf16 (insert_subvector undef,
                             (v4bf16 V64:$Rm),
                             (i64 0))))),
                         VectorIndexS:$idx)))))),
           (BF16DOTlanev4bf16 (v2f32 V64:$Rd), (v4bf16 V64:$Rn),
                              (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
                              VectorIndexS:$idx)>;
 }
 
+let Predicates = [HasNEONorStreamingSVE, HasBF16] in {
+def BFCVT : BF16ToSinglePrecision<"bfcvt">;
+}
+
 // ARMv8.6A AArch64 matrix multiplication
 let Predicates = [HasMatMulInt8] in {
 def  SMMLA : SIMDThreeSameVectorMatMul<0, 0, "smmla", int_aarch64_neon_smmla>;
 def  UMMLA : SIMDThreeSameVectorMatMul<0, 1, "ummla", int_aarch64_neon_ummla>;
 def USMMLA : SIMDThreeSameVectorMatMul<1, 0, "usmmla", int_aarch64_neon_usmmla>;
 defm USDOT : SIMDThreeSameVectorDot<0, 1, "usdot", int_aarch64_neon_usdot>;
 defm USDOTlane : SIMDThreeSameVectorDotIndex<0, 1, 0b10, "usdot", int_aarch64_neon_usdot>;
 

llvm/test/MC/AArch64/SME/streaming-mode-neon-bf16.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+streaming-sve,+bf16 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=-neon < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+streaming-sve,+bf16 < %s \
+// RUN:        | llvm-objdump --mattr=+bf16 -d - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+streaming-sve,+bf16 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+streaming-sve,+bf16 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+bfcvt h5, s3
+// CHECK-INST: bfcvt h5, s3
+// CHECK-ENCODING: [0x65,0x40,0x63,0x1e]
+// CHECK-ERROR: instruction requires: bf16

llvm/test/MC/AArch64/SME/streaming-mode-neon-negative.s

-// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+streaming-sve 2>&1 < %s| FileCheck %s
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+streaming-sve,+bf16 2>&1 < %s| FileCheck %s
 
 // ------------------------------------------------------------------------- //
 // Check FABD is illegal in streaming mode
 
 fabd s0, s1, s2
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: neon
 // CHECK-NEXT: fabd s0, s1, s2
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Check non-scalar v8.6a BFloat16 instructions are illegal in streaming mode
+
+bfcvtn v5.4h, v5.4s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: neon
+// CHECK-NEXT: bfcvtn v5.4h, v5.4s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: