[DAGCombiner][AMDGPU] Canonicalize constants to the RHS of MULHU/MULHS.

[craig.topper]

Summary

This allows special constants like to 0 to be recognized. It's also
expected by isel patterns if a target had a mulh with immediate instructions.
The commuting done by tablegen won't commute patterns with immediates since it
expects DAGCombine to have done it.

[foad]

LGTM, thanks!

llvm/test/CodeGen/AMDGPU/sdiv64.ll

1211

Looks like there is some further cleanup possible here. This instruction is "add 0 with carry out" which is pretty useless.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 //===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (ISD::isConstantSplatVectorAllZeros(N0.getNode()) ||
         ISD::isConstantSplatVectorAllZeros(N1.getNode()))
       return DAG.getConstant(0, DL, VT);
   }
 
   // fold (mulhs c1, c2)
   if (SDValue C = DAG.FoldConstantArithmetic(ISD::MULHS, DL, VT, {N0, N1}))
     return C;
 
+  // canonicalize constant to RHS.
+  if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
+      !DAG.isConstantIntBuildVectorOrConstantInt(N1))
+    return DAG.getNode(ISD::MULHS, DL, N->getVTList(), N1, N0);
+
   // fold (mulhs x, 0) -> 0
   if (isNullConstant(N1))
     return N1;
   // fold (mulhs x, 1) -> (sra x, size(x)-1)
   if (isOneConstant(N1))
     return DAG.getNode(ISD::SRA, DL, N0.getValueType(), N0,
                        DAG.getConstant(N0.getScalarValueSizeInBits() - 1, DL,
                                        getShiftAmountTy(N0.getValueType())));
if (ISD::isConstantSplatVectorAllZeros(N0.getNode()) ||
         ISD::isConstantSplatVectorAllZeros(N1.getNode()))
       return DAG.getConstant(0, DL, VT);
   }
 
   // fold (mulhu c1, c2)
   if (SDValue C = DAG.FoldConstantArithmetic(ISD::MULHU, DL, VT, {N0, N1}))
     return C;
 
+  // canonicalize constant to RHS.
+  if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
+      !DAG.isConstantIntBuildVectorOrConstantInt(N1))
+    return DAG.getNode(ISD::MULHU, DL, N->getVTList(), N1, N0);
+
   // fold (mulhu x, 0) -> 0
   if (isNullConstant(N1))
     return N1;
   // fold (mulhu x, 1) -> 0
   if (isOneConstant(N1))
     return DAG.getConstant(0, DL, N0.getValueType());
   // fold (mulhu x, undef) -> 0
   if (N0.isUndef() || N1.isUndef())

llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll

 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s2
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s2
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s4, s8
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2

 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
 ; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v2, s2
-; GFX6-NEXT:    v_mul_hi_u32 v5, s2, v0
+; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s2
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v5, v0, s2
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, v0, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v4
 ; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v4
 ; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v5
 ; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v5
 ; GFX6-NEXT:    v_mul_lo_u32 v5, v2, v5

 ; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
 ; GFX6-NEXT:    s_mov_b32 s3, 0x12d8fb
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s3
-; GFX6-NEXT:    v_mul_hi_u32 v3, s3, v0
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s3
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s3
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s0, v4
 ; GFX6-NEXT:    v_mov_b32_e32 v3, s1
 ; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v3, v2, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s3, v4
 ; GFX6-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
 ; GFX6-NEXT:    s_mov_b32 s0, 0x12d8fa

 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
+; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s8
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s8
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s8
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v2, s8
-; GFX9-NEXT:    v_mul_hi_u32 v6, s8, v0
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, s8
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v0, s8
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
 ; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
 ; GFX9-NEXT:    v_sub_u32_e32 v4, v4, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v8

 ; GFX9-NEXT:    s_mov_b32 s3, 0x12d8fb
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s3
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s3
-; GFX9-NEXT:    v_mul_hi_u32 v3, s3, v0
+; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s3
 ; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, s0, v4
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s1
 ; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v3, v2, vcc
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s3, v4
 ; GFX9-NEXT:    v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc
 ; GFX9-NEXT:    s_mov_b32 s3, 0x12d8fa
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s3, v3

 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_ashr_i32 s0, s9, 31
 ; GFX6-NEXT:    s_lshr_b32 s0, s0, 20
-; GFX6-NEXT:    v_mul_hi_u32 v2, s6, v0
+; GFX6-NEXT:    v_mul_hi_u32 v2, v0, s6
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v1, s6
 ; GFX6-NEXT:    s_add_u32 s2, s8, s0
 ; GFX6-NEXT:    s_addc_u32 s3, s9, 0
 ; GFX6-NEXT:    s_ashr_i32 s8, s11, 31
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s6
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2

 ; GFX6-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
 ; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
 ; GFX6-NEXT:    v_mul_lo_u32 v5, v2, s6
-; GFX6-NEXT:    v_mul_hi_u32 v7, s6, v0
+; GFX6-NEXT:    v_mul_hi_u32 v7, v0, s6
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
 ; GFX6-NEXT:    v_mul_lo_u32 v7, v0, s6
 ; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, v0, v5
 ; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v5
 ; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v5
 ; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v7
 ; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v7
 ; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7

 ; GFX6-NEXT:    s_movk_i32 s9, 0xfff
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s9
-; GFX6-NEXT:    v_mul_hi_u32 v3, s9, v0
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s9
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s9
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s0, v4
 ; GFX6-NEXT:    v_mov_b32_e32 v3, s1
 ; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v3, v2, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s9, v4
 ; GFX6-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
 ; GFX6-NEXT:    s_movk_i32 s0, 0xffe

 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s2, s5, 31
 ; GFX9-NEXT:    s_lshr_b32 s2, s2, 20
-; GFX9-NEXT:    v_mul_hi_u32 v2, s8, v0
+; GFX9-NEXT:    v_mul_hi_u32 v2, v0, s8
 ; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s8
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s8
 ; GFX9-NEXT:    s_add_u32 s4, s4, s2
 ; GFX9-NEXT:    s_addc_u32 s5, s5, 0
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v5

 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v4, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v2, s8
-; GFX9-NEXT:    v_mul_hi_u32 v7, s8, v0
+; GFX9-NEXT:    v_mul_hi_u32 v7, v0, s8
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v0, s8
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
 ; GFX9-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
 ; GFX9-NEXT:    v_add_u32_e32 v5, v7, v5
 ; GFX9-NEXT:    v_sub_u32_e32 v5, v5, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v5

 ; GFX9-NEXT:    s_movk_i32 s3, 0xfff
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v5
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v4, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v6, v2, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s3
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s3
-; GFX9-NEXT:    v_mul_hi_u32 v3, s3, v0
+; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s3
 ; GFX9-NEXT:    v_sub_co_u32_e32 v5, vcc, s6, v5
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s7
 ; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v3, v2, vcc
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s3, v5
 ; GFX9-NEXT:    v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc
 ; GFX9-NEXT:    s_movk_i32 s3, 0xffe
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s3, v3

 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s2
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s2
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s4, s8
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2

 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
 ; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v2, s2
-; GFX6-NEXT:    v_mul_hi_u32 v5, s2, v0
+; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s2
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v5, v0, s2
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, v0, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v4
 ; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v4
 ; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v5
 ; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v5
 ; GFX6-NEXT:    v_mul_lo_u32 v5, v2, v5

 ; GFX6-NEXT:    v_mul_lo_u32 v4, s1, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
 ; GFX6-NEXT:    s_mov_b32 s3, 0x12d8fb
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
-; GFX6-NEXT:    v_mul_hi_u32 v2, s3, v0
+; GFX6-NEXT:    v_mul_hi_u32 v2, v0, s3
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s3
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s3
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
 ; GFX6-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v0
 ; GFX6-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v1, vcc

 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
+; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s8
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s8
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s8
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v2, s8
-; GFX9-NEXT:    v_mul_hi_u32 v6, s8, v0
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, s8
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v0, s8
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
 ; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
 ; GFX9-NEXT:    v_sub_u32_e32 v4, v4, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v8

 ; GFX9-NEXT:    v_mul_lo_u32 v4, s1, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s1, v0
 ; GFX9-NEXT:    s_mov_b32 s3, 0x12d8fb
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
-; GFX9-NEXT:    v_mul_hi_u32 v2, s3, v0
+; GFX9-NEXT:    v_mul_hi_u32 v2, v0, s3
 ; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s3
 ; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
 ; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
 ; GFX9-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, s0, v0
 ; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v2, v1, vcc
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s3, v0
 ; GFX9-NEXT:    v_subbrev_co_u32_e32 v3, vcc, 0, v1, vcc

llvm/test/CodeGen/AMDGPU/sdiv64.ll

 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
-; GCN-NEXT:    v_mul_hi_u32 v0, 24, v0
-; GCN-NEXT:    v_mul_hi_u32 v5, 24, v3
-; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
+; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
+; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
+; GCN-NEXT:    v_mov_b32_e32 v5, s9
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v5, vcc
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v3, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, 0, v0
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v2, s8, v1
 ; GCN-NEXT:    v_mul_hi_u32 v3, s8, v0
 ; GCN-NEXT:    v_mul_lo_u32 v4, s9, v0
-; GCN-NEXT:    v_mov_b32_e32 v5, s9
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GCN-NEXT:    v_mul_lo_u32 v3, s8, v0
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v2
 ; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 24, v3
 ; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
 ; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s8, v3
 ; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]

 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v12, vcc
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v7, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v4, v6, s[4:5]
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v4, 24
-; GCN-NEXT:    v_mul_hi_u32 v3, 24, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, 24, v4
-; GCN-NEXT:    v_mul_hi_u32 v4, 0, v4
+; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
+; GCN-NEXT:    v_mul_hi_u32 v4, v4, 24
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v13, v6, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v4, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, 0, v3
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v12, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v6, v0, v3
 ; GCN-NEXT:    v_mul_lo_u32 v7, v1, v3
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
 ; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
 ; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v5
 ; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 24, v6

 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v10, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v12, vcc
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v7, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v4, v6, s[4:5]
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    s_mov_b32 s4, 0x8000
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
-; GCN-NEXT:    v_mul_hi_u32 v3, s4, v3
-; GCN-NEXT:    v_mul_hi_u32 v5, s4, v4
-; GCN-NEXT:    v_lshlrev_b32_e32 v6, 15, v4
-; GCN-NEXT:    v_mul_hi_u32 v4, 0, v4
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v13, v5, vcc
+; GCN-NEXT:    v_lshrrev_b32_e32 v5, 17, v4
+; GCN-NEXT:    v_lshlrev_b32_e32 v4, 15, v4
+; GCN-NEXT:    v_lshrrev_b32_e32 v3, 17, v3
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v5, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, 0, v3
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v12, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v6, v0, v3
 ; GCN-NEXT:    v_mul_lo_u32 v7, v1, v3
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
 ; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
 ; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v5
-; GCN-NEXT:    v_sub_i32_e32 v6, vcc, s4, v6
+; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0x8000, v6
 ; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v7, v1, vcc
 ; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v6, v0
 ; GCN-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v1
 ; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
 ; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v1

llvm/test/CodeGen/AMDGPU/srem64.ll

 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
-; GCN-NEXT:    v_mul_hi_u32 v0, 24, v0
-; GCN-NEXT:    v_mul_hi_u32 v5, 24, v3
-; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
+; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
+; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v5, vcc
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v3, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, 0, v0
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, s8, v1
 ; GCN-NEXT:    v_mul_hi_u32 v2, s8, v0
 ; GCN-NEXT:    v_mul_lo_u32 v3, s9, v0
 ; GCN-NEXT:    v_mul_lo_u32 v0, s8, v0
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
 ; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
 ; GCN-NEXT:    v_mov_b32_e32 v3, s9

 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
 ; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
-; GCN-NEXT:    v_mul_hi_u32 v2, 24, v2
-; GCN-NEXT:    v_mul_hi_u32 v5, 24, v3
-; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
+; GCN-NEXT:    v_mul_hi_u32 v2, v2, 24
+; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v12, v5, vcc
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v12, v3, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, 0, v2
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v4, vcc
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v11, vcc
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v3, v0, v3
 ; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
 ; GCN-NEXT:    v_mul_lo_u32 v5, v1, v2
 ; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
 ; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 24, v2

 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
 ; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT:    s_mov_b32 s4, 0x8000
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; GCN-NEXT:    v_mul_hi_u32 v2, s4, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s4, v3
-; GCN-NEXT:    v_lshlrev_b32_e32 v5, 15, v3
-; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v12, v4, vcc
+; GCN-NEXT:    v_lshrrev_b32_e32 v4, 17, v3
+; GCN-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
+; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v12, v4, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, 0, v2
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v4, vcc
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v11, vcc
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v3, v0, v3
 ; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
 ; GCN-NEXT:    v_mul_lo_u32 v5, v1, v2
 ; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
-; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s4, v2
+; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0x8000, v2
 ; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
 ; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
 ; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
 ; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
 ; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1

llvm/test/CodeGen/AMDGPU/udiv64.ll

 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v5, s[2:3]
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
 ; GCN-NEXT:    v_mov_b32_e32 v3, s6
 ; GCN-NEXT:    v_alignbit_b32 v3, s7, v3, 24
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
-; GCN-NEXT:    v_mul_hi_u32 v5, v3, v1
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, v2
-; GCN-NEXT:    v_mul_hi_u32 v6, v3, v2
-; GCN-NEXT:    v_mul_hi_u32 v1, 0, v1
-; GCN-NEXT:    v_mul_hi_u32 v2, 0, v2
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v6, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, 0, v4
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v5, v1, vcc
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v8, vcc
+; GCN-NEXT:    v_mul_hi_u32 v1, v3, v1
+; GCN-NEXT:    v_mul_hi_u32 v2, v3, v2
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v9, v2, vcc
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, 0, v1
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v8, vcc
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, 0, v1
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v9, v2, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v0, v2
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v1
 ; GCN-NEXT:    v_mul_lo_u32 v6, v0, v1
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_sub_i32_e32 v3, vcc, v3, v6
 ; GCN-NEXT:    v_subb_u32_e32 v4, vcc, 0, v4, vcc
 ; GCN-NEXT:    v_sub_i32_e32 v5, vcc, v3, v0
 ; GCN-NEXT:    v_subbrev_u32_e32 v6, vcc, 0, v4, vcc
 ; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v6