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Differential D107447

[RISCV] Add tests covering shuffles which can be optimized
ClosedPublic

Authored by frasercrmck on Aug 4 2021, 5:04 AM.

Details

Reviewers
craig.topper
rogfer01
HsiangKai
khchen
evandro
Commits
rGb5c608c37775: [RISCV] Add tests covering shuffles which can be optimized
Summary

These shuffles all take the form of a "splat" of the LHS and/or RHS to
some degree, with one or two elements needing patched up afterwards. We
currently lower all of these to full LHS/RHS vector-index shuffles with
vrgather.vv.

Diff Detail

Event Timeline

frasercrmck created this revision.Aug 4 2021, 5:04 AM
Herald added subscribers: vkmr, luismarques, apazos and 21 others. · View Herald TranscriptAug 4 2021, 5:04 AM
frasercrmck requested review of this revision.Aug 4 2021, 5:04 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 4 2021, 5:04 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
frasercrmck added a child revision: D107449: [RISCV] Improve codegen for shuffles with LHS/RHS splats.Aug 4 2021, 5:05 AM
Harbormaster completed remote builds in B117874: Diff 364059.Aug 4 2021, 5:40 AM
craig.topper accepted this revision.Aug 6 2021, 11:45 AM

LGTM

This revision is now accepted and ready to land.Aug 6 2021, 11:45 AM
Closed by commit rGb5c608c37775: [RISCV] Add tests covering shuffles which can be optimized (authored by frasercrmck). · Explain WhyAug 9 2021, 2:30 AM
This revision was automatically updated to reflect the committed changes.
frasercrmck added a commit: rGb5c608c37775: [RISCV] Add tests covering shuffles which can be optimized.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
233 lines

Diff 365129

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

Show First 20 Lines • Show All 334 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, tu, mu
; CHECK-NEXT: vrgather.vv v8, v25, v26, v0.t ; CHECK-NEXT: vrgather.vv v8, v25, v26, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 0> %y = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
%z = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %z = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
%w = shufflevector <4 x i8> %y, <4 x i8> %z, <4 x i32> <i32 0, i32 4, i32 1, i32 5> %w = shufflevector <4 x i8> %y, <4 x i8> %z, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
ret <4 x i8> %w ret <4 x i8> %w
} }
define <8 x i8> @splat_ve4(<8 x i8> %v) {
; CHECK-LABEL: splat_ve4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vi v25, v8, 4
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
ret <8 x i8> %shuff
}
define <8 x i8> @splat_ve4_ins_i0ve2(<8 x i8> %v) {
; CHECK-LABEL: splat_ve4_ins_i0ve2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v26, 4
; CHECK-NEXT: addi a0, zero, 2
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, tu, mu
; CHECK-NEXT: vmv.s.x v26, a0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vv v25, v8, v26
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 2, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
ret <8 x i8> %shuff
}
define <8 x i8> @splat_ve4_ins_i1ve3(<8 x i8> %v) {
; CHECK-LABEL: splat_ve4_ins_i1ve3:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 3
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v25, a0
; CHECK-NEXT: vmv.v.i v26, 4
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v26, v25, 1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vv v25, v8, v26
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 4, i32 3, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
ret <8 x i8> %shuff
}
define <8 x i8> @splat_ve2_we0(<8 x i8> %v, <8 x i8> %w) {
; CHECK-LABEL: splat_ve2_we0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v26, 2
; CHECK-NEXT: vrgather.vv v25, v8, v26
; CHECK-NEXT: addi a0, zero, 66
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, tu, mu
; CHECK-NEXT: vrgather.vv v25, v9, v26, v0.t
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff
}
define <8 x i8> @splat_ve2_we0_ins_i0ve4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-LABEL: splat_ve2_we0_ins_i0ve4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v26, 2
; CHECK-NEXT: addi a0, zero, 4
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, tu, mu
; CHECK-NEXT: vmv.s.x v26, a0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vv v25, v8, v26
; CHECK-NEXT: addi a0, zero, 66
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, tu, mu
; CHECK-NEXT: vrgather.vv v25, v9, v26, v0.t
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 4, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff
}
define <8 x i8> @splat_ve2_we0_ins_i0we4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-LABEL: splat_ve2_we0_ins_i0we4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v26, 2
; CHECK-NEXT: vrgather.vv v25, v8, v26
; CHECK-NEXT: addi a0, zero, 67
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v26, 4
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; CHECK-NEXT: vrgather.vv v25, v9, v26, v0.t
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 12, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff
}
define <8 x i8> @splat_ve2_we0_ins_i2ve4(<8 x i8> %v, <8 x i8> %w) {
; RV32-LABEL: splat_ve2_we0_ins_i2ve4:
; RV32: # %bb.0:
; RV32-NEXT: lui a0, 8256
; RV32-NEXT: addi a0, a0, 514
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vmv.v.x v26, a0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vrgather.vv v25, v8, v26
; RV32-NEXT: addi a0, zero, 66
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmv.v.i v26, 0
; RV32-NEXT: vsetvli zero, zero, e8, mf2, tu, mu
; RV32-NEXT: vrgather.vv v25, v9, v26, v0.t
; RV32-NEXT: vmv1r.v v8, v25
; RV32-NEXT: ret
;
; RV64-LABEL: splat_ve2_we0_ins_i2ve4:
; RV64: # %bb.0:
; RV64-NEXT: lui a0, 8256
; RV64-NEXT: addiw a0, a0, 514
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vmv.v.x v26, a0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vrgather.vv v25, v8, v26
; RV64-NEXT: addi a0, zero, 66
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmv.v.i v26, 0
; RV64-NEXT: vsetvli zero, zero, e8, mf2, tu, mu
; RV64-NEXT: vrgather.vv v25, v9, v26, v0.t
; RV64-NEXT: vmv1r.v v8, v25
; RV64-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff
}
define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-LABEL: splat_ve2_we0_ins_i2we4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v26, 2
; CHECK-NEXT: vrgather.vv v25, v8, v26
; CHECK-NEXT: addi a0, zero, 4
; CHECK-NEXT: vmv.s.x v26, a0
; CHECK-NEXT: vmv.v.i v27, 0
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v27, v26, 2
; CHECK-NEXT: addi a0, zero, 70
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; CHECK-NEXT: vrgather.vv v25, v9, v27, v0.t
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 12, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff
}
define <8 x i8> @splat_ve2_we0_ins_i2ve4_i5we6(<8 x i8> %v, <8 x i8> %w) {
; RV32-LABEL: splat_ve2_we0_ins_i2ve4_i5we6:
; RV32: # %bb.0:
; RV32-NEXT: addi a0, zero, 6
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmv.s.x v25, a0
; RV32-NEXT: vmv.v.i v26, 0
; RV32-NEXT: vsetivli zero, 6, e8, mf2, tu, mu
; RV32-NEXT: vslideup.vi v26, v25, 5
; RV32-NEXT: lui a0, 8256
; RV32-NEXT: addi a0, a0, 2
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vmv.v.x v27, a0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vrgather.vv v25, v8, v27
; RV32-NEXT: addi a0, zero, 98
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; RV32-NEXT: vrgather.vv v25, v9, v26, v0.t
; RV32-NEXT: vmv1r.v v8, v25
; RV32-NEXT: ret
;
; RV64-LABEL: splat_ve2_we0_ins_i2ve4_i5we6:
; RV64: # %bb.0:
; RV64-NEXT: addi a0, zero, 6
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmv.s.x v25, a0
; RV64-NEXT: vmv.v.i v26, 0
; RV64-NEXT: vsetivli zero, 6, e8, mf2, tu, mu
; RV64-NEXT: vslideup.vi v26, v25, 5
; RV64-NEXT: lui a0, 8256
; RV64-NEXT: addiw a0, a0, 2
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vmv.v.x v27, a0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vrgather.vv v25, v8, v27
; RV64-NEXT: addi a0, zero, 98
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; RV64-NEXT: vrgather.vv v25, v9, v26, v0.t
; RV64-NEXT: vmv1r.v v8, v25
; RV64-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 2, i32 2, i32 14, i32 8, i32 2>
ret <8 x i8> %shuff
}
define <8 x i8> @widen_splat_ve3(<4 x i8> %v) {
; CHECK-LABEL: widen_splat_ve3:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v25, v8, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v25, v26, 4
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vi v8, v25, 3
; CHECK-NEXT: ret
%shuf = shufflevector <4 x i8> %v, <4 x i8> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
ret <8 x i8> %shuf
}