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Differential D106884

GlobalISel: Have lowerStore handle some unaligned stores
ClosedPublic

Authored by arsenm on Jul 27 2021, 8:50 AM.

Details

Reviewers
aemerson
paquette
dsanders
aditya_nandakumar
bogner
Summary

This is NFC until some of the AMDGPU legalization rules are ripped
out.

Diff Detail

Revision Contents

PathSize
llvm/
lib/
CodeGen/
GlobalISel/
31 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
44 lines

Diff 362183

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,050 Lines • ▼ Show 20 Lines if (StoreWidth != StoreSizeInBits) {
MachineMemOperand *NewMMO = MachineMemOperand *NewMMO =
MF.getMachineMemOperand(&MMO, MMO.getPointerInfo(), WideTy); MF.getMachineMemOperand(&MMO, MMO.getPointerInfo(), WideTy);
MIRBuilder.buildStore(ZextInReg, PtrReg, *NewMMO); MIRBuilder.buildStore(ZextInReg, PtrReg, *NewMMO);
StoreMI.eraseFromParent(); StoreMI.eraseFromParent();
return Legalized; return Legalized;
} }
if (isPowerOf2_32(MemTy.getSizeInBits())) unsigned MemSizeInBits = MemTy.getSizeInBits();
uint64_t LargeSplitSize, SmallSplitSize;
if (!isPowerOf2_32(MemSizeInBits)) {
LargeSplitSize = PowerOf2Floor(MemTy.getSizeInBits());
SmallSplitSize = MemTy.getSizeInBits() - LargeSplitSize;
} else {
auto &Ctx = MF.getFunction().getContext();
if (TLI.allowsMemoryAccess(Ctx, MIRBuilder.getDataLayout(), MemTy, MMO))
return UnableToLegalize; // Don't know what we're being asked to do. return UnableToLegalize; // Don't know what we're being asked to do.
SmallSplitSize = LargeSplitSize = MemSizeInBits / 2;
}
// Extend to the next pow-2. If this store was itself the result of lowering, // Extend to the next pow-2. If this store was itself the result of lowering,
// e.g. an s56 store being broken into s32 + s24, we might have a stored type // e.g. an s56 store being broken into s32 + s24, we might have a stored type
// that's wider the stored size. // that's wider than the stored size.
const LLT NewSrcTy = LLT::scalar(NextPowerOf2(MemTy.getSizeInBits())); unsigned AnyExtSize = PowerOf2Ceil(SrcTy.getSizeInBits());
const LLT NewSrcTy = LLT::scalar(AnyExtSize);
if (SrcTy.isPointer()) {
const LLT IntPtrTy = LLT::scalar(SrcTy.getSizeInBits());
SrcReg = MIRBuilder.buildPtrToInt(IntPtrTy, SrcReg).getReg(0);
}
auto ExtVal = MIRBuilder.buildAnyExtOrTrunc(NewSrcTy, SrcReg); auto ExtVal = MIRBuilder.buildAnyExtOrTrunc(NewSrcTy, SrcReg);
// Obtain the smaller value by shifting away the larger value. // Obtain the smaller value by shifting away the larger value.
uint64_t LargeSplitSize = PowerOf2Floor(MemTy.getSizeInBits());
uint64_t SmallSplitSize = MemTy.getSizeInBits() - LargeSplitSize;
auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, LargeSplitSize); auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, LargeSplitSize);
auto SmallVal = MIRBuilder.buildLShr(NewSrcTy, ExtVal, ShiftAmt); auto SmallVal = MIRBuilder.buildLShr(NewSrcTy, ExtVal, ShiftAmt);
// Generate the PtrAdd and truncating stores. // Generate the PtrAdd and truncating stores.
LLT PtrTy = MRI.getType(PtrReg); LLT PtrTy = MRI.getType(PtrReg);
auto OffsetCst = MIRBuilder.buildConstant( auto OffsetCst = MIRBuilder.buildConstant(
LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8); LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8);
Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
auto SmallPtr = auto SmallPtr =
MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst); MIRBuilder.buildPtrAdd(PtrTy, PtrReg, OffsetCst);
MachineMemOperand *LargeMMO = MachineMemOperand *LargeMMO =
MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8); MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
MachineMemOperand *SmallMMO = MachineMemOperand *SmallMMO =
MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8); MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8);
MIRBuilder.buildStore(ExtVal, PtrReg, *LargeMMO); MIRBuilder.buildStore(ExtVal, PtrReg, *LargeMMO);
MIRBuilder.buildStore(SmallVal, SmallPtr, *SmallMMO); MIRBuilder.buildStore(SmallVal, SmallPtr, *SmallMMO);
StoreMI.eraseFromParent(); StoreMI.eraseFromParent();
▲ Show 20 Lines • Show All 4,237 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 820 Lines • ▼ Show 20 Lines bb.0:
; SI: G_STORE [[ANYEXT]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1) ; SI: G_STORE [[ANYEXT]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64) ; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32) ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; SI: G_STORE [[COPY9]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1) ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; CI-LABEL: name: test_store_global_s48_align1 ; CI-LABEL: name: test_store_global_s48_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 ; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; CI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; CI: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64) ; CI: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; CI: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY2]](s64) ; CI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY3]], [[C]](s32) ; CI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C]](s32)
; CI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64) ; CI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; CI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64) ; CI: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s32), align 1, addrspace 1)
; CI: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store (s32), align 1, addrspace 1) ; CI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, align 1, addrspace 1)
; CI: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; CI: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, align 1, addrspace 1)
; VI-LABEL: name: test_store_global_s48_align1 ; VI-LABEL: name: test_store_global_s48_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 ; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; VI: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64) ; VI: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; VI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY2]](s64), 0 ; VI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY2]](s64), 0
; VI: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64) ; VI: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; VI: [[EXTRACT1:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY3]](s64), 32 ; VI: [[EXTRACT1:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY3]](s64), 32
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
Show All 24 Lines bb.0:
; VI: G_STORE [[ANYEXT]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1) ; VI: G_STORE [[ANYEXT]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64) ; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
; VI: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR3]](s16) ; VI: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR3]](s16)
; VI: G_STORE [[ANYEXT1]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1) ; VI: G_STORE [[ANYEXT1]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; GFX9-LABEL: name: test_store_global_s48_align1 ; GFX9-LABEL: name: test_store_global_s48_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64) ; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; GFX9: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY2]](s64) ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY3]], [[C]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; GFX9: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64) ; GFX9: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64) ; GFX9: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s32), align 1, addrspace 1)
; GFX9: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store (s32), align 1, addrspace 1) ; GFX9: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, align 1, addrspace 1)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; GFX9: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, align 1, addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1 %0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3 %1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s48) = G_TRUNC %1 %2:_(s48) = G_TRUNC %1
G_STORE %2, %0 :: (store (s48), align 1, addrspace 1) G_STORE %2, %0 :: (store (s48), align 1, addrspace 1)
... ...
--- ---
name: test_store_global_s48_align2 name: test_store_global_s48_align2
Show All 19 Lines bb.0:
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64) ; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT1]](s16) ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT1]](s16)
; SI: G_STORE [[ANYEXT]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1) ; SI: G_STORE [[ANYEXT]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; CI-LABEL: name: test_store_global_s48_align2 ; CI-LABEL: name: test_store_global_s48_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 ; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; CI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; CI: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64) ; CI: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; CI: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY2]](s64) ; CI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY3]], [[C]](s32) ; CI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C]](s32)
; CI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64) ; CI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; CI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64) ; CI: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s32), align 2, addrspace 1)
; CI: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store (s32), align 2, addrspace 1) ; CI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; CI: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; CI: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI-LABEL: name: test_store_global_s48_align2 ; VI-LABEL: name: test_store_global_s48_align2
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 ; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; VI: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64) ; VI: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; VI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY2]](s64), 0 ; VI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY2]](s64), 0
; VI: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64) ; VI: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; VI: [[EXTRACT1:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY3]](s64), 32 ; VI: [[EXTRACT1:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY3]](s64), 32
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT]], [[C]](s32) ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT]], [[C]](s32)
; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32) ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
; VI: G_STORE [[COPY4]](s32), [[COPY]](p1) :: (store (s16), addrspace 1) ; VI: G_STORE [[COPY4]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 ; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64) ; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; VI: G_STORE [[COPY5]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1) ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64) ; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT1]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT1]](s16)
; VI: G_STORE [[ANYEXT]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1) ; VI: G_STORE [[ANYEXT]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; GFX9-LABEL: name: test_store_global_s48_align2 ; GFX9-LABEL: name: test_store_global_s48_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64) ; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; GFX9: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY2]](s64) ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY3]], [[C]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; GFX9: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64) ; GFX9: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64) ; GFX9: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s32), align 2, addrspace 1)
; GFX9: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store (s32), align 2, addrspace 1) ; GFX9: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; GFX9: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1 %0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3 %1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s48) = G_TRUNC %1 %2:_(s48) = G_TRUNC %1
G_STORE %2, %0 :: (store (s48), align 2, addrspace 1) G_STORE %2, %0 :: (store (s48), align 2, addrspace 1)
... ...
# --- # ---
# name: test_store_global_s48_align4 # name: test_store_global_s48_align4
▲ Show 20 Lines • Show All 7,733 Lines • Show Last 20 Lines