[AMDGPU] Legalize operands of V_ADDC_U32_e32 and friends

[foad]

Summary

These instructions have an implicit use of vcc which counts towards the
constant bus limit. Pre gfx10 this means that the explicit operands
cannot be sgprs. Use the custom inserter hook to call legalizeOperands
to enforce that restriction.

Fixes https://bugs.llvm.org/show_bug.cgi?id=51217

[foad]

The patch attached to https://bugs.llvm.org/show_bug.cgi?id=51217 tests this. I'm not sure how else to test it, because normally 64-bit add/sub gets selected to a pseudo, which is expanded to add_co/addc by some code in EmitInstrWithCustomInserter which already calls legalizeOperands on the addc.

[arsenm]

Can you test this with the carry out intrinsics?

[foad]

In D106868#2907193, @arsenm wrote:

Can you test this with the carry out intrinsics?

I don't think so because it only affects the carry-in instructions.

[arsenm]

In D106868#2907206, @foad wrote:

In D106868#2907193, @arsenm wrote:

Can you test this with the carry out intrinsics?

I don't think so because it only affects the carry-in instructions.

If you have a wider carry out intrinsic (e.g. i128) it should need legalization involving carry in

[foad]

Add a test case that fails verification without this fix.

[RKSimon]

Any objections? This is currently blocking D106471.

[rampitec]

LGTM

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

case AMDGPU::V_SUBREV_CO_U32_e32: {
     if (NeedClampOperand)
       I.addImm(0); // clamp bit for e64 encoding
 
     TII->legalizeOperands(*I);
 
     MI.eraseFromParent();
     return BB;
   }
+  case AMDGPU::V_ADDC_U32_e32:
+  case AMDGPU::V_SUBB_U32_e32:
+  case AMDGPU::V_SUBBREV_U32_e32:
+    // These instructions have an implicit use of vcc which counts towards the
+    // constant bus limit.
+    TII->legalizeOperands(MI);
+    return BB;
   case AMDGPU::DS_GWS_INIT:
   case AMDGPU::DS_GWS_SEMA_BR:
   case AMDGPU::DS_GWS_BARRIER:
     if (Subtarget->needsAlignedVGPRs()) {
       // Add implicit aligned super-reg to force alignment on the data operand.
       const DebugLoc &DL = MI.getDebugLoc();
       MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
       const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();

llvm/lib/Target/AMDGPU/VOP2Instructions.td

multiclass VOP2bInst <string opName,
                       string revOp = opName,
                       bit GFX9Renamed = 0,
                       bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
   let renamedInGFX9 = GFX9Renamed in {
     let SchedRW = [Write32Bit, WriteSALU] in {
       let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
         def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
                    Commutable_REV<revOp#"_e32", !eq(revOp, opName)> {
-          let usesCustomInserter = !eq(P.NumSrcArgs, 2);
+          let usesCustomInserter = true;
         }
 
         foreach _ = BoolToList<P.HasExtSDWA>.ret in
           def _sdwa  : VOP2_SDWA_Pseudo <opName, P> {
             let AsmMatchConverter = "cvtSdwaVOP2b";
           }
         foreach _ = BoolToList<P.HasExtDPP>.ret in
           def _dpp  : VOP2_DPP_Pseudo <opName, P>;