[AArch64] Implement floating point subreg copies

[paquette]

llvm/test/CodeGen/AArch64/GlobalISel/postrapseudos-fmov-fp-subreg.mir

1

This test should probably be under llvm/test/CodeGen/AArch64, not under GlobalISel.

[jroelofs]

move test. support all of {hsdq}x{hsdq}

[jroelofs]

The motivating case for this turned out to be a bug in selection of G_UNMERGE_VALUES.

See: https://reviews.llvm.org/D105935

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

   if (SrcReg == AArch64::NZCV) {
     assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy");
     BuildMI(MBB, I, DL, get(AArch64::MRS), DestReg)
         .addImm(AArch64SysReg::NZCV)
         .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc));
     return;
   }
 
-#ifndef NDEBUG
   const TargetRegisterInfo &TRI = getRegisterInfo();
+  if (AArch64::FPR64RegClass.contains(DestReg) &&
+      AArch64::FPR32RegClass.contains(SrcReg)) {
+    DestReg = TRI.getSubReg(DestReg, AArch64::ssub);
+    BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
+      .addReg(SrcReg, getKillRegState(KillSrc));
+    return;
+  }
+
+  if ((AArch64::FPR64RegClass.contains(DestReg) ||
+       AArch64::FPR32RegClass.contains(DestReg)) &&
+      AArch64::FPR16RegClass.contains(SrcReg)) {
+    DestReg = TRI.getSubReg(DestReg, AArch64::hsub);
+    BuildMI(MBB, I, DL, get(AArch64::FMOVHr), DestReg)
+      .addReg(SrcReg, getKillRegState(KillSrc));
+    return;
+  }
+
+#ifndef NDEBUG
   errs() << TRI.getRegAsmName(DestReg) << " = COPY "
          << TRI.getRegAsmName(SrcReg) << "\n";
 #endif
   llvm_unreachable("unimplemented reg-to-reg copy");
 }
 
 static void storeRegPairToStackSlot(const TargetRegisterInfo &TRI,
                                     MachineBasicBlock &MBB,

llvm/test/CodeGen/AArch64/GlobalISel/postrapseudos-fmov-fp-subreg.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc < %s -run-pass=postrapseudos -mtriple=arm64-apple-ios -o - | FileCheck %s
+
+...
+---
+name:            fmov_d0_s0
+tracksRegLiveness: true
+liveins:
+  - { reg: '$s0' }
+body:             |
+  bb.0:
+    liveins: $s0
+
+    ; CHECK-LABEL: name: fmov_d0_s0
+    ; CHECK: liveins: $s0
+    ; CHECK: $s0 = FMOVSr $s0, implicit killed $d0, implicit-def $q0
+    ; CHECK: RET_ReallyLR
+    renamable $d0 = COPY renamable $s0, implicit killed $d0, implicit-def $q0
+    RET_ReallyLR
+
+...
+---
+name:            fmov_d0_h0
+tracksRegLiveness: true
+liveins:
+  - { reg: '$h0' }
+body:             |
+  bb.0:
+    liveins: $h0
+
+    ; CHECK-LABEL: name: fmov_d0_h0
+    ; CHECK: liveins: $h0
+    ; CHECK: $h0 = FMOVHr $h0, implicit killed $d0, implicit-def $q0
+    ; CHECK: RET_ReallyLR
+    renamable $d0 = COPY renamable $h0, implicit killed $d0, implicit-def $q0
+    RET_ReallyLR
+
+...
+---
+name:            fmov_s0_h0
+tracksRegLiveness: true
+liveins:
+  - { reg: '$h0' }
+body:             |
+  bb.0:
+    liveins: $h0
+
+    ; CHECK-LABEL: name: fmov_s0_h0
+    ; CHECK: liveins: $h0
+    ; CHECK: $h0 = FMOVHr $h0, implicit killed $s0, implicit-def $q0
+    ; CHECK: RET_ReallyLR
+    renamable $s0 = COPY renamable $h0, implicit killed $s0, implicit-def $q0
+    RET_ReallyLR