[PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

[NeHuang]

Summary

This patch is in a series of patches to provide builtins for compatibility
with the XL compiler. This patch add the builtin and emit target independent
code for __cmpb.

Backend test case (IR) emitting the single instruction cmpb (llvm/test/CodeGen/PowerPC/cmpb.ll)

; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux-gnu -mcpu pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu pwr7 -vec-extabi < %s | FileCheck %s

define i64 @test64(i64 %x, i64 %y) #0 {
; CHECK-LABEL: test64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    cmpb 3, 3, 4
; CHECK-NEXT:    blr
entry:
  %shr19 = lshr i64 %x, 56
  %conv21 = trunc i64 %shr19 to i32
  %shr43 = lshr i64 %y, 56
  %conv45 = trunc i64 %shr43 to i32
  %0 = xor i64 %y, %x
  %1 = and i64 %0, 255
  %cmp = icmp eq i64 %1, 0
  %2 = and i64 %0, 65280
  %cmp52 = icmp eq i64 %2, 0
  %3 = and i64 %0, 16711680
  %cmp58 = icmp eq i64 %3, 0
  %4 = and i64 %0, 4278190080
  %cmp64 = icmp eq i64 %4, 0
  %5 = and i64 %0, 1095216660480
  %cmp70 = icmp eq i64 %5, 0
  %6 = and i64 %0, 280375465082880
  %cmp76 = icmp eq i64 %6, 0
  %7 = and i64 %0, 71776119061217280
  %cmp82 = icmp eq i64 %7, 0
  %cmp88 = icmp eq i32 %conv21, %conv45
  %conv92 = select i1 %cmp, i64 255, i64 0
  %conv93 = select i1 %cmp52, i64 65280, i64 0
  %or = or i64 %conv92, %conv93
  %conv95 = select i1 %cmp58, i64 16711680, i64 0
  %or97 = or i64 %or, %conv95
  %conv98 = select i1 %cmp64, i64 4278190080, i64 0
  %or100 = or i64 %or97, %conv98
  %conv101 = select i1 %cmp70, i64 1095216660480, i64 0
  %or103 = or i64 %or100, %conv101
  %conv104 = select i1 %cmp76, i64 280375465082880, i64 0
  %or106 = or i64 %or103, %conv104
  %conv107 = select i1 %cmp82, i64 71776119061217280, i64 0
  %or109 = or i64 %or106, %conv107
  %conv110 = select i1 %cmp88, i64 -72057594037927936, i64 0
  %or112 = or i64 %or109, %conv110
  ret i64 %or112
}

[NeHuang]

gentle ping

[NeHuang]

Remove entry check in test case.

[nemanjai]

Also if we are going to be emitting this complex sequence, in the description of the patch, point out the test case that shows the back end handles this and emits a single instruction.

clang/lib/CodeGen/CGBuiltin.cpp

15081

I find it rather surprising that we are emitting this complex sequence for this builtin. Perhaps there is a good reason for doing so, but at the very least, this requires a thorough explanation in a comment.

One additional concern I have with this is that if some transformation proves that some portion of this is unused (perhaps using DemandedBits analysis), it may optimize out a portion of this, thereby making the sequence emit a whole bunch of xor's, or's, rotates, etc.

For example:

...
unsigned long long A = __builtin_ppc_cmpb(B, C);
return A & 0xFF00FF00FF00FF;

It is entirely possible that the optimizer will get rid of some of the produced instructions and then the back end won't be able to emit a single cmpb but will have to emit a whole bunch of scalar instructions.

[NeHuang]

clang/lib/CodeGen/CGBuiltin.cpp

15081

• The backend test case define i64 @test64(i64 %x, i64 %y) is in llvm/test/CodeGen/PowerPC/cmpb.ll
• Also Tried the test case and results look fine.

$ cat test_cmpb.c
long long test_cmpb(long long a, long long b) {
  //return __cmpb(a, b);
  unsigned long long A = __builtin_ppc_cmpb(a, b);
  return A & 0xFF00FF00FF00FF;
}
$ clang -cc1 -O3 -triple powerpc-unknown-aix test_cmpb.c -target-cpu pwr9 -S -o test_cmpb_32bit.s
...
.test_cmpb:
# %bb.0:                                # %entry
        cmpb 4, 6, 4
        lis 6, 255
        cmpb 3, 5, 3
        ori 6, 6, 255
        and 4, 4, 6
        and 3, 3, 6
        blr
$ clang -cc1 -O3 -triple powerpc64-unknown-aix test_cmpb.c -target-cpu pwr9 -S -o test_cmpb_64bit.s
.test_cmpb:
# %bb.0:                                # %entry
        cmpb 3, 4, 3
        lis 4, 255
        ori 4, 4, 255
        rldimi 4, 4, 32, 0
        and 3, 3, 4
        blr

[NeHuang]

clang/lib/CodeGen/CGBuiltin.cpp

15081

The intension of emitting this complex sequence for this builtin is to produce the target independent code matching the backend test case IR (in the description) and produce asm results matching xlc. Verified the target IR will produce expected asm results for 32 bit and 64 bit.

• For 64 bit

cmpb 3, 3, 4
blr

• For 32 bit

cmpb 4, 6, 4
cmpb 3, 5, 3
blr

[NeHuang]

Address review comment to rework 32 bit handling.

[nemanjai]

Mostly minor comments, but it'll be good to have another look to make sure they're all addressed.

clang/lib/CodeGen/CGBuiltin.cpp

15101

Nit: no else after return.

15104

These comments are superfluous. You have the entire sequence listed above, no need to repeat it piece-wise here.

15105

Please do not name variables with non-descriptive single letters. It is somewhat conventional to use suffixes such as Hi/Lo for high/low order parts of a value.

llvm/include/llvm/IR/IntrinsicsPowerPC.td

1537 ↗

(On Diff #359467)

Line too long?

[NeHuang]

Address review comments from Nemanja.

[NeHuang]

Rebased the patch with ToT.

[NeHuang]

clang-format

[nemanjai]

LGTM. Thank you.

[jroelofs]

I moved a couple of new tests from this patch from CodeGen -> CodeGen/PowerPC so they don't fail when the PPC backend isn't built: f6769b663a0d4432b5e00e0c03904a5dfba7b077

[NeHuang]

Thanks @jroelofs for moving the test cases! Those cases were added in https://reviews.llvm.org/D105946 and I have notified the author.

clang/include/clang/Basic/BuiltinsPPC.def

 BUILTIN(__builtin_ppc_dcbt, "vv*", "")
 BUILTIN(__builtin_ppc_dcbtst, "vv*", "")
 BUILTIN(__builtin_ppc_dcbz, "vv*", "")
 BUILTIN(__builtin_ppc_icbt, "vv*", "")
 // Compare
 BUILTIN(__builtin_ppc_cmpeqb, "LLiLLiLLi", "")
 BUILTIN(__builtin_ppc_cmprb, "iCiii", "")
 BUILTIN(__builtin_ppc_setb, "LLiLLiLLi", "")
+BUILTIN(__builtin_ppc_cmpb, "LLiLLiLLi", "")
 // Multiply
 BUILTIN(__builtin_ppc_mulhd, "LLiLiLi", "")
 BUILTIN(__builtin_ppc_mulhdu, "ULLiULiULi", "")
 BUILTIN(__builtin_ppc_mulhw, "iii", "")
 BUILTIN(__builtin_ppc_mulhwu, "UiUiUi", "")
 BUILTIN(__builtin_ppc_maddhd, "LLiLLiLLiLLi", "")
 BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "")
 BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "")

clang/lib/Basic/Targets/PPC.cpp

static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__dcbst", "__builtin_ppc_dcbst");
   Builder.defineMacro("__dcbt", "__builtin_ppc_dcbt");
   Builder.defineMacro("__dcbtst", "__builtin_ppc_dcbtst");
   Builder.defineMacro("__dcbz", "__builtin_ppc_dcbz");
   Builder.defineMacro("__icbt", "__builtin_ppc_icbt");
   Builder.defineMacro("__cmpeqb", "__builtin_ppc_cmpeqb");
   Builder.defineMacro("__cmprb", "__builtin_ppc_cmprb");
   Builder.defineMacro("__setb", "__builtin_ppc_setb");
+  Builder.defineMacro("__cmpb", "__builtin_ppc_cmpb");
   Builder.defineMacro("__mulhd", "__builtin_ppc_mulhd");
   Builder.defineMacro("__mulhdu", "__builtin_ppc_mulhdu");
   Builder.defineMacro("__mulhw", "__builtin_ppc_mulhw");
   Builder.defineMacro("__mulhwu", "__builtin_ppc_mulhwu");
   Builder.defineMacro("__maddhd", "__builtin_ppc_maddhd");
   Builder.defineMacro("__maddhdu", "__builtin_ppc_maddhdu");
   Builder.defineMacro("__maddld", "__builtin_ppc_maddld");
   Builder.defineMacro("__rlwnm", "__builtin_ppc_rlwnm");

clang/lib/CodeGen/CGBuiltin.cpp

case PPC::BI__builtin_ppc_rlwimi: {
     return Builder.CreateOr(X, Y);
   }
   case PPC::BI__builtin_ppc_rlwnm: {
     llvm::Type *Ty = Ops[0]->getType();
     Function *F = CGM.getIntrinsic(Intrinsic::fshl, Ty);
     Value *shift = Builder.CreateCall(F, {Ops[0], Ops[0], Ops[1]});
     return Builder.CreateAnd(shift, Ops[2]);
   }
+  case PPC::BI__builtin_ppc_cmpb: {
+    llvm::Type *Ty = Ops[0]->getType();
+    Value *Zero = Constant::getNullValue(Ty);
+    Value *Res = Constant::getNullValue(Ty);
+    Value *X = Builder.CreateXor(Ops[0], Ops[1]);
+    for (int i = 0; i < 8; i++) {
+      int64_t Mask = (int64_t)0xff << i * 8;
+      Value *Cmp = Builder.CreateICmpEQ(
+          Builder.CreateAnd(X, ConstantInt::getSigned(Ty, Mask)), Zero);
+      Value *Select =
+          Builder.CreateSelect(Cmp, ConstantInt::getSigned(Ty, Mask), Zero);
+      Res = Builder.CreateOr(Res, Select);
+    }
+    return Res;
+  }
   // Copy sign
   case PPC::BI__builtin_vsx_xvcpsgnsp:
   case PPC::BI__builtin_vsx_xvcpsgndp: {
     llvm::Type *ResultType = ConvertType(E->getType());
     Value *X = EmitScalarExpr(E->getArg(0));
     Value *Y = EmitScalarExpr(E->getArg(1));
     ID = Intrinsic::copysign;
     llvm::Function *F = CGM.getIntrinsic(ID, ResultType);
     return Builder.CreateCall(F, {X, Y});
   }
   // Rounding/truncation
   case PPC::BI__builtin_vsx_xvrspip:
   case PPC::BI__builtin_vsx_xvrdpip:
   case PPC::BI__builtin_vsx_xvrdpim:
   case PPC::BI__builtin_vsx_xvrspim:
   case PPC::BI__builtin_vsx_xvrdpi:
   case PPC::BI__builtin_vsx_xvrspi:
   case PPC::BI__builtin_vsx_xvrdpic:

clang/test/CodeGen/builtins-ppc-xlcompat-compare.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+// CHECK-LABEL: @test_builtin_ppc_cmpb(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[LLA_ADDR:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    [[LLB_ADDR:%.*]] = alloca i64, align 8
+// CHECK-NEXT:    store i64 [[LLA:%.*]], i64* [[LLA_ADDR]], align 8
+// CHECK-NEXT:    store i64 [[LLB:%.*]], i64* [[LLB_ADDR]], align 8
+// CHECK-NEXT:    [[TMP0:%.*]] = load i64, i64* [[LLA_ADDR]], align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load i64, i64* [[LLB_ADDR]], align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = xor i64 [[TMP0]], [[TMP1]]
+// CHECK-NEXT:    [[TMP3:%.*]] = and i64 [[TMP2]], 255
+// CHECK-NEXT:    [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 0
+// CHECK-NEXT:    [[TMP5:%.*]] = select i1 [[TMP4]], i64 255, i64 0
+// CHECK-NEXT:    [[TMP6:%.*]] = or i64 0, [[TMP5]]
+// CHECK-NEXT:    [[TMP7:%.*]] = and i64 [[TMP2]], 65280
+// CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 0
+// CHECK-NEXT:    [[TMP9:%.*]] = select i1 [[TMP8]], i64 65280, i64 0
+// CHECK-NEXT:    [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]]
+// CHECK-NEXT:    [[TMP11:%.*]] = and i64 [[TMP2]], 16711680
+// CHECK-NEXT:    [[TMP12:%.*]] = icmp eq i64 [[TMP11]], 0
+// CHECK-NEXT:    [[TMP13:%.*]] = select i1 [[TMP12]], i64 16711680, i64 0
+// CHECK-NEXT:    [[TMP14:%.*]] = or i64 [[TMP10]], [[TMP13]]
+// CHECK-NEXT:    [[TMP15:%.*]] = and i64 [[TMP2]], 4278190080
+// CHECK-NEXT:    [[TMP16:%.*]] = icmp eq i64 [[TMP15]], 0
+// CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i64 4278190080, i64 0
+// CHECK-NEXT:    [[TMP18:%.*]] = or i64 [[TMP14]], [[TMP17]]
+// CHECK-NEXT:    [[TMP19:%.*]] = and i64 [[TMP2]], 1095216660480
+// CHECK-NEXT:    [[TMP20:%.*]] = icmp eq i64 [[TMP19]], 0
+// CHECK-NEXT:    [[TMP21:%.*]] = select i1 [[TMP20]], i64 1095216660480, i64 0
+// CHECK-NEXT:    [[TMP22:%.*]] = or i64 [[TMP18]], [[TMP21]]
+// CHECK-NEXT:    [[TMP23:%.*]] = and i64 [[TMP2]], 280375465082880
+// CHECK-NEXT:    [[TMP24:%.*]] = icmp eq i64 [[TMP23]], 0
+// CHECK-NEXT:    [[TMP25:%.*]] = select i1 [[TMP24]], i64 280375465082880, i64 0
+// CHECK-NEXT:    [[TMP26:%.*]] = or i64 [[TMP22]], [[TMP25]]
+// CHECK-NEXT:    [[TMP27:%.*]] = and i64 [[TMP2]], 71776119061217280
+// CHECK-NEXT:    [[TMP28:%.*]] = icmp eq i64 [[TMP27]], 0
+// CHECK-NEXT:    [[TMP29:%.*]] = select i1 [[TMP28]], i64 71776119061217280, i64 0
+// CHECK-NEXT:    [[TMP30:%.*]] = or i64 [[TMP26]], [[TMP29]]
+// CHECK-NEXT:    [[TMP31:%.*]] = and i64 [[TMP2]], -72057594037927936
+// CHECK-NEXT:    [[TMP32:%.*]] = icmp eq i64 [[TMP31]], 0
+// CHECK-NEXT:    [[TMP33:%.*]] = select i1 [[TMP32]], i64 -72057594037927936, i64 0
+// CHECK-NEXT:    [[TMP34:%.*]] = or i64 [[TMP30]], [[TMP33]]
+// CHECK-NEXT:    ret i64 [[TMP34]]
+//
+long long test_builtin_ppc_cmpb(long long lla, long long llb) {
+  return __builtin_ppc_cmpb(lla, llb);
+}