[PowerPC] Add PowerPC cmpb builtin and emit target indepedent code for XL compatibility

[NeHuang]

Summary

This patch is in a series of patches to provide builtins for compatibility
with the XL compiler. This patch add the builtin and emit target independent
code for __cmpb.

Backend test case (IR) emitting the single instruction cmpb (llvm/test/CodeGen/PowerPC/cmpb.ll)

; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux-gnu -mcpu pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu pwr7 -vec-extabi < %s | FileCheck %s

define i64 @test64(i64 %x, i64 %y) #0 {
; CHECK-LABEL: test64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    cmpb 3, 3, 4
; CHECK-NEXT:    blr
entry:
  %shr19 = lshr i64 %x, 56
  %conv21 = trunc i64 %shr19 to i32
  %shr43 = lshr i64 %y, 56
  %conv45 = trunc i64 %shr43 to i32
  %0 = xor i64 %y, %x
  %1 = and i64 %0, 255
  %cmp = icmp eq i64 %1, 0
  %2 = and i64 %0, 65280
  %cmp52 = icmp eq i64 %2, 0
  %3 = and i64 %0, 16711680
  %cmp58 = icmp eq i64 %3, 0
  %4 = and i64 %0, 4278190080
  %cmp64 = icmp eq i64 %4, 0
  %5 = and i64 %0, 1095216660480
  %cmp70 = icmp eq i64 %5, 0
  %6 = and i64 %0, 280375465082880
  %cmp76 = icmp eq i64 %6, 0
  %7 = and i64 %0, 71776119061217280
  %cmp82 = icmp eq i64 %7, 0
  %cmp88 = icmp eq i32 %conv21, %conv45
  %conv92 = select i1 %cmp, i64 255, i64 0
  %conv93 = select i1 %cmp52, i64 65280, i64 0
  %or = or i64 %conv92, %conv93
  %conv95 = select i1 %cmp58, i64 16711680, i64 0
  %or97 = or i64 %or, %conv95
  %conv98 = select i1 %cmp64, i64 4278190080, i64 0
  %or100 = or i64 %or97, %conv98
  %conv101 = select i1 %cmp70, i64 1095216660480, i64 0
  %or103 = or i64 %or100, %conv101
  %conv104 = select i1 %cmp76, i64 280375465082880, i64 0
  %or106 = or i64 %or103, %conv104
  %conv107 = select i1 %cmp82, i64 71776119061217280, i64 0
  %or109 = or i64 %or106, %conv107
  %conv110 = select i1 %cmp88, i64 -72057594037927936, i64 0
  %or112 = or i64 %or109, %conv110
  ret i64 %or112
}

[NeHuang]

gentle ping

[NeHuang]

Remove entry check in test case.

[nemanjai]

Also if we are going to be emitting this complex sequence, in the description of the patch, point out the test case that shows the back end handles this and emits a single instruction.

clang/lib/CodeGen/CGBuiltin.cpp

15081

I find it rather surprising that we are emitting this complex sequence for this builtin. Perhaps there is a good reason for doing so, but at the very least, this requires a thorough explanation in a comment.

One additional concern I have with this is that if some transformation proves that some portion of this is unused (perhaps using DemandedBits analysis), it may optimize out a portion of this, thereby making the sequence emit a whole bunch of xor's, or's, rotates, etc.

For example:

...
unsigned long long A = __builtin_ppc_cmpb(B, C);
return A & 0xFF00FF00FF00FF;

It is entirely possible that the optimizer will get rid of some of the produced instructions and then the back end won't be able to emit a single cmpb but will have to emit a whole bunch of scalar instructions.

[NeHuang]

clang/lib/CodeGen/CGBuiltin.cpp

15081

• The backend test case define i64 @test64(i64 %x, i64 %y) is in llvm/test/CodeGen/PowerPC/cmpb.ll
• Also Tried the test case and results look fine.

$ cat test_cmpb.c
long long test_cmpb(long long a, long long b) {
  //return __cmpb(a, b);
  unsigned long long A = __builtin_ppc_cmpb(a, b);
  return A & 0xFF00FF00FF00FF;
}
$ clang -cc1 -O3 -triple powerpc-unknown-aix test_cmpb.c -target-cpu pwr9 -S -o test_cmpb_32bit.s
...
.test_cmpb:
# %bb.0:                                # %entry
        cmpb 4, 6, 4
        lis 6, 255
        cmpb 3, 5, 3
        ori 6, 6, 255
        and 4, 4, 6
        and 3, 3, 6
        blr
$ clang -cc1 -O3 -triple powerpc64-unknown-aix test_cmpb.c -target-cpu pwr9 -S -o test_cmpb_64bit.s
.test_cmpb:
# %bb.0:                                # %entry
        cmpb 3, 4, 3
        lis 4, 255
        ori 4, 4, 255
        rldimi 4, 4, 32, 0
        and 3, 3, 4
        blr

[NeHuang]

clang/lib/CodeGen/CGBuiltin.cpp

15081

The intension of emitting this complex sequence for this builtin is to produce the target independent code matching the backend test case IR (in the description) and produce asm results matching xlc. Verified the target IR will produce expected asm results for 32 bit and 64 bit.

• For 64 bit

cmpb 3, 3, 4
blr

• For 32 bit

cmpb 4, 6, 4
cmpb 3, 5, 3
blr

[NeHuang]

Address review comment to rework 32 bit handling.

[nemanjai]

Mostly minor comments, but it'll be good to have another look to make sure they're all addressed.

clang/lib/CodeGen/CGBuiltin.cpp

15101

Nit: no else after return.

15104

These comments are superfluous. You have the entire sequence listed above, no need to repeat it piece-wise here.

15105

Please do not name variables with non-descriptive single letters. It is somewhat conventional to use suffixes such as Hi/Lo for high/low order parts of a value.

llvm/include/llvm/IR/IntrinsicsPowerPC.td

1537

Line too long?

[NeHuang]

Address review comments from Nemanja.

[NeHuang]

Rebased the patch with ToT.

[NeHuang]

clang-format

[nemanjai]

LGTM. Thank you.

[jroelofs]

I moved a couple of new tests from this patch from CodeGen -> CodeGen/PowerPC so they don't fail when the PPC backend isn't built: f6769b663a0d4432b5e00e0c03904a5dfba7b077

[NeHuang]

Thanks @jroelofs for moving the test cases! Those cases were added in https://reviews.llvm.org/D105946 and I have notified the author.

clang/include/clang/Basic/BuiltinsPPC.def

 BUILTIN(__builtin_ppc_swdiv_nochk, "ddd", "")
 BUILTIN(__builtin_ppc_swdivs_nochk, "fff", "")
 BUILTIN(__builtin_ppc_alignx, "vIivC*", "nc")
 BUILTIN(__builtin_ppc_rdlam, "UWiUWiUWiUWIi", "nc")
 // Compare
 BUILTIN(__builtin_ppc_cmpeqb, "LLiLLiLLi", "")
 BUILTIN(__builtin_ppc_cmprb, "iCIiii", "")
 BUILTIN(__builtin_ppc_setb, "LLiLLiLLi", "")
+BUILTIN(__builtin_ppc_cmpb, "LLiLLiLLi", "")
 // Multiply
 BUILTIN(__builtin_ppc_mulhd, "LLiLiLi", "")
 BUILTIN(__builtin_ppc_mulhdu, "ULLiULiULi", "")
 BUILTIN(__builtin_ppc_mulhw, "iii", "")
 BUILTIN(__builtin_ppc_mulhwu, "UiUiUi", "")
 BUILTIN(__builtin_ppc_maddhd, "LLiLLiLLiLLi", "")
 BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "")
 BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "")

clang/lib/Basic/Targets/PPC.cpp

static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__fctidz", "__builtin_ppc_fctidz");
   Builder.defineMacro("__fctiw", "__builtin_ppc_fctiw");
   Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
   Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
   Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
   Builder.defineMacro("__cmpeqb", "__builtin_ppc_cmpeqb");
   Builder.defineMacro("__cmprb", "__builtin_ppc_cmprb");
   Builder.defineMacro("__setb", "__builtin_ppc_setb");
+  Builder.defineMacro("__cmpb", "__builtin_ppc_cmpb");
   Builder.defineMacro("__mulhd", "__builtin_ppc_mulhd");
   Builder.defineMacro("__mulhdu", "__builtin_ppc_mulhdu");
   Builder.defineMacro("__mulhw", "__builtin_ppc_mulhw");
   Builder.defineMacro("__mulhwu", "__builtin_ppc_mulhwu");
   Builder.defineMacro("__maddhd", "__builtin_ppc_maddhd");
   Builder.defineMacro("__maddhdu", "__builtin_ppc_maddhdu");
   Builder.defineMacro("__maddld", "__builtin_ppc_maddld");
   Builder.defineMacro("__rlwnm", "__builtin_ppc_rlwnm");

clang/lib/CodeGen/CGBuiltin.cpp

case PPC::BI__builtin_vsx_xvsqrtdp: {
     } else {
       llvm::Function *F = CGM.getIntrinsic(Intrinsic::sqrt, ResultType);
       return Builder.CreateCall(F, X);
     }
   }
   // Count leading zeros
   case PPC::BI__builtin_altivec_vclzb:
   case PPC::BI__builtin_altivec_vclzh:
   case PPC::BI__builtin_altivec_vclzw:
   case PPC::BI__builtin_altivec_vclzd: {
     llvm::Type *ResultType = ConvertType(E->getType());
     Value *X = EmitScalarExpr(E->getArg(0));
     Value *Undef = ConstantInt::get(Builder.getInt1Ty(), false);
     Function *F = CGM.getIntrinsic(Intrinsic::ctlz, ResultType);
     return Builder.CreateCall(F, {X, Undef});
   }
   case PPC::BI__builtin_altivec_vctzb:
   case PPC::BI__builtin_altivec_vctzh:
   case PPC::BI__builtin_altivec_vctzw:
   case PPC::BI__builtin_altivec_vctzd: {
     llvm::Type *ResultType = ConvertType(E->getType());
     Value *X = EmitScalarExpr(E->getArg(0));
     Value *Undef = ConstantInt::get(Builder.getInt1Ty(), false);
     Function *F = CGM.getIntrinsic(Intrinsic::cttz, ResultType);
     return Builder.CreateCall(F, {X, Undef});
   }
   case PPC::BI__builtin_altivec_vec_replace_elt:
   case PPC::BI__builtin_altivec_vec_replace_unaligned: {
     // The third argument of vec_replace_elt and vec_replace_unaligned must
     // be a compile time constant and will be emitted either to the vinsw
     // or vinsd instruction.
     ConstantInt *ArgCI = dyn_cast<ConstantInt>(Ops[2]);
     assert(ArgCI &&
            "Third Arg to vinsw/vinsd intrinsic must be a constant integer!");
     llvm::Type *ResultType = ConvertType(E->getType());
     llvm::Function *F = nullptr;
     Value *Call = nullptr;
     int64_t ConstArg = ArgCI->getSExtValue();
     unsigned ArgWidth = Ops[1]->getType()->getPrimitiveSizeInBits();
     bool Is32Bit = false;
     assert((ArgWidth == 32 || ArgWidth == 64) && "Invalid argument width");
case PPC::BI__builtin_ppc_poppar8: {
 
     llvm::Type *ResultType = ConvertType(E->getType());
     Value *Result = Builder.CreateAnd(Tmp, llvm::ConstantInt::get(ArgType, 1));
     if (Result->getType() != ResultType)
       Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true,
                                      "cast");
     return Result;
   }
-
+  case PPC::BI__builtin_ppc_cmpb: {
+    if (getTarget().getTriple().isPPC64()) {
+      Function *F =
+          CGM.getIntrinsic(Intrinsic::ppc_cmpb, {Int64Ty, Int64Ty, Int64Ty});
+      return Builder.CreateCall(F, Ops, "cmpb");
+    }
+    // For 32 bit, emit the code as below:
+    // %conv = trunc i64 %a to i32
+    // %conv1 = trunc i64 %b to i32
+    // %shr = lshr i64 %a, 32
+    // %conv2 = trunc i64 %shr to i32
+    // %shr3 = lshr i64 %b, 32
+    // %conv4 = trunc i64 %shr3 to i32
+    // %0 = tail call i32 @llvm.ppc.cmpb32(i32 %conv, i32 %conv1)
+    // %conv5 = zext i32 %0 to i64
+    // %1 = tail call i32 @llvm.ppc.cmpb32(i32 %conv2, i32 %conv4)
+    // %conv614 = zext i32 %1 to i64
+    // %shl = shl nuw i64 %conv614, 32
+    // %or = or i64 %shl, %conv5
+    // ret i64 %or
+    Function *F =
+        CGM.getIntrinsic(Intrinsic::ppc_cmpb, {Int32Ty, Int32Ty, Int32Ty});
+    Value *ArgOneLo = Builder.CreateTrunc(Ops[0], Int32Ty);
+    Value *ArgTwoLo = Builder.CreateTrunc(Ops[1], Int32Ty);
+    Constant *ShiftAmt = ConstantInt::get(Int64Ty, 32);
+    Value *ArgOneHi =
+        Builder.CreateTrunc(Builder.CreateLShr(Ops[0], ShiftAmt), Int32Ty);
+    Value *ArgTwoHi =
+        Builder.CreateTrunc(Builder.CreateLShr(Ops[1], ShiftAmt), Int32Ty);
+    Value *ResLo = Builder.CreateZExt(
+        Builder.CreateCall(F, {ArgOneLo, ArgTwoLo}, "cmpb"), Int64Ty);
+    Value *ResHiShift = Builder.CreateZExt(
+        Builder.CreateCall(F, {ArgOneHi, ArgTwoHi}, "cmpb"), Int64Ty);
+    Value *ResHi = Builder.CreateShl(ResHiShift, ShiftAmt);
+    return Builder.CreateOr(ResLo, ResHi);
+  }
   // Copy sign
   case PPC::BI__builtin_vsx_xvcpsgnsp:
   case PPC::BI__builtin_vsx_xvcpsgndp: {
     llvm::Type *ResultType = ConvertType(E->getType());
     Value *X = EmitScalarExpr(E->getArg(0));
     Value *Y = EmitScalarExpr(E->getArg(1));
     ID = Intrinsic::copysign;
     llvm::Function *F = CGM.getIntrinsic(ID, ResultType);

clang/test/CodeGen/builtins-ppc-xlcompat-compare.c

+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix=CHECK-64B
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s --check-prefix=CHECK-64B
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix=CHECK-32B
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix=CHECK-64B
+
+// CHECK-64B-LABEL: @test_builtin_ppc_cmpb(
+// CHECK-64B:         [[LLA_ADDR:%.*]] = alloca i64, align 8
+// CHECK-64B-NEXT:    [[LLB_ADDR:%.*]] = alloca i64, align 8
+// CHECK-64B-NEXT:    store i64 [[LLA:%.*]], i64* [[LLA_ADDR]], align 8
+// CHECK-64B-NEXT:    store i64 [[LLB:%.*]], i64* [[LLB_ADDR]], align 8
+// CHECK-64B-NEXT:    [[TMP0:%.*]] = load i64, i64* [[LLA_ADDR]], align 8
+// CHECK-64B-NEXT:    [[TMP1:%.*]] = load i64, i64* [[LLB_ADDR]], align 8
+// CHECK-64B-NEXT:    [[CMPB:%.*]] = call i64 @llvm.ppc.cmpb.i64.i64.i64(i64 [[TMP0]], i64 [[TMP1]])
+// CHECK-64B-NEXT:    ret i64 [[CMPB]]
+//
+// CHECK-32B-LABEL: @test_builtin_ppc_cmpb(
+// CHECK-32B:         [[LLA_ADDR:%.*]] = alloca i64, align 8
+// CHECK-32B-NEXT:    [[LLB_ADDR:%.*]] = alloca i64, align 8
+// CHECK-32B-NEXT:    store i64 [[LLA:%.*]], i64* [[LLA_ADDR]], align 8
+// CHECK-32B-NEXT:    store i64 [[LLB:%.*]], i64* [[LLB_ADDR]], align 8
+// CHECK-32B-NEXT:    [[TMP0:%.*]] = load i64, i64* [[LLA_ADDR]], align 8
+// CHECK-32B-NEXT:    [[TMP1:%.*]] = load i64, i64* [[LLB_ADDR]], align 8
+// CHECK-32B-NEXT:    [[TMP2:%.*]] = trunc i64 [[TMP0]] to i32
+// CHECK-32B-NEXT:    [[TMP3:%.*]] = trunc i64 [[TMP1]] to i32
+// CHECK-32B-NEXT:    [[TMP4:%.*]] = lshr i64 [[TMP0]], 32
+// CHECK-32B-NEXT:    [[TMP5:%.*]] = trunc i64 [[TMP4]] to i32
+// CHECK-32B-NEXT:    [[TMP6:%.*]] = lshr i64 [[TMP1]], 32
+// CHECK-32B-NEXT:    [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
+// CHECK-32B-NEXT:    [[CMPB:%.*]] = call i32 @llvm.ppc.cmpb.i32.i32.i32(i32 [[TMP2]], i32 [[TMP3]])
+// CHECK-32B-NEXT:    [[TMP8:%.*]] = zext i32 [[CMPB]] to i64
+// CHECK-32B-NEXT:    [[CMPB1:%.*]] = call i32 @llvm.ppc.cmpb.i32.i32.i32(i32 [[TMP5]], i32 [[TMP7]])
+// CHECK-32B-NEXT:    [[TMP9:%.*]] = zext i32 [[CMPB1]] to i64
+// CHECK-32B-NEXT:    [[TMP10:%.*]] = shl i64 [[TMP9]], 32
+// CHECK-32B-NEXT:    [[TMP11:%.*]] = or i64 [[TMP8]], [[TMP10]]
+// CHECK-32B-NEXT:    ret i64 [[TMP11]]
+//
+long long test_builtin_ppc_cmpb(long long lla, long long llb) {
+  return __builtin_ppc_cmpb(lla, llb);
+}

llvm/include/llvm/IR/IntrinsicsPowerPC.td

let TargetPrefix = "ppc" in {
   def int_ppc_dcbt  : GCCBuiltin<"__builtin_ppc_dcbt">,
                       Intrinsic<[], [llvm_ptr_ty],
     [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
   def int_ppc_dcbtst : GCCBuiltin<"__builtin_ppc_dcbtst">,
                        Intrinsic<[], [llvm_ptr_ty],
     [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
   def int_ppc_dcbz  : GCCBuiltin<"__builtin_ppc_dcbz">,
                       Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_icbt : GCCBuiltin<"__builtin_ppc_icbt">,
                      Intrinsic<[], [llvm_ptr_ty], []>;
   
   // Population Count in each Byte.
   def int_ppc_popcntb : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrNoMem]>;
   
   // sync instruction (i.e. sync 0, a.k.a hwsync)
   def int_ppc_sync : GCCBuiltin<"__builtin_ppc_sync">,
                      Intrinsic<[], [], []>;
def int_ppc_cmpeqb
         Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
   def int_ppc_cmprb
       : GCCBuiltin<"__builtin_ppc_cmprb">,
         Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
                   [IntrNoMem, ImmArg<ArgIndex<0>>]>;
   def int_ppc_setb
       : GCCBuiltin<"__builtin_ppc_setb">,
         Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+  def int_ppc_cmpb
+      : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty, llvm_anyint_ty],
+                  [IntrNoMem]>;
   // multiply
   def int_ppc_mulhd
       : GCCBuiltin<"__builtin_ppc_mulhd">,
         Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
   def int_ppc_mulhdu
       : GCCBuiltin<"__builtin_ppc_mulhdu">,
         Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
   def int_ppc_mulhw

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 def : Pat<(i64 (int_ppc_mulhdu g8rc:$a, g8rc:$b)),
           (i64 (MULHDU $a, $b))>;
 def : Pat<(int_ppc_load8r ForceXForm:$ptr),
           (LDBRX ForceXForm:$ptr)>;
 def : Pat<(int_ppc_store8r g8rc:$a, ForceXForm:$ptr),
           (STDBRX g8rc:$a, ForceXForm:$ptr)>;
 }
 
+def : Pat<(i64 (int_ppc_cmpb g8rc:$a, g8rc:$b)),
+          (i64 (CMPB8 $a, $b))>;
+
 let Predicates = [IsISA3_0] in {
 // DARN (deliver random number)
 // L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random
 def : Pat<(int_ppc_darn32), (EXTRACT_SUBREG (DARN 0), sub_32)>;
 def : Pat<(int_ppc_darn), (DARN 1)>;
 def : Pat<(int_ppc_darnraw), (DARN 2)>;
 
 class X_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 let Predicates = [IsISA3_0] in {
 def : Pat<(i32 (int_ppc_cmprb i32:$a, gprc:$b, gprc:$c)),
           (i32 (SETB (CMPRB u1imm:$a, $b, $c)))>;
 }
 def : Pat<(i32 (int_ppc_mulhw gprc:$a, gprc:$b)),
           (i32 (MULHW $a, $b))>;
 def : Pat<(i32 (int_ppc_mulhwu gprc:$a, gprc:$b)),
           (i32 (MULHWU $a, $b))>;
+def : Pat<(i32 (int_ppc_cmpb gprc:$a, gprc:$b)),
+          (i32 (CMPB $a, $b))>;
 
 def : Pat<(int_ppc_load2r ForceXForm:$ptr),
           (LHBRX ForceXForm:$ptr)>;
 def : Pat<(int_ppc_load4r ForceXForm:$ptr),
           (LWBRX ForceXForm:$ptr)>;
 def : Pat<(int_ppc_store2r gprc:$a, ForceXForm:$ptr),
           (STHBRX gprc:$a, ForceXForm:$ptr)>;
 def : Pat<(int_ppc_store4r gprc:$a, ForceXForm:$ptr),

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+
+define i64 @test_cmpb(i64 %a, i64 %b) {
+; CHECK-LABEL: test_cmpb:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpb 4, 4, 6
+; CHECK-NEXT:    cmpb 3, 3, 5
+; CHECK-NEXT:    blr
+entry:
+  %0 = trunc i64 %a to i32
+  %1 = trunc i64 %b to i32
+  %2 = lshr i64 %a, 32
+  %3 = trunc i64 %2 to i32
+  %4 = lshr i64 %b, 32
+  %5 = trunc i64 %4 to i32
+  %cmpb = tail call i32 @llvm.ppc.cmpb.i32.i32.i32(i32 %0, i32 %1)
+  %6 = zext i32 %cmpb to i64
+  %cmpb1 = tail call i32 @llvm.ppc.cmpb.i32.i32.i32(i32 %3, i32 %5)
+  %7 = zext i32 %cmpb1 to i64
+  %8 = shl nuw i64 %7, 32
+  %9 = or i64 %8, %6
+  ret i64 %9
+}
+
+declare i32 @llvm.ppc.cmpb.i32.i32.i32(i32, i32)

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 < %s | FileCheck %s
+
+define i64 @test_cmpb(i64 %a, i64 %b) {
+; CHECK-LABEL: test_cmpb:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpb 3, 3, 4
+; CHECK-NEXT:    blr
+entry:
+  %cmpb = tail call i64 @llvm.ppc.cmpb.i64.i64.i64(i64 %a, i64 %b)
+  ret i64 %cmpb
+}
+
+declare i64 @llvm.ppc.cmpb.i64.i64.i64(i64, i64)