Page MenuHomePhabricator

[RISCV] Teach vsetvli insertion to remember when predecessors have same AVL and SEW/LMUL ratio if their VTYPEs otherwise mismatch.
ClosedPublic

Authored by craig.topper on Thu, Jun 10, 3:28 PM.

Details

Summary

Previously we went directly to unknown state on VTYPE mismatch.
If we instead remember the partial match, we can use this to
still use X0, X0 vsetvli in successors if AVL and needed SEW/LMUL
ratio match.

Diff Detail

Event Timeline

craig.topper created this revision.Thu, Jun 10, 3:28 PM
craig.topper requested review of this revision.Thu, Jun 10, 3:28 PM
Herald added a project: Restricted Project. · View Herald TranscriptThu, Jun 10, 3:28 PM
Herald added a subscriber: MaskRay. · View Herald Transcript

Fixed typo in comment

kito-cheng added inline comments.Mon, Jun 14, 8:58 PM
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
65–66

Need init SEWLMULRatioOnly here.

craig.topper added inline comments.Mon, Jun 14, 9:08 PM
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
65–66

Thanks!

Initialize member variable

frasercrmck added inline comments.Wed, Jun 16, 2:26 AM
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
227

I'm wondering if removing this use of the == operator is a sign we shouldn't have one for these types. Is it confusing to have different meaning of equality? Alternatively perhaps this operator is now unused so can be axed without much discussion.

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
501

Nit but this comment feels like it's missing something in The AVL is the same the SEW/LMUL ratio. A comma, or an and?

Address review feedback

frasercrmck accepted this revision.Fri, Jun 18, 12:39 AM

LGTM, thanks!

This revision is now accepted and ready to land.Fri, Jun 18, 12:39 AM