[clang][AIX] Enable inlined quadword atomic operations

[lkail]

Summary

If target cpu is pwr8+, we can generate inlined quadword lock free atomic operations, thus no need to generate libcalls into libatomic.

[qiucf]

clang/lib/Basic/Targets/PPC.cpp

336

What about ppc64?

Also, seems there's no need to add pwr10 here.

clang/lib/Basic/Targets/PPC.h

442

We don't need this at all for Linux?

[lkail]

Address comments.

[lkail]

clang/lib/Basic/Targets/PPC.cpp

336

What about ppc64?

Instructions needed for inline quadword atomics like lqarx and stqcx are only user-space viable in pwr8 and above. However, pwr6 and pwr7 also feature ppc64.

[hubert.reinterpretcast]

clang/test/CodeGen/ppc64-quadword-atomics.c

11

Can you add a link to something that demonstrates that the implementation of __atomic_exchange is also lock-free when running on pwr8 and up?

[lkail]

clang/test/CodeGen/ppc64-quadword-atomics.c

11

https://reviews.llvm.org/D103614#C2646926NL5 All related lock-free codegen is in the parent revision.

[hubert.reinterpretcast]

clang/test/CodeGen/ppc64-quadword-atomics.c

11

That change is for the compiler. I am looking for something that makes the libatomic implementation correspondingly lock-free for this type (even if libatomic needs to be deployable on pwr7).

[lkail]

Most are covered by https://reviews.llvm.org/D122377 already.

clang/lib/Basic/Targets/PPC.h

class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
   bool HasBPERMD = false;
   bool HasExtDiv = false;
   bool HasP9Vector = false;
   bool HasSPE = false;
   bool PairedVectorMemops = false;
   bool HasP10Vector = false;
   bool HasPCRelativeMemops = false;
   bool HasPrefixInstrs = false;
+  bool HasQuadwordAtomics = false;
 
 protected:
   std::string ABI;
 
 public:
   PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
       : TargetInfo(Triple) {
     SuitableAlign = 128;
PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
     if (Triple.isOSAIX() || Triple.isOSLinux())
       DataLayout += "-S128-v256:256:256-v512:512:512";
     resetDataLayout(DataLayout);
 
     // PPC64 supports atomics up to 8 bytes.
     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
   }
 
+  void setMaxAtomicWidth() override {
+    if (getTriple().isOSAIX() && getTriple().isArch64Bit() &&
+        hasFeature("quadword-atomics"))
+      MaxAtomicInlineWidth = 128;
+  }
+
   BuiltinVaListKind getBuiltinVaListKind() const override {
     return TargetInfo::CharPtrBuiltinVaList;
   }
 
   // PPC64 Linux-specific ABI options.
   bool setABI(const std::string &Name) override {
     if (Name == "elfv1" || Name == "elfv2") {
       ABI = Name;

clang/lib/Basic/Targets/PPC.cpp

for (const auto &Feature : Features) {
     } else if (Feature == "+paired-vector-memops") {
       PairedVectorMemops = true;
     } else if (Feature == "+mma") {
       HasMMA = true;
     } else if (Feature == "+rop-protect") {
       HasROPProtect = true;
     } else if (Feature == "+privileged") {
       HasPrivileged = true;
+    } else if (Feature == "+quadword-atomics") {
+      HasQuadwordAtomics = true;
     }
     // TODO: Finish this list and add an assert that we've handled them
     // all.
   }
 
   return true;
 }
 
Features["vsx"] = llvm::StringSwitch<bool>(CPU)
                         .Case("pwr8", true)
                         .Case("pwr7", true)
                         .Default(false);
   Features["htm"] = llvm::StringSwitch<bool>(CPU)
                         .Case("ppc64le", true)
                         .Case("pwr9", true)
                         .Case("pwr8", true)
                         .Default(false);
+  Features["quadword-atomics"] = llvm::StringSwitch<bool>(CPU)
+                                     .Case("pwr10", true)
+                                     .Case("pwr9", true)
+                                     .Case("pwr8", true)
+                                     .Default(false);
 
   // ROP Protect is off by default.
   Features["rop-protect"] = false;
   // Privileged instructions are off by default.
   Features["privileged"] = false;
 
   Features["spe"] = llvm::StringSwitch<bool>(CPU)
                         .Case("8548", true)
return llvm::StringSwitch<bool>(Feature)
       .Case("paired-vector-memops", PairedVectorMemops)
       .Case("power10-vector", HasP10Vector)
       .Case("pcrelative-memops", HasPCRelativeMemops)
       .Case("prefix-instrs", HasPrefixInstrs)
       .Case("spe", HasSPE)
       .Case("mma", HasMMA)
       .Case("rop-protect", HasROPProtect)
       .Case("privileged", HasPrivileged)
+      .Case("quadword-atomics", HasQuadwordAtomics)
       .Default(false);
 }
 
 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
                                       StringRef Name, bool Enabled) const {
   if (Enabled) {
     if (Name == "efpu2")
       Features["spe"] = true;

clang/test/CodeGen/ppc64-quadword-atomics.c

+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr9 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr10 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+
+struct Quadword { long long a[2]; } __attribute__((aligned (16)));
+
+// CHECK-NOT: call void @__atomic_exchange
+// CHECK: +quadword-atomics
+struct Quadword test_xchg(struct Quadword *ptr, struct Quadword new) {
+  struct Quadword old;
+  __atomic_exchange(ptr, &new, &old, __ATOMIC_SEQ_CST);
+  return old;
+}