[PowerPC] Support ppc-asm-full-reg-names for AIX

[qiucf]

Summary

This restriction was introduced in D39016.

[steven.zhang]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

599

bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
  if (!FullRegNamesWithPercent || TT.getOS() == Triple::AIX)
    return false;

Could you please double confirm on why we need this check for AIX.

[nemanjai]

Historically, the letter prefixes were always stripped out because AIX and Linux assemblers don't accept them. The mentioned patch added the ability to produce prefixes with percent sign and letter which is actually accepted by the Linux assembler (GNU as). It was thought (not known) at the time that AIX does not accept this %<letter> syntax either so the guard for AIX was kept. If you can confirm that the AIX system assembler accepts this syntax, then this is fine.

I suppose it is fine either way since we never took the extra step of making -ppc-reg-with-percent-prefix the default, but if we do choose to make that the default at some point, we can only do so if the AIX assembler also supports it.

[qiucf]

In D94282#2486270, @nemanjai wrote:

Historically, the letter prefixes were always stripped out because AIX and Linux assemblers don't accept them. The mentioned patch added the ability to produce prefixes with percent sign and letter which is actually accepted by the Linux assembler (GNU as). It was thought (not known) at the time that AIX does not accept this %<letter> syntax either so the guard for AIX was kept. If you can confirm that the AIX system assembler accepts this syntax, then this is fine.

I suppose it is fine either way since we never took the extra step of making -ppc-reg-with-percent-prefix the default, but if we do choose to make that the default at some point, we can only do so if the AIX assembler also supports it.

Thanks for the historical information. I saw GNU as on AIX supports -mregnames/-mno-regnames and accepts assembly with regname or precent prefixes, but did not found any such option from AIX system assembler. And LLVM MC assembler also doesn't work since AsmParser for XCOFF is not ready yet.

[jsji]

I think we should enable this for lit testing purpose.

The options (-ppc-asm-full-reg-names, -ppc-reg-with-percent-prefix) are not on by default, so it won't cause problem by default.
If user add this option explicitly, then most of the time it should be for debug or lit testing.

We can add one warning on AIX when the option is on, mentioning that showing full reg names won't be accepted by default AIX assembler for now, just for reading or lit purpose.

[nemanjai]

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll

7

We can probably get rid of the --check-prefix here since the AIX asm should match the Linux asm, won't it?

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

 /// showRegistersWithPercentPrefix - Check if this register name should be
 /// printed with a percentage symbol as prefix.
 bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
   if (!FullRegNamesWithPercent || TT.getOS() == Triple::AIX)
     return false;
 
   switch (RegName[0]) {
   default:
     return false;
   case 'r':
   case 'f':
   case 'q':
   case 'v':
   case 'c':
     return true;
   }
 }
const char *CRBits[] = {
     "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
   };
   return CRBits[RegEncoding];
 }
 
 // showRegistersWithPrefix - This method determines whether registers
 // should be number-only or include the prefix.
 bool PPCInstPrinter::showRegistersWithPrefix() const {
-  if (TT.getOS() == Triple::AIX)
-    return false;
   return FullRegNamesWithPercent || FullRegNames;
 }
 
 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
                                   const MCSubtargetInfo &STI, raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
     unsigned Reg = Op.getReg();

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
 ; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
 
 define i64 @test_cmpb(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_cmpb:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpb 4, 4, 6
-; CHECK-NEXT:    cmpb 3, 3, 5
+; CHECK-NEXT:    cmpb r4, r4, r6
+; CHECK-NEXT:    cmpb r3, r3, r5
 ; CHECK-NEXT:    blr
 entry:
   %0 = trunc i64 %a to i32
   %1 = trunc i64 %b to i32
   %2 = lshr i64 %a, 32
   %3 = trunc i64 %2 to i32
   %4 = lshr i64 %b, 32
   %5 = trunc i64 %4 to i32

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
 ; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
 
 define dso_local i32 @test_builtin_ppc_popcntb_i32(i32 %a) local_unnamed_addr {
 ; CHECK-LABEL: test_builtin_ppc_popcntb_i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    popcntb 3, 3
+; CHECK-NEXT:    popcntb r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %popcntb = tail call i32 @llvm.ppc.popcntb.i32.i32(i32 %a)
   ret i32 %popcntb
 }
 declare i32 @llvm.ppc.popcntb.i32.i32(i32)
 
 define dso_local void @test_builtin_ppc_eieio() {
 ; CHECK-LABEL: test_builtin_ppc_eieio:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ori 2, 2, 0
-; CHECK-NEXT:    ori 2, 2, 0
+; CHECK-NEXT:    ori r2, r2, 0
+; CHECK-NEXT:    ori r2, r2, 0
 ; CHECK-NEXT:    eieio
 ; CHECK-NEXT:    blr
 entry:
   call void @llvm.ppc.eieio()
   ret void
 }
 declare void @llvm.ppc.eieio()
 
 define dso_local void @test_builtin_ppc_iospace_eieio() {
 ; CHECK-LABEL: test_builtin_ppc_iospace_eieio:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ori 2, 2, 0
-; CHECK-NEXT:    ori 2, 2, 0
+; CHECK-NEXT:    ori r2, r2, 0
+; CHECK-NEXT:    ori r2, r2, 0
 ; CHECK-NEXT:    eieio
 ; CHECK-NEXT:    blr
 entry:
   call void @llvm.ppc.iospace.eieio()
   ret void
 }
 declare void @llvm.ppc.iospace.eieio()
 

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
 ; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
 ; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
 
 define dso_local i64 @test_builtin_ppc_popcntb_i64(i64 %a) local_unnamed_addr {
 ; CHECK-LABEL: test_builtin_ppc_popcntb_i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    popcntb r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: test_builtin_ppc_popcntb_i64:
 ; CHECK-AIX:       # %bb.0: # %entry
-; CHECK-AIX-NEXT:    popcntb 3, 3
+; CHECK-AIX-NEXT:    popcntb r3, r3
 ; CHECK-AIX-NEXT:    blr
 entry:
   %popcntb = tail call i64 @llvm.ppc.popcntb.i64.i64(i64 %a)
   ret i64 %popcntb
 }
 declare i64 @llvm.ppc.popcntb.i64.i64(i64)
 
 define dso_local void @test_builtin_ppc_eieio() {
 ; CHECK-LABEL: test_builtin_ppc_eieio:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r2, r2, 0
 ; CHECK-NEXT:    ori r2, r2, 0
 ; CHECK-NEXT:    eieio
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: test_builtin_ppc_eieio:
 ; CHECK-AIX:       # %bb.0: # %entry
-; CHECK-AIX-NEXT:    ori 2, 2, 0
-; CHECK-AIX-NEXT:    ori 2, 2, 0
+; CHECK-AIX-NEXT:    ori r2, r2, 0
+; CHECK-AIX-NEXT:    ori r2, r2, 0
 ; CHECK-AIX-NEXT:    eieio
 ; CHECK-AIX-NEXT:    blr
 entry:
   call void @llvm.ppc.eieio()
   ret void
 }
 declare void @llvm.ppc.eieio()
 
 define dso_local void @test_builtin_ppc_iospace_eieio() {
 ; CHECK-LABEL: test_builtin_ppc_iospace_eieio:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r2, r2, 0
 ; CHECK-NEXT:    ori r2, r2, 0
 ; CHECK-NEXT:    eieio
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: test_builtin_ppc_iospace_eieio:
 ; CHECK-AIX:       # %bb.0: # %entry
-; CHECK-AIX-NEXT:    ori 2, 2, 0
-; CHECK-AIX-NEXT:    ori 2, 2, 0
+; CHECK-AIX-NEXT:    ori r2, r2, 0
+; CHECK-AIX-NEXT:    ori r2, r2, 0
 ; CHECK-AIX-NEXT:    eieio
 ; CHECK-AIX-NEXT:    blr
 entry:
   call void @llvm.ppc.iospace.eieio()
   ret void
 }
 declare void @llvm.ppc.iospace.eieio()
 

 ; CHECK-LABEL: test_builtin_ppc_icbt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ld r3, -8(r1)
 ; CHECK-NEXT:    icbt 0, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: test_builtin_ppc_icbt:
 ; CHECK-AIX:       # %bb.0: # %entry
-; CHECK-AIX-NEXT:    ld 3, -8(1)
-; CHECK-AIX-NEXT:    icbt 0, 0, 3
+; CHECK-AIX-NEXT:    ld r3, -8(r1)
+; CHECK-AIX-NEXT:    icbt 0, 0, r3
 ; CHECK-AIX-NEXT:    blr
 entry:
   %a = alloca i8*, align 8
   %0 = load i8*, i8** %a, align 8
   call void @llvm.ppc.icbt(i8* %0)
   ret void
 }
 declare void @llvm.ppc.icbt(i8*)

llvm/test/CodeGen/PowerPC/reg-names.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names < %s | FileCheck -check-prefix=CHECK-FN %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -ppc-asm-full-reg-names < %s | FileCheck -check-prefix=CHECK-FN %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -ppc-reg-with-percent-prefix < %s | FileCheck -check-prefix=CHECK-PN %s
 
 define i64 @test1(i64 %a, i64 %b) {
 ; CHECK-LABEL: @test1
 ; CHECK-FN-LABEL: @test1
 
 entry:
   ret i64 %b