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Differential D103331

[RISCV] Masked compares should use a tail agnostic policy.
ClosedPublic

Authored by craig.topper on May 28 2021, 11:21 AM.

Details

Reviewers
frasercrmck
evandro
HsiangKai
khchen
arcbbb
rogfer01
Commits
rGae3ab4f0ec61: [RISCV] Masked compares should use a tail agnostic policy.
Summary

Writes of a mask result are always tail agnostic.

Unfortunately, this seems to have made codegen worse. I can only
think this must be because the vsetvli was acting as some sort
of barrier that prevented some code movement in the scheduler.

Diff Detail

Event Timeline

craig.topper created this revision.May 28 2021, 11:21 AM
Herald added subscribers: StephenFan, vkmr, luismarques and 23 others. · View Herald TranscriptMay 28 2021, 11:21 AM
craig.topper requested review of this revision.May 28 2021, 11:21 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 28 2021, 11:21 AM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B106740: Diff 348559.May 28 2021, 11:57 AM
craig.topper updated this revision to Diff 349005.Jun 1 2021, 10:11 AM

Rebase

Harbormaster completed remote builds in B107063: Diff 349005.Jun 1 2021, 11:02 AM
craig.topper updated this revision to Diff 349916.Jun 4 2021, 10:35 AM

Rebase

Harbormaster completed remote builds in B107706: Diff 349916.Jun 4 2021, 11:14 AM
arcbbb accepted this revision.Jun 7 2021, 8:03 PM

LGTM

This revision is now accepted and ready to land.Jun 7 2021, 8:03 PM
Closed by commit rGae3ab4f0ec61: [RISCV] Masked compares should use a tail agnostic policy. (authored by craig.topper). · Explain WhyJun 7 2021, 9:56 PM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGae3ab4f0ec61: [RISCV] Masked compares should use a tail agnostic policy..

Revision Contents

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llvm/
lib/
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RISCV/
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test/
CodeGen/
RISCV/
rvv/
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Diff 349005

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 1,457 Lines • ▼ Show 20 Lines
multiclass VPseudoBinaryM<VReg RetClass, multiclass VPseudoBinaryM<VReg RetClass,
VReg Op1Class, VReg Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = ""> { string Constraint = ""> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class, def "_" # MInfo.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
Constraint>; Constraint>;
let ForceTailAgnostic = true in
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class, def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class,
Op2Class, Constraint>; Op2Class, Constraint>;
} }
} }
multiclass VPseudoBinaryEmul<VReg RetClass, multiclass VPseudoBinaryEmul<VReg RetClass,
VReg Op1Class, VReg Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
▲ Show 20 Lines • Show All 3,011 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v9 ; CHECK-NEXT: vmfeq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v9 ; CHECK-NEXT: vmfeq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v9 ; CHECK-NEXT: vmfeq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v10 ; CHECK-NEXT: vmfeq.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v12 ; CHECK-NEXT: vmfeq.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v9 ; CHECK-NEXT: vmfeq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v9 ; CHECK-NEXT: vmfeq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v10 ; CHECK-NEXT: vmfeq.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v12 ; CHECK-NEXT: vmfeq.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v9 ; CHECK-NEXT: vmfeq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v10 ; CHECK-NEXT: vmfeq.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v12 ; CHECK-NEXT: vmfeq.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 33 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
Show All 32 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
Show All 39 Lines
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f64_f64: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64.f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64.f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 40 Lines
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f64_f64: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64.f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64.f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 40 Lines
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f64_f64: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64.f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64.f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
double %2, double %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v9 ; CHECK-NEXT: vmfeq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v9 ; CHECK-NEXT: vmfeq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v9 ; CHECK-NEXT: vmfeq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v10 ; CHECK-NEXT: vmfeq.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v12 ; CHECK-NEXT: vmfeq.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v9 ; CHECK-NEXT: vmfeq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v9 ; CHECK-NEXT: vmfeq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v10 ; CHECK-NEXT: vmfeq.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v12 ; CHECK-NEXT: vmfeq.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v9 ; CHECK-NEXT: vmfeq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v10 ; CHECK-NEXT: vmfeq.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v12 ; CHECK-NEXT: vmfeq.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfeq.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfeq.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 33 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
Show All 32 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64.f64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f64_f64: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64.f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64.f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64.f64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f64_f64: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64.f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64.f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64.f64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f64_f64: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64.f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64.f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
double %2, double %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v9, v8 ; CHECK-NEXT: vmfle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v9, v8 ; CHECK-NEXT: vmfle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmfle.vv v0, v9, v8 ; CHECK-NEXT: vmfle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v10, v8 ; CHECK-NEXT: vmfle.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v12, v8 ; CHECK-NEXT: vmfle.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v9, v8 ; CHECK-NEXT: vmfle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmfle.vv v0, v9, v8 ; CHECK-NEXT: vmfle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v10, v8 ; CHECK-NEXT: vmfle.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v12, v8 ; CHECK-NEXT: vmfle.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmfle.vv v0, v9, v8 ; CHECK-NEXT: vmfle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v10, v8 ; CHECK-NEXT: vmfle.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v12, v8 ; CHECK-NEXT: vmfle.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 33 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f16_f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f16_f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f16_f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
Show All 32 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmfge_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfge_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv16f16_f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f32_f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f32_f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f32_f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f32_f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
Show All 39 Lines
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f64_f64: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64.f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64.f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 40 Lines
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f64_f64: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64.f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64.f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 40 Lines
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f64_f64: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64.f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64.f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
double %2, double %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v9, v8 ; CHECK-NEXT: vmfle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v9, v8 ; CHECK-NEXT: vmfle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmfle.vv v0, v9, v8 ; CHECK-NEXT: vmfle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v10, v8 ; CHECK-NEXT: vmfle.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v12, v8 ; CHECK-NEXT: vmfle.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v9, v8 ; CHECK-NEXT: vmfle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmfle.vv v0, v9, v8 ; CHECK-NEXT: vmfle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v10, v8 ; CHECK-NEXT: vmfle.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v12, v8 ; CHECK-NEXT: vmfle.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmfle.vv v0, v9, v8 ; CHECK-NEXT: vmfle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v10, v8 ; CHECK-NEXT: vmfle.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v12, v8 ; CHECK-NEXT: vmfle.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 33 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f16_f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f16_f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f16_f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
Show All 32 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmfge_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfge_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv16f16_f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f32_f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f32_f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f32_f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f32_f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64.f64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f64_f64: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64.f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64.f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64.f64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f64_f64: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64.f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64.f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64.f64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f64_f64: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64.f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64.f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
double %2, double %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: vmflt.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v12, v8 ; CHECK-NEXT: vmflt.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: vmflt.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v12, v8 ; CHECK-NEXT: vmflt.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: vmflt.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v12, v8 ; CHECK-NEXT: vmflt.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 33 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
Show All 32 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
Show All 39 Lines
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f64_f64: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64.f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64.f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 40 Lines
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f64_f64: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 40 Lines
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f64_f64: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64.f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64.f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
double %2, double %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: vmflt.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v12, v8 ; CHECK-NEXT: vmflt.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: vmflt.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v12, v8 ; CHECK-NEXT: vmflt.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: vmflt.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v12, v8 ; CHECK-NEXT: vmflt.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 33 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
Show All 32 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64.f64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f64_f64: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64.f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64.f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.f64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f64_f64: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64.f64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f64_f64: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64.f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64.f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
double %2, double %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: vmfle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: vmfle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: vmfle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: vmfle.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v12 ; CHECK-NEXT: vmfle.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: vmfle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: vmfle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: vmfle.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v12 ; CHECK-NEXT: vmfle.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: vmfle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: vmfle.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v12 ; CHECK-NEXT: vmfle.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 33 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
Show All 32 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
Show All 39 Lines
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f64_f64: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 40 Lines
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f64_f64: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 40 Lines
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f64_f64: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
double %2, double %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: vmfle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: vmfle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: vmfle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: vmfle.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v12 ; CHECK-NEXT: vmfle.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: vmfle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: vmfle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: vmfle.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v12 ; CHECK-NEXT: vmfle.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: vmfle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: vmfle.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v12 ; CHECK-NEXT: vmfle.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfle.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 33 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
Show All 32 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f64_f64: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f64_f64: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f64_f64: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
double %2, double %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: vmflt.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v12 ; CHECK-NEXT: vmflt.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: vmflt.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v12 ; CHECK-NEXT: vmflt.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: vmflt.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v12 ; CHECK-NEXT: vmflt.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 33 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
Show All 32 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmflt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmflt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
Show All 39 Lines
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f64_f64: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64.f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64.f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 40 Lines
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f64_f64: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64.f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64.f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 40 Lines
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f64_f64: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64.f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64.f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
double %2, double %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: vmflt.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v12 ; CHECK-NEXT: vmflt.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: vmflt.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v12 ; CHECK-NEXT: vmflt.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: vmflt.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v12 ; CHECK-NEXT: vmflt.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmflt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 33 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
Show All 32 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmflt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmflt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64.f64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f64_f64: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64.f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64.f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64.f64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f64_f64: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64.f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64.f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64.f64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f64_f64: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64.f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64.f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
double %2, double %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v10 ; CHECK-NEXT: vmfne.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v12 ; CHECK-NEXT: vmfne.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v10 ; CHECK-NEXT: vmfne.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v12 ; CHECK-NEXT: vmfne.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v10 ; CHECK-NEXT: vmfne.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v12 ; CHECK-NEXT: vmfne.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 33 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
Show All 32 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmfne_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfne_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
Show All 39 Lines
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f64_f64: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64.f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64.f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 40 Lines
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f64_f64: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 40 Lines
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f64_f64: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64.f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64.f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
double %2, double %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v10 ; CHECK-NEXT: vmfne.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v12 ; CHECK-NEXT: vmfne.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v10 ; CHECK-NEXT: vmfne.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v12 ; CHECK-NEXT: vmfne.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v10 ; CHECK-NEXT: vmfne.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v12 ; CHECK-NEXT: vmfne.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmfne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 33 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
Show All 32 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmfne_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfne_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
Show All 32 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64.f64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f64_f64: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64.f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64.f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
Show All 32 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f64_f64: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
Show All 32 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64.f64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f64_f64: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t ; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64.f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64.f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
double %2, double %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v10 ; CHECK-NEXT: vmseq.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v12 ; CHECK-NEXT: vmseq.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v10 ; CHECK-NEXT: vmseq.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v12 ; CHECK-NEXT: vmseq.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v10 ; CHECK-NEXT: vmseq.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v12 ; CHECK-NEXT: vmseq.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v10 ; CHECK-NEXT: vmseq.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v12 ; CHECK-NEXT: vmseq.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmseq_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmseq_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vv v25, v8, v26, v0.t ; CHECK-NEXT: vmseq.vv v25, v8, v26, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vv v25, v8, v26, v0.t ; CHECK-NEXT: vmseq.vv v25, v8, v26, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vlse64.v v28, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vv v25, v8, v28, v0.t ; CHECK-NEXT: vmseq.vv v25, v8, v28, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmseq_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmseq_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v10 ; CHECK-NEXT: vmseq.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v12 ; CHECK-NEXT: vmseq.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v10 ; CHECK-NEXT: vmseq.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v12 ; CHECK-NEXT: vmseq.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v10 ; CHECK-NEXT: vmseq.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v12 ; CHECK-NEXT: vmseq.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v10 ; CHECK-NEXT: vmseq.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmseq.vv v0, v8, v12 ; CHECK-NEXT: vmseq.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmseq.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmseq.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmseq_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmseq_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmseq_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmseq_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: vmsle.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: vmsle.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: vmsle.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: vmsle.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: vmsle.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: vmsle.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: vmsle.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: vmsle.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
Show All 29 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
Show All 29 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
Show All 29 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,m1,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
Show All 29 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,m2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v10 ; CHECK-NEXT: vmxor.mm v0, v25, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
Show All 29 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsge_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsge_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,m4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v12 ; CHECK-NEXT: vmxor.mm v0, v25, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
Show All 29 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
Show All 29 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
Show All 29 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
Show All 29 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,m2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v10 ; CHECK-NEXT: vmxor.mm v0, v25, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
Show All 29 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,m4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v12 ; CHECK-NEXT: vmxor.mm v0, v25, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
Show All 29 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
Show All 29 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32,m1,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
Show All 29 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32,m2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v10 ; CHECK-NEXT: vmxor.mm v0, v25, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
Show All 29 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32,m4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v12 ; CHECK-NEXT: vmxor.mm v0, v25, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
Show All 40 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vv v25, v26, v8, v0.t ; CHECK-NEXT: vmsle.vv v25, v26, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vv v25, v26, v8, v0.t ; CHECK-NEXT: vmsle.vv v25, v26, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vlse64.v v28, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vv v25, v28, v8, v0.t ; CHECK-NEXT: vmsle.vv v25, v28, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, -15, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, -15, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, -13, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, -13, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, -11, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, -11, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, -9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, -9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vi v25, v8, -7, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, -7, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsge_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsge_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vi v25, v8, -5, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, -5, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, -3, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, -3, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, -1, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, -1, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 0, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vi v25, v8, 2, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 2, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vi v25, v8, 4, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 4, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 6, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 6, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vi v25, v8, 10, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vi v25, v8, 12, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
▲ Show 20 Lines • Show All 279 Lines • ▼ Show 20 Lines
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vlse64.v v25, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vmsle.vv v0, v25, v8, v0.t ; CHECK-NEXT: vmsle.vv v0, v25, v8, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3) i32 %3)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu
; CHECK-NEXT: vmsle.vv v25, v26, v8, v0.t ; CHECK-NEXT: vmsle.vv v25, v26, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 9 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vlse64.v v28, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmsle.vv v25, v28, v8, v0.t ; CHECK-NEXT: vmsle.vv v25, v28, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3) i32 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: vmsle.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: vmsle.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: vmsle.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: vmsle.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: vmsle.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: vmsle.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: vmsle.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: vmsle.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
Show All 29 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
Show All 29 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
Show All 29 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,m1,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
Show All 29 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,m2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v10 ; CHECK-NEXT: vmxor.mm v0, v25, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
Show All 29 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsge_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsge_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,m4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v12 ; CHECK-NEXT: vmxor.mm v0, v25, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
Show All 29 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
Show All 29 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
Show All 29 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
Show All 29 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,m2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v10 ; CHECK-NEXT: vmxor.mm v0, v25, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
Show All 29 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,m4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v12 ; CHECK-NEXT: vmxor.mm v0, v25, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
Show All 29 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
Show All 29 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32,m1,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
Show All 29 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32,m2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v10 ; CHECK-NEXT: vmxor.mm v0, v25, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
Show All 29 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32,m4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v12 ; CHECK-NEXT: vmxor.mm v0, v25, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
Show All 29 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
Show All 29 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64,m2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v10 ; CHECK-NEXT: vmxor.mm v0, v25, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
Show All 29 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64,m4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v12 ; CHECK-NEXT: vmxor.mm v0, v25, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
Show All 16 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, -15, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, -15, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, -13, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, -13, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, -11, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, -11, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, -9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, -9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vi v25, v8, -7, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, -7, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsge_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsge_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vi v25, v8, -5, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, -5, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, -3, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, -3, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, -1, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, -1, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 0, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vi v25, v8, 2, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 2, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vi v25, v8, 4, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 4, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 6, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 6, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vi v25, v8, 10, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vi v25, v8, 12, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 14, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 14, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vi v25, v8, -16, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, -16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vi v25, v8, -14, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, -14, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
▲ Show 20 Lines • Show All 331 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: vmsleu.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: vmsleu.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: vmsleu.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: vmsleu.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: vmsleu.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: vmsleu.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: vmsleu.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: vmsleu.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
Show All 29 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
Show All 29 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
Show All 29 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,m1,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
Show All 29 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,m2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v10 ; CHECK-NEXT: vmxor.mm v0, v25, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
Show All 29 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,m4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v12 ; CHECK-NEXT: vmxor.mm v0, v25, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
Show All 29 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
Show All 29 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
Show All 29 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
Show All 29 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,m2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v10 ; CHECK-NEXT: vmxor.mm v0, v25, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
Show All 29 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,m4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v12 ; CHECK-NEXT: vmxor.mm v0, v25, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
Show All 29 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
Show All 29 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32,m1,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
Show All 29 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32,m2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v10 ; CHECK-NEXT: vmxor.mm v0, v25, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
Show All 29 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32,m4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v12 ; CHECK-NEXT: vmxor.mm v0, v25, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
Show All 40 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vv v25, v26, v8, v0.t ; CHECK-NEXT: vmsleu.vv v25, v26, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vv v25, v26, v8, v0.t ; CHECK-NEXT: vmsleu.vv v25, v26, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vlse64.v v28, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vv v25, v28, v8, v0.t ; CHECK-NEXT: vmsleu.vv v25, v28, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, -15, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, -15, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, -13, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, -13, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, -11, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, -11, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, -9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, -9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, -7, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, -7, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, -5, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, -5, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, -3, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, -3, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vv v25, v8, v8, v0.t ; CHECK-NEXT: vmseq.vv v25, v8, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 0, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, 2, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 2, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, 4, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 4, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 6, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 6, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 8, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, 10, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, 12, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 14, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 14, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, -16, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, -16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, -14, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, -14, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
▲ Show 20 Lines • Show All 279 Lines • ▼ Show 20 Lines
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vlse64.v v25, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vmsleu.vv v0, v25, v8, v0.t ; CHECK-NEXT: vmsleu.vv v0, v25, v8, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3) i32 %3)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu
; CHECK-NEXT: vmsleu.vv v25, v26, v8, v0.t ; CHECK-NEXT: vmsleu.vv v25, v26, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 9 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vlse64.v v28, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmsleu.vv v25, v28, v8, v0.t ; CHECK-NEXT: vmsleu.vv v25, v28, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3) i32 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: vmsleu.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: vmsleu.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: vmsleu.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: vmsleu.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: vmsleu.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: vmsleu.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: vmsleu.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: vmsleu.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 32 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
Show All 29 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
Show All 29 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
Show All 29 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,m1,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
Show All 29 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,m2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v10 ; CHECK-NEXT: vmxor.mm v0, v25, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
Show All 29 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8,m4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v12 ; CHECK-NEXT: vmxor.mm v0, v25, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
Show All 29 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
Show All 29 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
Show All 29 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
Show All 29 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,m2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v10 ; CHECK-NEXT: vmxor.mm v0, v25, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
Show All 29 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16,m4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v12 ; CHECK-NEXT: vmxor.mm v0, v25, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
Show All 29 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
Show All 29 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32,m1,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
Show All 29 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32,m2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v10 ; CHECK-NEXT: vmxor.mm v0, v25, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
Show All 29 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32,m4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v12 ; CHECK-NEXT: vmxor.mm v0, v25, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
Show All 29 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v9 ; CHECK-NEXT: vmxor.mm v0, v25, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
Show All 29 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64,m2,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v10 ; CHECK-NEXT: vmxor.mm v0, v25, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
Show All 29 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64,m4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v12 ; CHECK-NEXT: vmxor.mm v0, v25, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
Show All 16 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, -15, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, -15, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, -13, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, -13, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, -11, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, -11, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, -9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, -9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, -7, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, -7, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, -5, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, -5, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, -3, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, -3, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vv v25, v8, v8, v0.t ; CHECK-NEXT: vmseq.vv v25, v8, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 0, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, 2, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 2, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, 4, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 4, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 6, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 6, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 8, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, 10, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, 12, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 14, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 14, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, -16, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, -16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, -14, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, -14, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
▲ Show 20 Lines • Show All 331 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v10, v8 ; CHECK-NEXT: vmslt.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v12, v8 ; CHECK-NEXT: vmslt.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v10, v8 ; CHECK-NEXT: vmslt.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v12, v8 ; CHECK-NEXT: vmslt.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v10, v8 ; CHECK-NEXT: vmslt.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v12, v8 ; CHECK-NEXT: vmslt.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v10, v8 ; CHECK-NEXT: vmslt.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v12, v8 ; CHECK-NEXT: vmslt.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vv v25, v26, v8, v0.t ; CHECK-NEXT: vmslt.vv v25, v26, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vv v25, v26, v8, v0.t ; CHECK-NEXT: vmslt.vv v25, v26, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vlse64.v v28, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vv v25, v28, v8, v0.t ; CHECK-NEXT: vmslt.vv v25, v28, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v10, v8 ; CHECK-NEXT: vmslt.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v12, v8 ; CHECK-NEXT: vmslt.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v10, v8 ; CHECK-NEXT: vmslt.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v12, v8 ; CHECK-NEXT: vmslt.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v10, v8 ; CHECK-NEXT: vmslt.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v12, v8 ; CHECK-NEXT: vmslt.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v10, v8 ; CHECK-NEXT: vmslt.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v12, v8 ; CHECK-NEXT: vmslt.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v10, v8 ; CHECK-NEXT: vmsltu.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v12, v8 ; CHECK-NEXT: vmsltu.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v10, v8 ; CHECK-NEXT: vmsltu.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v12, v8 ; CHECK-NEXT: vmsltu.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v10, v8 ; CHECK-NEXT: vmsltu.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v12, v8 ; CHECK-NEXT: vmsltu.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v10, v8 ; CHECK-NEXT: vmsltu.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v12, v8 ; CHECK-NEXT: vmsltu.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vv v25, v26, v8, v0.t ; CHECK-NEXT: vmsltu.vv v25, v26, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vv v25, v26, v8, v0.t ; CHECK-NEXT: vmsltu.vv v25, v26, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vlse64.v v28, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vv v25, v28, v8, v0.t ; CHECK-NEXT: vmsltu.vv v25, v28, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v10, v8 ; CHECK-NEXT: vmsltu.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v12, v8 ; CHECK-NEXT: vmsltu.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v10, v8 ; CHECK-NEXT: vmsltu.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v12, v8 ; CHECK-NEXT: vmsltu.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v10, v8 ; CHECK-NEXT: vmsltu.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v12, v8 ; CHECK-NEXT: vmsltu.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v25, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v10, v8 ; CHECK-NEXT: vmsltu.vv v25, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v12, v8 ; CHECK-NEXT: vmsltu.vv v25, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v10 ; CHECK-NEXT: vmsle.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v12 ; CHECK-NEXT: vmsle.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v10 ; CHECK-NEXT: vmsle.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v12 ; CHECK-NEXT: vmsle.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v10 ; CHECK-NEXT: vmsle.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v12 ; CHECK-NEXT: vmsle.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v10 ; CHECK-NEXT: vmsle.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v12 ; CHECK-NEXT: vmsle.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsle_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsle_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vv v25, v8, v26, v0.t ; CHECK-NEXT: vmsle.vv v25, v8, v26, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vv v25, v8, v26, v0.t ; CHECK-NEXT: vmsle.vv v25, v8, v26, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vlse64.v v28, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vv v25, v8, v28, v0.t ; CHECK-NEXT: vmsle.vv v25, v8, v28, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsle_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsle_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v10 ; CHECK-NEXT: vmsle.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v12 ; CHECK-NEXT: vmsle.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v10 ; CHECK-NEXT: vmsle.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v12 ; CHECK-NEXT: vmsle.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v10 ; CHECK-NEXT: vmsle.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v12 ; CHECK-NEXT: vmsle.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v10 ; CHECK-NEXT: vmsle.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmsle.vv v0, v8, v12 ; CHECK-NEXT: vmsle.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsle.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsle.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsle_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsle_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsle_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsle_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v10 ; CHECK-NEXT: vmsleu.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v12 ; CHECK-NEXT: vmsleu.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v10 ; CHECK-NEXT: vmsleu.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v12 ; CHECK-NEXT: vmsleu.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v10 ; CHECK-NEXT: vmsleu.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v12 ; CHECK-NEXT: vmsleu.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v10 ; CHECK-NEXT: vmsleu.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v12 ; CHECK-NEXT: vmsleu.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vv v25, v8, v26, v0.t ; CHECK-NEXT: vmsleu.vv v25, v8, v26, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vv v25, v8, v26, v0.t ; CHECK-NEXT: vmsleu.vv v25, v8, v26, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vlse64.v v28, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vv v25, v8, v28, v0.t ; CHECK-NEXT: vmsleu.vv v25, v8, v28, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v10 ; CHECK-NEXT: vmsleu.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v12 ; CHECK-NEXT: vmsleu.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v10 ; CHECK-NEXT: vmsleu.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v12 ; CHECK-NEXT: vmsleu.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v10 ; CHECK-NEXT: vmsleu.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v12 ; CHECK-NEXT: vmsleu.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v10 ; CHECK-NEXT: vmsleu.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmsleu.vv v0, v8, v12 ; CHECK-NEXT: vmsleu.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsleu.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsleu.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v10 ; CHECK-NEXT: vmslt.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v12 ; CHECK-NEXT: vmslt.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v10 ; CHECK-NEXT: vmslt.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v12 ; CHECK-NEXT: vmslt.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v10 ; CHECK-NEXT: vmslt.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v12 ; CHECK-NEXT: vmslt.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v10 ; CHECK-NEXT: vmslt.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v12 ; CHECK-NEXT: vmslt.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmslt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmslt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vv v25, v8, v26, v0.t ; CHECK-NEXT: vmslt.vv v25, v8, v26, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vv v25, v8, v26, v0.t ; CHECK-NEXT: vmslt.vv v25, v8, v26, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vlse64.v v28, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vv v25, v8, v28, v0.t ; CHECK-NEXT: vmslt.vv v25, v8, v28, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, -15, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, -15, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, -13, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, -13, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, -11, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, -11, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, -9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, -9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vi v25, v8, -7, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, -7, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmslt_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmslt_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vi v25, v8, -5, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, -5, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, -3, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, -3, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, -1, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, -1, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 0, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vi v25, v8, 2, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 2, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vi v25, v8, 4, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 4, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 6, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 6, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vi v25, v8, 10, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vi v25, v8, 12, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v10 ; CHECK-NEXT: vmslt.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v12 ; CHECK-NEXT: vmslt.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v10 ; CHECK-NEXT: vmslt.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v12 ; CHECK-NEXT: vmslt.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v10 ; CHECK-NEXT: vmslt.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v12 ; CHECK-NEXT: vmslt.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v10 ; CHECK-NEXT: vmslt.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmslt.vv v0, v8, v12 ; CHECK-NEXT: vmslt.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmslt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmslt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmslt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmslt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, -15, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, -15, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, -13, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, -13, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, -11, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, -11, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, -9, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, -9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vi v25, v8, -7, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, -7, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmslt_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmslt_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vi v25, v8, -5, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, -5, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, -3, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, -3, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, -1, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, -1, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 0, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vi v25, v8, 2, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 2, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vi v25, v8, 4, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 4, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 6, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 6, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vi v25, v8, 10, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vi v25, v8, 12, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v25, v8, 14, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, 14, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vi v25, v8, -16, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, -16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vi v25, v8, -14, v0.t ; CHECK-NEXT: vmsle.vi v25, v8, -14, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 -13, i64 -13,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v10 ; CHECK-NEXT: vmsltu.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v12 ; CHECK-NEXT: vmsltu.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v10 ; CHECK-NEXT: vmsltu.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v12 ; CHECK-NEXT: vmsltu.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v10 ; CHECK-NEXT: vmsltu.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v12 ; CHECK-NEXT: vmsltu.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v10 ; CHECK-NEXT: vmsltu.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v12 ; CHECK-NEXT: vmsltu.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vv v25, v8, v26, v0.t ; CHECK-NEXT: vmsltu.vv v25, v8, v26, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vv v25, v8, v26, v0.t ; CHECK-NEXT: vmsltu.vv v25, v8, v26, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vlse64.v v28, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vv v25, v8, v28, v0.t ; CHECK-NEXT: vmsltu.vv v25, v8, v28, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, -15, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, -15, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, -13, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, -13, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, -11, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, -11, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, -9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, -9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vi v25, v8, -7, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, -7, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vi v25, v8, -5, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, -5, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, -3, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, -3, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vv v25, v8, v8, v0.t ; CHECK-NEXT: vmsne.vv v25, v8, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 0, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vi v25, v8, 2, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 2, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vi v25, v8, 4, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 4, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 6, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 6, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 8, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vi v25, v8, 10, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vi v25, v8, 12, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 14, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 14, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vi v25, v8, -16, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, -16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vi v25, v8, -14, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, -14, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 -13, i64 -13,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v10 ; CHECK-NEXT: vmsltu.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v12 ; CHECK-NEXT: vmsltu.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v10 ; CHECK-NEXT: vmsltu.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v12 ; CHECK-NEXT: vmsltu.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v10 ; CHECK-NEXT: vmsltu.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v12 ; CHECK-NEXT: vmsltu.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v10 ; CHECK-NEXT: vmsltu.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmsltu.vv v0, v8, v12 ; CHECK-NEXT: vmsltu.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsltu.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsltu.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64(
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64(
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64(
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, -15, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, -15, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, -13, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, -13, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, -11, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, -11, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, -9, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, -9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vi v25, v8, -7, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, -7, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vi v25, v8, -5, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, -5, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, -3, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, -3, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vv v25, v8, v8, v0.t ; CHECK-NEXT: vmsne.vv v25, v8, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 0, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vi v25, v8, 2, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 2, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vi v25, v8, 4, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 4, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 6, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 6, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 8, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 8, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vi v25, v8, 10, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vi v25, v8, 12, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vi v25, v8, 14, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, 14, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vi v25, v8, -16, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, -16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vi v25, v8, -14, v0.t ; CHECK-NEXT: vmsleu.vi v25, v8, -14, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 -13, i64 -13,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v10 ; CHECK-NEXT: vmsne.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v12 ; CHECK-NEXT: vmsne.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v10 ; CHECK-NEXT: vmsne.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v12 ; CHECK-NEXT: vmsne.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v10 ; CHECK-NEXT: vmsne.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v12 ; CHECK-NEXT: vmsne.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v10 ; CHECK-NEXT: vmsne.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v12 ; CHECK-NEXT: vmsne.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsne_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsne_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vv v25, v8, v26, v0.t ; CHECK-NEXT: vmsne.vv v25, v8, v26, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vv v25, v8, v26, v0.t ; CHECK-NEXT: vmsne.vv v25, v8, v26, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vlse64.v v28, (a0), zero
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vv v25, v8, v28, v0.t ; CHECK-NEXT: vmsne.vv v25, v8, v28, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsne_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsne_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll

Show All 25 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v10 ; CHECK-NEXT: vmsne.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e8,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v12 ; CHECK-NEXT: vmsne.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e8,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v10 ; CHECK-NEXT: vmsne.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v12 ; CHECK-NEXT: vmsne.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v10 ; CHECK-NEXT: vmsne.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v12 ; CHECK-NEXT: vmsne.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v25, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v10 ; CHECK-NEXT: vmsne.vv v25, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmsne.vv v0, v8, v12 ; CHECK-NEXT: vmsne.vv v25, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu ; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmsne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmsne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
Show All 31 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 30 Linesdeclare <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsne_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsne_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 30 Linesdeclare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 30 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 30 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 30 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 30 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsne_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsne_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
Show All 18 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 18 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t ; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }