[RISCV] Fix operand order in fixed-length VM(OR|AND)NOT patterns

[frasercrmck]

Summary

Where the RVV specification writes vs2, vs1, our TableGen patterns use
rs1, rs2. These differences can easily cause confusion. The VMANDNOT
instruction performs LHS && !RHS, and similarly for VMORNOT.

[frasercrmck]

Should we try and get this into the 12.0.1 release?

[craig.topper]

LGTM. Let's try to get it into the 12.0.1 release.

[jrtc27]

Does the vs2, vs1 operand order in the spec make sense? Would vs1, vs2 not be more natural?

[frasercrmck]

In D102606#2764127, @craig.topper wrote:

LGTM. Let's try to get it into the 12.0.1 release.

My bad, it seems that the 12 release doesn't have the fixed-length RVV support. Time flies.

In D102606#2764964, @jrtc27 wrote:

Does the vs2, vs1 operand order in the spec make sense? Would vs1, vs2 not be more natural?

To me, vs1,vs2 would certainly be more natural and it is indeed vs1,vs2 in a select few operations. To be honest, I can't think of a way that it has to be the way it is. Perhaps it's more consistent and requires fewer unique operand names across the full instruction set.

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, VR:$rs2, VLOpFrag)),
                  VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;
   def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, VR:$rs2, VLOpFrag)),
             (!cast<Instruction>("PseudoVMOR_MM_" # mti.LMul.MX)
                  VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;
   def : Pat<(mti.Mask (riscv_vmxor_vl VR:$rs1, VR:$rs2, VLOpFrag)),
             (!cast<Instruction>("PseudoVMXOR_MM_" # mti.LMul.MX)
                  VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;
 
-  def : Pat<(mti.Mask (riscv_vmand_vl (riscv_vmnot_vl VR:$rs1,
-                                                      VLOpFrag),
-                                      VR:$rs2, VLOpFrag)),
+  def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1,
+                                      (riscv_vmnot_vl VR:$rs2, VLOpFrag),
+                                      VLOpFrag)),
             (!cast<Instruction>("PseudoVMANDNOT_MM_" # mti.LMul.MX)
                  VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;
-  def : Pat<(mti.Mask (riscv_vmor_vl (riscv_vmnot_vl VR:$rs1,
-                                                     VLOpFrag),
-                                     VR:$rs2, VLOpFrag)),
+  def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1,
+                                     (riscv_vmnot_vl VR:$rs2, VLOpFrag),
+                                     VLOpFrag)),
             (!cast<Instruction>("PseudoVMORNOT_MM_" # mti.LMul.MX)
                  VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;
   // XOR is associative so we need 2 patterns for VMXNOR.
   def : Pat<(mti.Mask (riscv_vmxor_vl (riscv_vmnot_vl VR:$rs1,
                                                       VLOpFrag),
                                      VR:$rs2, VLOpFrag)),
             (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX)
                  VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll

 }
 
 define void @andnot_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
 ; CHECK-LABEL: andnot_v8i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vle1.v v25, (a0)
 ; CHECK-NEXT:    vle1.v v26, (a1)
-; CHECK-NEXT:    vmandnot.mm v25, v25, v26
+; CHECK-NEXT:    vmandnot.mm v25, v26, v25
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = load <8 x i1>, <8 x i1>* %x
   %b = load <8 x i1>, <8 x i1>* %y
   %c = xor <8 x i1> %a, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
   %d = and <8 x i1> %b, %c
   store <8 x i1> %d, <8 x i1>* %x
   ret void
 }
 
 define void @ornot_v16i1(<16 x i1>* %x, <16 x i1>* %y) {
 ; CHECK-LABEL: ornot_v16i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a2, 16, e8,m1,ta,mu
 ; CHECK-NEXT:    vle1.v v25, (a0)
 ; CHECK-NEXT:    vle1.v v26, (a1)
-; CHECK-NEXT:    vmornot.mm v25, v25, v26
+; CHECK-NEXT:    vmornot.mm v25, v26, v25
 ; CHECK-NEXT:    vse1.v v25, (a0)
 ; CHECK-NEXT:    ret
   %a = load <16 x i1>, <16 x i1>* %x
   %b = load <16 x i1>, <16 x i1>* %y
   %c = xor <16 x i1> %a, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
   %d = or <16 x i1> %b, %c
   store <16 x i1> %d, <16 x i1>* %x
   ret void

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll

 ; CHECK-NEXT:    addi a1, zero, 1
 ; CHECK-NEXT:    bnez a0, .LBB0_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a1, zero
 ; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    vsetivli a0, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a1
 ; CHECK-NEXT:    vmsne.vi v26, v25, 0
-; CHECK-NEXT:    vmandnot.mm v25, v26, v8
+; CHECK-NEXT:    vmandnot.mm v25, v8, v26
 ; CHECK-NEXT:    vmand.mm v26, v0, v26
 ; CHECK-NEXT:    vmor.mm v0, v26, v25
 ; CHECK-NEXT:    ret
   %v = select i1 %c, <1 x i1> %a, <1 x i1> %b
   ret <1 x i1> %v
 }
 
 define <1 x i1> @selectcc_v1i1(i1 signext %a, i1 signext %b, <1 x i1> %c, <1 x i1> %d) {
 ; CHECK-LABEL: selectcc_v1i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor a0, a0, a1
 ; CHECK-NEXT:    andi a1, a0, 1
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    bnez a1, .LBB1_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a0, zero
 ; CHECK-NEXT:  .LBB1_2:
 ; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vmsne.vi v26, v25, 0
-; CHECK-NEXT:    vmandnot.mm v25, v26, v8
+; CHECK-NEXT:    vmandnot.mm v25, v8, v26
 ; CHECK-NEXT:    vmand.mm v26, v0, v26
 ; CHECK-NEXT:    vmor.mm v0, v26, v25
 ; CHECK-NEXT:    ret
   %cmp = icmp ne i1 %a, %b
   %v = select i1 %cmp, <1 x i1> %c, <1 x i1> %d
   ret <1 x i1> %v
 }
 
 define <2 x i1> @select_v2i1(i1 zeroext %c, <2 x i1> %a, <2 x i1> %b) {
 ; CHECK-LABEL: select_v2i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 1
 ; CHECK-NEXT:    bnez a0, .LBB2_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a1, zero
 ; CHECK-NEXT:  .LBB2_2:
 ; CHECK-NEXT:    vsetivli a0, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a1
 ; CHECK-NEXT:    vmsne.vi v26, v25, 0
-; CHECK-NEXT:    vmandnot.mm v25, v26, v8
+; CHECK-NEXT:    vmandnot.mm v25, v8, v26
 ; CHECK-NEXT:    vmand.mm v26, v0, v26
 ; CHECK-NEXT:    vmor.mm v0, v26, v25
 ; CHECK-NEXT:    ret
   %v = select i1 %c, <2 x i1> %a, <2 x i1> %b
   ret <2 x i1> %v
 }
 
 define <2 x i1> @selectcc_v2i1(i1 signext %a, i1 signext %b, <2 x i1> %c, <2 x i1> %d) {
 ; CHECK-LABEL: selectcc_v2i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor a0, a0, a1
 ; CHECK-NEXT:    andi a1, a0, 1
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    bnez a1, .LBB3_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a0, zero
 ; CHECK-NEXT:  .LBB3_2:
 ; CHECK-NEXT:    vsetivli a1, 2, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vmsne.vi v26, v25, 0
-; CHECK-NEXT:    vmandnot.mm v25, v26, v8
+; CHECK-NEXT:    vmandnot.mm v25, v8, v26
 ; CHECK-NEXT:    vmand.mm v26, v0, v26
 ; CHECK-NEXT:    vmor.mm v0, v26, v25
 ; CHECK-NEXT:    ret
   %cmp = icmp ne i1 %a, %b
   %v = select i1 %cmp, <2 x i1> %c, <2 x i1> %d
   ret <2 x i1> %v
 }
 
 define <4 x i1> @select_v4i1(i1 zeroext %c, <4 x i1> %a, <4 x i1> %b) {
 ; CHECK-LABEL: select_v4i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 1
 ; CHECK-NEXT:    bnez a0, .LBB4_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a1, zero
 ; CHECK-NEXT:  .LBB4_2:
 ; CHECK-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a1
 ; CHECK-NEXT:    vmsne.vi v26, v25, 0
-; CHECK-NEXT:    vmandnot.mm v25, v26, v8
+; CHECK-NEXT:    vmandnot.mm v25, v8, v26
 ; CHECK-NEXT:    vmand.mm v26, v0, v26
 ; CHECK-NEXT:    vmor.mm v0, v26, v25
 ; CHECK-NEXT:    ret
   %v = select i1 %c, <4 x i1> %a, <4 x i1> %b
   ret <4 x i1> %v
 }
 
 define <4 x i1> @selectcc_v4i1(i1 signext %a, i1 signext %b, <4 x i1> %c, <4 x i1> %d) {
 ; CHECK-LABEL: selectcc_v4i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor a0, a0, a1
 ; CHECK-NEXT:    andi a1, a0, 1
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    bnez a1, .LBB5_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a0, zero
 ; CHECK-NEXT:  .LBB5_2:
 ; CHECK-NEXT:    vsetivli a1, 4, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vmsne.vi v26, v25, 0
-; CHECK-NEXT:    vmandnot.mm v25, v26, v8
+; CHECK-NEXT:    vmandnot.mm v25, v8, v26
 ; CHECK-NEXT:    vmand.mm v26, v0, v26
 ; CHECK-NEXT:    vmor.mm v0, v26, v25
 ; CHECK-NEXT:    ret
   %cmp = icmp ne i1 %a, %b
   %v = select i1 %cmp, <4 x i1> %c, <4 x i1> %d
   ret <4 x i1> %v
 }
 
 define <8 x i1> @select_v8i1(i1 zeroext %c, <8 x i1> %a, <8 x i1> %b) {
 ; CHECK-LABEL: select_v8i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 1
 ; CHECK-NEXT:    bnez a0, .LBB6_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a1, zero
 ; CHECK-NEXT:  .LBB6_2:
 ; CHECK-NEXT:    vsetivli a0, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a1
 ; CHECK-NEXT:    vmsne.vi v26, v25, 0
-; CHECK-NEXT:    vmandnot.mm v25, v26, v8
+; CHECK-NEXT:    vmandnot.mm v25, v8, v26
 ; CHECK-NEXT:    vmand.mm v26, v0, v26
 ; CHECK-NEXT:    vmor.mm v0, v26, v25
 ; CHECK-NEXT:    ret
   %v = select i1 %c, <8 x i1> %a, <8 x i1> %b
   ret <8 x i1> %v
 }
 
 define <8 x i1> @selectcc_v8i1(i1 signext %a, i1 signext %b, <8 x i1> %c, <8 x i1> %d) {
 ; CHECK-LABEL: selectcc_v8i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor a0, a0, a1
 ; CHECK-NEXT:    andi a1, a0, 1
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    bnez a1, .LBB7_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a0, zero
 ; CHECK-NEXT:  .LBB7_2:
 ; CHECK-NEXT:    vsetivli a1, 8, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vmsne.vi v26, v25, 0
-; CHECK-NEXT:    vmandnot.mm v25, v26, v8
+; CHECK-NEXT:    vmandnot.mm v25, v8, v26
 ; CHECK-NEXT:    vmand.mm v26, v0, v26
 ; CHECK-NEXT:    vmor.mm v0, v26, v25
 ; CHECK-NEXT:    ret
   %cmp = icmp ne i1 %a, %b
   %v = select i1 %cmp, <8 x i1> %c, <8 x i1> %d
   ret <8 x i1> %v
 }
 
 define <16 x i1> @select_v16i1(i1 zeroext %c, <16 x i1> %a, <16 x i1> %b) {
 ; CHECK-LABEL: select_v16i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a1, zero, 1
 ; CHECK-NEXT:    bnez a0, .LBB8_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a1, zero
 ; CHECK-NEXT:  .LBB8_2:
 ; CHECK-NEXT:    vsetivli a0, 16, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a1
 ; CHECK-NEXT:    vmsne.vi v26, v25, 0
-; CHECK-NEXT:    vmandnot.mm v25, v26, v8
+; CHECK-NEXT:    vmandnot.mm v25, v8, v26
 ; CHECK-NEXT:    vmand.mm v26, v0, v26
 ; CHECK-NEXT:    vmor.mm v0, v26, v25
 ; CHECK-NEXT:    ret
   %v = select i1 %c, <16 x i1> %a, <16 x i1> %b
   ret <16 x i1> %v
 }
 
 define <16 x i1> @selectcc_v16i1(i1 signext %a, i1 signext %b, <16 x i1> %c, <16 x i1> %d) {
 ; CHECK-LABEL: selectcc_v16i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor a0, a0, a1
 ; CHECK-NEXT:    andi a1, a0, 1
 ; CHECK-NEXT:    addi a0, zero, 1
 ; CHECK-NEXT:    bnez a1, .LBB9_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a0, zero
 ; CHECK-NEXT:  .LBB9_2:
 ; CHECK-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vmsne.vi v26, v25, 0
-; CHECK-NEXT:    vmandnot.mm v25, v26, v8
+; CHECK-NEXT:    vmandnot.mm v25, v8, v26
 ; CHECK-NEXT:    vmand.mm v26, v0, v26
 ; CHECK-NEXT:    vmor.mm v0, v26, v25
 ; CHECK-NEXT:    ret
   %cmp = icmp ne i1 %a, %b
   %v = select i1 %cmp, <16 x i1> %c, <16 x i1> %d
   ret <16 x i1> %v
 }