Page MenuHomePhabricator

[AArch64][SVE] Fix isel failure for FP-extending loads
ClosedPublic

Authored by sdesmalen on May 7 2021, 1:13 AM.

Details

Summary

DAGCombiner tries to combine a (fpext (load)) to (fround (extload))
but SVE has no FP-extending loads. By marking these as expand,
the combine no longer happens.

This also fixes a similar issue for fptrunc, where the source type
is not a legal type.

Diff Detail

Event Timeline

sdesmalen created this revision.May 7 2021, 1:13 AM
sdesmalen requested review of this revision.May 7 2021, 1:13 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 7 2021, 1:13 AM
bsmith added a comment.May 7 2021, 3:35 AM

Does the same issue also apply to fixed length codegen?

Does the same issue also apply to fixed length codegen?

Existing code (in same function under hasNeon()) already sets this to Expand for all fixed-width vectors.

bsmith accepted this revision.May 7 2021, 3:51 AM

Does the same issue also apply to fixed length codegen?

Existing code (in same function under hasNeon()) already sets this to Expand for all fixed-width vectors.

In that case, LGTM, thanks!

This revision is now accepted and ready to land.May 7 2021, 3:51 AM
This revision was automatically updated to reflect the committed changes.