[MC][RISCV] Add RISCV MCObjectFileInfo

[flip1995]

Summary

This makes sure, that the text section will have a 2-byte alignment, if
the +c extension is enabled.

[luismarques]

The banners were copied from other files but not updated to match the new file.

IIRC no one was opposed to this alignment change when we discussed it in a recent RISC-V sync-up call, but let's give it some time for more people to chime in.

llvm/test/MC/RISCV/align.s

41

enable -> enabled

[flip1995]

rebased

[MaskRay]

llvm/lib/MC/MCObjectFileInfo.cpp

965 ↗

(On Diff #347640)

{}

= default doesn't change the fact that it is user-defined. IMHO {} is the prevailing style.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.cpp

22

Use just one variable. Don't keep Ctx

24

Drop braces around simple statements.

Just use ? :

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.h

20

Is this used?

[flip1995]

addressed review comments and rebased

[flip1995]

Fixed clang-tidy error

[MaskRay]

riscv64-linux-gnu-as -march=rv64gc a.s does use 2-byte alignment, so I think this may be fine.

I just cannot find sufficient justification for such a change.

[flip1995]

I just cannot find sufficient justification for such a change.

So besides getting the same behavior between GCC and LLVM, this change also improves code size for RISC-V. This is because there doesn't have to be padding added between functions, if they aren't 4 byte aligned.

[flip1995]

ping

[MaskRay]

Ping other reviewers. Personally I think the necessity is unclear.

[asb]

I'd be inclined to accept this on the basis that wherever it's not overly burdensome I've typically tried to match our output to GCC (mainly to avoid wasting time looking at irrelevant differences), and the change itself seems uncomplicated.

@flip1995: thanks for your patience, could you please rebase as this doesn't apply cleanly against current main.

If anyone has strong concerns about landing this, please speak up now!

[flip1995]

Rebased

[MaskRay]

LGTM.

[flip1995]

Rebased + Formatted

llvm/lib/Target/RISCV/MCTargetDesc/CMakeLists.txt

 add_llvm_component_library(LLVMRISCVDesc
   RISCVAsmBackend.cpp
   RISCVBaseInfo.cpp
   RISCVELFObjectWriter.cpp
   RISCVInstPrinter.cpp
   RISCVMCAsmInfo.cpp
   RISCVMCCodeEmitter.cpp
   RISCVMCExpr.cpp
+  RISCVMCObjectFileInfo.cpp
   RISCVMCTargetDesc.cpp
   RISCVMatInt.cpp
   RISCVTargetStreamer.cpp
   RISCVELFStreamer.cpp
 
   LINK_COMPONENTS
   MC
   RISCVInfo
   Support
 
   ADD_TO_COMPONENT
   RISCV
 )

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.h

+//===-- RISCVMCAsmInfo.h - RISCV Asm Info ----------------------*- C++ -*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the declaration of the RISCVMCAsmInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCOBJECTFILEINFO_H
+#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCOBJECTFILEINFO_H
+
+#include "llvm/MC/MCObjectFileInfo.h"
+
+namespace llvm {
+class Triple;
+
+class RISCVMCObjectFileInfo : public MCObjectFileInfo {
+public:
+  unsigned getTextSectionAlignment() const;
+};
+
+} // namespace llvm
+
+#endif

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.cpp

+//===-- RISCVMCAsmInfo.cpp - RISCV Asm properties -------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the declarations of the RISCVMCAsmInfo properties.
+//
+//===----------------------------------------------------------------------===//
+
+#include "RISCVMCObjectFileInfo.h"
+#include "RISCVMCTargetDesc.h"
+#include "llvm/MC/MCContext.h"
+
+using namespace llvm;
+
+unsigned RISCVMCObjectFileInfo::getTextSectionAlignment() const {
+  MCContext &Ctx = getContext();
+  const MCSubtargetInfo *STI = Ctx.getSubtargetInfo();
+  if (STI->hasFeature(RISCV::FeatureStdExtC)) {
+    return 2;
+  }
+  return 4;
+}

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp

 ///
 //===----------------------------------------------------------------------===//
 
 #include "RISCVMCTargetDesc.h"
 #include "RISCVBaseInfo.h"
 #include "RISCVELFStreamer.h"
 #include "RISCVInstPrinter.h"
 #include "RISCVMCAsmInfo.h"
+#include "RISCVMCObjectFileInfo.h"
 #include "RISCVTargetStreamer.h"
 #include "TargetInfo/RISCVTargetInfo.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
 #define GET_INSTRINFO_MC_DESC
 #include "RISCVGenInstrInfo.inc"
static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
 
   MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true);
   MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0);
   MAI->addInitialFrameState(Inst);
 
   return MAI;
 }
 
+static MCObjectFileInfo *
+createRISCVMCObjectFileInfo(bool PIC, MCContext &ctx,
+                            bool LargeCodeModel = false) {
+  MCObjectFileInfo *MOFI = new RISCVMCObjectFileInfo();
+  MOFI->InitMCObjectFileInfo(PIC, ctx, LargeCodeModel);
+  return MOFI;
+}
+
 static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
                                                    StringRef CPU, StringRef FS) {
   if (CPU.empty())
     CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
   if (CPU == "generic")
     report_fatal_error(Twine("CPU 'generic' is not supported. Use ") +
                        (TT.isArch64Bit() ? "generic-rv64" : "generic-rv32"));
   return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);

 
 static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) {
   return new RISCVMCInstrAnalysis(Info);
 }
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
   for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
     TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
+    TargetRegistry::RegisterMCObjectFileInfo(*T, createRISCVMCObjectFileInfo);
     TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
     TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
     TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
     TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
     TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
     TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
     TargetRegistry::RegisterObjectTargetStreamer(
         *T, createRISCVObjectTargetStreamer);

llvm/test/MC/RISCV/align.s

 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,-relax < %s \
 # RUN:     | llvm-readobj -r - | FileCheck -check-prefix=C-EXT-NORELAX-RELOC %s
 
 # We need to insert N-MinNopSize bytes NOPs and R_RISCV_ALIGN relocation
 # type for .align N directive when linker relaxation enabled.
 # Linker could satisfy alignment by removing NOPs after linker relaxation.
 
 # The first R_RISCV_ALIGN come from
-# MCELFStreamer::InitSections() emitCodeAlignment(4).
+# MCELFStreamer::InitSections() emitCodeAlignment(getTextSectionAligntment()).
 # C-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0x2
 # C-EXT-RELAX-INST:  c.nop
 test:
   .p2align 2
-# C-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0x2
-# C-EXT-RELAX-INST:  c.nop
+# If the +c extension is enable, the text section will be 2-byte aligned, so
+# one c.nop instruction is sufficient.
+# C-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN - 0x2
+# C-EXT-RELAX-INST-NOT:  c.nop
   bne     zero, a0, .LBB0_2
   mv  a0, zero
   .p2align 3
 # RELAX-RELOC: R_RISCV_ALIGN - 0x4
 # RELAX-INST:  addi    zero, zero, 0
 # C-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0x6
 # C-EXT-RELAX-INST:  addi    zero, zero, 0
 # C-EXT-RELAX-INST:  c.nop