[PowerPC] Handle inline assembly clobber of link regsiter

[stefanp]

Summary

This patch adds the handling of clobbers of the link register LR for inline
assembly.

This patch is to fix:
https://bugs.llvm.org/show_bug.cgi?id=50147

[nathanchance]

I added this commit on top of a45fd436aef4d5712da99f8292f5d0b16794892c, built a master branch Linux kernel from ppc44x_defconfig, and booted in under QEMU 5.0.1 without any issues as before. Thanks for the quick fix!

[efriedma]

You probably also want the following testcase:

define void @UseLR() {
  tail call void asm sideeffect "", "{lr}"(i32 1)
  ret void
}

[stefanp]

Cleanup the source code according to clang format.

Minor changes for formatting.

[stefanp]

In D101657#2735219, @efriedma wrote:

You probably also want the following testcase:

define void @UseLR() {
  tail call void asm sideeffect "", "{lr}"(i32 1)
  ret void
}

I looked into doing this but PowerPC does not have enough support for special registers (like lr) for us to be able to do this test correctly. The backend does not recognize the copy of the value 1 to the LR register and it does not know how to correctly spill special registers. This is on our TODO list and we will address these issues in a separate patch. Also, at this point, the clang frontend does not recognize the lr register as a valid input register anyway. (This work is also on our TODO list.) The plan is to address both of these deficiencies in future patches.

Basically, if we try this example from C source we get:

$ cat useLR.c

void foo() {
  asm(""
      : 
      : "l"(1));
}

$ clang -O2 -S useLR.c
clang: /data/stefanp/Wyvern/main/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:8657: void llvm::SelectionDAGBuilder::visitInlineAsm(const llvm::CallBase &): Assertion `(OpInfo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType == TargetLowering::C_Register) && "Unknown constraint type!"' failed.
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace, preprocessed source, and associated run script.

We will add this test when we add more support for special regsiters on PowerPC.

[nathanchance]

Is there anything we can do to help get this merged? It would be nice to have this fixed in LLVM 12.0.1, which is going to have its first release candidate soon.

[nemanjai]

LGTM other than the allocatable nit. Let's go with this fix for now to unblock the kernel build and we'll follow-up with a more complete fix for other reserved registers later.

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

413

Should these have the let isAllocatable = 0 as well? Seems like they should.

[stefanp]

Added missing let isAllocatable = 0.

[nickdesaulniers]

llvm/test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll

77–95

@jyknight points out in review of D115688 that something looks fishy with this callbr unit test, and I think he's right (and I'm sorry I didn't catch this earlier in code review).

Let's say the asm string actually writes to lr rather than being simply a nop in this example, hence why it's in the clobber list. In that case, branching to the lr (returning) will not branch to the restored value of lr, but the one updated from the inline asm. I don't think that's correct.

Should the mflr/mtlr "surround" the user supplied asm? Otherwise this looks like a pointless spill+reload on the indirect branch.

[nickdesaulniers]

llvm/test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll

77–95

Looks like prologepilog insertion is where things go wrong, perhaps?

That said, running just this IR function through:

$ llc -mtriple=powerpc64le-unknown-linux-unknown -verify-machineinstrs /android0/llvm-project/llvm/test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll  -ppc-asm-full-reg-names -stop-before=prologepilog -o callbr.mir
$ llc -run-pass=prologepilog callbr.mir -o -

Doesn't produce the same output as

$ llc -mtriple=powerpc64le-unknown-linux-unknown -verify-machineinstrs /android0/llvm-project/llvm/test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll  -ppc-asm-full-reg-names -stop-after=prologepilog -o -

does (when observing the results of prologepilog)...I must be holding MIR wrong. Though it looks like shrink-wrap may also be involved, IIUC?

diff --git a/llvm/lib/CodeGen/ShrinkWrap.cpp b/llvm/lib/CodeGen/ShrinkWrap.cpp
index f89069e9f728..67d6bc249ef9 100644
--- a/llvm/lib/CodeGen/ShrinkWrap.cpp
+++ b/llvm/lib/CodeGen/ShrinkWrap.cpp
@@ -504,6 +504,10 @@ bool ShrinkWrap::runOnMachineFunction(MachineFunction &MF) {
     }
 
     for (const MachineInstr &MI : MBB) {
+      if (MI.getOpcode() == TargetOpcode::INLINEASM_BR) {
+        LLVM_DEBUG(dbgs() << "inlineasm_br prevents shrink-wrapping\n");
+        return false;
+      }
       if (!useOrDefCSROrFI(MI, RS.get()))
         continue;
       // Save (resp. restore) point must dominate (resp. post dominate)

seems to fix this, but I suspect it's overly conservative? Let's discuss in D116424?

llvm/lib/Target/PowerPC/PPCISelLowering.h

private:
     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerGlobalTLSAddressAIX(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerGlobalTLSAddressLinux(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the PPCISelLowering class.
PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
 
   // Match BITREVERSE to customized fast code sequence in the td file.
   setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
   setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
 
   // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
   setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
 
+  // Custom lower inline assembly to check for special registers.
+  setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
+  setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom);
+
   // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
   for (MVT VT : MVT::integer_valuetypes()) {
     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
   }
 
   if (Subtarget.isISA3_0()) {
     setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);

 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
                                                   SelectionDAG &DAG) const {
   if (Subtarget.isAIXABI())
     report_fatal_error("ADJUST_TRAMPOLINE operation is not supported on AIX.");
 
   return Op.getOperand(0);
 }
 
+SDValue PPCTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
+  MachineFunction &MF = DAG.getMachineFunction();
+  PPCFunctionInfo &MFI = *MF.getInfo<PPCFunctionInfo>();
+
+  assert((Op.getOpcode() == ISD::INLINEASM ||
+          Op.getOpcode() == ISD::INLINEASM_BR) &&
+         "Expecting Inline ASM node.");
+
+  // If an LR store is already known to be required then there is not point in
+  // checking this ASM as well.
+  if (MFI.isLRStoreRequired())
+    return Op;
+
+  // Inline ASM nodes have an optional last operand that is an incoming Flag of
+  // type MVT::Glue. We want to ignore this last operand if that is the case.
+  unsigned NumOps = Op.getNumOperands();
+  if (Op.getOperand(NumOps - 1).getValueType() == MVT::Glue)
+    --NumOps;
+
+  // Check all operands that may contain the LR.
+  for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
+    unsigned Flags = cast<ConstantSDNode>(Op.getOperand(i))->getZExtValue();
+    unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
+    ++i; // Skip the ID value.
+
+    switch (InlineAsm::getKind(Flags)) {
+    default:
+      llvm_unreachable("Bad flags!");
+    case InlineAsm::Kind_RegUse:
+    case InlineAsm::Kind_Imm:
+    case InlineAsm::Kind_Mem:
+      i += NumVals;
+      break;
+    case InlineAsm::Kind_Clobber:
+    case InlineAsm::Kind_RegDef:
+    case InlineAsm::Kind_RegDefEarlyClobber: {
+      for (; NumVals; --NumVals, ++i) {
+        Register Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
+        if (Reg != PPC::LR && Reg != PPC::LR8)
+          continue;
+        MFI.setLRStoreRequired();
+        return Op;
+      }
+      break;
+    }
+    }
+  }
+
+  return Op;
+}
+
 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
                                                 SelectionDAG &DAG) const {
   if (Subtarget.isAIXABI())
     report_fatal_error("INIT_TRAMPOLINE operation is not supported on AIX.");
 
   SDValue Chain = Op.getOperand(0);
   SDValue Trmp = Op.getOperand(1); // trampoline
   SDValue FPtr = Op.getOperand(2); // nested function
SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::GlobalTLSAddress:   return LowerGlobalTLSAddress(Op, DAG);
   case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
   case ISD::STRICT_FSETCC:
   case ISD::STRICT_FSETCCS:
   case ISD::SETCC:              return LowerSETCC(Op, DAG);
   case ISD::INIT_TRAMPOLINE:    return LowerINIT_TRAMPOLINE(Op, DAG);
   case ISD::ADJUST_TRAMPOLINE:  return LowerADJUST_TRAMPOLINE(Op, DAG);
 
+  case ISD::INLINEASM:
+  case ISD::INLINEASM_BR:       return LowerINLINEASM(Op, DAG);
   // Variable argument lowering.
   case ISD::VASTART:            return LowerVASTART(Op, DAG);
   case ISD::VAARG:              return LowerVAARG(Op, DAG);
   case ISD::VACOPY:             return LowerVACOPY(Op, DAG);
 
   case ISD::STACKRESTORE:       return LowerSTACKRESTORE(Op, DAG);
   case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
   case ISD::GET_DYNAMIC_AREA_OFFSET:
return std::make_pair(0U, &PPC::CRBITRCRegClass);
              Constraint == "wf" || Constraint == "wi") &&
              Subtarget.hasVSX()) {
     return std::make_pair(0U, &PPC::VSRCRegClass);
   } else if ((Constraint == "ws" || Constraint == "ww") && Subtarget.hasVSX()) {
     if (VT == MVT::f32 && Subtarget.hasP8Vector())
       return std::make_pair(0U, &PPC::VSSRCRegClass);
     else
       return std::make_pair(0U, &PPC::VSFRCRegClass);
+  } else if (Constraint == "lr") {
+    if (VT == MVT::i64)
+      return std::make_pair(0U, &PPC::LR8RCRegClass);
+    else
+      return std::make_pair(0U, &PPC::LRRCRegClass);
   }
 
   // Handle special cases of physical registers that are not properly handled
   // by the base class.
   if (Constraint[0] == '{' && Constraint[Constraint.size() - 1] == '}') {
     // If we name a VSX register, we can't defer to the base class because it
     // will not recognize the correct register (their names will be VSL{0-31}
     // and V{0-31} so they won't match). So we match them here.

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

 // multiple basic blocks.
 def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> {
   let isAllocatable = 0;
 }
 def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> {
   let isAllocatable = 0;
 }
 
+def LRRC : RegisterClass<"PPC", [i32], 32, (add LR)> {
+  let isAllocatable = 0;
+}
+def LR8RC : RegisterClass<"PPC", [i64], 64, (add LR8)> {
+  let isAllocatable = 0;
+}
+
 def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>;
 def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY, XER)> {
   let CopyCost = -1;
 }
 
 let SubRegIndices = [sub_pair0, sub_pair1] in {
   def ACC0 : ACC<0, "acc0", [VSRp0, VSRp1]>, DwarfRegNum<[0, 0]>;
   def ACC1 : ACC<1, "acc1", [VSRp2, VSRp3]>, DwarfRegNum<[0, 0]>;

llvm/test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-unknown -verify-machineinstrs %s \
+; RUN: -ppc-asm-full-reg-names -o - | FileCheck %s --check-prefix=PPC64LE
+; RUN: llc -mtriple=powerpc64-unknown-linux-unknown -verify-machineinstrs %s \
+; RUN: -ppc-asm-full-reg-names -o - | FileCheck %s --check-prefix=PPC64BE
+
+define dso_local void @ClobberLR() local_unnamed_addr #0 {
+; PPC64LE-LABEL: ClobberLR:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    mflr r0
+; PPC64LE-NEXT:    std r0, 16(r1)
+; PPC64LE-NEXT:    stdu r1, -32(r1)
+; PPC64LE-NEXT:    #APP
+; PPC64LE-NEXT:    #NO_APP
+; PPC64LE-NEXT:    addi r1, r1, 32
+; PPC64LE-NEXT:    ld r0, 16(r1)
+; PPC64LE-NEXT:    mtlr r0
+; PPC64LE-NEXT:    blr
+;
+; PPC64BE-LABEL: ClobberLR:
+; PPC64BE:       # %bb.0: # %entry
+; PPC64BE-NEXT:    mflr r0
+; PPC64BE-NEXT:    std r0, 16(r1)
+; PPC64BE-NEXT:    stdu r1, -48(r1)
+; PPC64BE-NEXT:    #APP
+; PPC64BE-NEXT:    #NO_APP
+; PPC64BE-NEXT:    addi r1, r1, 48
+; PPC64BE-NEXT:    ld r0, 16(r1)
+; PPC64BE-NEXT:    mtlr r0
+; PPC64BE-NEXT:    blr
+entry:
+  tail call void asm sideeffect "", "~{lr}"()
+  ret void
+}
+
+define dso_local void @ClobberR5() local_unnamed_addr #0 {
+; PPC64LE-LABEL: ClobberR5:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    #APP
+; PPC64LE-NEXT:    #NO_APP
+; PPC64LE-NEXT:    blr
+;
+; PPC64BE-LABEL: ClobberR5:
+; PPC64BE:       # %bb.0: # %entry
+; PPC64BE-NEXT:    #APP
+; PPC64BE-NEXT:    #NO_APP
+; PPC64BE-NEXT:    blr
+entry:
+  tail call void asm sideeffect "", "~{r5}"()
+  ret void
+}
+
+define dso_local void @ClobberR15() local_unnamed_addr #0 {
+; PPC64LE-LABEL: ClobberR15:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    std r15, -136(r1) # 8-byte Folded Spill
+; PPC64LE-NEXT:    #APP
+; PPC64LE-NEXT:    #NO_APP
+; PPC64LE-NEXT:    ld r15, -136(r1) # 8-byte Folded Reload
+; PPC64LE-NEXT:    blr
+;
+; PPC64BE-LABEL: ClobberR15:
+; PPC64BE:       # %bb.0: # %entry
+; PPC64BE-NEXT:    std r15, -136(r1) # 8-byte Folded Spill
+; PPC64BE-NEXT:    #APP
+; PPC64BE-NEXT:    #NO_APP
+; PPC64BE-NEXT:    ld r15, -136(r1) # 8-byte Folded Reload
+; PPC64BE-NEXT:    blr
+entry:
+  tail call void asm sideeffect "", "~{r15}"()
+  ret void
+}
+
+;; Test for INLINEASM_BR
+define dso_local signext i32 @ClobberLR_BR(i32 signext %in) #0 {
+; PPC64LE-LABEL: ClobberLR_BR:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    #APP
+; PPC64LE-NEXT:    nop
+; PPC64LE-NEXT:    #NO_APP
+; PPC64LE-NEXT:  # %bb.1: # %return
+; PPC64LE-NEXT:    extsw r3, r3
+; PPC64LE-NEXT:    blr
+; PPC64LE-NEXT:  .Ltmp0: # Block address taken
+; PPC64LE-NEXT:  .LBB3_2: # %return_early
+; PPC64LE-NEXT:    mflr r0
+; PPC64LE-NEXT:    std r0, 16(r1)
+; PPC64LE-NEXT:    stdu r1, -32(r1)
+; PPC64LE-NEXT:    li r3, 0
+; PPC64LE-NEXT:    addi r1, r1, 32
+; PPC64LE-NEXT:    ld r0, 16(r1)
+; PPC64LE-NEXT:    mtlr r0
+; PPC64LE-NEXT:    extsw r3, r3
+; PPC64LE-NEXT:    blr
+;
+; PPC64BE-LABEL: ClobberLR_BR:
+; PPC64BE:       # %bb.0: # %entry
+; PPC64BE-NEXT:    #APP
+; PPC64BE-NEXT:    nop
+; PPC64BE-NEXT:    #NO_APP
+; PPC64BE-NEXT:  # %bb.1: # %return
+; PPC64BE-NEXT:    extsw r3, r3
+; PPC64BE-NEXT:    blr
+; PPC64BE-NEXT:  .Ltmp0: # Block address taken
+; PPC64BE-NEXT:  .LBB3_2: # %return_early
+; PPC64BE-NEXT:    mflr r0
+; PPC64BE-NEXT:    std r0, 16(r1)
+; PPC64BE-NEXT:    stdu r1, -48(r1)
+; PPC64BE-NEXT:    li r3, 0
+; PPC64BE-NEXT:    addi r1, r1, 48
+; PPC64BE-NEXT:    ld r0, 16(r1)
+; PPC64BE-NEXT:    mtlr r0
+; PPC64BE-NEXT:    extsw r3, r3
+; PPC64BE-NEXT:    blr
+entry:
+  callbr void asm sideeffect "nop", "X,~{lr}"(i8* blockaddress(@ClobberLR_BR, %return_early))
+          to label %return [label %return_early]
+
+return_early:
+  br label %return
+
+return:
+  %retval.0 = phi i32 [ 0, %return_early ], [ %in, %entry ]
+  ret i32 %retval.0
+}
+
+define dso_local signext i32 @ClobberR5_BR(i32 signext %in) #0 {
+; PPC64LE-LABEL: ClobberR5_BR:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    #APP
+; PPC64LE-NEXT:    nop
+; PPC64LE-NEXT:    #NO_APP
+; PPC64LE-NEXT:  # %bb.1: # %return
+; PPC64LE-NEXT:    extsw r3, r3
+; PPC64LE-NEXT:    blr
+; PPC64LE-NEXT:  .Ltmp1: # Block address taken
+; PPC64LE-NEXT:  .LBB4_2: # %return_early
+; PPC64LE-NEXT:    li r3, 0
+; PPC64LE-NEXT:    extsw r3, r3
+; PPC64LE-NEXT:    blr
+;
+; PPC64BE-LABEL: ClobberR5_BR:
+; PPC64BE:       # %bb.0: # %entry
+; PPC64BE-NEXT:    #APP
+; PPC64BE-NEXT:    nop
+; PPC64BE-NEXT:    #NO_APP
+; PPC64BE-NEXT:  # %bb.1: # %return
+; PPC64BE-NEXT:    extsw r3, r3
+; PPC64BE-NEXT:    blr
+; PPC64BE-NEXT:  .Ltmp1: # Block address taken
+; PPC64BE-NEXT:  .LBB4_2: # %return_early
+; PPC64BE-NEXT:    li r3, 0
+; PPC64BE-NEXT:    extsw r3, r3
+; PPC64BE-NEXT:    blr
+entry:
+  callbr void asm sideeffect "nop", "X,~{r5}"(i8* blockaddress(@ClobberR5_BR, %return_early))
+          to label %return [label %return_early]
+
+return_early:
+  br label %return
+
+return:
+  %retval.0 = phi i32 [ 0, %return_early ], [ %in, %entry ]
+  ret i32 %retval.0
+}
+
+
+
+define dso_local void @DefLR() local_unnamed_addr #0 {
+; PPC64LE-LABEL: DefLR:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    mflr r0
+; PPC64LE-NEXT:    std r0, 16(r1)
+; PPC64LE-NEXT:    stdu r1, -32(r1)
+; PPC64LE-NEXT:    #APP
+; PPC64LE-NEXT:    #NO_APP
+; PPC64LE-NEXT:    addi r1, r1, 32
+; PPC64LE-NEXT:    ld r0, 16(r1)
+; PPC64LE-NEXT:    mtlr r0
+; PPC64LE-NEXT:    blr
+;
+; PPC64BE-LABEL: DefLR:
+; PPC64BE:       # %bb.0: # %entry
+; PPC64BE-NEXT:    mflr r0
+; PPC64BE-NEXT:    std r0, 16(r1)
+; PPC64BE-NEXT:    stdu r1, -48(r1)
+; PPC64BE-NEXT:    #APP
+; PPC64BE-NEXT:    #NO_APP
+; PPC64BE-NEXT:    addi r1, r1, 48
+; PPC64BE-NEXT:    ld r0, 16(r1)
+; PPC64BE-NEXT:    mtlr r0
+; PPC64BE-NEXT:    blr
+entry:
+  tail call i64 asm sideeffect "", "={lr}"()
+  ret void
+}
+
+define dso_local void @EarlyClobberLR() local_unnamed_addr #0 {
+; PPC64LE-LABEL: EarlyClobberLR:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    mflr r0
+; PPC64LE-NEXT:    std r0, 16(r1)
+; PPC64LE-NEXT:    stdu r1, -32(r1)
+; PPC64LE-NEXT:    #APP
+; PPC64LE-NEXT:    #NO_APP
+; PPC64LE-NEXT:    addi r1, r1, 32
+; PPC64LE-NEXT:    ld r0, 16(r1)
+; PPC64LE-NEXT:    mtlr r0
+; PPC64LE-NEXT:    blr
+;
+; PPC64BE-LABEL: EarlyClobberLR:
+; PPC64BE:       # %bb.0: # %entry
+; PPC64BE-NEXT:    mflr r0
+; PPC64BE-NEXT:    std r0, 16(r1)
+; PPC64BE-NEXT:    stdu r1, -48(r1)
+; PPC64BE-NEXT:    #APP
+; PPC64BE-NEXT:    #NO_APP
+; PPC64BE-NEXT:    addi r1, r1, 48
+; PPC64BE-NEXT:    ld r0, 16(r1)
+; PPC64BE-NEXT:    mtlr r0
+; PPC64BE-NEXT:    blr
+entry:
+  tail call i64 asm sideeffect "", "=&{lr}"()
+  ret void
+}
+
+define dso_local void @ClobberMulti() local_unnamed_addr #0 {
+; PPC64LE-LABEL: ClobberMulti:
+; PPC64LE:       # %bb.0: # %entry
+; PPC64LE-NEXT:    mflr r0
+; PPC64LE-NEXT:    std r15, -136(r1) # 8-byte Folded Spill
+; PPC64LE-NEXT:    std r16, -128(r1) # 8-byte Folded Spill
+; PPC64LE-NEXT:    std r0, 16(r1)
+; PPC64LE-NEXT:    stdu r1, -176(r1)
+; PPC64LE-NEXT:    #APP
+; PPC64LE-NEXT:    #NO_APP
+; PPC64LE-NEXT:    addi r1, r1, 176
+; PPC64LE-NEXT:    ld r0, 16(r1)
+; PPC64LE-NEXT:    ld r16, -128(r1) # 8-byte Folded Reload
+; PPC64LE-NEXT:    ld r15, -136(r1) # 8-byte Folded Reload
+; PPC64LE-NEXT:    mtlr r0
+; PPC64LE-NEXT:    blr
+;
+; PPC64BE-LABEL: ClobberMulti:
+; PPC64BE:       # %bb.0: # %entry
+; PPC64BE-NEXT:    mflr r0
+; PPC64BE-NEXT:    std r0, 16(r1)
+; PPC64BE-NEXT:    stdu r1, -192(r1)
+; PPC64BE-NEXT:    std r15, 56(r1) # 8-byte Folded Spill
+; PPC64BE-NEXT:    std r16, 64(r1) # 8-byte Folded Spill
+; PPC64BE-NEXT:    #APP
+; PPC64BE-NEXT:    #NO_APP
+; PPC64BE-NEXT:    ld r16, 64(r1) # 8-byte Folded Reload
+; PPC64BE-NEXT:    ld r15, 56(r1) # 8-byte Folded Reload
+; PPC64BE-NEXT:    addi r1, r1, 192
+; PPC64BE-NEXT:    ld r0, 16(r1)
+; PPC64BE-NEXT:    mtlr r0
+; PPC64BE-NEXT:    blr
+entry:
+  tail call void asm sideeffect "", "~{lr},~{r15},~{r16}"()
+  ret void
+}
+
+attributes #0 = { nounwind }