This is an archive of the discontinued LLVM Phabricator instance.

Differential D101096

[ARM] Transfer memory operands for VLDn
ClosedPublic

Authored by dmgreen on Apr 22 2021, 11:34 AM.

Details

Reviewers
simon_tatham
SjoerdMeijer
malharJ
efriedma
ostannard
samtebbs
Commits
rG15b5d1a5bf1f: [ARM] Transfer memory operands for VLDn
Summary

We create MMO's for the VLDn/VSTn intrinsics in ARMTargetLowering::getTgtMemIntrinsic, but they do not make it through to the instructions. This changes that in the various places it needs changing, allowing the MMO to propagate through to the final instruction. This can help in scheduling, not treating the VLD2/VST2 as a scheduling barrier.

Diff Detail

Revision Contents

PathSize
llvm/
include/
llvm/
IR/
14 lines
lib/
Target/
ARM/
2 lines
4 lines
test/
CodeGen/
Thumb2/
4 lines
28 lines
22 lines
12 lines
4 lines

Diff 342290

llvm/include/llvm/IR/IntrinsicsARM.td

Show First 20 Lines • Show All 1,126 Lines • ▼ Show 20 Linesdefm int_arm_mve_vcmulq : MVEMXPredicated<
[llvm_i32_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [llvm_i32_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
LLVMMatchType<0>, llvm_anyvector_ty>; LLVMMatchType<0>, llvm_anyvector_ty>;
defm int_arm_mve_vcmlaq : MVEPredicated< defm int_arm_mve_vcmlaq : MVEPredicated<
[llvm_anyvector_ty], [llvm_anyvector_ty],
[llvm_i32_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [llvm_i32_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
llvm_anyvector_ty>; llvm_anyvector_ty>;
def int_arm_mve_vld2q: Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], [llvm_anyptr_ty], [IntrReadMem, IntrArgMemOnly]>; def int_arm_mve_vld2q: Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], [llvm_anyptr_ty],
def int_arm_mve_vld4q: Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [llvm_anyptr_ty], [IntrReadMem, IntrArgMemOnly]>; [IntrReadMem, IntrArgMemOnly]>;
def int_arm_mve_vld4q: Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [llvm_anyptr_ty],
[IntrReadMem, IntrArgMemOnly]>;
def int_arm_mve_vst2q: Intrinsic<[], [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty], [IntrWriteMem, IntrArgMemOnly]>; def int_arm_mve_vst2q: Intrinsic<[], [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty],
def int_arm_mve_vst4q: Intrinsic<[], [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>, LLVMMatchType<1>, llvm_i32_ty], [IntrWriteMem, IntrArgMemOnly]>; [IntrWriteMem, IntrArgMemOnly], "", [SDNPMemOperand]>;
def int_arm_mve_vst4q: Intrinsic<[], [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>, LLVMMatchType<1>, llvm_i32_ty],
[IntrWriteMem, IntrArgMemOnly], "", [SDNPMemOperand]>;
// MVE vector absolute difference and accumulate across vector // MVE vector absolute difference and accumulate across vector
// The first operand is an 'unsigned' flag. The remaining operands are: // The first operand is an 'unsigned' flag. The remaining operands are:
// * accumulator // * accumulator
// * first vector operand // * first vector operand
// * second vector operand // * second vector operand
// * mask (only in predicated versions) // * mask (only in predicated versions)
defm int_arm_mve_vabav: MVEPredicated< defm int_arm_mve_vabav: MVEPredicated<
▲ Show 20 Lines • Show All 233 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

Show First 20 Lines • Show All 2,758 Lines • ▼ Show 20 Linesvoid ARMDAGToDAGISel::SelectMVE_VLD(SDNode *N, unsigned NumVecs,
SDValue Chain = N->getOperand(0); SDValue Chain = N->getOperand(0);
// Add a MVE_VLDn instruction for each Vec, except the last // Add a MVE_VLDn instruction for each Vec, except the last
for (unsigned Stage = 0; Stage < NumVecs - 1; ++Stage) { for (unsigned Stage = 0; Stage < NumVecs - 1; ++Stage) {
SDValue Ops[] = {Data, N->getOperand(PtrOperand), Chain}; SDValue Ops[] = {Data, N->getOperand(PtrOperand), Chain};
auto LoadInst = auto LoadInst =
CurDAG->getMachineNode(OurOpcodes[Stage], Loc, ResultTys, Ops); CurDAG->getMachineNode(OurOpcodes[Stage], Loc, ResultTys, Ops);
Data = SDValue(LoadInst, 0); Data = SDValue(LoadInst, 0);
Chain = SDValue(LoadInst, 1); Chain = SDValue(LoadInst, 1);
transferMemOperands(N, LoadInst);
} }
// The last may need a writeback on it // The last may need a writeback on it
if (HasWriteback) if (HasWriteback)
ResultTys = {DataTy, MVT::i32, MVT::Other}; ResultTys = {DataTy, MVT::i32, MVT::Other};
SDValue Ops[] = {Data, N->getOperand(PtrOperand), Chain}; SDValue Ops[] = {Data, N->getOperand(PtrOperand), Chain};
auto LoadInst = auto LoadInst =
CurDAG->getMachineNode(OurOpcodes[NumVecs - 1], Loc, ResultTys, Ops); CurDAG->getMachineNode(OurOpcodes[NumVecs - 1], Loc, ResultTys, Ops);
transferMemOperands(N, LoadInst);
unsigned i; unsigned i;
for (i = 0; i < NumVecs; i++) for (i = 0; i < NumVecs; i++)
ReplaceUses(SDValue(N, i), ReplaceUses(SDValue(N, i),
CurDAG->getTargetExtractSubreg(ARM::qsub_0 + i, Loc, VT, CurDAG->getTargetExtractSubreg(ARM::qsub_0 + i, Loc, VT,
SDValue(LoadInst, 0))); SDValue(LoadInst, 0)));
if (HasWriteback) if (HasWriteback)
ReplaceUses(SDValue(N, i++), SDValue(LoadInst, 1)); ReplaceUses(SDValue(N, i++), SDValue(LoadInst, 1));
▲ Show 20 Lines • Show All 2,791 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMInstrMVE.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 6,021 Lines • ▼ Show 20 Lines : MVE_vst24_base<n, stage, s.sizebits, wb,
"vst" # n.nvecs # stage # "." # s.lanesize>; "vst" # n.nvecs # stage # "." # s.lanesize>;
} }
def SDTARMVST2 : SDTypeProfile<1, 5, [SDTCisPtrTy<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVec<3>, def SDTARMVST2 : SDTypeProfile<1, 5, [SDTCisPtrTy<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVec<3>,
SDTCisSameAs<3, 4>, SDTCisVT<5, i32>]>; SDTCisSameAs<3, 4>, SDTCisVT<5, i32>]>;
def SDTARMVST4 : SDTypeProfile<1, 7, [SDTCisPtrTy<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVec<3>, def SDTARMVST4 : SDTypeProfile<1, 7, [SDTCisPtrTy<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVec<3>,
SDTCisSameAs<3, 4>, SDTCisSameAs<3, 5>, SDTCisSameAs<3, 4>, SDTCisSameAs<3, 5>,
SDTCisSameAs<3, 6>, SDTCisVT<7, i32>]>; SDTCisSameAs<3, 6>, SDTCisVT<7, i32>]>;
def MVEVST2UPD : SDNode<"ARMISD::VST2_UPD", SDTARMVST2, [SDNPHasChain]>; def MVEVST2UPD : SDNode<"ARMISD::VST2_UPD", SDTARMVST2, [SDNPHasChain, SDNPMemOperand]>;
def MVEVST4UPD : SDNode<"ARMISD::VST4_UPD", SDTARMVST4, [SDNPHasChain]>; def MVEVST4UPD : SDNode<"ARMISD::VST4_UPD", SDTARMVST4, [SDNPHasChain, SDNPMemOperand]>;
multiclass MVE_vst24_patterns<int lanesize, ValueType VT> { multiclass MVE_vst24_patterns<int lanesize, ValueType VT> {
foreach stage = [0,1] in foreach stage = [0,1] in
def : Pat<(int_arm_mve_vst2q i32:$addr, def : Pat<(int_arm_mve_vst2q i32:$addr,
(VT MQPR:$v0), (VT MQPR:$v1), (i32 stage)), (VT MQPR:$v0), (VT MQPR:$v1), (i32 stage)),
(!cast<Instruction>("MVE_VST2"#stage#"_"#lanesize) (!cast<Instruction>("MVE_VST2"#stage#"_"#lanesize)
(REG_SEQUENCE QQPR, VT:$v0, qsub_0, VT:$v1, qsub_1), (REG_SEQUENCE QQPR, VT:$v0, qsub_0, VT:$v1, qsub_1),
t2_addr_offset_none:$addr)>; t2_addr_offset_none:$addr)>;
▲ Show 20 Lines • Show All 1,383 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll

Show All 13 Lines
; CHECK-NEXT: sub sp, #112 ; CHECK-NEXT: sub sp, #112
; CHECK-NEXT: vld20.32 {q0, q1}, [r0] ; CHECK-NEXT: vld20.32 {q0, q1}, [r0]
; CHECK-NEXT: mov r5, r0 ; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: add.w lr, sp, #64 ; CHECK-NEXT: add.w lr, sp, #64
; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: vld21.32 {q0, q1}, [r5]! ; CHECK-NEXT: vld21.32 {q0, q1}, [r5]!
; CHECK-NEXT: adds r0, #64 ; CHECK-NEXT: adds r0, #64
; CHECK-NEXT: vstmia lr, {d0, d1, d2, d3} @ 32-byte Spill ; CHECK-NEXT: vstmia lr, {d0, d1, d2, d3} @ 32-byte Spill
; CHECK-NEXT: add.w lr, sp, #32
; CHECK-NEXT: vld20.32 {q0, q1}, [r0] ; CHECK-NEXT: vld20.32 {q0, q1}, [r0]
; CHECK-NEXT: add.w lr, sp, #32
; CHECK-NEXT: vld21.32 {q0, q1}, [r0] ; CHECK-NEXT: vld21.32 {q0, q1}, [r0]
; CHECK-NEXT: add.w r0, r4, #128 ; CHECK-NEXT: add.w r0, r4, #128
; CHECK-NEXT: vstmia lr, {d0, d1, d2, d3} @ 32-byte Spill ; CHECK-NEXT: vstmia lr, {d0, d1, d2, d3} @ 32-byte Spill
; CHECK-NEXT: vld20.32 {q0, q1}, [r0] ; CHECK-NEXT: vld20.32 {q0, q1}, [r0]
; CHECK-NEXT: vld21.32 {q0, q1}, [r0] ; CHECK-NEXT: vld21.32 {q0, q1}, [r0]
; CHECK-NEXT: add.w r0, r4, #192 ; CHECK-NEXT: add.w r0, r4, #192
; CHECK-NEXT: vstmia sp, {d0, d1, d2, d3} @ 32-byte Spill
; CHECK-NEXT: vld20.32 {q6, q7}, [r0] ; CHECK-NEXT: vld20.32 {q6, q7}, [r0]
; CHECK-NEXT: vstmia sp, {d0, d1, d2, d3} @ 32-byte Spill
; CHECK-NEXT: vld21.32 {q6, q7}, [r0] ; CHECK-NEXT: vld21.32 {q6, q7}, [r0]
; CHECK-NEXT: add.w r0, r4, #256 ; CHECK-NEXT: add.w r0, r4, #256
; CHECK-NEXT: vld20.32 {q4, q5}, [r0] ; CHECK-NEXT: vld20.32 {q4, q5}, [r0]
; CHECK-NEXT: vld21.32 {q4, q5}, [r0] ; CHECK-NEXT: vld21.32 {q4, q5}, [r0]
; CHECK-NEXT: bl external_function ; CHECK-NEXT: bl external_function
; CHECK-NEXT: vldmia sp, {d2, d3, d4, d5} @ 32-byte Reload ; CHECK-NEXT: vldmia sp, {d2, d3, d4, d5} @ 32-byte Reload
; CHECK-NEXT: add.w lr, sp, #32 ; CHECK-NEXT: add.w lr, sp, #32
; CHECK-NEXT: vstrw.32 q2, [r4, #80] ; CHECK-NEXT: vstrw.32 q2, [r4, #80]
▲ Show 20 Lines • Show All 65 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vld2.ll

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
define void @vld2_v16i32(<32 x i32> *%src, <16 x i32> *%dst) { define void @vld2_v16i32(<32 x i32> *%src, <16 x i32> *%dst) {
; CHECK-LABEL: vld2_v16i32: ; CHECK-LABEL: vld2_v16i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vld20.32 {q0, q1}, [r0] ; CHECK-NEXT: vld20.32 {q0, q1}, [r0]
; CHECK-NEXT: add.w r2, r0, #96 ; CHECK-NEXT: add.w r2, r0, #96
; CHECK-NEXT: add.w r3, r0, #64 ; CHECK-NEXT: add.w r3, r0, #64
; CHECK-NEXT: vld20.32 {q3, q4}, [r2]
; CHECK-NEXT: vld21.32 {q0, q1}, [r0]! ; CHECK-NEXT: vld21.32 {q0, q1}, [r0]!
; CHECK-NEXT: vld21.32 {q3, q4}, [r2]
; CHECK-NEXT: vld20.32 {q5, q6}, [r0]
; CHECK-NEXT: vadd.i32 q0, q0, q1 ; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: vld20.32 {q1, q2}, [r3] ; CHECK-NEXT: vld20.32 {q1, q2}, [r3]
; CHECK-NEXT: vld20.32 {q3, q4}, [r2] ; CHECK-NEXT: vadd.i32 q3, q3, q4
; CHECK-NEXT: vld20.32 {q5, q6}, [r0]
; CHECK-NEXT: vld21.32 {q5, q6}, [r0] ; CHECK-NEXT: vld21.32 {q5, q6}, [r0]
; CHECK-NEXT: vld21.32 {q1, q2}, [r3] ; CHECK-NEXT: vld21.32 {q1, q2}, [r3]
; CHECK-NEXT: vld21.32 {q3, q4}, [r2] ; CHECK-NEXT: vstrw.32 q3, [r1, #48]
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q1_q2 ; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q1_q2
; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vadd.i32 q5, q5, q6 ; CHECK-NEXT: vadd.i32 q5, q5, q6
; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vadd.i32 q1, q1, q2 ; CHECK-NEXT: vadd.i32 q1, q1, q2
; CHECK-NEXT: vadd.i32 q3, q3, q4
; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: vstrw.32 q3, [r1, #48]
; CHECK-NEXT: vstrw.32 q5, [r1, #16] ; CHECK-NEXT: vstrw.32 q5, [r1, #16]
; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <32 x i32>, <32 x i32>* %src, align 4 %l1 = load <32 x i32>, <32 x i32>* %src, align 4
%s1 = shufflevector <32 x i32> %l1, <32 x i32> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> %s1 = shufflevector <32 x i32> %l1, <32 x i32> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
%s2 = shufflevector <32 x i32> %l1, <32 x i32> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> %s2 = shufflevector <32 x i32> %l1, <32 x i32> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
%a = add <16 x i32> %s1, %s2 %a = add <16 x i32> %s1, %s2
store <16 x i32> %a, <16 x i32> *%dst store <16 x i32> %a, <16 x i32> *%dst
▲ Show 20 Lines • Show All 370 Lines • ▼ Show 20 Lines
define void @vld2_v16f32(<32 x float> *%src, <16 x float> *%dst) { define void @vld2_v16f32(<32 x float> *%src, <16 x float> *%dst) {
; CHECK-LABEL: vld2_v16f32: ; CHECK-LABEL: vld2_v16f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vld20.32 {q0, q1}, [r0] ; CHECK-NEXT: vld20.32 {q0, q1}, [r0]
; CHECK-NEXT: add.w r2, r0, #96 ; CHECK-NEXT: add.w r2, r0, #96
; CHECK-NEXT: add.w r3, r0, #64 ; CHECK-NEXT: add.w r3, r0, #64
; CHECK-NEXT: vld20.32 {q3, q4}, [r2]
; CHECK-NEXT: vld21.32 {q0, q1}, [r0]! ; CHECK-NEXT: vld21.32 {q0, q1}, [r0]!
; CHECK-NEXT: vld21.32 {q3, q4}, [r2]
; CHECK-NEXT: vld20.32 {q5, q6}, [r0]
; CHECK-NEXT: vadd.f32 q0, q0, q1 ; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: vld20.32 {q1, q2}, [r3] ; CHECK-NEXT: vld20.32 {q1, q2}, [r3]
; CHECK-NEXT: vld20.32 {q3, q4}, [r2] ; CHECK-NEXT: vadd.f32 q3, q3, q4
; CHECK-NEXT: vld20.32 {q5, q6}, [r0]
; CHECK-NEXT: vld21.32 {q5, q6}, [r0] ; CHECK-NEXT: vld21.32 {q5, q6}, [r0]
; CHECK-NEXT: vld21.32 {q1, q2}, [r3] ; CHECK-NEXT: vld21.32 {q1, q2}, [r3]
; CHECK-NEXT: vld21.32 {q3, q4}, [r2] ; CHECK-NEXT: vstrw.32 q3, [r1, #48]
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q1_q2 ; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q1_q2
; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vadd.f32 q5, q5, q6 ; CHECK-NEXT: vadd.f32 q5, q5, q6
; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vadd.f32 q1, q1, q2 ; CHECK-NEXT: vadd.f32 q1, q1, q2
; CHECK-NEXT: vadd.f32 q3, q3, q4
; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: vstrw.32 q3, [r1, #48]
; CHECK-NEXT: vstrw.32 q5, [r1, #16] ; CHECK-NEXT: vstrw.32 q5, [r1, #16]
; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <32 x float>, <32 x float>* %src, align 4 %l1 = load <32 x float>, <32 x float>* %src, align 4
%s1 = shufflevector <32 x float> %l1, <32 x float> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> %s1 = shufflevector <32 x float> %l1, <32 x float> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
%s2 = shufflevector <32 x float> %l1, <32 x float> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> %s2 = shufflevector <32 x float> %l1, <32 x float> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
%a = fadd <16 x float> %s1, %s2 %a = fadd <16 x float> %s1, %s2
store <16 x float> %a, <16 x float> *%dst store <16 x float> %a, <16 x float> *%dst
▲ Show 20 Lines • Show All 195 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vld4.ll

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: adds r0, #128 ; CHECK-NEXT: adds r0, #128
; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r2]! ; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r2]!
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 ; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3
; CHECK-NEXT: vadd.i32 q4, q2, q3 ; CHECK-NEXT: vadd.i32 q4, q2, q3
; CHECK-NEXT: vadd.i32 q0, q0, q1 ; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: vstrw.32 q4, [sp, #112] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q4, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q0, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vld40.32 {q1, q2, q3, q4}, [r3] ; CHECK-NEXT: vld40.32 {q1, q2, q3, q4}, [r3]
; CHECK-NEXT: vstrw.32 q0, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q6, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vld41.32 {q1, q2, q3, q4}, [r3] ; CHECK-NEXT: vld41.32 {q1, q2, q3, q4}, [r3]
; CHECK-NEXT: vldrw.u32 q5, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vld42.32 {q1, q2, q3, q4}, [r3] ; CHECK-NEXT: vld42.32 {q1, q2, q3, q4}, [r3]
; CHECK-NEXT: vadd.i32 q6, q5, q6
; CHECK-NEXT: vstrw.32 q6, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vld43.32 {q1, q2, q3, q4}, [r3] ; CHECK-NEXT: vld43.32 {q1, q2, q3, q4}, [r3]
; CHECK-NEXT: vldrw.u32 q6, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q5, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q4, [sp, #80] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q4, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vmov q0, q1 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: vadd.i32 q6, q5, q6
; CHECK-NEXT: vldrw.u32 q5, [sp, #80] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q5, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vadd.i32 q0, q0, q2 ; CHECK-NEXT: vadd.i32 q0, q0, q2
; CHECK-NEXT: vstrw.32 q6, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vadd.i32 q1, q3, q5 ; CHECK-NEXT: vadd.i32 q1, q3, q5
; CHECK-NEXT: vadd.i32 q0, q0, q1 ; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: vstrw.32 q0, [sp, #96] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q0, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r2] ; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r2]
; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r2] ; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r2]
; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r2] ; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r2]
; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r2] ; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r2]
; CHECK-NEXT: vstmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill ; CHECK-NEXT: vstmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill
▲ Show 20 Lines • Show All 770 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: adds r0, #128 ; CHECK-NEXT: adds r0, #128
; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r2]! ; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r2]!
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 ; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3
; CHECK-NEXT: vadd.f32 q4, q2, q3 ; CHECK-NEXT: vadd.f32 q4, q2, q3
; CHECK-NEXT: vadd.f32 q0, q0, q1 ; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: vstrw.32 q4, [sp, #112] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q4, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q0, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vld40.32 {q1, q2, q3, q4}, [r3] ; CHECK-NEXT: vld40.32 {q1, q2, q3, q4}, [r3]
; CHECK-NEXT: vstrw.32 q0, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q6, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vld41.32 {q1, q2, q3, q4}, [r3] ; CHECK-NEXT: vld41.32 {q1, q2, q3, q4}, [r3]
; CHECK-NEXT: vldrw.u32 q5, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vld42.32 {q1, q2, q3, q4}, [r3] ; CHECK-NEXT: vld42.32 {q1, q2, q3, q4}, [r3]
; CHECK-NEXT: vadd.f32 q6, q5, q6
; CHECK-NEXT: vstrw.32 q6, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vld43.32 {q1, q2, q3, q4}, [r3] ; CHECK-NEXT: vld43.32 {q1, q2, q3, q4}, [r3]
; CHECK-NEXT: vldrw.u32 q6, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q5, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q4, [sp, #80] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q4, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vmov q0, q1 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: vadd.f32 q6, q5, q6
; CHECK-NEXT: vldrw.u32 q5, [sp, #80] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q5, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vadd.f32 q0, q0, q2 ; CHECK-NEXT: vadd.f32 q0, q0, q2
; CHECK-NEXT: vstrw.32 q6, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vadd.f32 q1, q3, q5 ; CHECK-NEXT: vadd.f32 q1, q3, q5
; CHECK-NEXT: vadd.f32 q0, q0, q1 ; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: vstrw.32 q0, [sp, #96] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q0, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r2] ; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r2]
; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r2] ; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r2]
; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r2] ; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r2]
; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r2] ; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r2]
; CHECK-NEXT: vstmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill ; CHECK-NEXT: vstmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill
▲ Show 20 Lines • Show All 197 Lines • ▼ Show 20 Lines
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #88 ; CHECK-NEXT: .pad #88
; CHECK-NEXT: sub sp, #88 ; CHECK-NEXT: sub sp, #88
; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]! ; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]!
; CHECK-NEXT: vstmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill
; CHECK-NEXT: vld40.16 {q4, q5, q6, q7}, [r0] ; CHECK-NEXT: vld40.16 {q4, q5, q6, q7}, [r0]
; CHECK-NEXT: vstmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill
; CHECK-NEXT: vld41.16 {q4, q5, q6, q7}, [r0] ; CHECK-NEXT: vld41.16 {q4, q5, q6, q7}, [r0]
; CHECK-NEXT: vld42.16 {q4, q5, q6, q7}, [r0] ; CHECK-NEXT: vld42.16 {q4, q5, q6, q7}, [r0]
; CHECK-NEXT: vld43.16 {q4, q5, q6, q7}, [r0] ; CHECK-NEXT: vld43.16 {q4, q5, q6, q7}, [r0]
; CHECK-NEXT: @ kill: def $q4 killed $q4 killed $q4_q5_q6_q7 ; CHECK-NEXT: @ kill: def $q4 killed $q4 killed $q4_q5_q6_q7
; CHECK-NEXT: vadd.f16 q0, q6, q7 ; CHECK-NEXT: vadd.f16 q0, q6, q7
; CHECK-NEXT: vadd.f16 q4, q4, q5 ; CHECK-NEXT: vadd.f16 q4, q4, q5
; CHECK-NEXT: vstrw.32 q0, [sp, #64] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q0, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload
▲ Show 20 Lines • Show All 163 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vst2.ll

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vldrw.u32 q7, [r0, #64] ; CHECK-NEXT: vldrw.u32 q7, [r0, #64]
; CHECK-NEXT: vldrw.u32 q1, [r0, #112] ; CHECK-NEXT: vldrw.u32 q1, [r0, #112]
; CHECK-NEXT: vldrw.u32 q3, [r0, #96] ; CHECK-NEXT: vldrw.u32 q3, [r0, #96]
; CHECK-NEXT: vldrw.u32 q5, [r0, #80] ; CHECK-NEXT: vldrw.u32 q5, [r0, #80]
; CHECK-NEXT: vldrw.u32 q6, [r0] ; CHECK-NEXT: vldrw.u32 q6, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #48] ; CHECK-NEXT: vldrw.u32 q0, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0, #32] ; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
; CHECK-NEXT: vldrw.u32 q4, [r0, #16] ; CHECK-NEXT: vldrw.u32 q4, [r0, #16]
; CHECK-NEXT: vst20.32 {q6, q7}, [r1]
; CHECK-NEXT: add.w r0, r1, #96 ; CHECK-NEXT: add.w r0, r1, #96
; CHECK-NEXT: add.w r2, r1, #64 ; CHECK-NEXT: add.w r2, r1, #64
; CHECK-NEXT: vst20.32 {q6, q7}, [r1]
; CHECK-NEXT: vst21.32 {q6, q7}, [r1]! ; CHECK-NEXT: vst21.32 {q6, q7}, [r1]!
; CHECK-NEXT: vst20.32 {q4, q5}, [r1] ; CHECK-NEXT: vst20.32 {q4, q5}, [r1]
; CHECK-NEXT: vst21.32 {q4, q5}, [r1]
; CHECK-NEXT: vst20.32 {q2, q3}, [r2] ; CHECK-NEXT: vst20.32 {q2, q3}, [r2]
; CHECK-NEXT: vst21.32 {q2, q3}, [r2]
; CHECK-NEXT: vst20.32 {q0, q1}, [r0] ; CHECK-NEXT: vst20.32 {q0, q1}, [r0]
; CHECK-NEXT: vst21.32 {q4, q5}, [r1]
; CHECK-NEXT: vst21.32 {q2, q3}, [r2]
; CHECK-NEXT: vst21.32 {q0, q1}, [r0] ; CHECK-NEXT: vst21.32 {q0, q1}, [r0]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <16 x i32>, <16 x i32>* %src, i32 0 %s1 = getelementptr <16 x i32>, <16 x i32>* %src, i32 0
%l1 = load <16 x i32>, <16 x i32>* %s1, align 4 %l1 = load <16 x i32>, <16 x i32>* %s1, align 4
%s2 = getelementptr <16 x i32>, <16 x i32>* %src, i32 1 %s2 = getelementptr <16 x i32>, <16 x i32>* %src, i32 1
%l2 = load <16 x i32>, <16 x i32>* %s2, align 4 %l2 = load <16 x i32>, <16 x i32>* %s2, align 4
▲ Show 20 Lines • Show All 360 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vldrw.u32 q7, [r0, #64] ; CHECK-NEXT: vldrw.u32 q7, [r0, #64]
; CHECK-NEXT: vldrw.u32 q1, [r0, #112] ; CHECK-NEXT: vldrw.u32 q1, [r0, #112]
; CHECK-NEXT: vldrw.u32 q3, [r0, #96] ; CHECK-NEXT: vldrw.u32 q3, [r0, #96]
; CHECK-NEXT: vldrw.u32 q5, [r0, #80] ; CHECK-NEXT: vldrw.u32 q5, [r0, #80]
; CHECK-NEXT: vldrw.u32 q6, [r0] ; CHECK-NEXT: vldrw.u32 q6, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #48] ; CHECK-NEXT: vldrw.u32 q0, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0, #32] ; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
; CHECK-NEXT: vldrw.u32 q4, [r0, #16] ; CHECK-NEXT: vldrw.u32 q4, [r0, #16]
; CHECK-NEXT: vst20.32 {q6, q7}, [r1]
; CHECK-NEXT: add.w r0, r1, #96 ; CHECK-NEXT: add.w r0, r1, #96
; CHECK-NEXT: add.w r2, r1, #64 ; CHECK-NEXT: add.w r2, r1, #64
; CHECK-NEXT: vst20.32 {q6, q7}, [r1]
; CHECK-NEXT: vst21.32 {q6, q7}, [r1]! ; CHECK-NEXT: vst21.32 {q6, q7}, [r1]!
; CHECK-NEXT: vst20.32 {q4, q5}, [r1] ; CHECK-NEXT: vst20.32 {q4, q5}, [r1]
; CHECK-NEXT: vst21.32 {q4, q5}, [r1]
; CHECK-NEXT: vst20.32 {q2, q3}, [r2] ; CHECK-NEXT: vst20.32 {q2, q3}, [r2]
; CHECK-NEXT: vst21.32 {q2, q3}, [r2]
; CHECK-NEXT: vst20.32 {q0, q1}, [r0] ; CHECK-NEXT: vst20.32 {q0, q1}, [r0]
; CHECK-NEXT: vst21.32 {q4, q5}, [r1]
; CHECK-NEXT: vst21.32 {q2, q3}, [r2]
; CHECK-NEXT: vst21.32 {q0, q1}, [r0] ; CHECK-NEXT: vst21.32 {q0, q1}, [r0]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <16 x float>, <16 x float>* %src, i32 0 %s1 = getelementptr <16 x float>, <16 x float>* %src, i32 0
%l1 = load <16 x float>, <16 x float>* %s1, align 4 %l1 = load <16 x float>, <16 x float>* %s1, align 4
%s2 = getelementptr <16 x float>, <16 x float>* %src, i32 1 %s2 = getelementptr <16 x float>, <16 x float>* %src, i32 1
%l2 = load <16 x float>, <16 x float>* %s2, align 4 %l2 = load <16 x float>, <16 x float>* %s2, align 4
▲ Show 20 Lines • Show All 223 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vst4.ll

Show First 20 Lines • Show All 169 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vldmia r2, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Reload ; CHECK-NEXT: vldmia r2, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Reload
; CHECK-NEXT: add.w r0, r1, #192 ; CHECK-NEXT: add.w r0, r1, #192
; CHECK-NEXT: adds r1, #128 ; CHECK-NEXT: adds r1, #128
; CHECK-NEXT: vmov q3, q2 ; CHECK-NEXT: vmov q3, q2
; CHECK-NEXT: vst40.32 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst40.32 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst41.32 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst41.32 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst42.32 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst42.32 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst43.32 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vst43.32 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: add sp, #216 ; CHECK-NEXT: add sp, #216
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: pop {r4, r5} ; CHECK-NEXT: pop {r4, r5}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <16 x i32>, <16 x i32>* %src, i32 0 %s1 = getelementptr <16 x i32>, <16 x i32>* %src, i32 0
%l1 = load <16 x i32>, <16 x i32>* %s1, align 4 %l1 = load <16 x i32>, <16 x i32>* %s1, align 4
▲ Show 20 Lines • Show All 750 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vldmia r2, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Reload ; CHECK-NEXT: vldmia r2, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Reload
; CHECK-NEXT: add.w r0, r1, #192 ; CHECK-NEXT: add.w r0, r1, #192
; CHECK-NEXT: adds r1, #128 ; CHECK-NEXT: adds r1, #128
; CHECK-NEXT: vmov q3, q2 ; CHECK-NEXT: vmov q3, q2
; CHECK-NEXT: vst40.32 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst40.32 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst41.32 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst41.32 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst42.32 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst42.32 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst43.32 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vst43.32 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: add sp, #216 ; CHECK-NEXT: add sp, #216
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: pop {r4, r5} ; CHECK-NEXT: pop {r4, r5}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <16 x float>, <16 x float>* %src, i32 0 %s1 = getelementptr <16 x float>, <16 x float>* %src, i32 0
%l1 = load <16 x float>, <16 x float>* %s1, align 4 %l1 = load <16 x float>, <16 x float>* %s1, align 4
▲ Show 20 Lines • Show All 385 Lines • Show Last 20 Lines