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Differential D100821

[RISCV] Implement the vmmv.m/vmnot.m builtin.
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Authored by HsiangKai on Apr 20 2021, 12:38 AM.

Details

Reviewers
craig.topper
khchen
frasercrmck
Commits
rG4b2434172cc1: [RISCV] Implement the vmmv.m/vmnot.m builtin.

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Event Timeline

HsiangKai created this revision.Apr 20 2021, 12:38 AM
Herald added subscribers: StephenFan, vkmr, dexonsmith and 25 others. · View Herald TranscriptApr 20 2021, 12:38 AM
HsiangKai requested review of this revision.Apr 20 2021, 12:38 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 20 2021, 12:38 AM
Herald added subscribers: cfe-commits, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B99630: Diff 338734.Apr 20 2021, 1:11 AM
rogfer01 added a comment.Apr 22 2021, 1:43 AM

I can reproduce the crash above in my computer, so something is definitely off.

Looks like we emit this

case RISCV::BI__builtin_rvv_vmmv_m_b8:                
case RISCV::BI__builtin_rvv_vmmv_m_b4:                
case RISCV::BI__builtin_rvv_vmmv_m_b2:                
case RISCV::BI__builtin_rvv_vmmv_m_b1:                
case RISCV::BI__builtin_rvv_vmmv_m_b16:               
case RISCV::BI__builtin_rvv_vmmv_m_b32:               
case RISCV::BI__builtin_rvv_vmmv_m_b64:               
case RISCV::BI__builtin_rvv_vmand_mm_b8:              
case RISCV::BI__builtin_rvv_vmand_mm_b4:              
case RISCV::BI__builtin_rvv_vmand_mm_b2:              
case RISCV::BI__builtin_rvv_vmand_mm_b1:              
case RISCV::BI__builtin_rvv_vmand_mm_b16:             
case RISCV::BI__builtin_rvv_vmand_mm_b32:             
case RISCV::BI__builtin_rvv_vmand_mm_b64:             
  ID = Intrinsic::riscv_vmand;                        
  IntrinsicTypes = {ResultType, Ops[2]->getType()};   
  break;

But Ops has size 2 so this is accessing past the end. I observed the crash with clang::RISCV::BI__builtin_rvv_vmmv_m_b1 but I assume it happens with the other ones as well.

I think the description of the builtin should be def : RVVBuiltin<"m", "m", type_range>; as these are like unary operations, aren't they?

HsiangKai added a comment.Apr 22 2021, 7:51 PM
In D100821#2707667, @rogfer01 wrote:

I can reproduce the crash above in my computer, so something is definitely off.

Looks like we emit this

case RISCV::BI__builtin_rvv_vmmv_m_b8:                
case RISCV::BI__builtin_rvv_vmmv_m_b4:                
case RISCV::BI__builtin_rvv_vmmv_m_b2:                
case RISCV::BI__builtin_rvv_vmmv_m_b1:                
case RISCV::BI__builtin_rvv_vmmv_m_b16:               
case RISCV::BI__builtin_rvv_vmmv_m_b32:               
case RISCV::BI__builtin_rvv_vmmv_m_b64:               
case RISCV::BI__builtin_rvv_vmand_mm_b8:              
case RISCV::BI__builtin_rvv_vmand_mm_b4:              
case RISCV::BI__builtin_rvv_vmand_mm_b2:              
case RISCV::BI__builtin_rvv_vmand_mm_b1:              
case RISCV::BI__builtin_rvv_vmand_mm_b16:             
case RISCV::BI__builtin_rvv_vmand_mm_b32:             
case RISCV::BI__builtin_rvv_vmand_mm_b64:             
  ID = Intrinsic::riscv_vmand;                        
  IntrinsicTypes = {ResultType, Ops[2]->getType()};   
  break;

But Ops has size 2 so this is accessing past the end. I observed the crash with clang::RISCV::BI__builtin_rvv_vmmv_m_b1 but I assume it happens with the other ones as well.

I think the description of the builtin should be def : RVVBuiltin<"m", "m", type_range>; as these are like unary operations, aren't they?

The fix is put in https://reviews.llvm.org/D100819#inline-952584. I will land D100819 today.

HsiangKai updated this revision to Diff 339875.Apr 22 2021, 10:00 PM

Rebase.

Harbormaster completed remote builds in B100452: Diff 339875.Apr 22 2021, 10:37 PM
rogfer01 added a comment.Apr 23 2021, 1:11 AM
In D100821#2710998, @HsiangKai wrote:

Rebase.

Thanks, I had missed that and my comment above was wrong.

HsiangKai added a comment.Apr 23 2021, 5:12 AM
In D100821#2711395, @rogfer01 wrote:
In D100821#2710998, @HsiangKai wrote:

Rebase.

Thanks, I had missed that and my comment above was wrong.

That's fine. Thanks for your review.

khchen accepted this revision.Apr 25 2021, 8:17 PM

LGTM.

This revision is now accepted and ready to land.Apr 25 2021, 8:17 PM
Closed by commit rG4b2434172cc1: [RISCV] Implement the vmmv.m/vmnot.m builtin. (authored by HsiangKai). · Explain WhyApr 26 2021, 1:00 AM
This revision was automatically updated to reflect the committed changes.
HsiangKai added a commit: rG4b2434172cc1: [RISCV] Implement the vmmv.m/vmnot.m builtin..

Revision Contents

PathSize
clang/
include/
clang/
Basic/
19 lines
test/
CodeGen/
RISCV/
rvv-intrinsics-overloaded/
107 lines
107 lines
rvv-intrinsics/
107 lines
107 lines

Diff 339875

clang/include/clang/Basic/riscv_vector.td

Show First 20 Lines • Show All 838 Lines • ▼ Show 20 Lines let Name = NAME,
break; break;
} }
}] in { }] in {
def : RVVBuiltin<"v", "vv", type_range>; def : RVVBuiltin<"v", "vv", type_range>;
def : RVVBuiltin<"Uv", "UvUv", type_range>; def : RVVBuiltin<"Uv", "UvUv", type_range>;
} }
} }
multiclass RVVPseudoMaskBuiltin<string IR, string type_range> {
let Name = NAME,
IRName = IR,
HasMask = false,
ManualCodegen = [{
{
// op1, vl
IntrinsicTypes = {ResultType,
Ops[1]->getType()};
Ops.insert(Ops.begin() + 1, Ops[0]);
break;
}
}] in {
def : RVVBuiltin<"m", "mm", type_range>;
}
}
// 6. Configuration-Setting Instructions // 6. Configuration-Setting Instructions
// 6.1. vsetvli/vsetvl instructions // 6.1. vsetvli/vsetvl instructions
let HasVL = false, let HasVL = false,
HasMask = false, HasMask = false,
HasSideEffects = true, HasSideEffects = true,
Log2LMUL = [0], Log2LMUL = [0],
ManualCodegen = [{IntrinsicTypes = {ResultType};}] in // Set XLEN type ManualCodegen = [{IntrinsicTypes = {ResultType};}] in // Set XLEN type
{ {
▲ Show 20 Lines • Show All 440 Lines • ▼ Show 20 Lines
def vmxor : RVVMaskBinBuiltin; def vmxor : RVVMaskBinBuiltin;
def vmor : RVVMaskBinBuiltin; def vmor : RVVMaskBinBuiltin;
def vmnor : RVVMaskBinBuiltin; def vmnor : RVVMaskBinBuiltin;
def vmornot : RVVMaskBinBuiltin; def vmornot : RVVMaskBinBuiltin;
def vmxnor : RVVMaskBinBuiltin; def vmxnor : RVVMaskBinBuiltin;
// pseudoinstructions // pseudoinstructions
def vmclr : RVVMaskNullaryBuiltin; def vmclr : RVVMaskNullaryBuiltin;
def vmset : RVVMaskNullaryBuiltin; def vmset : RVVMaskNullaryBuiltin;
defm vmmv_m : RVVPseudoMaskBuiltin<"vmand", "c">;
defm vmnot_m : RVVPseudoMaskBuiltin<"vmnand", "c">;
// 16.2. Vector mask population count vpopc // 16.2. Vector mask population count vpopc
def vpopc : RVVMaskOp0Builtin<"um">; def vpopc : RVVMaskOp0Builtin<"um">;
// 16.3. vfirst find-first-set mask bit // 16.3. vfirst find-first-set mask bit
def vfirst : RVVMaskOp0Builtin<"lm">; def vfirst : RVVMaskOp0Builtin<"lm">;
// 16.4. vmsbf.m set-before-first mask bit // 16.4. vmsbf.m set-before-first mask bit
▲ Show 20 Lines • Show All 146 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmmv.c

  • This file was added.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -target-feature +m -Werror -Wall -S -o - %s >/dev/null 2>%t
// RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmmv_m_b1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i32(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP1]], i32 [[VL:%.*]]) #[[ATTR8:[0-9]+]]
// CHECK-RV32-NEXT: ret <vscale x 64 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmmv_m_b1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP1]], i64 [[VL:%.*]]) #[[ATTR8:[0-9]+]]
// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
//
vbool1_t test_vmmv_m_b1 (vbool1_t op1, size_t vl) {
return vmmv(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmmv_m_b2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i32(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[OP1]], i32 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 32 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmmv_m_b2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[OP1]], i64 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
//
vbool2_t test_vmmv_m_b2 (vbool2_t op1, size_t vl) {
return vmmv(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmmv_m_b4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i32(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP1]], i32 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmmv_m_b4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP1]], i64 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
vbool4_t test_vmmv_m_b4 (vbool4_t op1, size_t vl) {
return vmmv(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmmv_m_b8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i32(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[OP1]], i32 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 8 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmmv_m_b8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[OP1]], i64 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
//
vbool8_t test_vmmv_m_b8 (vbool8_t op1, size_t vl) {
return vmmv(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmmv_m_b16(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i32(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[OP1]], i32 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 4 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmmv_m_b16(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[OP1]], i64 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
//
vbool16_t test_vmmv_m_b16 (vbool16_t op1, size_t vl) {
return vmmv(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmmv_m_b32(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i32(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[OP1]], i32 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 2 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmmv_m_b32(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[OP1]], i64 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
//
vbool32_t test_vmmv_m_b32 (vbool32_t op1, size_t vl) {
return vmmv(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmmv_m_b64(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i32(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[OP1]], i32 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 1 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmmv_m_b64(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[OP1]], i64 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
//
vbool64_t test_vmmv_m_b64 (vbool64_t op1, size_t vl) {
return vmmv(op1, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnot.c

  • This file was added.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -target-feature +m -Werror -Wall -S -o - %s >/dev/null 2>%t
// RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmnot_m_b1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i32(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP1]], i32 [[VL:%.*]]) #[[ATTR8:[0-9]+]]
// CHECK-RV32-NEXT: ret <vscale x 64 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmnot_m_b1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP1]], i64 [[VL:%.*]]) #[[ATTR8:[0-9]+]]
// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
//
vbool1_t test_vmnot_m_b1 (vbool1_t op1, size_t vl) {
return vmnot(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmnot_m_b2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i32(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[OP1]], i32 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 32 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmnot_m_b2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[OP1]], i64 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
//
vbool2_t test_vmnot_m_b2 (vbool2_t op1, size_t vl) {
return vmnot(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmnot_m_b4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i32(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP1]], i32 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmnot_m_b4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP1]], i64 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
vbool4_t test_vmnot_m_b4 (vbool4_t op1, size_t vl) {
return vmnot(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmnot_m_b8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i32(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[OP1]], i32 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 8 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmnot_m_b8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[OP1]], i64 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
//
vbool8_t test_vmnot_m_b8 (vbool8_t op1, size_t vl) {
return vmnot(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmnot_m_b16(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i32(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[OP1]], i32 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 4 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmnot_m_b16(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[OP1]], i64 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
//
vbool16_t test_vmnot_m_b16 (vbool16_t op1, size_t vl) {
return vmnot(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmnot_m_b32(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i32(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[OP1]], i32 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 2 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmnot_m_b32(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[OP1]], i64 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
//
vbool32_t test_vmnot_m_b32 (vbool32_t op1, size_t vl) {
return vmnot(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmnot_m_b64(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i32(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[OP1]], i32 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV32-NEXT: ret <vscale x 1 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmnot_m_b64(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[OP1]], i64 [[VL:%.*]]) #[[ATTR8]]
// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
//
vbool64_t test_vmnot_m_b64 (vbool64_t op1, size_t vl) {
return vmnot(op1, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics/vmmv.c

  • This file was added.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -target-feature +m -Werror -Wall -S -o - %s >/dev/null 2>%t
// RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmmv_m_b1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i32(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP1]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 64 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmmv_m_b1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP1]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
//
vbool1_t test_vmmv_m_b1 (vbool1_t op1, size_t vl) {
return vmmv_m_b1(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmmv_m_b2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i32(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[OP1]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 32 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmmv_m_b2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[OP1]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
//
vbool2_t test_vmmv_m_b2 (vbool2_t op1, size_t vl) {
return vmmv_m_b2(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmmv_m_b4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i32(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP1]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmmv_m_b4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP1]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
vbool4_t test_vmmv_m_b4 (vbool4_t op1, size_t vl) {
return vmmv_m_b4(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmmv_m_b8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i32(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[OP1]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmmv_m_b8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[OP1]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
//
vbool8_t test_vmmv_m_b8 (vbool8_t op1, size_t vl) {
return vmmv_m_b8(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmmv_m_b16(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i32(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[OP1]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmmv_m_b16(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[OP1]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
//
vbool16_t test_vmmv_m_b16 (vbool16_t op1, size_t vl) {
return vmmv_m_b16(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmmv_m_b32(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i32(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[OP1]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmmv_m_b32(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[OP1]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
//
vbool32_t test_vmmv_m_b32 (vbool32_t op1, size_t vl) {
return vmmv_m_b32(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmmv_m_b64(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i32(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[OP1]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmmv_m_b64(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[OP1]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
//
vbool64_t test_vmmv_m_b64 (vbool64_t op1, size_t vl) {
return vmmv_m_b64(op1, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics/vmnot.c

  • This file was added.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -target-feature +m -Werror -Wall -S -o - %s >/dev/null 2>%t
// RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmnot_m_b1(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i32(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP1]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 64 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmnot_m_b1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP1]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
//
vbool1_t test_vmnot_m_b1 (vbool1_t op1, size_t vl) {
return vmnot_m_b1(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmnot_m_b2(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i32(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[OP1]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 32 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmnot_m_b2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[OP1]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
//
vbool2_t test_vmnot_m_b2 (vbool2_t op1, size_t vl) {
return vmnot_m_b2(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmnot_m_b4(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i32(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP1]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmnot_m_b4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP1]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
vbool4_t test_vmnot_m_b4 (vbool4_t op1, size_t vl) {
return vmnot_m_b4(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmnot_m_b8(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i32(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[OP1]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 8 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmnot_m_b8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[OP1]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
//
vbool8_t test_vmnot_m_b8 (vbool8_t op1, size_t vl) {
return vmnot_m_b8(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmnot_m_b16(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i32(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[OP1]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 4 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmnot_m_b16(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[OP1]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
//
vbool16_t test_vmnot_m_b16 (vbool16_t op1, size_t vl) {
return vmnot_m_b16(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmnot_m_b32(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i32(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[OP1]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 2 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmnot_m_b32(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[OP1]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
//
vbool32_t test_vmnot_m_b32 (vbool32_t op1, size_t vl) {
return vmnot_m_b32(op1, vl);
}
// CHECK-RV32-LABEL: @test_vmnot_m_b64(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i32(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[OP1]], i32 [[VL:%.*]])
// CHECK-RV32-NEXT: ret <vscale x 1 x i1> [[TMP0]]
//
// CHECK-RV64-LABEL: @test_vmnot_m_b64(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[OP1]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
//
vbool64_t test_vmnot_m_b64 (vbool64_t op1, size_t vl) {
return vmnot_m_b64(op1, vl);
}