[AIX] Adjust CSR order to avoid breaking ABI regarding traceback

[lkail]

Summary

Allocate non-volatile registers in order to be compatible with ABI, regarding gpr_save.

Quoted from https://www.ibm.com/docs/en/ssw_aix_72/assembler/assembler_pdf.pdf page55,

The preferred method of using GPRs is to use the volatile registers first. Next, use the nonvolatile registers
in descending order, starting with GPR31.

This patch is based on @jsji 's initial draft.

Tested on test-suite and SPEC, found no degradation.

[jsji]

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

307

Add comments about the AIX sequence.

313

Please make this a Subtarget function, something like PPCSubtarget::getGPRAllocationOrder, so that we don't need to duplicate code here.

llvm/test/CodeGen/PowerPC/inc-of-add.ll

165

Why removing these lines?

[nemanjai]

Please add some info about how this affects functions that need the frame pointer. Do we get more/less saves/restores? Does something go wrong?

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

313

The name should indicate that it is the index into the list of allocation orders. So maybe PPCSubtarget::getGPRAllocationOrderIdx()

[lkail]

llvm/test/CodeGen/PowerPC/inc-of-add.ll

165

I think it should be due utils/update_llc_test_checks.py is unable to handle different output with a same check prefix. I'll re-generate check for AIX.

[lkail]

Address comments.

[lkail]

Please add some info about how this affects functions that need the frame pointer. Do we get more/less saves/restores? Does something go wrong?

Looks nothing changed if a function needs frame pointer. No change found in test/CodeGen/PowerPC/aix-framepointer-save-restore.ll.

[shchenz]

llvm/lib/Target/PowerPC/PPCSubtarget.h

421

Can we use 0 here? 0 is not a valid allocation order index in the td file?

llvm/test/CodeGen/PowerPC/aix-csr-alloc.ll

9

In the allocation order definition, $x2 is allocatable, but here we don't have it. Maybe we can also use $x2 on AIX like what we did for ELF? Yeah, this should be not related to this patch, we can do it in another follow-up.

[lkail]

llvm/lib/Target/PowerPC/PPCSubtarget.h

421

0 corresponds to the default allocation order which is defined as the last argument of RegisterClass.
This can be checked in PPCGenRegisterInfo.inc

static inline unsigned GPRCAltOrderSelect(const MachineFunction &MF) {
    return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
  }

static ArrayRef<MCPhysReg> GPRCGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, PPC::FP, PPC::BP, PPC::R2 };
  static const MCPhysReg AltOrder2[] = { PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R31, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R0, PPC::R1, PPC::FP, PPC::BP };
  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRCRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1),
    makeArrayRef(AltOrder2)
  };
  const unsigned Select = GPRCAltOrderSelect(MF);
  assert(Select < 3);
  return Order[Select];
}

[lkail]

llvm/test/CodeGen/PowerPC/aix-csr-alloc.ll

9

// Always reserve r2 on AIX for now.
// TODO: Make r2 allocatable on AIX/XCOFF for some leaf functions.
if (Subtarget.isAIXABI())
  markSuperRegs(Reserved, PPC::R2);  // System-reserved register

Looks so, good point.

[qiucf]

llvm/test/CodeGen/PowerPC/inc-of-add.ll

165

Will D97106 help?

[lkail]

llvm/test/CodeGen/PowerPC/inc-of-add.ll

165

Looks it can't be applied cleanly and need rebase. Get through the patch, I think it would help. It's better than keeping silence when updating tests.

[ZarkoCA]

LGTM, thanks for rebasing and updating the patch. Just some comment suggestions.
I guess you may want to wait for the other reviewers to check if their comments were addressed to their liking.

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

304–312

320

We can also remove references to Darwin here and below since there isn't support for that PPC Subtarget in llc anymore. But this is just a suggestion as this isn't the main point of the patch.

llvm/test/CodeGen/PowerPC/aix-tracetable-csr.ll

17–20

Thank you for rebasing the patch because now this test is included and it shows exactly what this patch fixes with the traceback table.

[jsji]

LGTM. Thanks.

[xingxue]

Have we checked the allocation of non-volatile FPRs and VRs? Is it always in descending order, i.e. starting with FPR31 or VR31?

[lkail]

• Adjust comments
• Per @xingxue 's comment, show allocation orders of float and vector registers.

[xingxue]

LGTM, thanks!

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

 def RM: PPCReg<"**ROUNDING MODE**">;
 
 /// Register classes
 // Allocate volatiles first
 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
 def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12),
                                                     (sequence "R%u", 30, 13),
                                                     R31, R0, R1, FP, BP)> {
   // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
   // put it at the end of the list.
-  let AltOrders = [(add (sub GPRC, R2), R2)];
+  // On AIX, CSRs are allocated starting from R31 according to:
+  // https://www.ibm.com/docs/en/ssw_aix_72/assembler/assembler_pdf.pdf.
+  // This also helps setting the correct `NumOfGPRsSaved' in traceback table.
+  let AltOrders = [(add (sub GPRC, R2), R2),
+                   (add (sequence "R%u", 2, 12),
+                        (sequence "R%u", 31, 13), R0, R1, FP, BP)];
   let AltOrderSelect = [{
-    return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
+    return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
   }];
 }
 
 def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
                                                 (sequence "X%u", 30, 14),
                                                 X31, X13, X0, X1, FP8, BP8)> {
   // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
   // put it at the end of the list.
-  let AltOrders = [(add (sub G8RC, X2), X2)];
+  let AltOrders = [(add (sub G8RC, X2), X2),
+                   (add (sequence "X%u", 2, 12),
+                        (sequence "X%u", 31, 13), X0, X1, FP8, BP8)];
   let AltOrderSelect = [{
-    return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
+    return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
   }];
 }
 
 // For some instructions r0 is special (representing the value 0 instead of
 // the value in the r0 register), and we use these register subclasses to
 // prevent r0 from being allocated for use by those instructions.
 def GPRC_NOR0 : RegisterClass<"PPC", [i32,f32], 32, (add (sub GPRC, R0), ZERO)> {
   // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
   // put it at the end of the list.
-  let AltOrders = [(add (sub GPRC_NOR0, R2), R2)];
+  let AltOrders = [(add (sub GPRC_NOR0, R2), R2),
+                   (add (sequence "R%u", 2, 12),
+                        (sequence "R%u", 31, 13), R1, FP, BP, ZERO)];
   let AltOrderSelect = [{
-    return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
+    return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
   }];
 }
 
 def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)> {
   // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
   // put it at the end of the list.
-  let AltOrders = [(add (sub G8RC_NOX0, X2), X2)];
+  let AltOrders = [(add (sub G8RC_NOX0, X2), X2),
+                   (add (sequence "X%u", 2, 12),
+                        (sequence "X%u", 31, 13), X1, FP8, BP8, ZERO8)];
   let AltOrderSelect = [{
-    return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
+    return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
   }];
 }
 
 def SPERC : RegisterClass<"PPC", [f64], 64, (add (sequence "S%u", 2, 12),
                                                 (sequence "S%u", 30, 13),
                                                 S31, S0, S1)>;
 
 // Allocate volatiles first, then non-volatiles in reverse order. With the SVR4

llvm/lib/Target/PowerPC/PPCSubtarget.h

public:
   }
 
   bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
 
   bool isPredictableSelectIsExpensive() const {
     return PredictableSelectIsExpensive;
   }
 
+  // Select allocation orders of GPRC and G8RC. It should be strictly consistent
+  // with corresponding AltOrders in PPCRegisterInfo.td.
+  unsigned getGPRAllocationOrderIdx() const {
+    if (is64BitELFABI())
+      return 1;
+    if (isAIXABI())
+      return 2;
+    return 0;
+  }
+
   // GlobalISEL
   const CallLowering *getCallLowering() const override;
   const RegisterBankInfo *getRegBankInfo() const override;
   const LegalizerInfo *getLegalizerInfo() const override;
   InstructionSelector *getInstructionSelector() const override;
 };
 } // End llvm namespace
 
 #endif

llvm/test/CodeGen/PowerPC/aix-cc-abi.ll

 ; ASM32PWR4-DAG:   stw [[REG:[0-9]+]], 152(1)
 ; ASM32PWR4-DAG:   stw [[REG:[0-9]+]], 156(1)
 ; ASM32PWR4-DAG:   stw [[REG:[0-9]+]], 160(1)
 ; ASM32PWR4-DAG:   stw [[REG:[0-9]+]], 164(1)
 ; ASM32PWR4:       bl .mix_floats
 
 ; ASM64PWR4:      mflr 0
 ; ASM64PWR4-DAG:  std 0, 16(1)
-; ASM64PWR4-DAG:  stdu 1, -256(1)
+; ASM64PWR4-DAG:  stdu 1, -240(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 112(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 120(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 128(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 136(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 144(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 152(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 160(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 168(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 176(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 184(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 192(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 200(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 208(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 216(1)
 ; ASM64PWR4:      bl .mix_floats

llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll

 ; 32BIT-DAG:      $r8 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r9 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r10 = COPY %{{[0-9]+}}
 ; 32BIT-NEXT:     BL_NOP <mcsymbol .test_byval_mem3>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:     ADJCALLSTACKUP 92, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_mem3:
 
-; ASM32BIT:       stwu 1, -112(1)
+; ASM32BIT:       stwu 1, -96(1)
 ; ASM32BIT-DAG:   lwz [[REG:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32BIT-DAG:   addi 3, 1, 56
 ; ASM32BIT-DAG:   addi 4, [[REG]], 24
 ; ASM32BIT-DAG:   li 5, 33
 ; ASM32BIT-NEXT:  bl .memcpy[PR]
 ; ASM32BIT-DAG:   lwz 5, 0([[REG]])
 ; ASM32BIT-DAG:   lwz 6, 4([[REG]])
 ; ASM32BIT-DAG:   lwz 7, 8([[REG]])
 ; ASM32BIT-DAG:   lwz 8, 12([[REG]])
 ; ASM32BIT-DAG:   lwz 9, 16([[REG]])
 ; ASM32BIT-DAG:   lwz 10, 20([[REG]])
 ; ASM32BIT:       bl .test_byval_mem3
-; ASM32BIT:       addi 1, 1, 112
+; ASM32BIT:       addi 1, 1, 96
 
 ; The memcpy call was inlined in 64-bit so MIR test is redundant and omitted.
 ; ASM64BIT:       stdu 1, -128(1)
 ; ASM64BIT-DAG:   ld [[REG1:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64BIT-DAG:   ld [[REG2:[0-9]+]], 48([[REG1]])
 ; ASM64BIT-DAG:   std [[REG2]], 112(1)
 ; ASM64BIT-DAG:   lbz [[REG3:[0-9]+]], 56([[REG1]])
 ; ASM64BIT-DAG:   stb [[REG3]], 120(1)

 ; 32BIT-DAG:      $r6 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r7 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r8 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r9 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r10 = COPY %{{[0-9]+}}
 ; 32BIT-NEXT:     BL_NOP <mcsymbol .test_byval_mem4>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:     ADJCALLSTACKUP 316, 0, implicit-def dead $r1, implicit $r1
 
-; ASM32BIT:       stwu 1, -336(1)
+; ASM32BIT:       stwu 1, -320(1)
 ; ASM32BIT-NEXT:  stw [[REG1:[0-9]+]], {{[0-9]+}}(1)
 ; ASM32BIT:       lwz [[REG1]], L..C{{[0-9]+}}(2)
 ; ASM32BIT-DAG:   lhz [[REG2:[0-9]+]], 28([[REG1]])
 ; ASM32BIT-DAG:   sth [[REG2]], 56(1)
 ; ASM32BIT-DAG:   lbz [[REG3:[0-9]+]], 30([[REG1]])
 ; ASM32BIT-DAG:   stb [[REG3]], 58(1)
 ; ASM32BIT-DAG:   addi 3, 1, 60
 ; ASM32BIT-DAG:   lwz 4, L..C{{[0-9]+}}(2)
 ; ASM32BIT-DAG:   li 5, 256
 ; ASM32BIT-NEXT:  bl .memcpy[PR]
 ; ASM32BIT-DAG:   lwz 4, 0([[REG1]])
 ; ASM32BIT-DAG:   lwz 5, 4([[REG1]])
 ; ASM32BIT-DAG:   lwz 6, 8([[REG1]])
 ; ASM32BIT-DAG:   lwz 7, 12([[REG1]])
 ; ASM32BIT-DAG:   lwz 8, 16([[REG1]])
 ; ASM32BIT-DAG:   lwz 9, 20([[REG1]])
 ; ASM32BIT-DAG:   lwz 10, 24([[REG1]])
 ; ASM32BIT:       bl .test_byval_mem4
-; ASM32BIT:       addi 1, 1, 336
+; ASM32BIT:       addi 1, 1, 320
 
 ; Confirm the expected memcpy call is independent of the call to test_byval_mem4.
 ; 64BIT:          ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:     %0:g8rc_and_g8rc_nox0 = LDtoc @gS256, $x2 :: (load (s64) from got)
 ; 64BIT-NEXT:     %1:g8rc = nuw ADDI8 %0, 24
 ; 64BIT-NEXT:     %2:g8rc = nuw ADDI8 $x1, 112
 ; 64BIT-NEXT:     %3:g8rc = LI8 232
 ; 64BIT-DAG:      $x3 = COPY %2
 ; 64BIT-DAG:      $x4 = COPY %1
 ; 64BIT-DAG:      $x5 = COPY %3
 ; 64BIT-NEXT:     BL8_NOP &".memcpy[PR]", csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1, implicit-def $x3
 ; 64BIT-NEXT:     ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT:          ADJCALLSTACKDOWN 344, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-DAG:      $x3 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x4 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x5 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x6 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x7 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x8 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x9 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x10 = COPY %{{[0-9]+}}
 ; 64BIT-NEXT:     BL8_NOP <mcsymbol .test_byval_mem4>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:     ADJCALLSTACKUP 344, 0, implicit-def dead $r1, implicit $r1
 
-; ASM64BIT:       stdu 1, -368(1)
+; ASM64BIT:       stdu 1, -352(1)
 ; ASM64BIT-DAG:   ld [[REG1:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64BIT-DAG:   addi 3, 1, 112
 ; ASM64BIT-DAG:   addi 4, [[REG1]], 24
 ; ASM64BIT-DAG:   li 5, 232
 ; ASM64BIT-NEXT:  bl .memcpy[PR]
 ; ASM64BIT-DAG:   ld [[REG2:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64BIT-DAG:   ld 4, 0([[REG2]])
 ; ASM64BIT-DAG:   ld 5, 8([[REG2]])
 ; ASM64BIT-DAG:   ld 6, 16([[REG2]])
 ; ASM64BIT-DAG:   lwz [[REG3:[0-9]+]], 24([[REG2]])
 ; ASM64BIT-DAG:   lhz [[REG4:[0-9]+]], 28([[REG2]])
 ; ASM64BIT-DAG:   lbz 7, 30([[REG2]])
 ; ASM64BIT-DAG:   rlwinm 7, 7, 8, 16, 23
 ; ASM64BIT-DAG:   rlwimi 7, [[REG4]], 16, 0, 15
 ; ASM64BIT-DAG:   rldimi 7, [[REG3]], 32, 0
 ; ASM64BIT-DAG:   ld 8, 0([[REG1]])
 ; ASM64BIT-DAG:   ld 9, 8([[REG1]])
 ; ASM64BIT-DAG:   ld 10, 16([[REG1]])
 ; ASM64BIT:       bl .test_byval_mem4
-; ASM64BIT:       addi 1, 1, 368
+; ASM64BIT:       addi 1, 1, 352
 
 define void @test_byval_mem4(i32, %struct_S31* byval(%struct_S31) align 1, %struct_S256* byval(%struct_S256) align 1 %s) {
 entry:
   ret void
 }
 
 ; CHECK-LABEL:    name:            test_byval_mem4
 

llvm/test/CodeGen/PowerPC/aix-csr-alloc.ll

+; REQUIRES: asserts
+; RUN: llc -mtriple=powerpc64-aix-xcoff -debug-only=regalloc < %s 2>&1 | \
+; RUN:   FileCheck --check-prefix=AIX-64 %s
+; RUN: llc -mtriple=powerpc-aix-xcoff -debug-only=regalloc < %s 2>&1 | \
+; RUN:   FileCheck --check-prefix=AIX-32 %s
+
+define i32 @g(i32 %a, i32 %b) {
+; AIX-64: AllocationOrder(G8RC_and_G8RC_NOX0) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x31 $x30 $x29 $x28 $x27 $x26 $x25 $x24 $x23 $x22 $x21 $x20 $x19 $x18 $x17 $x16 $x15 $x14 ]
+; AIX-64: AllocationOrder(G8RC) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x0 $x31 $x30 $x29 $x28 $x27 $x26 $x25 $x24 $x23 $x22 $x21 $x20 $x19 $x18 $x17 $x16 $x15 $x14 ]
+; AIX-32: AllocationOrder(GPRC) = [ $r3 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $r12 $r0 $r31 $r30 $r29 $r28 $r27 $r26 $r25 $r24 $r23 $r22 $r21 $r20 $r19 $r18 $r17 $r16 $r15 $r14 $r13 ]
+; AIX-32: AllocationOrder(GPRC_and_GPRC_NOR0) = [ $r3 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $r12 $r31 $r30 $r29 $r28 $r27 $r26 $r25 $r24 $r23 $r22 $r21 $r20 $r19 $r18 $r17 $r16 $r15 $r14 $r13 ]
+  %c = add i32 %a, %b
+  %d = shl i32 %a, 4
+  %cmp = icmp slt i32 %c, %d
+  %e = select i1 %cmp, i32 %a, i32 %b
+  ret i32 %e
+}
+
+define float @f(float %a, float %b) {
+; AIX-32: AllocationOrder(F4RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 ]
+  %c = fadd float %a, %b
+  ret float %c
+}
+
+define double @d(double %a, double %b) {
+; AIX-64: AllocationOrder(VFRC) = [ $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $vf31 $vf30 $vf29 $vf28 $vf27 $vf26 $vf25 $vf24 $vf23 $vf22 $vf21 $vf20 ]
+; AIX-64: AllocationOrder(F8RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 ]
+  %c = fadd double %a, %b
+  ret double %c
+}

llvm/test/CodeGen/PowerPC/aix-tracetable-csr.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefix=AIX-64 %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefix=AIX-32 %s
 
 %0 = type { i8*, i8*, i8*, i8*, i8*, i32, i32, i32, i16, i16, [4 x i64] }
 %1 = type { [167 x i64] }
 %2 = type { [179 x i64] }
 %3 = type { i64, void (i32, %3*)*, i64, i64 }
 
 declare i32 @wibble(%1*) local_unnamed_addr #0
 
 declare hidden fastcc i32 @spam(%1*, %2*, %3*) unnamed_addr #0
 
 ; Function Attrs: nounwind
 define void @baz(%3* %0) local_unnamed_addr #2 {
-; AIX-64: std 30
-; AIX-64: .byte 0x02 # -HasVectorInfo, -HasExtensionTable, NumOfGPRsSaved = 2
-; AIX-32: stw 30
-; AIX-32: .byte 0x02 # -HasVectorInfo, -HasExtensionTable, NumOfGPRsSaved = 2
+; AIX-64: std 31
+; AIX-64: .byte 0x01 # -HasVectorInfo, -HasExtensionTable, NumOfGPRsSaved = 1
+; AIX-32: stw 31
+; AIX-32: .byte 0x01 # -HasVectorInfo, -HasExtensionTable, NumOfGPRsSaved = 1
   %2 = call signext i32 @wibble(%1* nonnull undef) #2
   %3 = call fastcc zeroext i32 @spam(%1* nonnull undef, %2* nonnull undef, %3* nonnull %0)
   unreachable
 }

llvm/test/CodeGen/PowerPC/inc-of-add.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=ppc32-unknown-unknown | FileCheck %s --check-prefixes=ALL,PPC32
 ; RUN: llc < %s -mtriple=powerpc64-unknown-unknown | FileCheck %s --check-prefixes=ALL,PPC64,PPC64BE
-; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff | FileCheck %s --check-prefixes=ALL,PPC64,PPC64BE
+; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff | FileCheck %s --check-prefixes=ALL,PPC64,PPC64BE,AIX-PPC64
 ; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s --check-prefixes=ALL,PPC64,PPC64LE
 
 ; These two forms are equivalent:
 ;   sub %y, (xor %x, -1)
 ;   add (add %x, 1), %y
 ; Some targets may prefer one to the other.
 
 define i8 @scalar_i8(i8 %x, i8 %y) nounwind {

 ; PPC32-NEXT:    lwz 25, 36(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 24, 32(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 23, 28(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 22, 24(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 21, 20(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    addi 1, 1, 64
 ; PPC32-NEXT:    blr
 ;
-; PPC64BE-LABEL: vector_i128_i8:
-; PPC64BE:       # %bb.0:
-; PPC64BE-NEXT:    std 21, -88(1) # 8-byte Folded Spill
-; PPC64BE-NEXT:    lbz 21, 207(1)
-; PPC64BE-NEXT:    std 22, -80(1) # 8-byte Folded Spill
-; PPC64BE-NEXT:    std 23, -72(1) # 8-byte Folded Spill
-; PPC64BE-NEXT:    std 25, -56(1) # 8-byte Folded Spill
-; PPC64BE-NEXT:    std 24, -64(1) # 8-byte Folded Spill
-; PPC64BE-NEXT:    std 28, -32(1) # 8-byte Folded Spill
-; PPC64BE-NEXT:    std 27, -40(1) # 8-byte Folded Spill
-; PPC64BE-NEXT:    std 26, -48(1) # 8-byte Folded Spill
-; PPC64BE-NEXT:    std 30, -16(1) # 8-byte Folded Spill
-; PPC64BE-NEXT:    std 29, -24(1) # 8-byte Folded Spill
-; PPC64BE-NEXT:    lbz 22, 199(1)
-; PPC64BE-NEXT:    lbz 23, 191(1)
-; PPC64BE-NEXT:    add 6, 21, 6
-; PPC64BE-NEXT:    lbz 21, 231(1)
-; PPC64BE-NEXT:    add 5, 22, 5
-; PPC64BE-NEXT:    lbz 22, 223(1)
-; PPC64BE-NEXT:    add 4, 23, 4
-; PPC64BE-NEXT:    lbz 23, 215(1)
-; PPC64BE-NEXT:    add 9, 21, 9
-; PPC64BE-NEXT:    lbz 25, 127(1)
-; PPC64BE-NEXT:    add 8, 22, 8
-; PPC64BE-NEXT:    lbz 21, 255(1)
-; PPC64BE-NEXT:    add 7, 23, 7
-; PPC64BE-NEXT:    lbz 24, 119(1)
-; PPC64BE-NEXT:    addi 9, 9, 1
-; PPC64BE-NEXT:    lbz 22, 247(1)
-; PPC64BE-NEXT:    add 25, 21, 25
-; PPC64BE-NEXT:    lbz 23, 239(1)
-; PPC64BE-NEXT:    addi 8, 8, 1
-; PPC64BE-NEXT:    lbz 28, 151(1)
-; PPC64BE-NEXT:    add 24, 22, 24
-; PPC64BE-NEXT:    lbz 21, 279(1)
-; PPC64BE-NEXT:    add 10, 23, 10
-; PPC64BE-NEXT:    lbz 27, 143(1)
-; PPC64BE-NEXT:    addi 10, 10, 1
-; PPC64BE-NEXT:    lbz 22, 271(1)
-; PPC64BE-NEXT:    add 28, 21, 28
-; PPC64BE-NEXT:    lbz 26, 135(1)
-; PPC64BE-NEXT:    addi 7, 7, 1
-; PPC64BE-NEXT:    lbz 23, 263(1)
-; PPC64BE-NEXT:    add 27, 22, 27
-; PPC64BE-NEXT:    lbz 11, 183(1)
-; PPC64BE-NEXT:    addi 6, 6, 1
-; PPC64BE-NEXT:    lbz 21, 311(1)
-; PPC64BE-NEXT:    add 26, 23, 26
-; PPC64BE-NEXT:    lbz 12, 175(1)
-; PPC64BE-NEXT:    addi 5, 5, 1
-; PPC64BE-NEXT:    lbz 0, 303(1)
-; PPC64BE-NEXT:    add 11, 21, 11
-; PPC64BE-NEXT:    lbz 30, 167(1)
-; PPC64BE-NEXT:    addi 11, 11, 1
-; PPC64BE-NEXT:    lbz 22, 295(1)
-; PPC64BE-NEXT:    add 12, 0, 12
-; PPC64BE-NEXT:    lbz 29, 159(1)
-; PPC64BE-NEXT:    addi 4, 4, 1
-; PPC64BE-NEXT:    lbz 23, 287(1)
-; PPC64BE-NEXT:    add 30, 22, 30
-; PPC64BE-NEXT:    stb 11, 15(3)
-; PPC64BE-NEXT:    addi 11, 12, 1
-; PPC64BE-NEXT:    add 29, 23, 29
-; PPC64BE-NEXT:    stb 11, 14(3)
-; PPC64BE-NEXT:    addi 11, 30, 1
-; PPC64BE-NEXT:    stb 11, 13(3)
-; PPC64BE-NEXT:    addi 11, 29, 1
-; PPC64BE-NEXT:    stb 11, 12(3)
-; PPC64BE-NEXT:    addi 11, 28, 1
-; PPC64BE-NEXT:    stb 11, 11(3)
-; PPC64BE-NEXT:    addi 11, 27, 1
-; PPC64BE-NEXT:    stb 11, 10(3)
-; PPC64BE-NEXT:    addi 11, 26, 1
-; PPC64BE-NEXT:    stb 11, 9(3)
-; PPC64BE-NEXT:    addi 11, 25, 1
-; PPC64BE-NEXT:    stb 11, 8(3)
-; PPC64BE-NEXT:    addi 11, 24, 1
-; PPC64BE-NEXT:    stb 11, 7(3)
-; PPC64BE-NEXT:    stb 10, 6(3)
-; PPC64BE-NEXT:    stb 9, 5(3)
-; PPC64BE-NEXT:    stb 8, 4(3)
-; PPC64BE-NEXT:    stb 7, 3(3)
-; PPC64BE-NEXT:    stb 6, 2(3)
-; PPC64BE-NEXT:    stb 5, 1(3)
-; PPC64BE-NEXT:    stb 4, 0(3)
-; PPC64BE-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
-; PPC64BE-NEXT:    ld 29, -24(1) # 8-byte Folded Reload
-; PPC64BE-NEXT:    ld 28, -32(1) # 8-byte Folded Reload
-; PPC64BE-NEXT:    ld 27, -40(1) # 8-byte Folded Reload
-; PPC64BE-NEXT:    ld 26, -48(1) # 8-byte Folded Reload
-; PPC64BE-NEXT:    ld 25, -56(1) # 8-byte Folded Reload
-; PPC64BE-NEXT:    ld 24, -64(1) # 8-byte Folded Reload
-; PPC64BE-NEXT:    ld 23, -72(1) # 8-byte Folded Reload
-; PPC64BE-NEXT:    ld 22, -80(1) # 8-byte Folded Reload
-; PPC64BE-NEXT:    ld 21, -88(1) # 8-byte Folded Reload
-; PPC64BE-NEXT:    blr
+; AIX-PPC64-LABEL: vector_i128_i8:
+; AIX-PPC64:       # %bb.0:
+; AIX-PPC64-NEXT:    std 22, -80(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT:    lbz 22, 207(1)
+; AIX-PPC64-NEXT:    std 23, -72(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT:    std 24, -64(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT:    std 26, -48(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT:    std 25, -56(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT:    std 29, -24(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT:    std 28, -32(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT:    std 27, -40(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT:    std 31, -8(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT:    std 30, -16(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT:    lbz 23, 199(1)
+; AIX-PPC64-NEXT:    lbz 24, 191(1)
+; AIX-PPC64-NEXT:    add 6, 22, 6
+; AIX-PPC64-NEXT:    lbz 22, 231(1)
+; AIX-PPC64-NEXT:    add 5, 23, 5
+; AIX-PPC64-NEXT:    lbz 23, 223(1)
+; AIX-PPC64-NEXT:    add 4, 24, 4
+; AIX-PPC64-NEXT:    lbz 24, 215(1)
+; AIX-PPC64-NEXT:    add 9, 22, 9
+; AIX-PPC64-NEXT:    lbz 26, 127(1)
+; AIX-PPC64-NEXT:    add 8, 23, 8
+; AIX-PPC64-NEXT:    lbz 22, 255(1)
+; AIX-PPC64-NEXT:    add 7, 24, 7
+; AIX-PPC64-NEXT:    lbz 25, 119(1)
+; AIX-PPC64-NEXT:    addi 9, 9, 1
+; AIX-PPC64-NEXT:    lbz 23, 247(1)
+; AIX-PPC64-NEXT:    add 26, 22, 26
+; AIX-PPC64-NEXT:    lbz 24, 239(1)
+; AIX-PPC64-NEXT:    addi 8, 8, 1
+; AIX-PPC64-NEXT:    lbz 29, 151(1)
+; AIX-PPC64-NEXT:    add 25, 23, 25
+; AIX-PPC64-NEXT:    lbz 22, 279(1)
+; AIX-PPC64-NEXT:    add 10, 24, 10
+; AIX-PPC64-NEXT:    lbz 28, 143(1)
+; AIX-PPC64-NEXT:    addi 10, 10, 1
+; AIX-PPC64-NEXT:    lbz 23, 271(1)
+; AIX-PPC64-NEXT:    add 29, 22, 29
+; AIX-PPC64-NEXT:    lbz 27, 135(1)
+; AIX-PPC64-NEXT:    addi 7, 7, 1
+; AIX-PPC64-NEXT:    lbz 24, 263(1)
+; AIX-PPC64-NEXT:    add 28, 23, 28
+; AIX-PPC64-NEXT:    lbz 11, 183(1)
+; AIX-PPC64-NEXT:    addi 6, 6, 1
+; AIX-PPC64-NEXT:    lbz 22, 311(1)
+; AIX-PPC64-NEXT:    add 27, 24, 27
+; AIX-PPC64-NEXT:    lbz 12, 175(1)
+; AIX-PPC64-NEXT:    addi 5, 5, 1
+; AIX-PPC64-NEXT:    lbz 0, 303(1)
+; AIX-PPC64-NEXT:    add 11, 22, 11
+; AIX-PPC64-NEXT:    lbz 31, 167(1)
+; AIX-PPC64-NEXT:    addi 11, 11, 1
+; AIX-PPC64-NEXT:    lbz 23, 295(1)
+; AIX-PPC64-NEXT:    add 12, 0, 12
+; AIX-PPC64-NEXT:    lbz 30, 159(1)
+; AIX-PPC64-NEXT:    addi 4, 4, 1
+; AIX-PPC64-NEXT:    lbz 24, 287(1)
+; AIX-PPC64-NEXT:    add 31, 23, 31
+; AIX-PPC64-NEXT:    stb 11, 15(3)
+; AIX-PPC64-NEXT:    addi 11, 12, 1
+; AIX-PPC64-NEXT:    add 30, 24, 30
+; AIX-PPC64-NEXT:    stb 11, 14(3)
+; AIX-PPC64-NEXT:    addi 11, 31, 1
+; AIX-PPC64-NEXT:    stb 11, 13(3)
+; AIX-PPC64-NEXT:    addi 11, 30, 1
+; AIX-PPC64-NEXT:    stb 11, 12(3)
+; AIX-PPC64-NEXT:    addi 11, 29, 1
+; AIX-PPC64-NEXT:    stb 11, 11(3)
+; AIX-PPC64-NEXT:    addi 11, 28, 1
+; AIX-PPC64-NEXT:    stb 11, 10(3)
+; AIX-PPC64-NEXT:    addi 11, 27, 1
+; AIX-PPC64-NEXT:    stb 11, 9(3)
+; AIX-PPC64-NEXT:    addi 11, 26, 1
+; AIX-PPC64-NEXT:    stb 11, 8(3)
+; AIX-PPC64-NEXT:    addi 11, 25, 1
+; AIX-PPC64-NEXT:    stb 11, 7(3)
+; AIX-PPC64-NEXT:    stb 10, 6(3)
+; AIX-PPC64-NEXT:    stb 9, 5(3)
+; AIX-PPC64-NEXT:    stb 8, 4(3)
+; AIX-PPC64-NEXT:    stb 7, 3(3)
+; AIX-PPC64-NEXT:    stb 6, 2(3)
+; AIX-PPC64-NEXT:    stb 5, 1(3)
+; AIX-PPC64-NEXT:    stb 4, 0(3)
+; AIX-PPC64-NEXT:    ld 31, -8(1) # 8-byte Folded Reload
+; AIX-PPC64-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
+; AIX-PPC64-NEXT:    ld 29, -24(1) # 8-byte Folded Reload
+; AIX-PPC64-NEXT:    ld 28, -32(1) # 8-byte Folded Reload
+; AIX-PPC64-NEXT:    ld 27, -40(1) # 8-byte Folded Reload
+; AIX-PPC64-NEXT:    ld 26, -48(1) # 8-byte Folded Reload
+; AIX-PPC64-NEXT:    ld 25, -56(1) # 8-byte Folded Reload
+; AIX-PPC64-NEXT:    ld 24, -64(1) # 8-byte Folded Reload
+; AIX-PPC64-NEXT:    ld 23, -72(1) # 8-byte Folded Reload
+; AIX-PPC64-NEXT:    ld 22, -80(1) # 8-byte Folded Reload
+; AIX-PPC64-NEXT:    blr
 ;
 ; PPC64LE-LABEL: vector_i128_i8:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    xxlnor 34, 34, 34
 ; PPC64LE-NEXT:    vsububm 2, 3, 2
 ; PPC64LE-NEXT:    blr
   %t0 = add <16 x i8> %x, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %t1 = add <16 x i8> %y, %t0

 ; PPC32-NEXT:    lwz 30, 24(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 29, 20(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 28, 16(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 27, 12(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 26, 8(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    addi 1, 1, 32
 ; PPC32-NEXT:    blr
 ;
-; PPC64BE-LABEL: vector_i128_i16:
-; PPC64BE:       # %bb.0:
-; PPC64BE-NEXT:    std 25, -56(1) # 8-byte Folded Spill
-; PPC64BE-NEXT:    std 26, -48(1) # 8-byte Folded Spill
-; PPC64BE-NEXT:    std 27, -40(1) # 8-byte Folded Spill
-; PPC64BE-NEXT:    std 28, -32(1) # 8-byte Folded Spill
-; PPC64BE-NEXT:    std 29, -24(1) # 8-byte Folded Spill
-; PPC64BE-NEXT:    std 30, -16(1) # 8-byte Folded Spill
-; PPC64BE-NEXT:    lhz 11, 118(1)
-; PPC64BE-NEXT:    lhz 12, 182(1)
-; PPC64BE-NEXT:    lhz 0, 174(1)
-; PPC64BE-NEXT:    lhz 30, 166(1)
-; PPC64BE-NEXT:    add 11, 12, 11
-; PPC64BE-NEXT:    lhz 29, 158(1)
-; PPC64BE-NEXT:    add 10, 0, 10
-; PPC64BE-NEXT:    lhz 28, 142(1)
-; PPC64BE-NEXT:    add 9, 30, 9
-; PPC64BE-NEXT:    lhz 27, 126(1)
-; PPC64BE-NEXT:    add 8, 29, 8
-; PPC64BE-NEXT:    lhz 26, 134(1)
-; PPC64BE-NEXT:    add 6, 28, 6
-; PPC64BE-NEXT:    lhz 25, 150(1)
-; PPC64BE-NEXT:    add 4, 27, 4
-; PPC64BE-NEXT:    add 5, 26, 5
-; PPC64BE-NEXT:    addi 11, 11, 1
-; PPC64BE-NEXT:    add 7, 25, 7
-; PPC64BE-NEXT:    addi 10, 10, 1
-; PPC64BE-NEXT:    addi 9, 9, 1
-; PPC64BE-NEXT:    addi 8, 8, 1
-; PPC64BE-NEXT:    addi 7, 7, 1
-; PPC64BE-NEXT:    addi 6, 6, 1
-; PPC64BE-NEXT:    addi 5, 5, 1
-; PPC64BE-NEXT:    addi 4, 4, 1
-; PPC64BE-NEXT:    sth 11, 14(3)
-; PPC64BE-NEXT:    sth 10, 12(3)
-; PPC64BE-NEXT:    sth 9, 10(3)
-; PPC64BE-NEXT:    sth 8, 8(3)
-; PPC64BE-NEXT:    sth 7, 6(3)
-; PPC64BE-NEXT:    sth 6, 4(3)
-; PPC64BE-NEXT:    sth 5, 2(3)
-; PPC64BE-NEXT:    sth 4, 0(3)
-; PPC64BE-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
-; PPC64BE-NEXT:    ld 29, -24(1) # 8-byte Folded Reload
-; PPC64BE-NEXT:    ld 28, -32(1) # 8-byte Folded Reload
-; PPC64BE-NEXT:    ld 27, -40(1) # 8-byte Folded Reload
-; PPC64BE-NEXT:    ld 26, -48(1) # 8-byte Folded Reload
-; PPC64BE-NEXT:    ld 25, -56(1) # 8-byte Folded Reload
-; PPC64BE-NEXT:    blr
+; AIX-PPC64-LABEL: vector_i128_i16:
+; AIX-PPC64:       # %bb.0:
+; AIX-PPC64-NEXT:    std 26, -48(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT:    std 27, -40(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT:    std 28, -32(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT:    std 29, -24(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT:    std 30, -16(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT:    std 31, -8(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT:    lhz 11, 118(1)
+; AIX-PPC64-NEXT:    lhz 12, 182(1)
+; AIX-PPC64-NEXT:    lhz 0, 174(1)
+; AIX-PPC64-NEXT:    lhz 31, 166(1)
+; AIX-PPC64-NEXT:    add 11, 12, 11
+; AIX-PPC64-NEXT:    lhz 30, 158(1)
+; AIX-PPC64-NEXT:    add 10, 0, 10
+; AIX-PPC64-NEXT:    lhz 29, 142(1)
+; AIX-PPC64-NEXT:    add 9, 31, 9
+; AIX-PPC64-NEXT:    lhz 28, 126(1)
+; AIX-PPC64-NEXT:    add 8, 30, 8
+; AIX-PPC64-NEXT:    lhz 27, 134(1)
+; AIX-PPC64-NEXT:    add 6, 29, 6
+; AIX-PPC64-NEXT:    lhz 26, 150(1)
+; AIX-PPC64-NEXT:    add 4, 28, 4
+; AIX-PPC64-NEXT:    add 5, 27, 5
+; AIX-PPC64-NEXT:    addi 11, 11, 1
+; AIX-PPC64-NEXT:    add 7, 26, 7
+; AIX-PPC64-NEXT:    addi 10, 10, 1
+; AIX-PPC64-NEXT:    addi 9, 9, 1
+; AIX-PPC64-NEXT:    addi 8, 8, 1
+; AIX-PPC64-NEXT:    addi 7, 7, 1
+; AIX-PPC64-NEXT:    addi 6, 6, 1
+; AIX-PPC64-NEXT:    addi 5, 5, 1
+; AIX-PPC64-NEXT:    addi 4, 4, 1
+; AIX-PPC64-NEXT:    sth 11, 14(3)
+; AIX-PPC64-NEXT:    sth 10, 12(3)
+; AIX-PPC64-NEXT:    sth 9, 10(3)
+; AIX-PPC64-NEXT:    sth 8, 8(3)
+; AIX-PPC64-NEXT:    sth 7, 6(3)
+; AIX-PPC64-NEXT:    sth 6, 4(3)
+; AIX-PPC64-NEXT:    sth 5, 2(3)
+; AIX-PPC64-NEXT:    sth 4, 0(3)
+; AIX-PPC64-NEXT:    ld 31, -8(1) # 8-byte Folded Reload
+; AIX-PPC64-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
+; AIX-PPC64-NEXT:    ld 29, -24(1) # 8-byte Folded Reload
+; AIX-PPC64-NEXT:    ld 28, -32(1) # 8-byte Folded Reload
+; AIX-PPC64-NEXT:    ld 27, -40(1) # 8-byte Folded Reload
+; AIX-PPC64-NEXT:    ld 26, -48(1) # 8-byte Folded Reload
+; AIX-PPC64-NEXT:    blr
 ;
 ; PPC64LE-LABEL: vector_i128_i16:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    xxlnor 34, 34, 34
 ; PPC64LE-NEXT:    vsubuhm 2, 3, 2
 ; PPC64LE-NEXT:    blr
   %t0 = add <8 x i16> %x, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %t1 = add <8 x i16> %y, %t0