This is an archive of the discontinued LLVM Phabricator instance.

[RISCV][Clang] Add some RVV Permutation intrinsic functions.
ClosedPublic

Authored by khchen on Apr 8 2021, 10:18 AM.

Details

Summary

Support the following instructions.

  1. Vector Slide Instructions
  2. Vector Register Gather Instructions
  3. Vector Compress Instruction

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Diff Detail

Event Timeline

khchen created this revision.Apr 8 2021, 10:18 AM
khchen requested review of this revision.Apr 8 2021, 10:18 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 8 2021, 10:18 AM
This revision is now accepted and ready to land.Apr 8 2021, 12:15 PM
This revision was landed with ongoing or failed builds.Apr 11 2021, 7:30 PM
This revision was automatically updated to reflect the committed changes.
clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c