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Show First 20 Lines • Show All 267 Lines • ▼ Show 20 Lines	multiclass RVVUnsignedBinBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "csil",		: RVVOutOp1BuiltinSet<NAME, "csil",
[["vv", "Uv", "UvUvUv"],		[["vv", "Uv", "UvUvUv"],
["vx", "Uv", "UvUvUe"]]>;		["vx", "Uv", "UvUvUe"]]>;

multiclass RVVIntBinBuiltinSet		multiclass RVVIntBinBuiltinSet
: RVVSignedBinBuiltinSet,		: RVVSignedBinBuiltinSet,
RVVUnsignedBinBuiltinSet;		RVVUnsignedBinBuiltinSet;

		multiclass RVVSlideOneBuiltinSet
		: RVVOutOp1BuiltinSet<NAME, "csil",
		[["vx", "v", "vve"],
		["vx", "Uv", "UvUve"]]>;

multiclass RVVSignedShiftBuiltinSet		multiclass RVVSignedShiftBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "csil",		: RVVOutOp1BuiltinSet<NAME, "csil",
[["vv", "v", "vvUv"],		[["vv", "v", "vvUv"],
["vx", "v", "vvz"]]>;		["vx", "v", "vvz"]]>;

multiclass RVVUnsignedShiftBuiltinSet		multiclass RVVUnsignedShiftBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "csil",		: RVVOutOp1BuiltinSet<NAME, "csil",
[["vv", "Uv", "UvUvUv"],		[["vv", "Uv", "UvUvUv"],
▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines	class RVVMaskNullaryBuiltin : RVVOutBuiltin<"m", "m", "c"> {
let HasNoMaskedOverloaded = false;		let HasNoMaskedOverloaded = false;
}		}

class RVVMaskOp0Builtin<string prototype> : RVVOp0Builtin<"m", prototype, "c"> {		class RVVMaskOp0Builtin<string prototype> : RVVOp0Builtin<"m", prototype, "c"> {
let Name = NAME # "_m";		let Name = NAME # "_m";
let HasMaskedOffOperand = false;		let HasMaskedOffOperand = false;
}		}

		let HasMaskedOffOperand = false in {
		multiclass RVVSlideBuiltinSet {
		defm "" : RVVOutBuiltinSet<NAME, "csilfd",
		[["vx","v", "vvvz"]]>;
		defm "" : RVVOutBuiltinSet<NAME, "csil",
		[["vx","Uv", "UvUvUvz"]]>;
		}
		}

class RVVFloatingUnaryBuiltin<string builtin_suffix, string ir_suffix,		class RVVFloatingUnaryBuiltin<string builtin_suffix, string ir_suffix,
string prototype>		string prototype>
: RVVOutBuiltin<ir_suffix, prototype, "fd"> {		: RVVOutBuiltin<ir_suffix, prototype, "fd"> {
let Name = NAME # "_" # builtin_suffix;		let Name = NAME # "_" # builtin_suffix;
}		}

class RVVFloatingUnaryVVBuiltin : RVVFloatingUnaryBuiltin<"v", "v", "vv">;		class RVVFloatingUnaryVVBuiltin : RVVFloatingUnaryBuiltin<"v", "v", "vv">;
▲ Show 20 Lines • Show All 766 Lines • ▼ Show 20 Lines
let HasNoMaskedOverloaded = false in {		let HasNoMaskedOverloaded = false in {
// 16.8. Vector Iota Instruction		// 16.8. Vector Iota Instruction
defm viota : RVVOutBuiltinSet<"viota", "csil", [["m", "Uv", "Uvm"]]>;		defm viota : RVVOutBuiltinSet<"viota", "csil", [["m", "Uv", "Uvm"]]>;

// 16.9. Vector Element Index Instruction		// 16.9. Vector Element Index Instruction
defm vid : RVVOutBuiltinSet<"vid", "csil", [["v", "v", "v"],		defm vid : RVVOutBuiltinSet<"vid", "csil", [["v", "v", "v"],
["v", "Uv", "Uv"]]>;		["v", "Uv", "Uv"]]>;
}		}

		// 17. Vector Permutation Instructions
		// 17.1. Integer Scalar Move Instructions
		// TODO

		// 17.2. Floating-Point Scalar Move Instructions
		// TODO

		// 17.3. Vector Slide Instructions
		// 17.3.1. Vector Slideup Instructions
		defm vslideup : RVVSlideBuiltinSet;
		// 17.3.2. Vector Slidedown Instructions
		defm vslidedown : RVVSlideBuiltinSet;

		// 17.3.3. Vector Slide1up Instructions
		defm vslide1up : RVVSlideOneBuiltinSet;
		defm vfslide1up : RVVFloatingBinVFBuiltinSet;

		// 17.3.4. Vector Slide1down Instruction
		defm vslide1down : RVVSlideOneBuiltinSet;
		defm vfslide1down : RVVFloatingBinVFBuiltinSet;

		// 17.4. Vector Register Gather Instructions
		// signed and floating type
		defm vrgather : RVVOutBuiltinSet<"vrgather_vv", "csilfd",
		[["vv", "v", "vvUv"]]>;
		defm vrgather : RVVOutBuiltinSet<"vrgather_vx", "csilfd",
		[["vx", "v", "vvz"]]>;
		defm vrgatherei16 : RVVOutBuiltinSet<"vrgatherei16_vv", "csilfd",
		[["vv", "v", "vv(Log2EEW:4)Uv"]]>;
		// unsigned type
		defm vrgather : RVVOutBuiltinSet<"vrgather_vv", "csil",
		[["vv", "Uv", "UvUvUv"]]>;
		defm vrgather : RVVOutBuiltinSet<"vrgather_vx", "csil",
		[["vx", "Uv", "UvUvz"]]>;
		defm vrgatherei16 : RVVOutBuiltinSet<"vrgatherei16_vv", "csil",
		[["vv", "Uv", "UvUv(Log2EEW:4)Uv"]]>;

		// 17.5. Vector Compress Instruction
		let HasMask = false, PermuteOperands = [2, 0, 1] in {
		// signed and floating type
		defm vcompress : RVVOutBuiltinSet<"vcompress", "csilfd",
		[["vm", "v", "vvvm"]]>;
		// unsigned type
		defm vcompress : RVVOutBuiltinSet<"vcompress", "csil",
		[["vm", "Uv", "UvUvUvm"]]>;
		}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c

This file was added.

				// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
				// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 \| FileCheck --check-prefix=ASM --allow-empty %s

				// ASM-NOT: warning
				#include <riscv_vector.h>

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i32(<vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR6:#.*]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR6:#.*]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vfslide1down_vf_f32mf2(vfloat32mf2_t src, float value,
				size_t vl) {
				return vfslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i32(<vscale x 2 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfslide1down_vf_f32m1(vfloat32m1_t src, float value,
				size_t vl) {
				return vfslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i32(<vscale x 4 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vfslide1down_vf_f32m2(vfloat32m2_t src, float value,
				size_t vl) {
				return vfslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i32(<vscale x 8 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vfslide1down_vf_f32m4(vfloat32m4_t src, float value,
				size_t vl) {
				return vfslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vfslide1down.nxv16f32.f32.i32(<vscale x 16 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vfslide1down.nxv16f32.f32.i64(<vscale x 16 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vfslide1down_vf_f32m8(vfloat32m8_t src, float value,
				size_t vl) {
				return vfslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfslide1down.nxv1f64.f64.i32(<vscale x 1 x double> [[SRC:%.]], double [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfslide1down.nxv1f64.f64.i64(<vscale x 1 x double> [[SRC:%.]], double [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfslide1down_vf_f64m1(vfloat64m1_t src, double value,
				size_t vl) {
				return vfslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vfslide1down.nxv2f64.f64.i32(<vscale x 2 x double> [[SRC:%.]], double [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vfslide1down.nxv2f64.f64.i64(<vscale x 2 x double> [[SRC:%.]], double [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vfslide1down_vf_f64m2(vfloat64m2_t src, double value,
				size_t vl) {
				return vfslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vfslide1down.nxv4f64.f64.i32(<vscale x 4 x double> [[SRC:%.]], double [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vfslide1down.nxv4f64.f64.i64(<vscale x 4 x double> [[SRC:%.]], double [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vfslide1down_vf_f64m4(vfloat64m4_t src, double value,
				size_t vl) {
				return vfslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vfslide1down.nxv8f64.f64.i32(<vscale x 8 x double> [[SRC:%.]], double [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vfslide1down.nxv8f64.f64.i64(<vscale x 8 x double> [[SRC:%.]], double [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vfslide1down_vf_f64m8(vfloat64m8_t src, double value,
				size_t vl) {
				return vfslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1down.mask.nxv1f32.f32.i32(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1down.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vfslide1down_vf_f32mf2_m(vbool64_t mask,
				vfloat32mf2_t maskedoff,
				vfloat32mf2_t src, float value,
				size_t vl) {
				return vfslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfslide1down.mask.nxv2f32.f32.i32(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfslide1down.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfslide1down_vf_f32m1_m(vbool32_t mask,
				vfloat32m1_t maskedoff,
				vfloat32m1_t src, float value,
				size_t vl) {
				return vfslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vfslide1down.mask.nxv4f32.f32.i32(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vfslide1down.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vfslide1down_vf_f32m2_m(vbool16_t mask,
				vfloat32m2_t maskedoff,
				vfloat32m2_t src, float value,
				size_t vl) {
				return vfslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vfslide1down.mask.nxv8f32.f32.i32(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vfslide1down.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vfslide1down_vf_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff,
				vfloat32m4_t src, float value,
				size_t vl) {
				return vfslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vfslide1down.mask.nxv16f32.f32.i32(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vfslide1down.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vfslide1down_vf_f32m8_m(vbool4_t mask, vfloat32m8_t maskedoff,
				vfloat32m8_t src, float value,
				size_t vl) {
				return vfslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfslide1down.mask.nxv1f64.f64.i32(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfslide1down.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfslide1down_vf_f64m1_m(vbool64_t mask,
				vfloat64m1_t maskedoff,
				vfloat64m1_t src, double value,
				size_t vl) {
				return vfslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vfslide1down.mask.nxv2f64.f64.i32(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vfslide1down.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vfslide1down_vf_f64m2_m(vbool32_t mask,
				vfloat64m2_t maskedoff,
				vfloat64m2_t src, double value,
				size_t vl) {
				return vfslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vfslide1down.mask.nxv4f64.f64.i32(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vfslide1down.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vfslide1down_vf_f64m4_m(vbool16_t mask,
				vfloat64m4_t maskedoff,
				vfloat64m4_t src, double value,
				size_t vl) {
				return vfslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vfslide1down.mask.nxv8f64.f64.i32(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vfslide1down.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vfslide1down_vf_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
				vfloat64m8_t src, double value,
				size_t vl) {
				return vfslide1down(mask, maskedoff, src, value, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c

This file was added.

				// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
				// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 \| FileCheck --check-prefix=ASM --allow-empty %s

				// ASM-NOT: warning
				#include <riscv_vector.h>

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i32(<vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR6:#.*]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR6:#.*]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vfslide1up_vf_f32mf2(vfloat32mf2_t src, float value,
				size_t vl) {
				return vfslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i32(<vscale x 2 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfslide1up_vf_f32m1(vfloat32m1_t src, float value,
				size_t vl) {
				return vfslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i32(<vscale x 4 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vfslide1up_vf_f32m2(vfloat32m2_t src, float value,
				size_t vl) {
				return vfslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i32(<vscale x 8 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vfslide1up_vf_f32m4(vfloat32m4_t src, float value,
				size_t vl) {
				return vfslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vfslide1up.nxv16f32.f32.i32(<vscale x 16 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vfslide1up.nxv16f32.f32.i64(<vscale x 16 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vfslide1up_vf_f32m8(vfloat32m8_t src, float value,
				size_t vl) {
				return vfslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfslide1up.nxv1f64.f64.i32(<vscale x 1 x double> [[SRC:%.]], double [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfslide1up.nxv1f64.f64.i64(<vscale x 1 x double> [[SRC:%.]], double [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfslide1up_vf_f64m1(vfloat64m1_t src, double value,
				size_t vl) {
				return vfslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vfslide1up.nxv2f64.f64.i32(<vscale x 2 x double> [[SRC:%.]], double [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vfslide1up.nxv2f64.f64.i64(<vscale x 2 x double> [[SRC:%.]], double [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vfslide1up_vf_f64m2(vfloat64m2_t src, double value,
				size_t vl) {
				return vfslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vfslide1up.nxv4f64.f64.i32(<vscale x 4 x double> [[SRC:%.]], double [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vfslide1up.nxv4f64.f64.i64(<vscale x 4 x double> [[SRC:%.]], double [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vfslide1up_vf_f64m4(vfloat64m4_t src, double value,
				size_t vl) {
				return vfslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vfslide1up.nxv8f64.f64.i32(<vscale x 8 x double> [[SRC:%.]], double [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vfslide1up.nxv8f64.f64.i64(<vscale x 8 x double> [[SRC:%.]], double [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vfslide1up_vf_f64m8(vfloat64m8_t src, double value,
				size_t vl) {
				return vfslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1up.mask.nxv1f32.f32.i32(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1up.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vfslide1up_vf_f32mf2_m(vbool64_t mask,
				vfloat32mf2_t maskedoff,
				vfloat32mf2_t src, float value,
				size_t vl) {
				return vfslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfslide1up.mask.nxv2f32.f32.i32(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfslide1up.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfslide1up_vf_f32m1_m(vbool32_t mask, vfloat32m1_t maskedoff,
				vfloat32m1_t src, float value,
				size_t vl) {
				return vfslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vfslide1up.mask.nxv4f32.f32.i32(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vfslide1up.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vfslide1up_vf_f32m2_m(vbool16_t mask, vfloat32m2_t maskedoff,
				vfloat32m2_t src, float value,
				size_t vl) {
				return vfslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vfslide1up.mask.nxv8f32.f32.i32(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vfslide1up.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vfslide1up_vf_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff,
				vfloat32m4_t src, float value,
				size_t vl) {
				return vfslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vfslide1up.mask.nxv16f32.f32.i32(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vfslide1up.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vfslide1up_vf_f32m8_m(vbool4_t mask, vfloat32m8_t maskedoff,
				vfloat32m8_t src, float value,
				size_t vl) {
				return vfslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfslide1up.mask.nxv1f64.f64.i32(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfslide1up.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfslide1up_vf_f64m1_m(vbool64_t mask, vfloat64m1_t maskedoff,
				vfloat64m1_t src, double value,
				size_t vl) {
				return vfslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vfslide1up.mask.nxv2f64.f64.i32(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vfslide1up.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vfslide1up_vf_f64m2_m(vbool32_t mask, vfloat64m2_t maskedoff,
				vfloat64m2_t src, double value,
				size_t vl) {
				return vfslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vfslide1up.mask.nxv4f64.f64.i32(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vfslide1up.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vfslide1up_vf_f64m4_m(vbool16_t mask, vfloat64m4_t maskedoff,
				vfloat64m4_t src, double value,
				size_t vl) {
				return vfslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vfslide1up.mask.nxv8f64.f64.i32(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vfslide1up.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR6]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vfslide1up_vf_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
				vfloat64m8_t src, double value,
				size_t vl) {
				return vfslide1up(mask, maskedoff, src, value, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c

This file was added.

This file is larger than 256 KB, so syntax highlighting is disabled by default.

				// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
				// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 \| FileCheck --check-prefix=ASM --allow-empty %s

				// ASM-NOT: warning
				#include <riscv_vector.h>

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.nxv1i8.i32(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8:#.*]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8:#.*]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vrgather_vv_i8mf8(vint8mf8_t op1, vuint8mf8_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.nxv1i8.i32(<vscale x 1 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vrgather_vx_i8mf8(vint8mf8_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.nxv2i8.i32(<vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i8> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i8> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vrgather_vv_i8mf4(vint8mf4_t op1, vuint8mf4_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.nxv2i8.i32(<vscale x 2 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vrgather_vx_i8mf4(vint8mf4_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.nxv4i8.i32(<vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i8> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i8> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vrgather_vv_i8mf2(vint8mf2_t op1, vuint8mf2_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.nxv4i8.i32(<vscale x 4 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vrgather_vx_i8mf2(vint8mf2_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.nxv8i8.i32(<vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i8> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i8> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vrgather_vv_i8m1(vint8m1_t op1, vuint8m1_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.nxv8i8.i32(<vscale x 8 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vrgather_vx_i8m1(vint8m1_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.nxv16i8.i32(<vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i8> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i8> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vrgather_vv_i8m2(vint8m2_t op1, vuint8m2_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.nxv16i8.i32(<vscale x 16 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vrgather_vx_i8m2(vint8m2_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.nxv32i8.i32(<vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i8> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i8> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vrgather_vv_i8m4(vint8m4_t op1, vuint8m4_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.nxv32i8.i32(<vscale x 32 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vrgather_vx_i8m4(vint8m4_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.nxv64i8.i32(<vscale x 64 x i8> [[OP1:%.]], <vscale x 64 x i8> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.nxv64i8.i64(<vscale x 64 x i8> [[OP1:%.]], <vscale x 64 x i8> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vrgather_vv_i8m8(vint8m8_t op1, vuint8m8_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.nxv64i8.i32(<vscale x 64 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.nxv64i8.i64(<vscale x 64 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vrgather_vx_i8m8(vint8m8_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.nxv1i16.i32(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vrgather_vv_i16mf4(vint16mf4_t op1, vuint16mf4_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.nxv1i16.i32(<vscale x 1 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vrgather_vx_i16mf4(vint16mf4_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.nxv2i16.i32(<vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vrgather_vv_i16mf2(vint16mf2_t op1, vuint16mf2_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.nxv2i16.i32(<vscale x 2 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vrgather_vx_i16mf2(vint16mf2_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.nxv4i16.i32(<vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vrgather_vv_i16m1(vint16m1_t op1, vuint16m1_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.nxv4i16.i32(<vscale x 4 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vrgather_vx_i16m1(vint16m1_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.nxv8i16.i32(<vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vrgather_vv_i16m2(vint16m2_t op1, vuint16m2_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.nxv8i16.i32(<vscale x 8 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vrgather_vx_i16m2(vint16m2_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.nxv16i16.i32(<vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vrgather_vv_i16m4(vint16m4_t op1, vuint16m4_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.nxv16i16.i32(<vscale x 16 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vrgather_vx_i16m4(vint16m4_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.nxv32i16.i32(<vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.nxv32i16.i64(<vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vrgather_vv_i16m8(vint16m8_t op1, vuint16m8_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.nxv32i16.i32(<vscale x 32 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.nxv32i16.i64(<vscale x 32 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vrgather_vx_i16m8(vint16m8_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.nxv1i32.i32(<vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vrgather_vv_i32mf2(vint32mf2_t op1, vuint32mf2_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.nxv1i32.i32(<vscale x 1 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vrgather_vx_i32mf2(vint32mf2_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.nxv2i32.i32(<vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vrgather_vv_i32m1(vint32m1_t op1, vuint32m1_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.nxv2i32.i32(<vscale x 2 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vrgather_vx_i32m1(vint32m1_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.nxv4i32.i32(<vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vrgather_vv_i32m2(vint32m2_t op1, vuint32m2_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.i32(<vscale x 4 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vrgather_vx_i32m2(vint32m2_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.nxv8i32.i32(<vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vrgather_vv_i32m4(vint32m4_t op1, vuint32m4_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.nxv8i32.i32(<vscale x 8 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vrgather_vx_i32m4(vint32m4_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.nxv16i32.i32(<vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.nxv16i32.i64(<vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vrgather_vv_i32m8(vint32m8_t op1, vuint32m8_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.nxv16i32.i32(<vscale x 16 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.nxv16i32.i64(<vscale x 16 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vrgather_vx_i32m8(vint32m8_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.nxv1i64.i32(<vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.nxv1i64.i64(<vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vrgather_vv_i64m1(vint64m1_t op1, vuint64m1_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.nxv1i64.i32(<vscale x 1 x i64> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.nxv1i64.i64(<vscale x 1 x i64> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vrgather_vx_i64m1(vint64m1_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.nxv2i64.i32(<vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.nxv2i64.i64(<vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vrgather_vv_i64m2(vint64m2_t op1, vuint64m2_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.nxv2i64.i32(<vscale x 2 x i64> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.nxv2i64.i64(<vscale x 2 x i64> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vrgather_vx_i64m2(vint64m2_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.nxv4i64.i32(<vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.nxv4i64.i64(<vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vrgather_vv_i64m4(vint64m4_t op1, vuint64m4_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.nxv4i64.i32(<vscale x 4 x i64> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.nxv4i64.i64(<vscale x 4 x i64> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vrgather_vx_i64m4(vint64m4_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.nxv8i64.i32(<vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.nxv8i64.i64(<vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vrgather_vv_i64m8(vint64m8_t op1, vuint64m8_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.nxv8i64.i32(<vscale x 8 x i64> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.nxv8i64.i64(<vscale x 8 x i64> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vrgather_vx_i64m8(vint64m8_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.nxv1i8.i32(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vrgather_vv_u8mf8(vuint8mf8_t op1, vuint8mf8_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.nxv1i8.i32(<vscale x 1 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vrgather_vx_u8mf8(vuint8mf8_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.nxv2i8.i32(<vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i8> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i8> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vrgather_vv_u8mf4(vuint8mf4_t op1, vuint8mf4_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.nxv2i8.i32(<vscale x 2 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vrgather_vx_u8mf4(vuint8mf4_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.nxv4i8.i32(<vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i8> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i8> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vrgather_vv_u8mf2(vuint8mf2_t op1, vuint8mf2_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.nxv4i8.i32(<vscale x 4 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vrgather_vx_u8mf2(vuint8mf2_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.nxv8i8.i32(<vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i8> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i8> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vrgather_vv_u8m1(vuint8m1_t op1, vuint8m1_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.nxv8i8.i32(<vscale x 8 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vrgather_vx_u8m1(vuint8m1_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.nxv16i8.i32(<vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i8> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i8> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vrgather_vv_u8m2(vuint8m2_t op1, vuint8m2_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.nxv16i8.i32(<vscale x 16 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vrgather_vx_u8m2(vuint8m2_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.nxv32i8.i32(<vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i8> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i8> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vrgather_vv_u8m4(vuint8m4_t op1, vuint8m4_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.nxv32i8.i32(<vscale x 32 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vrgather_vx_u8m4(vuint8m4_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.nxv64i8.i32(<vscale x 64 x i8> [[OP1:%.]], <vscale x 64 x i8> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.nxv64i8.i64(<vscale x 64 x i8> [[OP1:%.]], <vscale x 64 x i8> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vrgather_vv_u8m8(vuint8m8_t op1, vuint8m8_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.nxv64i8.i32(<vscale x 64 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.nxv64i8.i64(<vscale x 64 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vrgather_vx_u8m8(vuint8m8_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.nxv1i16.i32(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vrgather_vv_u16mf4(vuint16mf4_t op1, vuint16mf4_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.nxv1i16.i32(<vscale x 1 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vrgather_vx_u16mf4(vuint16mf4_t op1, size_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.nxv2i16.i32(<vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vrgather_vv_u16mf2(vuint16mf2_t op1, vuint16mf2_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.nxv2i16.i32(<vscale x 2 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vrgather_vx_u16mf2(vuint16mf2_t op1, size_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.nxv4i16.i32(<vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vrgather_vv_u16m1(vuint16m1_t op1, vuint16m1_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.nxv4i16.i32(<vscale x 4 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vrgather_vx_u16m1(vuint16m1_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.nxv8i16.i32(<vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vrgather_vv_u16m2(vuint16m2_t op1, vuint16m2_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.nxv8i16.i32(<vscale x 8 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vrgather_vx_u16m2(vuint16m2_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.nxv16i16.i32(<vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vrgather_vv_u16m4(vuint16m4_t op1, vuint16m4_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.nxv16i16.i32(<vscale x 16 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vrgather_vx_u16m4(vuint16m4_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.nxv32i16.i32(<vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.nxv32i16.i64(<vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vrgather_vv_u16m8(vuint16m8_t op1, vuint16m8_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.nxv32i16.i32(<vscale x 32 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.nxv32i16.i64(<vscale x 32 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vrgather_vx_u16m8(vuint16m8_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.nxv1i32.i32(<vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vrgather_vv_u32mf2(vuint32mf2_t op1, vuint32mf2_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.nxv1i32.i32(<vscale x 1 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vrgather_vx_u32mf2(vuint32mf2_t op1, size_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.nxv2i32.i32(<vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vrgather_vv_u32m1(vuint32m1_t op1, vuint32m1_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.nxv2i32.i32(<vscale x 2 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vrgather_vx_u32m1(vuint32m1_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.nxv4i32.i32(<vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vrgather_vv_u32m2(vuint32m2_t op1, vuint32m2_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.i32(<vscale x 4 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vrgather_vx_u32m2(vuint32m2_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.nxv8i32.i32(<vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vrgather_vv_u32m4(vuint32m4_t op1, vuint32m4_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.nxv8i32.i32(<vscale x 8 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vrgather_vx_u32m4(vuint32m4_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.nxv16i32.i32(<vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.nxv16i32.i64(<vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vrgather_vv_u32m8(vuint32m8_t op1, vuint32m8_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.nxv16i32.i32(<vscale x 16 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.nxv16i32.i64(<vscale x 16 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vrgather_vx_u32m8(vuint32m8_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.nxv1i64.i32(<vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.nxv1i64.i64(<vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vrgather_vv_u64m1(vuint64m1_t op1, vuint64m1_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.nxv1i64.i32(<vscale x 1 x i64> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.nxv1i64.i64(<vscale x 1 x i64> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vrgather_vx_u64m1(vuint64m1_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.nxv2i64.i32(<vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.nxv2i64.i64(<vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vrgather_vv_u64m2(vuint64m2_t op1, vuint64m2_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.nxv2i64.i32(<vscale x 2 x i64> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.nxv2i64.i64(<vscale x 2 x i64> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vrgather_vx_u64m2(vuint64m2_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.nxv4i64.i32(<vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.nxv4i64.i64(<vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vrgather_vv_u64m4(vuint64m4_t op1, vuint64m4_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.nxv4i64.i32(<vscale x 4 x i64> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.nxv4i64.i64(<vscale x 4 x i64> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vrgather_vx_u64m4(vuint64m4_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.nxv8i64.i32(<vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.nxv8i64.i64(<vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vrgather_vv_u64m8(vuint64m8_t op1, vuint64m8_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.nxv8i64.i32(<vscale x 8 x i64> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.nxv8i64.i64(<vscale x 8 x i64> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vrgather_vx_u64m8(vuint64m8_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgather.vv.nxv1f32.i32(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgather.vv.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vrgather_vv_f32mf2(vfloat32mf2_t op1, vuint32mf2_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.nxv1f32.i32(<vscale x 1 x float> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vrgather_vx_f32mf2(vfloat32mf2_t op1, size_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgather.vv.nxv2f32.i32(<vscale x 2 x float> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgather.vv.nxv2f32.i64(<vscale x 2 x float> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vrgather_vv_f32m1(vfloat32m1_t op1, vuint32m1_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i32(<vscale x 2 x float> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i64(<vscale x 2 x float> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vrgather_vx_f32m1(vfloat32m1_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgather.vv.nxv4f32.i32(<vscale x 4 x float> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgather.vv.nxv4f32.i64(<vscale x 4 x float> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vrgather_vv_f32m2(vfloat32m2_t op1, vuint32m2_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.nxv4f32.i32(<vscale x 4 x float> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.nxv4f32.i64(<vscale x 4 x float> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vrgather_vx_f32m2(vfloat32m2_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgather.vv.nxv8f32.i32(<vscale x 8 x float> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgather.vv.nxv8f32.i64(<vscale x 8 x float> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vrgather_vv_f32m4(vfloat32m4_t op1, vuint32m4_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.nxv8f32.i32(<vscale x 8 x float> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.nxv8f32.i64(<vscale x 8 x float> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vrgather_vx_f32m4(vfloat32m4_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgather.vv.nxv16f32.i32(<vscale x 16 x float> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgather.vv.nxv16f32.i64(<vscale x 16 x float> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vrgather_vv_f32m8(vfloat32m8_t op1, vuint32m8_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgather.vx.nxv16f32.i32(<vscale x 16 x float> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgather.vx.nxv16f32.i64(<vscale x 16 x float> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vrgather_vx_f32m8(vfloat32m8_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgather.vv.nxv1f64.i32(<vscale x 1 x double> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgather.vv.nxv1f64.i64(<vscale x 1 x double> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vrgather_vv_f64m1(vfloat64m1_t op1, vuint64m1_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.nxv1f64.i32(<vscale x 1 x double> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.nxv1f64.i64(<vscale x 1 x double> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vrgather_vx_f64m1(vfloat64m1_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgather.vv.nxv2f64.i32(<vscale x 2 x double> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgather.vv.nxv2f64.i64(<vscale x 2 x double> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vrgather_vv_f64m2(vfloat64m2_t op1, vuint64m2_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.nxv2f64.i32(<vscale x 2 x double> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.nxv2f64.i64(<vscale x 2 x double> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vrgather_vx_f64m2(vfloat64m2_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgather.vv.nxv4f64.i32(<vscale x 4 x double> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgather.vv.nxv4f64.i64(<vscale x 4 x double> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vrgather_vv_f64m4(vfloat64m4_t op1, vuint64m4_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.nxv4f64.i32(<vscale x 4 x double> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.nxv4f64.i64(<vscale x 4 x double> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vrgather_vx_f64m4(vfloat64m4_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgather.vv.nxv8f64.i32(<vscale x 8 x double> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgather.vv.nxv8f64.i64(<vscale x 8 x double> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vrgather_vv_f64m8(vfloat64m8_t op1, vuint64m8_t index,
				size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgather.vx.nxv8f64.i32(<vscale x 8 x double> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgather.vx.nxv8f64.i64(<vscale x 8 x double> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vrgather_vx_f64m8(vfloat64m8_t op1, size_t index, size_t vl) {
				return vrgather(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.nxv1i8.i32(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vrgatherei16_vv_i8mf8(vint8mf8_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.nxv2i8.i32(<vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vrgatherei16_vv_i8mf4(vint8mf4_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.nxv4i8.i32(<vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vrgatherei16_vv_i8mf2(vint8mf2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i32(<vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vrgatherei16_vv_i8m1(vint8m1_t op1, vuint16m2_t op2, size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.nxv16i8.i32(<vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vrgatherei16_vv_i8m2(vint8m2_t op1, vuint16m4_t op2, size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.nxv32i8.i32(<vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vrgatherei16_vv_i8m4(vint8m4_t op1, vuint16m8_t op2, size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.nxv1i16.i32(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vrgatherei16_vv_i16mf4(vint16mf4_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.nxv2i16.i32(<vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vrgatherei16_vv_i16mf2(vint16mf2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.nxv4i16.i32(<vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vrgatherei16_vv_i16m1(vint16m1_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.nxv8i16.i32(<vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vrgatherei16_vv_i16m2(vint16m2_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.nxv16i16.i32(<vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vrgatherei16_vv_i16m4(vint16m4_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.nxv32i16.i32(<vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.nxv32i16.i64(<vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vrgatherei16_vv_i16m8(vint16m8_t op1, vuint16m8_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.nxv1i32.i32(<vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vrgatherei16_vv_i32mf2(vint32mf2_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgatherei16.vv.nxv2i32.i32(<vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgatherei16.vv.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vrgatherei16_vv_i32m1(vint32m1_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.nxv4i32.i32(<vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vrgatherei16_vv_i32m2(vint32m2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.nxv8i32.i32(<vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vrgatherei16_vv_i32m4(vint32m4_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.nxv16i32.i32(<vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.nxv16i32.i64(<vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vrgatherei16_vv_i32m8(vint32m8_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgatherei16.vv.nxv1i64.i32(<vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgatherei16.vv.nxv1i64.i64(<vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vrgatherei16_vv_i64m1(vint64m1_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgatherei16.vv.nxv2i64.i32(<vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgatherei16.vv.nxv2i64.i64(<vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vrgatherei16_vv_i64m2(vint64m2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.nxv4i64.i32(<vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.nxv4i64.i64(<vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vrgatherei16_vv_i64m4(vint64m4_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.nxv8i64.i32(<vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.nxv8i64.i64(<vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vrgatherei16_vv_i64m8(vint64m8_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.nxv1i8.i32(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vrgatherei16_vv_u8mf8(vuint8mf8_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.nxv2i8.i32(<vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vrgatherei16_vv_u8mf4(vuint8mf4_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.nxv4i8.i32(<vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vrgatherei16_vv_u8mf2(vuint8mf2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i32(<vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vrgatherei16_vv_u8m1(vuint8m1_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.nxv16i8.i32(<vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vrgatherei16_vv_u8m2(vuint8m2_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.nxv32i8.i32(<vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vrgatherei16_vv_u8m4(vuint8m4_t op1, vuint16m8_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.nxv1i16.i32(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vrgatherei16_vv_u16mf4(vuint16mf4_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.nxv2i16.i32(<vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vrgatherei16_vv_u16mf2(vuint16mf2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.nxv4i16.i32(<vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vrgatherei16_vv_u16m1(vuint16m1_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.nxv8i16.i32(<vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vrgatherei16_vv_u16m2(vuint16m2_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.nxv16i16.i32(<vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vrgatherei16_vv_u16m4(vuint16m4_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.nxv32i16.i32(<vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.nxv32i16.i64(<vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vrgatherei16_vv_u16m8(vuint16m8_t op1, vuint16m8_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.nxv1i32.i32(<vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vrgatherei16_vv_u32mf2(vuint32mf2_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgatherei16.vv.nxv2i32.i32(<vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgatherei16.vv.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vrgatherei16_vv_u32m1(vuint32m1_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.nxv4i32.i32(<vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vrgatherei16_vv_u32m2(vuint32m2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.nxv8i32.i32(<vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vrgatherei16_vv_u32m4(vuint32m4_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.nxv16i32.i32(<vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.nxv16i32.i64(<vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vrgatherei16_vv_u32m8(vuint32m8_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgatherei16.vv.nxv1i64.i32(<vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgatherei16.vv.nxv1i64.i64(<vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vrgatherei16_vv_u64m1(vuint64m1_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgatherei16.vv.nxv2i64.i32(<vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgatherei16.vv.nxv2i64.i64(<vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vrgatherei16_vv_u64m2(vuint64m2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.nxv4i64.i32(<vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.nxv4i64.i64(<vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vrgatherei16_vv_u64m4(vuint64m4_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.nxv8i64.i32(<vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.nxv8i64.i64(<vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vrgatherei16_vv_u64m8(vuint64m8_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i32(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vrgatherei16_vv_f32mf2(vfloat32mf2_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i32(<vscale x 2 x float> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vrgatherei16_vv_f32m1(vfloat32m1_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i32(<vscale x 4 x float> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vrgatherei16_vv_f32m2(vfloat32m2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.nxv8f32.i32(<vscale x 8 x float> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.nxv8f32.i64(<vscale x 8 x float> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vrgatherei16_vv_f32m4(vfloat32m4_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.nxv16f32.i32(<vscale x 16 x float> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.nxv16f32.i64(<vscale x 16 x float> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vrgatherei16_vv_f32m8(vfloat32m8_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgatherei16.vv.nxv1f64.i32(<vscale x 1 x double> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgatherei16.vv.nxv1f64.i64(<vscale x 1 x double> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vrgatherei16_vv_f64m1(vfloat64m1_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgatherei16.vv.nxv2f64.i32(<vscale x 2 x double> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgatherei16.vv.nxv2f64.i64(<vscale x 2 x double> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vrgatherei16_vv_f64m2(vfloat64m2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.nxv4f64.i32(<vscale x 4 x double> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.nxv4f64.i64(<vscale x 4 x double> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vrgatherei16_vv_f64m4(vfloat64m4_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.nxv8f64.i32(<vscale x 8 x double> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.nxv8f64.i64(<vscale x 8 x double> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vrgatherei16_vv_f64m8(vfloat64m8_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vrgather_vv_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff,
				vint8mf8_t op1, vuint8mf8_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vrgather_vx_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff,
				vint8mf8_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.mask.nxv2i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i8> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i8> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vrgather_vv_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff,
				vint8mf4_t op1, vuint8mf4_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.mask.nxv2i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vrgather_vx_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff,
				vint8mf4_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.mask.nxv4i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i8> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i8> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vrgather_vv_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff,
				vint8mf2_t op1, vuint8mf2_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.mask.nxv4i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vrgather_vx_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff,
				vint8mf2_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.mask.nxv8i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i8> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i8> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vrgather_vv_i8m1_m(vbool8_t mask, vint8m1_t maskedoff,
				vint8m1_t op1, vuint8m1_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.mask.nxv8i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vrgather_vx_i8m1_m(vbool8_t mask, vint8m1_t maskedoff,
				vint8m1_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.mask.nxv16i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i8> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i8> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vrgather_vv_i8m2_m(vbool4_t mask, vint8m2_t maskedoff,
				vint8m2_t op1, vuint8m2_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.mask.nxv16i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vrgather_vx_i8m2_m(vbool4_t mask, vint8m2_t maskedoff,
				vint8m2_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.mask.nxv32i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i8> [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i8> [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vrgather_vv_i8m4_m(vbool2_t mask, vint8m4_t maskedoff,
				vint8m4_t op1, vuint8m4_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.mask.nxv32i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vrgather_vx_i8m4_m(vbool2_t mask, vint8m4_t maskedoff,
				vint8m4_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.mask.nxv64i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[OP1:%.]], <vscale x 64 x i8> [[INDEX:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[OP1:%.]], <vscale x 64 x i8> [[INDEX:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vrgather_vv_i8m8_m(vbool1_t mask, vint8m8_t maskedoff,
				vint8m8_t op1, vuint8m8_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.mask.nxv64i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vrgather_vx_i8m8_m(vbool1_t mask, vint8m8_t maskedoff,
				vint8m8_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.mask.nxv1i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vrgather_vv_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff,
				vint16mf4_t op1, vuint16mf4_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.mask.nxv1i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vrgather_vx_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff,
				vint16mf4_t op1, size_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.mask.nxv2i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vrgather_vv_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff,
				vint16mf2_t op1, vuint16mf2_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.mask.nxv2i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vrgather_vx_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff,
				vint16mf2_t op1, size_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.mask.nxv4i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vrgather_vv_i16m1_m(vbool16_t mask, vint16m1_t maskedoff,
				vint16m1_t op1, vuint16m1_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.mask.nxv4i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vrgather_vx_i16m1_m(vbool16_t mask, vint16m1_t maskedoff,
				vint16m1_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.mask.nxv8i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vrgather_vv_i16m2_m(vbool8_t mask, vint16m2_t maskedoff,
				vint16m2_t op1, vuint16m2_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.mask.nxv8i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vrgather_vx_i16m2_m(vbool8_t mask, vint16m2_t maskedoff,
				vint16m2_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.mask.nxv16i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vrgather_vv_i16m4_m(vbool4_t mask, vint16m4_t maskedoff,
				vint16m4_t op1, vuint16m4_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.mask.nxv16i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vrgather_vx_i16m4_m(vbool4_t mask, vint16m4_t maskedoff,
				vint16m4_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.mask.nxv32i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vrgather_vv_i16m8_m(vbool2_t mask, vint16m8_t maskedoff,
				vint16m8_t op1, vuint16m8_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.mask.nxv32i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vrgather_vx_i16m8_m(vbool2_t mask, vint16m8_t maskedoff,
				vint16m8_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.mask.nxv1i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vrgather_vv_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff,
				vint32mf2_t op1, vuint32mf2_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.mask.nxv1i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vrgather_vx_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff,
				vint32mf2_t op1, size_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.mask.nxv2i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vrgather_vv_i32m1_m(vbool32_t mask, vint32m1_t maskedoff,
				vint32m1_t op1, vuint32m1_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.mask.nxv2i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vrgather_vx_i32m1_m(vbool32_t mask, vint32m1_t maskedoff,
				vint32m1_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.mask.nxv4i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vrgather_vv_i32m2_m(vbool16_t mask, vint32m2_t maskedoff,
				vint32m2_t op1, vuint32m2_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.mask.nxv4i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vrgather_vx_i32m2_m(vbool16_t mask, vint32m2_t maskedoff,
				vint32m2_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.mask.nxv8i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vrgather_vv_i32m4_m(vbool8_t mask, vint32m4_t maskedoff,
				vint32m4_t op1, vuint32m4_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.mask.nxv8i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vrgather_vx_i32m4_m(vbool8_t mask, vint32m4_t maskedoff,
				vint32m4_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.mask.nxv16i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vrgather_vv_i32m8_m(vbool4_t mask, vint32m8_t maskedoff,
				vint32m8_t op1, vuint32m8_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.mask.nxv16i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vrgather_vx_i32m8_m(vbool4_t mask, vint32m8_t maskedoff,
				vint32m8_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.mask.nxv1i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vrgather_vv_i64m1_m(vbool64_t mask, vint64m1_t maskedoff,
				vint64m1_t op1, vuint64m1_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.mask.nxv1i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vrgather_vx_i64m1_m(vbool64_t mask, vint64m1_t maskedoff,
				vint64m1_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.mask.nxv2i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vrgather_vv_i64m2_m(vbool32_t mask, vint64m2_t maskedoff,
				vint64m2_t op1, vuint64m2_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.mask.nxv2i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vrgather_vx_i64m2_m(vbool32_t mask, vint64m2_t maskedoff,
				vint64m2_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.mask.nxv4i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vrgather_vv_i64m4_m(vbool16_t mask, vint64m4_t maskedoff,
				vint64m4_t op1, vuint64m4_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.mask.nxv4i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vrgather_vx_i64m4_m(vbool16_t mask, vint64m4_t maskedoff,
				vint64m4_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.mask.nxv8i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vrgather_vv_i64m8_m(vbool8_t mask, vint64m8_t maskedoff,
				vint64m8_t op1, vuint64m8_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.mask.nxv8i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vrgather_vx_i64m8_m(vbool8_t mask, vint64m8_t maskedoff,
				vint64m8_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vrgather_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff,
				vuint8mf8_t op1, vuint8mf8_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vrgather_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff,
				vuint8mf8_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.mask.nxv2i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i8> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i8> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vrgather_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff,
				vuint8mf4_t op1, vuint8mf4_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.mask.nxv2i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vrgather_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff,
				vuint8mf4_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.mask.nxv4i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i8> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i8> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vrgather_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff,
				vuint8mf2_t op1, vuint8mf2_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.mask.nxv4i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vrgather_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff,
				vuint8mf2_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.mask.nxv8i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i8> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i8> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vrgather_vv_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff,
				vuint8m1_t op1, vuint8m1_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.mask.nxv8i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vrgather_vx_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff,
				vuint8m1_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.mask.nxv16i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i8> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i8> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vrgather_vv_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff,
				vuint8m2_t op1, vuint8m2_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.mask.nxv16i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vrgather_vx_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff,
				vuint8m2_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.mask.nxv32i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i8> [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i8> [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vrgather_vv_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff,
				vuint8m4_t op1, vuint8m4_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.mask.nxv32i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vrgather_vx_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff,
				vuint8m4_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.mask.nxv64i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[OP1:%.]], <vscale x 64 x i8> [[INDEX:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[OP1:%.]], <vscale x 64 x i8> [[INDEX:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vrgather_vv_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff,
				vuint8m8_t op1, vuint8m8_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.mask.nxv64i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vrgather_vx_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff,
				vuint8m8_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.mask.nxv1i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vrgather_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff,
				vuint16mf4_t op1, vuint16mf4_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.mask.nxv1i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vrgather_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff,
				vuint16mf4_t op1, size_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.mask.nxv2i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vrgather_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff,
				vuint16mf2_t op1, vuint16mf2_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.mask.nxv2i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vrgather_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff,
				vuint16mf2_t op1, size_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.mask.nxv4i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vrgather_vv_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff,
				vuint16m1_t op1, vuint16m1_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.mask.nxv4i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vrgather_vx_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff,
				vuint16m1_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.mask.nxv8i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vrgather_vv_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff,
				vuint16m2_t op1, vuint16m2_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.mask.nxv8i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vrgather_vx_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff,
				vuint16m2_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.mask.nxv16i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vrgather_vv_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff,
				vuint16m4_t op1, vuint16m4_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.mask.nxv16i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vrgather_vx_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff,
				vuint16m4_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.mask.nxv32i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vrgather_vv_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff,
				vuint16m8_t op1, vuint16m8_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.mask.nxv32i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vrgather_vx_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff,
				vuint16m8_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.mask.nxv1i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vrgather_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff,
				vuint32mf2_t op1, vuint32mf2_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.mask.nxv1i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vrgather_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff,
				vuint32mf2_t op1, size_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.mask.nxv2i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vrgather_vv_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff,
				vuint32m1_t op1, vuint32m1_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.mask.nxv2i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vrgather_vx_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff,
				vuint32m1_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.mask.nxv4i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vrgather_vv_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff,
				vuint32m2_t op1, vuint32m2_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.mask.nxv4i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vrgather_vx_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff,
				vuint32m2_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.mask.nxv8i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vrgather_vv_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff,
				vuint32m4_t op1, vuint32m4_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.mask.nxv8i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vrgather_vx_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff,
				vuint32m4_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.mask.nxv16i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vrgather_vv_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff,
				vuint32m8_t op1, vuint32m8_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.mask.nxv16i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vrgather_vx_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff,
				vuint32m8_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.mask.nxv1i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vrgather_vv_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff,
				vuint64m1_t op1, vuint64m1_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.mask.nxv1i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vrgather_vx_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff,
				vuint64m1_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.mask.nxv2i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vrgather_vv_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff,
				vuint64m2_t op1, vuint64m2_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.mask.nxv2i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vrgather_vx_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff,
				vuint64m2_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.mask.nxv4i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vrgather_vv_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff,
				vuint64m4_t op1, vuint64m4_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.mask.nxv4i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vrgather_vx_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff,
				vuint64m4_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.mask.nxv8i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vrgather_vv_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff,
				vuint64m8_t op1, vuint64m8_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.mask.nxv8i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vrgather_vx_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff,
				vuint64m8_t op1, size_t index, size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgather.vv.mask.nxv1f32.i32(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgather.vv.mask.nxv1f32.i64(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vrgather_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t maskedoff,
				vfloat32mf2_t op1, vuint32mf2_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.mask.nxv1f32.i32(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.mask.nxv1f32.i64(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vrgather_vx_f32mf2_m(vbool64_t mask, vfloat32mf2_t maskedoff,
				vfloat32mf2_t op1, size_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgather.vv.mask.nxv2f32.i32(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgather.vv.mask.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vrgather_vv_f32m1_m(vbool32_t mask, vfloat32m1_t maskedoff,
				vfloat32m1_t op1, vuint32m1_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.mask.nxv2f32.i32(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.mask.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vrgather_vx_f32m1_m(vbool32_t mask, vfloat32m1_t maskedoff,
				vfloat32m1_t op1, size_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgather.vv.mask.nxv4f32.i32(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgather.vv.mask.nxv4f32.i64(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vrgather_vv_f32m2_m(vbool16_t mask, vfloat32m2_t maskedoff,
				vfloat32m2_t op1, vuint32m2_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.mask.nxv4f32.i32(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.mask.nxv4f32.i64(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vrgather_vx_f32m2_m(vbool16_t mask, vfloat32m2_t maskedoff,
				vfloat32m2_t op1, size_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgather.vv.mask.nxv8f32.i32(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgather.vv.mask.nxv8f32.i64(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vrgather_vv_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff,
				vfloat32m4_t op1, vuint32m4_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.mask.nxv8f32.i32(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.mask.nxv8f32.i64(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vrgather_vx_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff,
				vfloat32m4_t op1, size_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgather.vv.mask.nxv16f32.i32(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgather.vv.mask.nxv16f32.i64(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vrgather_vv_f32m8_m(vbool4_t mask, vfloat32m8_t maskedoff,
				vfloat32m8_t op1, vuint32m8_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgather.vx.mask.nxv16f32.i32(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgather.vx.mask.nxv16f32.i64(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vrgather_vx_f32m8_m(vbool4_t mask, vfloat32m8_t maskedoff,
				vfloat32m8_t op1, size_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgather.vv.mask.nxv1f64.i32(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgather.vv.mask.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vrgather_vv_f64m1_m(vbool64_t mask, vfloat64m1_t maskedoff,
				vfloat64m1_t op1, vuint64m1_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.mask.nxv1f64.i32(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.mask.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vrgather_vx_f64m1_m(vbool64_t mask, vfloat64m1_t maskedoff,
				vfloat64m1_t op1, size_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgather.vv.mask.nxv2f64.i32(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgather.vv.mask.nxv2f64.i64(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vrgather_vv_f64m2_m(vbool32_t mask, vfloat64m2_t maskedoff,
				vfloat64m2_t op1, vuint64m2_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.mask.nxv2f64.i32(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.mask.nxv2f64.i64(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vrgather_vx_f64m2_m(vbool32_t mask, vfloat64m2_t maskedoff,
				vfloat64m2_t op1, size_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgather.vv.mask.nxv4f64.i32(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgather.vv.mask.nxv4f64.i64(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vrgather_vv_f64m4_m(vbool16_t mask, vfloat64m4_t maskedoff,
				vfloat64m4_t op1, vuint64m4_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.mask.nxv4f64.i32(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.mask.nxv4f64.i64(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vrgather_vx_f64m4_m(vbool16_t mask, vfloat64m4_t maskedoff,
				vfloat64m4_t op1, size_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgather.vv.mask.nxv8f64.i32(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgather.vv.mask.nxv8f64.i64(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vrgather_vv_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
				vfloat64m8_t op1, vuint64m8_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgather.vx.mask.nxv8f64.i32(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgather.vx.mask.nxv8f64.i64(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vrgather_vx_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
				vfloat64m8_t op1, size_t index,
				size_t vl) {
				return vrgather(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vrgatherei16_vv_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff,
				vint8mf8_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv2i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vrgatherei16_vv_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff,
				vint8mf4_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv4i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vrgatherei16_vv_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff,
				vint8mf2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv8i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vrgatherei16_vv_i8m1_m(vbool8_t mask, vint8m1_t maskedoff,
				vint8m1_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv16i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vrgatherei16_vv_i8m2_m(vbool4_t mask, vint8m2_t maskedoff,
				vint8m2_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv32i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vrgatherei16_vv_i8m4_m(vbool2_t mask, vint8m4_t maskedoff,
				vint8m4_t op1, vuint16m8_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv1i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vrgatherei16_vv_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff,
				vint16mf4_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv2i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vrgatherei16_vv_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff,
				vint16mf2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv4i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vrgatherei16_vv_i16m1_m(vbool16_t mask, vint16m1_t maskedoff,
				vint16m1_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv8i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vrgatherei16_vv_i16m2_m(vbool8_t mask, vint16m2_t maskedoff,
				vint16m2_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv16i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vrgatherei16_vv_i16m4_m(vbool4_t mask, vint16m4_t maskedoff,
				vint16m4_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv32i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vrgatherei16_vv_i16m8_m(vbool2_t mask, vint16m8_t maskedoff,
				vint16m8_t op1, vuint16m8_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv1i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vrgatherei16_vv_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff,
				vint32mf2_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv2i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vrgatherei16_vv_i32m1_m(vbool32_t mask, vint32m1_t maskedoff,
				vint32m1_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv4i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vrgatherei16_vv_i32m2_m(vbool16_t mask, vint32m2_t maskedoff,
				vint32m2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv8i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vrgatherei16_vv_i32m4_m(vbool8_t mask, vint32m4_t maskedoff,
				vint32m4_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv16i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vrgatherei16_vv_i32m8_m(vbool4_t mask, vint32m8_t maskedoff,
				vint32m8_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv1i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vrgatherei16_vv_i64m1_m(vbool64_t mask, vint64m1_t maskedoff,
				vint64m1_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv2i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vrgatherei16_vv_i64m2_m(vbool32_t mask, vint64m2_t maskedoff,
				vint64m2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv4i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vrgatherei16_vv_i64m4_m(vbool16_t mask, vint64m4_t maskedoff,
				vint64m4_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv8i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vrgatherei16_vv_i64m8_m(vbool8_t mask, vint64m8_t maskedoff,
				vint64m8_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vrgatherei16_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff,
				vuint8mf8_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv2i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vrgatherei16_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff,
				vuint8mf4_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv4i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vrgatherei16_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff,
				vuint8mf2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv8i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vrgatherei16_vv_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff,
				vuint8m1_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv16i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vrgatherei16_vv_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff,
				vuint8m2_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv32i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vrgatherei16_vv_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff,
				vuint8m4_t op1, vuint16m8_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv1i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vrgatherei16_vv_u16mf4_m(vbool64_t mask,
				vuint16mf4_t maskedoff,
				vuint16mf4_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv2i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vrgatherei16_vv_u16mf2_m(vbool32_t mask,
				vuint16mf2_t maskedoff,
				vuint16mf2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv4i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vrgatherei16_vv_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff,
				vuint16m1_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv8i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vrgatherei16_vv_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff,
				vuint16m2_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv16i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vrgatherei16_vv_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff,
				vuint16m4_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv32i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vrgatherei16_vv_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff,
				vuint16m8_t op1, vuint16m8_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv1i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vrgatherei16_vv_u32mf2_m(vbool64_t mask,
				vuint32mf2_t maskedoff,
				vuint32mf2_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv2i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vrgatherei16_vv_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff,
				vuint32m1_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv4i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vrgatherei16_vv_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff,
				vuint32m2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv8i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vrgatherei16_vv_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff,
				vuint32m4_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv16i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vrgatherei16_vv_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff,
				vuint32m8_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv1i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vrgatherei16_vv_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff,
				vuint64m1_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv2i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vrgatherei16_vv_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff,
				vuint64m2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv4i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vrgatherei16_vv_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff,
				vuint64m4_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv8i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vrgatherei16_vv_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff,
				vuint64m8_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv1f32.i32(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv1f32.i64(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vrgatherei16_vv_f32mf2_m(vbool64_t mask,
				vfloat32mf2_t maskedoff,
				vfloat32mf2_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv2f32.i32(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vrgatherei16_vv_f32m1_m(vbool32_t mask,
				vfloat32m1_t maskedoff,
				vfloat32m1_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv4f32.i32(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv4f32.i64(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vrgatherei16_vv_f32m2_m(vbool16_t mask,
				vfloat32m2_t maskedoff,
				vfloat32m2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv8f32.i32(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv8f32.i64(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vrgatherei16_vv_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff,
				vfloat32m4_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv16f32.i32(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv16f32.i64(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vrgatherei16_vv_f32m8_m(vbool4_t mask, vfloat32m8_t maskedoff,
				vfloat32m8_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv1f64.i32(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vrgatherei16_vv_f64m1_m(vbool64_t mask,
				vfloat64m1_t maskedoff,
				vfloat64m1_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv2f64.i32(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv2f64.i64(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vrgatherei16_vv_f64m2_m(vbool32_t mask,
				vfloat64m2_t maskedoff,
				vfloat64m2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv4f64.i32(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv4f64.i64(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vrgatherei16_vv_f64m4_m(vbool16_t mask,
				vfloat64m4_t maskedoff,
				vfloat64m4_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv8f64.i32(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv8f64.i64(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vrgatherei16_vv_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
				vfloat64m8_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16(mask, maskedoff, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c

This file was added.

				// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
				// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 \| FileCheck --check-prefix=ASM --allow-empty %s

				// ASM-NOT: warning
				#include <riscv_vector.h>

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i32(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8:#.*]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8:#.*]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vslide1down_vx_i8mf8(vint8mf8_t src, int8_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i32(<vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vslide1down_vx_i8mf4(vint8mf4_t src, int8_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i32(<vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vslide1down_vx_i8mf2(vint8mf2_t src, int8_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i32(<vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vslide1down_vx_i8m1(vint8m1_t src, int8_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i32(<vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vslide1down_vx_i8m2(vint8m2_t src, int8_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i32(<vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vslide1down_vx_i8m4(vint8m4_t src, int8_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i32(<vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vslide1down_vx_i8m8(vint8m8_t src, int8_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i32(<vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vslide1down_vx_i16mf4(vint16mf4_t src, int16_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i32(<vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vslide1down_vx_i16mf2(vint16mf2_t src, int16_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i32(<vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vslide1down_vx_i16m1(vint16m1_t src, int16_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1down.nxv8i16.i16.i32(<vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1down.nxv8i16.i16.i64(<vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vslide1down_vx_i16m2(vint16m2_t src, int16_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1down.nxv16i16.i16.i32(<vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1down.nxv16i16.i16.i64(<vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vslide1down_vx_i16m4(vint16m4_t src, int16_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1down.nxv32i16.i16.i32(<vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1down.nxv32i16.i16.i64(<vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vslide1down_vx_i16m8(vint16m8_t src, int16_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1down.nxv1i32.i32.i32(<vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1down.nxv1i32.i32.i64(<vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vslide1down_vx_i32mf2(vint32mf2_t src, int32_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1down.nxv2i32.i32.i32(<vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1down.nxv2i32.i32.i64(<vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vslide1down_vx_i32m1(vint32m1_t src, int32_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32.i32(<vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32.i64(<vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vslide1down_vx_i32m2(vint32m2_t src, int32_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1down.nxv8i32.i32.i32(<vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1down.nxv8i32.i32.i64(<vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vslide1down_vx_i32m4(vint32m4_t src, int32_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1down.nxv16i32.i32.i32(<vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1down.nxv16i32.i32.i64(<vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vslide1down_vx_i32m8(vint32m8_t src, int32_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64.i32(<vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64.i64(<vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vslide1down_vx_i64m1(vint64m1_t src, int64_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1down.nxv2i64.i64.i32(<vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1down.nxv2i64.i64.i64(<vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vslide1down_vx_i64m2(vint64m2_t src, int64_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1down.nxv4i64.i64.i32(<vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1down.nxv4i64.i64.i64(<vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vslide1down_vx_i64m4(vint64m4_t src, int64_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1down.nxv8i64.i64.i32(<vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1down.nxv8i64.i64.i64(<vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vslide1down_vx_i64m8(vint64m8_t src, int64_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i32(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vslide1down_vx_u8mf8(vuint8mf8_t src, uint8_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i32(<vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vslide1down_vx_u8mf4(vuint8mf4_t src, uint8_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i32(<vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vslide1down_vx_u8mf2(vuint8mf2_t src, uint8_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i32(<vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vslide1down_vx_u8m1(vuint8m1_t src, uint8_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i32(<vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vslide1down_vx_u8m2(vuint8m2_t src, uint8_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i32(<vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vslide1down_vx_u8m4(vuint8m4_t src, uint8_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i32(<vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vslide1down_vx_u8m8(vuint8m8_t src, uint8_t value, size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i32(<vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vslide1down_vx_u16mf4(vuint16mf4_t src, uint16_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i32(<vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vslide1down_vx_u16mf2(vuint16mf2_t src, uint16_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i32(<vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vslide1down_vx_u16m1(vuint16m1_t src, uint16_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1down.nxv8i16.i16.i32(<vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1down.nxv8i16.i16.i64(<vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vslide1down_vx_u16m2(vuint16m2_t src, uint16_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1down.nxv16i16.i16.i32(<vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1down.nxv16i16.i16.i64(<vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vslide1down_vx_u16m4(vuint16m4_t src, uint16_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1down.nxv32i16.i16.i32(<vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1down.nxv32i16.i16.i64(<vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vslide1down_vx_u16m8(vuint16m8_t src, uint16_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1down.nxv1i32.i32.i32(<vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1down.nxv1i32.i32.i64(<vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vslide1down_vx_u32mf2(vuint32mf2_t src, uint32_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1down.nxv2i32.i32.i32(<vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1down.nxv2i32.i32.i64(<vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vslide1down_vx_u32m1(vuint32m1_t src, uint32_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32.i32(<vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32.i64(<vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vslide1down_vx_u32m2(vuint32m2_t src, uint32_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1down.nxv8i32.i32.i32(<vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1down.nxv8i32.i32.i64(<vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vslide1down_vx_u32m4(vuint32m4_t src, uint32_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1down.nxv16i32.i32.i32(<vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1down.nxv16i32.i32.i64(<vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vslide1down_vx_u32m8(vuint32m8_t src, uint32_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64.i32(<vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64.i64(<vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vslide1down_vx_u64m1(vuint64m1_t src, uint64_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1down.nxv2i64.i64.i32(<vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1down.nxv2i64.i64.i64(<vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vslide1down_vx_u64m2(vuint64m2_t src, uint64_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1down.nxv4i64.i64.i32(<vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1down.nxv4i64.i64.i64(<vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vslide1down_vx_u64m4(vuint64m4_t src, uint64_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1down.nxv8i64.i64.i32(<vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1down.nxv8i64.i64.i64(<vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vslide1down_vx_u64m8(vuint64m8_t src, uint64_t value,
				size_t vl) {
				return vslide1down(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.mask.nxv1i8.i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vslide1down_vx_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff,
				vint8mf8_t src, int8_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1down.mask.nxv2i8.i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1down.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vslide1down_vx_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff,
				vint8mf4_t src, int8_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1down.mask.nxv4i8.i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1down.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vslide1down_vx_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff,
				vint8mf2_t src, int8_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1down.mask.nxv8i8.i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1down.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vslide1down_vx_i8m1_m(vbool8_t mask, vint8m1_t maskedoff,
				vint8m1_t src, int8_t value, size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1down.mask.nxv16i8.i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1down.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vslide1down_vx_i8m2_m(vbool4_t mask, vint8m2_t maskedoff,
				vint8m2_t src, int8_t value, size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1down.mask.nxv32i8.i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1down.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vslide1down_vx_i8m4_m(vbool2_t mask, vint8m4_t maskedoff,
				vint8m4_t src, int8_t value, size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1down.mask.nxv64i8.i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1down.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vslide1down_vx_i8m8_m(vbool1_t mask, vint8m8_t maskedoff,
				vint8m8_t src, int8_t value, size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1down.mask.nxv1i16.i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1down.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vslide1down_vx_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff,
				vint16mf4_t src, int16_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1down.mask.nxv2i16.i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1down.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vslide1down_vx_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff,
				vint16mf2_t src, int16_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1down.mask.nxv4i16.i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1down.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vslide1down_vx_i16m1_m(vbool16_t mask, vint16m1_t maskedoff,
				vint16m1_t src, int16_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1down.mask.nxv8i16.i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1down.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vslide1down_vx_i16m2_m(vbool8_t mask, vint16m2_t maskedoff,
				vint16m2_t src, int16_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1down.mask.nxv16i16.i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1down.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vslide1down_vx_i16m4_m(vbool4_t mask, vint16m4_t maskedoff,
				vint16m4_t src, int16_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1down.mask.nxv32i16.i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1down.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vslide1down_vx_i16m8_m(vbool2_t mask, vint16m8_t maskedoff,
				vint16m8_t src, int16_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1down.mask.nxv1i32.i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1down.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vslide1down_vx_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff,
				vint32mf2_t src, int32_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1down.mask.nxv2i32.i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1down.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vslide1down_vx_i32m1_m(vbool32_t mask, vint32m1_t maskedoff,
				vint32m1_t src, int32_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1down.mask.nxv4i32.i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1down.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vslide1down_vx_i32m2_m(vbool16_t mask, vint32m2_t maskedoff,
				vint32m2_t src, int32_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1down.mask.nxv8i32.i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1down.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vslide1down_vx_i32m4_m(vbool8_t mask, vint32m4_t maskedoff,
				vint32m4_t src, int32_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1down.mask.nxv16i32.i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1down.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vslide1down_vx_i32m8_m(vbool4_t mask, vint32m8_t maskedoff,
				vint32m8_t src, int32_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t maskedoff,
				vint64m1_t src, int64_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1down.mask.nxv2i64.i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1down.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t maskedoff,
				vint64m2_t src, int64_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1down.mask.nxv4i64.i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1down.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t maskedoff,
				vint64m4_t src, int64_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1down.mask.nxv8i64.i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1down.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t maskedoff,
				vint64m8_t src, int64_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.mask.nxv1i8.i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vslide1down_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff,
				vuint8mf8_t src, uint8_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1down.mask.nxv2i8.i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1down.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vslide1down_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff,
				vuint8mf4_t src, uint8_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1down.mask.nxv4i8.i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1down.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vslide1down_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff,
				vuint8mf2_t src, uint8_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1down.mask.nxv8i8.i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1down.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vslide1down_vx_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff,
				vuint8m1_t src, uint8_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1down.mask.nxv16i8.i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1down.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vslide1down_vx_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff,
				vuint8m2_t src, uint8_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1down.mask.nxv32i8.i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1down.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vslide1down_vx_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff,
				vuint8m4_t src, uint8_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1down.mask.nxv64i8.i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1down.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vslide1down_vx_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff,
				vuint8m8_t src, uint8_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1down.mask.nxv1i16.i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1down.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vslide1down_vx_u16mf4_m(vbool64_t mask,
				vuint16mf4_t maskedoff,
				vuint16mf4_t src, uint16_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1down.mask.nxv2i16.i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1down.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vslide1down_vx_u16mf2_m(vbool32_t mask,
				vuint16mf2_t maskedoff,
				vuint16mf2_t src, uint16_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1down.mask.nxv4i16.i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1down.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vslide1down_vx_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff,
				vuint16m1_t src, uint16_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1down.mask.nxv8i16.i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1down.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vslide1down_vx_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff,
				vuint16m2_t src, uint16_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1down.mask.nxv16i16.i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1down.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vslide1down_vx_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff,
				vuint16m4_t src, uint16_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1down.mask.nxv32i16.i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1down.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vslide1down_vx_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff,
				vuint16m8_t src, uint16_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1down.mask.nxv1i32.i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1down.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vslide1down_vx_u32mf2_m(vbool64_t mask,
				vuint32mf2_t maskedoff,
				vuint32mf2_t src, uint32_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1down.mask.nxv2i32.i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1down.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vslide1down_vx_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff,
				vuint32m1_t src, uint32_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1down.mask.nxv4i32.i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1down.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vslide1down_vx_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff,
				vuint32m2_t src, uint32_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1down.mask.nxv8i32.i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1down.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vslide1down_vx_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff,
				vuint32m4_t src, uint32_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1down.mask.nxv16i32.i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1down.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vslide1down_vx_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff,
				vuint32m8_t src, uint32_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vslide1down_vx_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff,
				vuint64m1_t src, uint64_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1down.mask.nxv2i64.i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1down.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vslide1down_vx_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff,
				vuint64m2_t src, uint64_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1down.mask.nxv4i64.i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1down.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vslide1down_vx_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff,
				vuint64m4_t src, uint64_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1down.mask.nxv8i64.i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1down.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vslide1down_vx_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff,
				vuint64m8_t src, uint64_t value,
				size_t vl) {
				return vslide1down(mask, maskedoff, src, value, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c

This file was added.

				// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
				// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 \| FileCheck --check-prefix=ASM --allow-empty %s

				// ASM-NOT: warning
				#include <riscv_vector.h>

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i32(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8:#.*]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8:#.*]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vslide1up_vx_i8mf8(vint8mf8_t src, int8_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i32(<vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vslide1up_vx_i8mf4(vint8mf4_t src, int8_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i32(<vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vslide1up_vx_i8mf2(vint8mf2_t src, int8_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i32(<vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vslide1up_vx_i8m1(vint8m1_t src, int8_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i32(<vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vslide1up_vx_i8m2(vint8m2_t src, int8_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i32(<vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vslide1up_vx_i8m4(vint8m4_t src, int8_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i32(<vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vslide1up_vx_i8m8(vint8m8_t src, int8_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i32(<vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vslide1up_vx_i16mf4(vint16mf4_t src, int16_t value,
				size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i32(<vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vslide1up_vx_i16mf2(vint16mf2_t src, int16_t value,
				size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i32(<vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vslide1up_vx_i16m1(vint16m1_t src, int16_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1up.nxv8i16.i16.i32(<vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1up.nxv8i16.i16.i64(<vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vslide1up_vx_i16m2(vint16m2_t src, int16_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1up.nxv16i16.i16.i32(<vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1up.nxv16i16.i16.i64(<vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vslide1up_vx_i16m4(vint16m4_t src, int16_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1up.nxv32i16.i16.i32(<vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1up.nxv32i16.i16.i64(<vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vslide1up_vx_i16m8(vint16m8_t src, int16_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1up.nxv1i32.i32.i32(<vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1up.nxv1i32.i32.i64(<vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vslide1up_vx_i32mf2(vint32mf2_t src, int32_t value,
				size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1up.nxv2i32.i32.i32(<vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1up.nxv2i32.i32.i64(<vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vslide1up_vx_i32m1(vint32m1_t src, int32_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1up.nxv4i32.i32.i32(<vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1up.nxv4i32.i32.i64(<vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vslide1up_vx_i32m2(vint32m2_t src, int32_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1up.nxv8i32.i32.i32(<vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1up.nxv8i32.i32.i64(<vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vslide1up_vx_i32m4(vint32m4_t src, int32_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1up.nxv16i32.i32.i32(<vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1up.nxv16i32.i32.i64(<vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vslide1up_vx_i32m8(vint32m8_t src, int32_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64.i32(<vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64.i64(<vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vslide1up_vx_i64m1(vint64m1_t src, int64_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1up.nxv2i64.i64.i32(<vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1up.nxv2i64.i64.i64(<vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vslide1up_vx_i64m2(vint64m2_t src, int64_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1up.nxv4i64.i64.i32(<vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1up.nxv4i64.i64.i64(<vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vslide1up_vx_i64m4(vint64m4_t src, int64_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1up.nxv8i64.i64.i32(<vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1up.nxv8i64.i64.i64(<vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vslide1up_vx_i64m8(vint64m8_t src, int64_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i32(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vslide1up_vx_u8mf8(vuint8mf8_t src, uint8_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i32(<vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vslide1up_vx_u8mf4(vuint8mf4_t src, uint8_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i32(<vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vslide1up_vx_u8mf2(vuint8mf2_t src, uint8_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i32(<vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vslide1up_vx_u8m1(vuint8m1_t src, uint8_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i32(<vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vslide1up_vx_u8m2(vuint8m2_t src, uint8_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i32(<vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vslide1up_vx_u8m4(vuint8m4_t src, uint8_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i32(<vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vslide1up_vx_u8m8(vuint8m8_t src, uint8_t value, size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i32(<vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vslide1up_vx_u16mf4(vuint16mf4_t src, uint16_t value,
				size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i32(<vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vslide1up_vx_u16mf2(vuint16mf2_t src, uint16_t value,
				size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i32(<vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vslide1up_vx_u16m1(vuint16m1_t src, uint16_t value,
				size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1up.nxv8i16.i16.i32(<vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1up.nxv8i16.i16.i64(<vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vslide1up_vx_u16m2(vuint16m2_t src, uint16_t value,
				size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1up.nxv16i16.i16.i32(<vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1up.nxv16i16.i16.i64(<vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vslide1up_vx_u16m4(vuint16m4_t src, uint16_t value,
				size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1up.nxv32i16.i16.i32(<vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1up.nxv32i16.i16.i64(<vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vslide1up_vx_u16m8(vuint16m8_t src, uint16_t value,
				size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1up.nxv1i32.i32.i32(<vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1up.nxv1i32.i32.i64(<vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vslide1up_vx_u32mf2(vuint32mf2_t src, uint32_t value,
				size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1up.nxv2i32.i32.i32(<vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1up.nxv2i32.i32.i64(<vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vslide1up_vx_u32m1(vuint32m1_t src, uint32_t value,
				size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1up.nxv4i32.i32.i32(<vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1up.nxv4i32.i32.i64(<vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vslide1up_vx_u32m2(vuint32m2_t src, uint32_t value,
				size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1up.nxv8i32.i32.i32(<vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1up.nxv8i32.i32.i64(<vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vslide1up_vx_u32m4(vuint32m4_t src, uint32_t value,
				size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1up.nxv16i32.i32.i32(<vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1up.nxv16i32.i32.i64(<vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vslide1up_vx_u32m8(vuint32m8_t src, uint32_t value,
				size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64.i32(<vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64.i64(<vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vslide1up_vx_u64m1(vuint64m1_t src, uint64_t value,
				size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1up.nxv2i64.i64.i32(<vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1up.nxv2i64.i64.i64(<vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vslide1up_vx_u64m2(vuint64m2_t src, uint64_t value,
				size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1up.nxv4i64.i64.i32(<vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1up.nxv4i64.i64.i64(<vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vslide1up_vx_u64m4(vuint64m4_t src, uint64_t value,
				size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1up.nxv8i64.i64.i32(<vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1up.nxv8i64.i64.i64(<vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vslide1up_vx_u64m8(vuint64m8_t src, uint64_t value,
				size_t vl) {
				return vslide1up(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.mask.nxv1i8.i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vslide1up_vx_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff,
				vint8mf8_t src, int8_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1up.mask.nxv2i8.i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1up.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vslide1up_vx_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff,
				vint8mf4_t src, int8_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1up.mask.nxv4i8.i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1up.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vslide1up_vx_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff,
				vint8mf2_t src, int8_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1up.mask.nxv8i8.i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1up.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vslide1up_vx_i8m1_m(vbool8_t mask, vint8m1_t maskedoff,
				vint8m1_t src, int8_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1up.mask.nxv16i8.i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1up.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vslide1up_vx_i8m2_m(vbool4_t mask, vint8m2_t maskedoff,
				vint8m2_t src, int8_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1up.mask.nxv32i8.i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1up.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vslide1up_vx_i8m4_m(vbool2_t mask, vint8m4_t maskedoff,
				vint8m4_t src, int8_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1up.mask.nxv64i8.i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1up.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vslide1up_vx_i8m8_m(vbool1_t mask, vint8m8_t maskedoff,
				vint8m8_t src, int8_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1up.mask.nxv1i16.i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1up.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vslide1up_vx_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff,
				vint16mf4_t src, int16_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1up.mask.nxv2i16.i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1up.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vslide1up_vx_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff,
				vint16mf2_t src, int16_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1up.mask.nxv4i16.i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1up.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vslide1up_vx_i16m1_m(vbool16_t mask, vint16m1_t maskedoff,
				vint16m1_t src, int16_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1up.mask.nxv8i16.i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1up.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vslide1up_vx_i16m2_m(vbool8_t mask, vint16m2_t maskedoff,
				vint16m2_t src, int16_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1up.mask.nxv16i16.i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1up.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vslide1up_vx_i16m4_m(vbool4_t mask, vint16m4_t maskedoff,
				vint16m4_t src, int16_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1up.mask.nxv32i16.i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1up.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vslide1up_vx_i16m8_m(vbool2_t mask, vint16m8_t maskedoff,
				vint16m8_t src, int16_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1up.mask.nxv1i32.i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1up.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vslide1up_vx_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff,
				vint32mf2_t src, int32_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1up.mask.nxv2i32.i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1up.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vslide1up_vx_i32m1_m(vbool32_t mask, vint32m1_t maskedoff,
				vint32m1_t src, int32_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1up.mask.nxv4i32.i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1up.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vslide1up_vx_i32m2_m(vbool16_t mask, vint32m2_t maskedoff,
				vint32m2_t src, int32_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1up.mask.nxv8i32.i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1up.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vslide1up_vx_i32m4_m(vbool8_t mask, vint32m4_t maskedoff,
				vint32m4_t src, int32_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1up.mask.nxv16i32.i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1up.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vslide1up_vx_i32m8_m(vbool4_t mask, vint32m8_t maskedoff,
				vint32m8_t src, int32_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1up.mask.nxv1i64.i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1up.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t maskedoff,
				vint64m1_t src, int64_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1up.mask.nxv2i64.i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1up.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t maskedoff,
				vint64m2_t src, int64_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1up.mask.nxv4i64.i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1up.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t maskedoff,
				vint64m4_t src, int64_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1up.mask.nxv8i64.i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1up.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t maskedoff,
				vint64m8_t src, int64_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.mask.nxv1i8.i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vslide1up_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff,
				vuint8mf8_t src, uint8_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1up.mask.nxv2i8.i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1up.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vslide1up_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff,
				vuint8mf4_t src, uint8_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1up.mask.nxv4i8.i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1up.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vslide1up_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff,
				vuint8mf2_t src, uint8_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1up.mask.nxv8i8.i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1up.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vslide1up_vx_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff,
				vuint8m1_t src, uint8_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1up.mask.nxv16i8.i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1up.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vslide1up_vx_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff,
				vuint8m2_t src, uint8_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1up.mask.nxv32i8.i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1up.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vslide1up_vx_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff,
				vuint8m4_t src, uint8_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1up.mask.nxv64i8.i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1up.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vslide1up_vx_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff,
				vuint8m8_t src, uint8_t value, size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1up.mask.nxv1i16.i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1up.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vslide1up_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff,
				vuint16mf4_t src, uint16_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1up.mask.nxv2i16.i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1up.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vslide1up_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff,
				vuint16mf2_t src, uint16_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1up.mask.nxv4i16.i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1up.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vslide1up_vx_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff,
				vuint16m1_t src, uint16_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1up.mask.nxv8i16.i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1up.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vslide1up_vx_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff,
				vuint16m2_t src, uint16_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1up.mask.nxv16i16.i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1up.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vslide1up_vx_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff,
				vuint16m4_t src, uint16_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1up.mask.nxv32i16.i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1up.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vslide1up_vx_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff,
				vuint16m8_t src, uint16_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1up.mask.nxv1i32.i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1up.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vslide1up_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff,
				vuint32mf2_t src, uint32_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1up.mask.nxv2i32.i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1up.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vslide1up_vx_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff,
				vuint32m1_t src, uint32_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1up.mask.nxv4i32.i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1up.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vslide1up_vx_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff,
				vuint32m2_t src, uint32_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1up.mask.nxv8i32.i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1up.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vslide1up_vx_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff,
				vuint32m4_t src, uint32_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1up.mask.nxv16i32.i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1up.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vslide1up_vx_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff,
				vuint32m8_t src, uint32_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1up.mask.nxv1i64.i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1up.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vslide1up_vx_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff,
				vuint64m1_t src, uint64_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1up.mask.nxv2i64.i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1up.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vslide1up_vx_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff,
				vuint64m2_t src, uint64_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1up.mask.nxv4i64.i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1up.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vslide1up_vx_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff,
				vuint64m4_t src, uint64_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1up.mask.nxv8i64.i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1up.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vslide1up_vx_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff,
				vuint64m8_t src, uint64_t value,
				size_t vl) {
				return vslide1up(mask, maskedoff, src, value, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c

This file was added.

				// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
				// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 \| FileCheck --check-prefix=ASM --allow-empty %s

				// ASM-NOT: warning
				#include <riscv_vector.h>

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i32(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.]]) [[ATTR8:#.]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.]]) [[ATTR8:#.]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vslidedown_vx_i8mf8(vint8mf8_t dst, vint8mf8_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8.i32(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vslidedown_vx_i8mf4(vint8mf4_t dst, vint8mf4_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8.i32(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vslidedown_vx_i8mf2(vint8mf2_t dst, vint8mf2_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8.i32(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vslidedown_vx_i8m1(vint8m1_t dst, vint8m1_t src, size_t offset,
				size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8.i32(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vslidedown_vx_i8m2(vint8m2_t dst, vint8m2_t src, size_t offset,
				size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8.i32(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vslidedown_vx_i8m4(vint8m4_t dst, vint8m4_t src, size_t offset,
				size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.nxv64i8.i32(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vslidedown_vx_i8m8(vint8m8_t dst, vint8m8_t src, size_t offset,
				size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16.i32(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vslidedown_vx_i16mf4(vint16mf4_t dst, vint16mf4_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16.i32(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vslidedown_vx_i16mf2(vint16mf2_t dst, vint16mf2_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16.i32(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vslidedown_vx_i16m1(vint16m1_t dst, vint16m1_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16.i32(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vslidedown_vx_i16m2(vint16m2_t dst, vint16m2_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16.i32(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vslidedown_vx_i16m4(vint16m4_t dst, vint16m4_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.nxv32i16.i32(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vslidedown_vx_i16m8(vint16m8_t dst, vint16m8_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32.i32(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vslidedown_vx_i32mf2(vint32mf2_t dst, vint32mf2_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32.i32(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vslidedown_vx_i32m1(vint32m1_t dst, vint32m1_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32.i32(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vslidedown_vx_i32m2(vint32m2_t dst, vint32m2_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32.i32(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vslidedown_vx_i32m4(vint32m4_t dst, vint32m4_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.nxv16i32.i32(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vslidedown_vx_i32m8(vint32m8_t dst, vint32m8_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64.i32(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vslidedown_vx_i64m1(vint64m1_t dst, vint64m1_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64.i32(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vslidedown_vx_i64m2(vint64m2_t dst, vint64m2_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64.i32(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vslidedown_vx_i64m4(vint64m4_t dst, vint64m4_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.nxv8i64.i32(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vslidedown_vx_i64m8(vint64m8_t dst, vint64m8_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i32(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vslidedown_vx_u8mf8(vuint8mf8_t dst, vuint8mf8_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8.i32(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vslidedown_vx_u8mf4(vuint8mf4_t dst, vuint8mf4_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8.i32(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vslidedown_vx_u8mf2(vuint8mf2_t dst, vuint8mf2_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8.i32(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vslidedown_vx_u8m1(vuint8m1_t dst, vuint8m1_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8.i32(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vslidedown_vx_u8m2(vuint8m2_t dst, vuint8m2_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8.i32(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vslidedown_vx_u8m4(vuint8m4_t dst, vuint8m4_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.nxv64i8.i32(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vslidedown_vx_u8m8(vuint8m8_t dst, vuint8m8_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16.i32(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vslidedown_vx_u16mf4(vuint16mf4_t dst, vuint16mf4_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16.i32(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vslidedown_vx_u16mf2(vuint16mf2_t dst, vuint16mf2_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16.i32(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vslidedown_vx_u16m1(vuint16m1_t dst, vuint16m1_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16.i32(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vslidedown_vx_u16m2(vuint16m2_t dst, vuint16m2_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16.i32(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vslidedown_vx_u16m4(vuint16m4_t dst, vuint16m4_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.nxv32i16.i32(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vslidedown_vx_u16m8(vuint16m8_t dst, vuint16m8_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32.i32(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vslidedown_vx_u32mf2(vuint32mf2_t dst, vuint32mf2_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32.i32(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vslidedown_vx_u32m1(vuint32m1_t dst, vuint32m1_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32.i32(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vslidedown_vx_u32m2(vuint32m2_t dst, vuint32m2_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32.i32(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vslidedown_vx_u32m4(vuint32m4_t dst, vuint32m4_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.nxv16i32.i32(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vslidedown_vx_u32m8(vuint32m8_t dst, vuint32m8_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64.i32(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vslidedown_vx_u64m1(vuint64m1_t dst, vuint64m1_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64.i32(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vslidedown_vx_u64m2(vuint64m2_t dst, vuint64m2_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64.i32(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vslidedown_vx_u64m4(vuint64m4_t dst, vuint64m4_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.nxv8i64.i32(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vslidedown_vx_u64m8(vuint64m8_t dst, vuint64m8_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i32(<vscale x 1 x float> [[DST:%.]], <vscale x 1 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> [[DST:%.]], <vscale x 1 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vslidedown_vx_f32mf2(vfloat32mf2_t dst, vfloat32mf2_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i32(<vscale x 2 x float> [[DST:%.]], <vscale x 2 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 2 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vslidedown_vx_f32m1(vfloat32m1_t dst, vfloat32m1_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i32(<vscale x 4 x float> [[DST:%.]], <vscale x 4 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float> [[DST:%.]], <vscale x 4 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vslidedown_vx_f32m2(vfloat32m2_t dst, vfloat32m2_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i32(<vscale x 8 x float> [[DST:%.]], <vscale x 8 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float> [[DST:%.]], <vscale x 8 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vslidedown_vx_f32m4(vfloat32m4_t dst, vfloat32m4_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vslidedown.nxv16f32.i32(<vscale x 16 x float> [[DST:%.]], <vscale x 16 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vslidedown.nxv16f32.i64(<vscale x 16 x float> [[DST:%.]], <vscale x 16 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vslidedown_vx_f32m8(vfloat32m8_t dst, vfloat32m8_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64.i32(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x double> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x double> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vslidedown_vx_f64m1(vfloat64m1_t dst, vfloat64m1_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64.i32(<vscale x 2 x double> [[DST:%.]], <vscale x 2 x double> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64.i64(<vscale x 2 x double> [[DST:%.]], <vscale x 2 x double> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vslidedown_vx_f64m2(vfloat64m2_t dst, vfloat64m2_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64.i32(<vscale x 4 x double> [[DST:%.]], <vscale x 4 x double> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64.i64(<vscale x 4 x double> [[DST:%.]], <vscale x 4 x double> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vslidedown_vx_f64m4(vfloat64m4_t dst, vfloat64m4_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vslidedown.nxv8f64.i32(<vscale x 8 x double> [[DST:%.]], <vscale x 8 x double> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vslidedown.nxv8f64.i64(<vscale x 8 x double> [[DST:%.]], <vscale x 8 x double> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vslidedown_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src,
				size_t offset, size_t vl) {
				return vslidedown(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8.i32(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vslidedown_vx_i8mf8_m(vbool64_t mask, vint8mf8_t dst,
				vint8mf8_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8.i32(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vslidedown_vx_i8mf4_m(vbool32_t mask, vint8mf4_t dst,
				vint8mf4_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8.i32(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vslidedown_vx_i8mf2_m(vbool16_t mask, vint8mf2_t dst,
				vint8mf2_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8.i32(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vslidedown_vx_i8m1_m(vbool8_t mask, vint8m1_t dst, vint8m1_t src,
				size_t offset, size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8.i32(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vslidedown_vx_i8m2_m(vbool4_t mask, vint8m2_t dst, vint8m2_t src,
				size_t offset, size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8.i32(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vslidedown_vx_i8m4_m(vbool2_t mask, vint8m4_t dst, vint8m4_t src,
				size_t offset, size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.mask.nxv64i8.i32(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vslidedown_vx_i8m8_m(vbool1_t mask, vint8m8_t dst, vint8m8_t src,
				size_t offset, size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16.i32(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vslidedown_vx_i16mf4_m(vbool64_t mask, vint16mf4_t dst,
				vint16mf4_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16.i32(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vslidedown_vx_i16mf2_m(vbool32_t mask, vint16mf2_t dst,
				vint16mf2_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16.i32(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vslidedown_vx_i16m1_m(vbool16_t mask, vint16m1_t dst,
				vint16m1_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16.i32(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vslidedown_vx_i16m2_m(vbool8_t mask, vint16m2_t dst,
				vint16m2_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16.i32(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vslidedown_vx_i16m4_m(vbool4_t mask, vint16m4_t dst,
				vint16m4_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.mask.nxv32i16.i32(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vslidedown_vx_i16m8_m(vbool2_t mask, vint16m8_t dst,
				vint16m8_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32.i32(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vslidedown_vx_i32mf2_m(vbool64_t mask, vint32mf2_t dst,
				vint32mf2_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32.i32(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vslidedown_vx_i32m1_m(vbool32_t mask, vint32m1_t dst,
				vint32m1_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32.i32(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vslidedown_vx_i32m2_m(vbool16_t mask, vint32m2_t dst,
				vint32m2_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32.i32(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vslidedown_vx_i32m4_m(vbool8_t mask, vint32m4_t dst,
				vint32m4_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.mask.nxv16i32.i32(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vslidedown_vx_i32m8_m(vbool4_t mask, vint32m8_t dst,
				vint32m8_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64.i32(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vslidedown_vx_i64m1_m(vbool64_t mask, vint64m1_t dst,
				vint64m1_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64.i32(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vslidedown_vx_i64m2_m(vbool32_t mask, vint64m2_t dst,
				vint64m2_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64.i32(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vslidedown_vx_i64m4_m(vbool16_t mask, vint64m4_t dst,
				vint64m4_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.mask.nxv8i64.i32(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vslidedown_vx_i64m8_m(vbool8_t mask, vint64m8_t dst,
				vint64m8_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8.i32(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vslidedown_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t dst,
				vuint8mf8_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8.i32(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vslidedown_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t dst,
				vuint8mf4_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8.i32(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vslidedown_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t dst,
				vuint8mf2_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8.i32(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vslidedown_vx_u8m1_m(vbool8_t mask, vuint8m1_t dst,
				vuint8m1_t src, size_t offset, size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8.i32(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vslidedown_vx_u8m2_m(vbool4_t mask, vuint8m2_t dst,
				vuint8m2_t src, size_t offset, size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8.i32(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vslidedown_vx_u8m4_m(vbool2_t mask, vuint8m4_t dst,
				vuint8m4_t src, size_t offset, size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.mask.nxv64i8.i32(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vslidedown_vx_u8m8_m(vbool1_t mask, vuint8m8_t dst,
				vuint8m8_t src, size_t offset, size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16.i32(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vslidedown_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t dst,
				vuint16mf4_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16.i32(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vslidedown_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t dst,
				vuint16mf2_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16.i32(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vslidedown_vx_u16m1_m(vbool16_t mask, vuint16m1_t dst,
				vuint16m1_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16.i32(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vslidedown_vx_u16m2_m(vbool8_t mask, vuint16m2_t dst,
				vuint16m2_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16.i32(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vslidedown_vx_u16m4_m(vbool4_t mask, vuint16m4_t dst,
				vuint16m4_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.mask.nxv32i16.i32(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vslidedown_vx_u16m8_m(vbool2_t mask, vuint16m8_t dst,
				vuint16m8_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32.i32(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vslidedown_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t dst,
				vuint32mf2_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32.i32(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vslidedown_vx_u32m1_m(vbool32_t mask, vuint32m1_t dst,
				vuint32m1_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32.i32(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vslidedown_vx_u32m2_m(vbool16_t mask, vuint32m2_t dst,
				vuint32m2_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32.i32(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vslidedown_vx_u32m4_m(vbool8_t mask, vuint32m4_t dst,
				vuint32m4_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.mask.nxv16i32.i32(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vslidedown_vx_u32m8_m(vbool4_t mask, vuint32m8_t dst,
				vuint32m8_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64.i32(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vslidedown_vx_u64m1_m(vbool64_t mask, vuint64m1_t dst,
				vuint64m1_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64.i32(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vslidedown_vx_u64m2_m(vbool32_t mask, vuint64m2_t dst,
				vuint64m2_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64.i32(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vslidedown_vx_u64m4_m(vbool16_t mask, vuint64m4_t dst,
				vuint64m4_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.mask.nxv8i64.i32(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vslidedown_vx_u64m8_m(vbool8_t mask, vuint64m8_t dst,
				vuint64m8_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32.i32(<vscale x 1 x float> [[DST:%.]], <vscale x 1 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32.i64(<vscale x 1 x float> [[DST:%.]], <vscale x 1 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vslidedown_vx_f32mf2_m(vbool64_t mask, vfloat32mf2_t dst,
				vfloat32mf2_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32.i32(<vscale x 2 x float> [[DST:%.]], <vscale x 2 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 2 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vslidedown_vx_f32m1_m(vbool32_t mask, vfloat32m1_t dst,
				vfloat32m1_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32.i32(<vscale x 4 x float> [[DST:%.]], <vscale x 4 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32.i64(<vscale x 4 x float> [[DST:%.]], <vscale x 4 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vslidedown_vx_f32m2_m(vbool16_t mask, vfloat32m2_t dst,
				vfloat32m2_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32.i32(<vscale x 8 x float> [[DST:%.]], <vscale x 8 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32.i64(<vscale x 8 x float> [[DST:%.]], <vscale x 8 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vslidedown_vx_f32m4_m(vbool8_t mask, vfloat32m4_t dst,
				vfloat32m4_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vslidedown.mask.nxv16f32.i32(<vscale x 16 x float> [[DST:%.]], <vscale x 16 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vslidedown.mask.nxv16f32.i64(<vscale x 16 x float> [[DST:%.]], <vscale x 16 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vslidedown_vx_f32m8_m(vbool4_t mask, vfloat32m8_t dst,
				vfloat32m8_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64.i32(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x double> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x double> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vslidedown_vx_f64m1_m(vbool64_t mask, vfloat64m1_t dst,
				vfloat64m1_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64.i32(<vscale x 2 x double> [[DST:%.]], <vscale x 2 x double> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64.i64(<vscale x 2 x double> [[DST:%.]], <vscale x 2 x double> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vslidedown_vx_f64m2_m(vbool32_t mask, vfloat64m2_t dst,
				vfloat64m2_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64.i32(<vscale x 4 x double> [[DST:%.]], <vscale x 4 x double> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64.i64(<vscale x 4 x double> [[DST:%.]], <vscale x 4 x double> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vslidedown_vx_f64m4_m(vbool16_t mask, vfloat64m4_t dst,
				vfloat64m4_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vslidedown.mask.nxv8f64.i32(<vscale x 8 x double> [[DST:%.]], <vscale x 8 x double> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vslidedown.mask.nxv8f64.i64(<vscale x 8 x double> [[DST:%.]], <vscale x 8 x double> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vslidedown_vx_f64m8_m(vbool8_t mask, vfloat64m8_t dst,
				vfloat64m8_t src, size_t offset,
				size_t vl) {
				return vslidedown(mask, dst, src, offset, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c

This file was added.

				// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
				// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 \| FileCheck --check-prefix=ASM --allow-empty %s

				// ASM-NOT: warning
				#include <riscv_vector.h>

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i32(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.]]) [[ATTR8:#.]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.]]) [[ATTR8:#.]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vslideup_vx_i8mf8(vint8mf8_t dst, vint8mf8_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i32(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vslideup_vx_i8mf4(vint8mf4_t dst, vint8mf4_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i32(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vslideup_vx_i8mf2(vint8mf2_t dst, vint8mf2_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i32(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vslideup_vx_i8m1(vint8m1_t dst, vint8m1_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i32(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vslideup_vx_i8m2(vint8m2_t dst, vint8m2_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i32(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vslideup_vx_i8m4(vint8m4_t dst, vint8m4_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i32(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vslideup_vx_i8m8(vint8m8_t dst, vint8m8_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i32(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vslideup_vx_i16mf4(vint16mf4_t dst, vint16mf4_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i32(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vslideup_vx_i16mf2(vint16mf2_t dst, vint16mf2_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i32(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vslideup_vx_i16m1(vint16m1_t dst, vint16m1_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i32(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vslideup_vx_i16m2(vint16m2_t dst, vint16m2_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i32(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vslideup_vx_i16m4(vint16m4_t dst, vint16m4_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i32(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vslideup_vx_i16m8(vint16m8_t dst, vint16m8_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i32(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vslideup_vx_i32mf2(vint32mf2_t dst, vint32mf2_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i32(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vslideup_vx_i32m1(vint32m1_t dst, vint32m1_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i32(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vslideup_vx_i32m2(vint32m2_t dst, vint32m2_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i32(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vslideup_vx_i32m4(vint32m4_t dst, vint32m4_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i32(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vslideup_vx_i32m8(vint32m8_t dst, vint32m8_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i32(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vslideup_vx_i64m1(vint64m1_t dst, vint64m1_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i32(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vslideup_vx_i64m2(vint64m2_t dst, vint64m2_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i32(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vslideup_vx_i64m4(vint64m4_t dst, vint64m4_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i32(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vslideup_vx_i64m8(vint64m8_t dst, vint64m8_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i32(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vslideup_vx_u8mf8(vuint8mf8_t dst, vuint8mf8_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i32(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vslideup_vx_u8mf4(vuint8mf4_t dst, vuint8mf4_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i32(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vslideup_vx_u8mf2(vuint8mf2_t dst, vuint8mf2_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i32(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vslideup_vx_u8m1(vuint8m1_t dst, vuint8m1_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i32(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vslideup_vx_u8m2(vuint8m2_t dst, vuint8m2_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i32(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vslideup_vx_u8m4(vuint8m4_t dst, vuint8m4_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i32(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vslideup_vx_u8m8(vuint8m8_t dst, vuint8m8_t src, size_t offset,
				size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i32(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vslideup_vx_u16mf4(vuint16mf4_t dst, vuint16mf4_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i32(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vslideup_vx_u16mf2(vuint16mf2_t dst, vuint16mf2_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i32(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vslideup_vx_u16m1(vuint16m1_t dst, vuint16m1_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i32(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vslideup_vx_u16m2(vuint16m2_t dst, vuint16m2_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i32(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vslideup_vx_u16m4(vuint16m4_t dst, vuint16m4_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i32(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vslideup_vx_u16m8(vuint16m8_t dst, vuint16m8_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i32(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vslideup_vx_u32mf2(vuint32mf2_t dst, vuint32mf2_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i32(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vslideup_vx_u32m1(vuint32m1_t dst, vuint32m1_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i32(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vslideup_vx_u32m2(vuint32m2_t dst, vuint32m2_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i32(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vslideup_vx_u32m4(vuint32m4_t dst, vuint32m4_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i32(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vslideup_vx_u32m8(vuint32m8_t dst, vuint32m8_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i32(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vslideup_vx_u64m1(vuint64m1_t dst, vuint64m1_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i32(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vslideup_vx_u64m2(vuint64m2_t dst, vuint64m2_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i32(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vslideup_vx_u64m4(vuint64m4_t dst, vuint64m4_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i32(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vslideup_vx_u64m8(vuint64m8_t dst, vuint64m8_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i32(<vscale x 1 x float> [[DST:%.]], <vscale x 1 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> [[DST:%.]], <vscale x 1 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vslideup_vx_f32mf2(vfloat32mf2_t dst, vfloat32mf2_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i32(<vscale x 2 x float> [[DST:%.]], <vscale x 2 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 2 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vslideup_vx_f32m1(vfloat32m1_t dst, vfloat32m1_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32.i32(<vscale x 4 x float> [[DST:%.]], <vscale x 4 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32.i64(<vscale x 4 x float> [[DST:%.]], <vscale x 4 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vslideup_vx_f32m2(vfloat32m2_t dst, vfloat32m2_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32.i32(<vscale x 8 x float> [[DST:%.]], <vscale x 8 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32.i64(<vscale x 8 x float> [[DST:%.]], <vscale x 8 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vslideup_vx_f32m4(vfloat32m4_t dst, vfloat32m4_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vslideup.nxv16f32.i32(<vscale x 16 x float> [[DST:%.]], <vscale x 16 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vslideup.nxv16f32.i64(<vscale x 16 x float> [[DST:%.]], <vscale x 16 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vslideup_vx_f32m8(vfloat32m8_t dst, vfloat32m8_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64.i32(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x double> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x double> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vslideup_vx_f64m1(vfloat64m1_t dst, vfloat64m1_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64.i32(<vscale x 2 x double> [[DST:%.]], <vscale x 2 x double> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64.i64(<vscale x 2 x double> [[DST:%.]], <vscale x 2 x double> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vslideup_vx_f64m2(vfloat64m2_t dst, vfloat64m2_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64.i32(<vscale x 4 x double> [[DST:%.]], <vscale x 4 x double> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64.i64(<vscale x 4 x double> [[DST:%.]], <vscale x 4 x double> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vslideup_vx_f64m4(vfloat64m4_t dst, vfloat64m4_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vslideup.nxv8f64.i32(<vscale x 8 x double> [[DST:%.]], <vscale x 8 x double> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vslideup.nxv8f64.i64(<vscale x 8 x double> [[DST:%.]], <vscale x 8 x double> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vslideup_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src,
				size_t offset, size_t vl) {
				return vslideup(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8.i32(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vslideup_vx_i8mf8_m(vbool64_t mask, vint8mf8_t dst,
				vint8mf8_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8.i32(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vslideup_vx_i8mf4_m(vbool32_t mask, vint8mf4_t dst,
				vint8mf4_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8.i32(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vslideup_vx_i8mf2_m(vbool16_t mask, vint8mf2_t dst,
				vint8mf2_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8.i32(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vslideup_vx_i8m1_m(vbool8_t mask, vint8m1_t dst, vint8m1_t src,
				size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8.i32(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vslideup_vx_i8m2_m(vbool4_t mask, vint8m2_t dst, vint8m2_t src,
				size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8.i32(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vslideup_vx_i8m4_m(vbool2_t mask, vint8m4_t dst, vint8m4_t src,
				size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.mask.nxv64i8.i32(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vslideup_vx_i8m8_m(vbool1_t mask, vint8m8_t dst, vint8m8_t src,
				size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16.i32(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vslideup_vx_i16mf4_m(vbool64_t mask, vint16mf4_t dst,
				vint16mf4_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16.i32(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vslideup_vx_i16mf2_m(vbool32_t mask, vint16mf2_t dst,
				vint16mf2_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16.i32(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vslideup_vx_i16m1_m(vbool16_t mask, vint16m1_t dst,
				vint16m1_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16.i32(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vslideup_vx_i16m2_m(vbool8_t mask, vint16m2_t dst,
				vint16m2_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16.i32(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vslideup_vx_i16m4_m(vbool4_t mask, vint16m4_t dst,
				vint16m4_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.mask.nxv32i16.i32(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vslideup_vx_i16m8_m(vbool2_t mask, vint16m8_t dst,
				vint16m8_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32.i32(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vslideup_vx_i32mf2_m(vbool64_t mask, vint32mf2_t dst,
				vint32mf2_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32.i32(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vslideup_vx_i32m1_m(vbool32_t mask, vint32m1_t dst,
				vint32m1_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32.i32(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vslideup_vx_i32m2_m(vbool16_t mask, vint32m2_t dst,
				vint32m2_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32.i32(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vslideup_vx_i32m4_m(vbool8_t mask, vint32m4_t dst,
				vint32m4_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.mask.nxv16i32.i32(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vslideup_vx_i32m8_m(vbool4_t mask, vint32m8_t dst,
				vint32m8_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64.i32(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vslideup_vx_i64m1_m(vbool64_t mask, vint64m1_t dst,
				vint64m1_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64.i32(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vslideup_vx_i64m2_m(vbool32_t mask, vint64m2_t dst,
				vint64m2_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64.i32(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vslideup_vx_i64m4_m(vbool16_t mask, vint64m4_t dst,
				vint64m4_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.mask.nxv8i64.i32(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vslideup_vx_i64m8_m(vbool8_t mask, vint64m8_t dst,
				vint64m8_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8.i32(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vslideup_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t dst,
				vuint8mf8_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8.i32(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vslideup_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t dst,
				vuint8mf4_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8.i32(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vslideup_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t dst,
				vuint8mf2_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8.i32(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vslideup_vx_u8m1_m(vbool8_t mask, vuint8m1_t dst,
				vuint8m1_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8.i32(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vslideup_vx_u8m2_m(vbool4_t mask, vuint8m2_t dst,
				vuint8m2_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8.i32(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vslideup_vx_u8m4_m(vbool2_t mask, vuint8m4_t dst,
				vuint8m4_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.mask.nxv64i8.i32(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vslideup_vx_u8m8_m(vbool1_t mask, vuint8m8_t dst,
				vuint8m8_t src, size_t offset, size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16.i32(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vslideup_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t dst,
				vuint16mf4_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16.i32(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vslideup_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t dst,
				vuint16mf2_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16.i32(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vslideup_vx_u16m1_m(vbool16_t mask, vuint16m1_t dst,
				vuint16m1_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16.i32(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vslideup_vx_u16m2_m(vbool8_t mask, vuint16m2_t dst,
				vuint16m2_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16.i32(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vslideup_vx_u16m4_m(vbool4_t mask, vuint16m4_t dst,
				vuint16m4_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.mask.nxv32i16.i32(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vslideup_vx_u16m8_m(vbool2_t mask, vuint16m8_t dst,
				vuint16m8_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32.i32(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vslideup_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t dst,
				vuint32mf2_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32.i32(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vslideup_vx_u32m1_m(vbool32_t mask, vuint32m1_t dst,
				vuint32m1_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32.i32(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vslideup_vx_u32m2_m(vbool16_t mask, vuint32m2_t dst,
				vuint32m2_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32.i32(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vslideup_vx_u32m4_m(vbool8_t mask, vuint32m4_t dst,
				vuint32m4_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.mask.nxv16i32.i32(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vslideup_vx_u32m8_m(vbool4_t mask, vuint32m8_t dst,
				vuint32m8_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64.i32(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vslideup_vx_u64m1_m(vbool64_t mask, vuint64m1_t dst,
				vuint64m1_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64.i32(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vslideup_vx_u64m2_m(vbool32_t mask, vuint64m2_t dst,
				vuint64m2_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64.i32(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vslideup_vx_u64m4_m(vbool16_t mask, vuint64m4_t dst,
				vuint64m4_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.mask.nxv8i64.i32(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vslideup_vx_u64m8_m(vbool8_t mask, vuint64m8_t dst,
				vuint64m8_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32.i32(<vscale x 1 x float> [[DST:%.]], <vscale x 1 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32.i64(<vscale x 1 x float> [[DST:%.]], <vscale x 1 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vslideup_vx_f32mf2_m(vbool64_t mask, vfloat32mf2_t dst,
				vfloat32mf2_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32.i32(<vscale x 2 x float> [[DST:%.]], <vscale x 2 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 2 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vslideup_vx_f32m1_m(vbool32_t mask, vfloat32m1_t dst,
				vfloat32m1_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32.i32(<vscale x 4 x float> [[DST:%.]], <vscale x 4 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32.i64(<vscale x 4 x float> [[DST:%.]], <vscale x 4 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vslideup_vx_f32m2_m(vbool16_t mask, vfloat32m2_t dst,
				vfloat32m2_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32.i32(<vscale x 8 x float> [[DST:%.]], <vscale x 8 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32.i64(<vscale x 8 x float> [[DST:%.]], <vscale x 8 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vslideup_vx_f32m4_m(vbool8_t mask, vfloat32m4_t dst,
				vfloat32m4_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vslideup.mask.nxv16f32.i32(<vscale x 16 x float> [[DST:%.]], <vscale x 16 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vslideup.mask.nxv16f32.i64(<vscale x 16 x float> [[DST:%.]], <vscale x 16 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vslideup_vx_f32m8_m(vbool4_t mask, vfloat32m8_t dst,
				vfloat32m8_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64.i32(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x double> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x double> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vslideup_vx_f64m1_m(vbool64_t mask, vfloat64m1_t dst,
				vfloat64m1_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64.i32(<vscale x 2 x double> [[DST:%.]], <vscale x 2 x double> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64.i64(<vscale x 2 x double> [[DST:%.]], <vscale x 2 x double> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vslideup_vx_f64m2_m(vbool32_t mask, vfloat64m2_t dst,
				vfloat64m2_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64.i32(<vscale x 4 x double> [[DST:%.]], <vscale x 4 x double> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64.i64(<vscale x 4 x double> [[DST:%.]], <vscale x 4 x double> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vslideup_vx_f64m4_m(vbool16_t mask, vfloat64m4_t dst,
				vfloat64m4_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vslideup.mask.nxv8f64.i32(<vscale x 8 x double> [[DST:%.]], <vscale x 8 x double> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vslideup.mask.nxv8f64.i64(<vscale x 8 x double> [[DST:%.]], <vscale x 8 x double> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]]) [[ATTR8]]
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vslideup_vx_f64m8_m(vbool8_t mask, vfloat64m8_t dst,
				vfloat64m8_t src, size_t offset,
				size_t vl) {
				return vslideup(mask, dst, src, offset, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c

This file was added.

				// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
				// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 \| FileCheck --check-prefix=ASM --allow-empty %s

				// ASM-NOT: warning
				#include <riscv_vector.h>

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i32(<vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vfslide1down_vf_f32mf2(vfloat32mf2_t src, float value,
				size_t vl) {
				return vfslide1down_vf_f32mf2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i32(<vscale x 2 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfslide1down_vf_f32m1(vfloat32m1_t src, float value,
				size_t vl) {
				return vfslide1down_vf_f32m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i32(<vscale x 4 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vfslide1down_vf_f32m2(vfloat32m2_t src, float value,
				size_t vl) {
				return vfslide1down_vf_f32m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i32(<vscale x 8 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vfslide1down_vf_f32m4(vfloat32m4_t src, float value,
				size_t vl) {
				return vfslide1down_vf_f32m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vfslide1down.nxv16f32.f32.i32(<vscale x 16 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vfslide1down.nxv16f32.f32.i64(<vscale x 16 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vfslide1down_vf_f32m8(vfloat32m8_t src, float value,
				size_t vl) {
				return vfslide1down_vf_f32m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfslide1down.nxv1f64.f64.i32(<vscale x 1 x double> [[SRC:%.]], double [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfslide1down.nxv1f64.f64.i64(<vscale x 1 x double> [[SRC:%.]], double [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfslide1down_vf_f64m1(vfloat64m1_t src, double value,
				size_t vl) {
				return vfslide1down_vf_f64m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vfslide1down.nxv2f64.f64.i32(<vscale x 2 x double> [[SRC:%.]], double [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vfslide1down.nxv2f64.f64.i64(<vscale x 2 x double> [[SRC:%.]], double [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vfslide1down_vf_f64m2(vfloat64m2_t src, double value,
				size_t vl) {
				return vfslide1down_vf_f64m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vfslide1down.nxv4f64.f64.i32(<vscale x 4 x double> [[SRC:%.]], double [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vfslide1down.nxv4f64.f64.i64(<vscale x 4 x double> [[SRC:%.]], double [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vfslide1down_vf_f64m4(vfloat64m4_t src, double value,
				size_t vl) {
				return vfslide1down_vf_f64m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vfslide1down.nxv8f64.f64.i32(<vscale x 8 x double> [[SRC:%.]], double [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vfslide1down.nxv8f64.f64.i64(<vscale x 8 x double> [[SRC:%.]], double [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vfslide1down_vf_f64m8(vfloat64m8_t src, double value,
				size_t vl) {
				return vfslide1down_vf_f64m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1down.mask.nxv1f32.f32.i32(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1down.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vfslide1down_vf_f32mf2_m(vbool64_t mask,
				vfloat32mf2_t maskedoff,
				vfloat32mf2_t src, float value,
				size_t vl) {
				return vfslide1down_vf_f32mf2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfslide1down.mask.nxv2f32.f32.i32(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfslide1down.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfslide1down_vf_f32m1_m(vbool32_t mask,
				vfloat32m1_t maskedoff,
				vfloat32m1_t src, float value,
				size_t vl) {
				return vfslide1down_vf_f32m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vfslide1down.mask.nxv4f32.f32.i32(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vfslide1down.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vfslide1down_vf_f32m2_m(vbool16_t mask,
				vfloat32m2_t maskedoff,
				vfloat32m2_t src, float value,
				size_t vl) {
				return vfslide1down_vf_f32m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vfslide1down.mask.nxv8f32.f32.i32(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vfslide1down.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vfslide1down_vf_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff,
				vfloat32m4_t src, float value,
				size_t vl) {
				return vfslide1down_vf_f32m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vfslide1down.mask.nxv16f32.f32.i32(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vfslide1down.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vfslide1down_vf_f32m8_m(vbool4_t mask, vfloat32m8_t maskedoff,
				vfloat32m8_t src, float value,
				size_t vl) {
				return vfslide1down_vf_f32m8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfslide1down.mask.nxv1f64.f64.i32(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfslide1down.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfslide1down_vf_f64m1_m(vbool64_t mask,
				vfloat64m1_t maskedoff,
				vfloat64m1_t src, double value,
				size_t vl) {
				return vfslide1down_vf_f64m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vfslide1down.mask.nxv2f64.f64.i32(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vfslide1down.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vfslide1down_vf_f64m2_m(vbool32_t mask,
				vfloat64m2_t maskedoff,
				vfloat64m2_t src, double value,
				size_t vl) {
				return vfslide1down_vf_f64m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vfslide1down.mask.nxv4f64.f64.i32(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vfslide1down.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vfslide1down_vf_f64m4_m(vbool16_t mask,
				vfloat64m4_t maskedoff,
				vfloat64m4_t src, double value,
				size_t vl) {
				return vfslide1down_vf_f64m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1down_vf_f64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vfslide1down.mask.nxv8f64.f64.i32(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1down_vf_f64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vfslide1down.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vfslide1down_vf_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
				vfloat64m8_t src, double value,
				size_t vl) {
				return vfslide1down_vf_f64m8_m(mask, maskedoff, src, value, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c

This file was added.

				// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
				// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 \| FileCheck --check-prefix=ASM --allow-empty %s

				// ASM-NOT: warning
				#include <riscv_vector.h>

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i32(<vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vfslide1up_vf_f32mf2(vfloat32mf2_t src, float value,
				size_t vl) {
				return vfslide1up_vf_f32mf2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i32(<vscale x 2 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfslide1up_vf_f32m1(vfloat32m1_t src, float value,
				size_t vl) {
				return vfslide1up_vf_f32m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i32(<vscale x 4 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vfslide1up_vf_f32m2(vfloat32m2_t src, float value,
				size_t vl) {
				return vfslide1up_vf_f32m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i32(<vscale x 8 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vfslide1up_vf_f32m4(vfloat32m4_t src, float value,
				size_t vl) {
				return vfslide1up_vf_f32m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vfslide1up.nxv16f32.f32.i32(<vscale x 16 x float> [[SRC:%.]], float [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vfslide1up.nxv16f32.f32.i64(<vscale x 16 x float> [[SRC:%.]], float [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vfslide1up_vf_f32m8(vfloat32m8_t src, float value,
				size_t vl) {
				return vfslide1up_vf_f32m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfslide1up.nxv1f64.f64.i32(<vscale x 1 x double> [[SRC:%.]], double [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfslide1up.nxv1f64.f64.i64(<vscale x 1 x double> [[SRC:%.]], double [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfslide1up_vf_f64m1(vfloat64m1_t src, double value,
				size_t vl) {
				return vfslide1up_vf_f64m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vfslide1up.nxv2f64.f64.i32(<vscale x 2 x double> [[SRC:%.]], double [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vfslide1up.nxv2f64.f64.i64(<vscale x 2 x double> [[SRC:%.]], double [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vfslide1up_vf_f64m2(vfloat64m2_t src, double value,
				size_t vl) {
				return vfslide1up_vf_f64m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vfslide1up.nxv4f64.f64.i32(<vscale x 4 x double> [[SRC:%.]], double [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vfslide1up.nxv4f64.f64.i64(<vscale x 4 x double> [[SRC:%.]], double [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vfslide1up_vf_f64m4(vfloat64m4_t src, double value,
				size_t vl) {
				return vfslide1up_vf_f64m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vfslide1up.nxv8f64.f64.i32(<vscale x 8 x double> [[SRC:%.]], double [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vfslide1up.nxv8f64.f64.i64(<vscale x 8 x double> [[SRC:%.]], double [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vfslide1up_vf_f64m8(vfloat64m8_t src, double value,
				size_t vl) {
				return vfslide1up_vf_f64m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1up.mask.nxv1f32.f32.i32(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vfslide1up.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vfslide1up_vf_f32mf2_m(vbool64_t mask,
				vfloat32mf2_t maskedoff,
				vfloat32mf2_t src, float value,
				size_t vl) {
				return vfslide1up_vf_f32mf2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfslide1up.mask.nxv2f32.f32.i32(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfslide1up.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfslide1up_vf_f32m1_m(vbool32_t mask, vfloat32m1_t maskedoff,
				vfloat32m1_t src, float value,
				size_t vl) {
				return vfslide1up_vf_f32m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vfslide1up.mask.nxv4f32.f32.i32(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vfslide1up.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vfslide1up_vf_f32m2_m(vbool16_t mask, vfloat32m2_t maskedoff,
				vfloat32m2_t src, float value,
				size_t vl) {
				return vfslide1up_vf_f32m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vfslide1up.mask.nxv8f32.f32.i32(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vfslide1up.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vfslide1up_vf_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff,
				vfloat32m4_t src, float value,
				size_t vl) {
				return vfslide1up_vf_f32m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vfslide1up.mask.nxv16f32.f32.i32(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vfslide1up.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[SRC:%.]], float [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vfslide1up_vf_f32m8_m(vbool4_t mask, vfloat32m8_t maskedoff,
				vfloat32m8_t src, float value,
				size_t vl) {
				return vfslide1up_vf_f32m8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfslide1up.mask.nxv1f64.f64.i32(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfslide1up.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfslide1up_vf_f64m1_m(vbool64_t mask, vfloat64m1_t maskedoff,
				vfloat64m1_t src, double value,
				size_t vl) {
				return vfslide1up_vf_f64m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vfslide1up.mask.nxv2f64.f64.i32(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vfslide1up.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vfslide1up_vf_f64m2_m(vbool32_t mask, vfloat64m2_t maskedoff,
				vfloat64m2_t src, double value,
				size_t vl) {
				return vfslide1up_vf_f64m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vfslide1up.mask.nxv4f64.f64.i32(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vfslide1up.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vfslide1up_vf_f64m4_m(vbool16_t mask, vfloat64m4_t maskedoff,
				vfloat64m4_t src, double value,
				size_t vl) {
				return vfslide1up_vf_f64m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vfslide1up_vf_f64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vfslide1up.mask.nxv8f64.f64.i32(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vfslide1up_vf_f64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vfslide1up.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[SRC:%.]], double [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vfslide1up_vf_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
				vfloat64m8_t src, double value,
				size_t vl) {
				return vfslide1up_vf_f64m8_m(mask, maskedoff, src, value, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c

This file was added.

This file is larger than 256 KB, so syntax highlighting is disabled by default.

				// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
				// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 \| FileCheck --check-prefix=ASM --allow-empty %s

				// ASM-NOT: warning
				#include <riscv_vector.h>

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.nxv1i8.i32(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vrgather_vv_i8mf8(vint8mf8_t op1, vuint8mf8_t index,
				size_t vl) {
				return vrgather_vv_i8mf8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.nxv1i8.i32(<vscale x 1 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vrgather_vx_i8mf8(vint8mf8_t op1, size_t index, size_t vl) {
				return vrgather_vx_i8mf8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.nxv2i8.i32(<vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i8> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i8> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vrgather_vv_i8mf4(vint8mf4_t op1, vuint8mf4_t index,
				size_t vl) {
				return vrgather_vv_i8mf4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.nxv2i8.i32(<vscale x 2 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vrgather_vx_i8mf4(vint8mf4_t op1, size_t index, size_t vl) {
				return vrgather_vx_i8mf4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.nxv4i8.i32(<vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i8> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i8> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vrgather_vv_i8mf2(vint8mf2_t op1, vuint8mf2_t index,
				size_t vl) {
				return vrgather_vv_i8mf2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.nxv4i8.i32(<vscale x 4 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vrgather_vx_i8mf2(vint8mf2_t op1, size_t index, size_t vl) {
				return vrgather_vx_i8mf2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.nxv8i8.i32(<vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i8> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i8> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vrgather_vv_i8m1(vint8m1_t op1, vuint8m1_t index, size_t vl) {
				return vrgather_vv_i8m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.nxv8i8.i32(<vscale x 8 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vrgather_vx_i8m1(vint8m1_t op1, size_t index, size_t vl) {
				return vrgather_vx_i8m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.nxv16i8.i32(<vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i8> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i8> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vrgather_vv_i8m2(vint8m2_t op1, vuint8m2_t index, size_t vl) {
				return vrgather_vv_i8m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.nxv16i8.i32(<vscale x 16 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vrgather_vx_i8m2(vint8m2_t op1, size_t index, size_t vl) {
				return vrgather_vx_i8m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.nxv32i8.i32(<vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i8> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i8> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vrgather_vv_i8m4(vint8m4_t op1, vuint8m4_t index, size_t vl) {
				return vrgather_vv_i8m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.nxv32i8.i32(<vscale x 32 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vrgather_vx_i8m4(vint8m4_t op1, size_t index, size_t vl) {
				return vrgather_vx_i8m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.nxv64i8.i32(<vscale x 64 x i8> [[OP1:%.]], <vscale x 64 x i8> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.nxv64i8.i64(<vscale x 64 x i8> [[OP1:%.]], <vscale x 64 x i8> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vrgather_vv_i8m8(vint8m8_t op1, vuint8m8_t index, size_t vl) {
				return vrgather_vv_i8m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.nxv64i8.i32(<vscale x 64 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.nxv64i8.i64(<vscale x 64 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vrgather_vx_i8m8(vint8m8_t op1, size_t index, size_t vl) {
				return vrgather_vx_i8m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.nxv1i16.i32(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vrgather_vv_i16mf4(vint16mf4_t op1, vuint16mf4_t index,
				size_t vl) {
				return vrgather_vv_i16mf4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.nxv1i16.i32(<vscale x 1 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vrgather_vx_i16mf4(vint16mf4_t op1, size_t index, size_t vl) {
				return vrgather_vx_i16mf4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.nxv2i16.i32(<vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vrgather_vv_i16mf2(vint16mf2_t op1, vuint16mf2_t index,
				size_t vl) {
				return vrgather_vv_i16mf2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.nxv2i16.i32(<vscale x 2 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vrgather_vx_i16mf2(vint16mf2_t op1, size_t index, size_t vl) {
				return vrgather_vx_i16mf2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.nxv4i16.i32(<vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vrgather_vv_i16m1(vint16m1_t op1, vuint16m1_t index,
				size_t vl) {
				return vrgather_vv_i16m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.nxv4i16.i32(<vscale x 4 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vrgather_vx_i16m1(vint16m1_t op1, size_t index, size_t vl) {
				return vrgather_vx_i16m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.nxv8i16.i32(<vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vrgather_vv_i16m2(vint16m2_t op1, vuint16m2_t index,
				size_t vl) {
				return vrgather_vv_i16m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.nxv8i16.i32(<vscale x 8 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vrgather_vx_i16m2(vint16m2_t op1, size_t index, size_t vl) {
				return vrgather_vx_i16m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.nxv16i16.i32(<vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vrgather_vv_i16m4(vint16m4_t op1, vuint16m4_t index,
				size_t vl) {
				return vrgather_vv_i16m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.nxv16i16.i32(<vscale x 16 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vrgather_vx_i16m4(vint16m4_t op1, size_t index, size_t vl) {
				return vrgather_vx_i16m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.nxv32i16.i32(<vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.nxv32i16.i64(<vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vrgather_vv_i16m8(vint16m8_t op1, vuint16m8_t index,
				size_t vl) {
				return vrgather_vv_i16m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.nxv32i16.i32(<vscale x 32 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.nxv32i16.i64(<vscale x 32 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vrgather_vx_i16m8(vint16m8_t op1, size_t index, size_t vl) {
				return vrgather_vx_i16m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.nxv1i32.i32(<vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vrgather_vv_i32mf2(vint32mf2_t op1, vuint32mf2_t index,
				size_t vl) {
				return vrgather_vv_i32mf2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.nxv1i32.i32(<vscale x 1 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vrgather_vx_i32mf2(vint32mf2_t op1, size_t index, size_t vl) {
				return vrgather_vx_i32mf2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.nxv2i32.i32(<vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vrgather_vv_i32m1(vint32m1_t op1, vuint32m1_t index,
				size_t vl) {
				return vrgather_vv_i32m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.nxv2i32.i32(<vscale x 2 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vrgather_vx_i32m1(vint32m1_t op1, size_t index, size_t vl) {
				return vrgather_vx_i32m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.nxv4i32.i32(<vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vrgather_vv_i32m2(vint32m2_t op1, vuint32m2_t index,
				size_t vl) {
				return vrgather_vv_i32m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.i32(<vscale x 4 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vrgather_vx_i32m2(vint32m2_t op1, size_t index, size_t vl) {
				return vrgather_vx_i32m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.nxv8i32.i32(<vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vrgather_vv_i32m4(vint32m4_t op1, vuint32m4_t index,
				size_t vl) {
				return vrgather_vv_i32m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.nxv8i32.i32(<vscale x 8 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vrgather_vx_i32m4(vint32m4_t op1, size_t index, size_t vl) {
				return vrgather_vx_i32m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.nxv16i32.i32(<vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.nxv16i32.i64(<vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vrgather_vv_i32m8(vint32m8_t op1, vuint32m8_t index,
				size_t vl) {
				return vrgather_vv_i32m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.nxv16i32.i32(<vscale x 16 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.nxv16i32.i64(<vscale x 16 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vrgather_vx_i32m8(vint32m8_t op1, size_t index, size_t vl) {
				return vrgather_vx_i32m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.nxv1i64.i32(<vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.nxv1i64.i64(<vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vrgather_vv_i64m1(vint64m1_t op1, vuint64m1_t index,
				size_t vl) {
				return vrgather_vv_i64m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.nxv1i64.i32(<vscale x 1 x i64> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.nxv1i64.i64(<vscale x 1 x i64> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vrgather_vx_i64m1(vint64m1_t op1, size_t index, size_t vl) {
				return vrgather_vx_i64m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.nxv2i64.i32(<vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.nxv2i64.i64(<vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vrgather_vv_i64m2(vint64m2_t op1, vuint64m2_t index,
				size_t vl) {
				return vrgather_vv_i64m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.nxv2i64.i32(<vscale x 2 x i64> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.nxv2i64.i64(<vscale x 2 x i64> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vrgather_vx_i64m2(vint64m2_t op1, size_t index, size_t vl) {
				return vrgather_vx_i64m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.nxv4i64.i32(<vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.nxv4i64.i64(<vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vrgather_vv_i64m4(vint64m4_t op1, vuint64m4_t index,
				size_t vl) {
				return vrgather_vv_i64m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.nxv4i64.i32(<vscale x 4 x i64> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.nxv4i64.i64(<vscale x 4 x i64> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vrgather_vx_i64m4(vint64m4_t op1, size_t index, size_t vl) {
				return vrgather_vx_i64m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.nxv8i64.i32(<vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.nxv8i64.i64(<vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vrgather_vv_i64m8(vint64m8_t op1, vuint64m8_t index,
				size_t vl) {
				return vrgather_vv_i64m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.nxv8i64.i32(<vscale x 8 x i64> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.nxv8i64.i64(<vscale x 8 x i64> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vrgather_vx_i64m8(vint64m8_t op1, size_t index, size_t vl) {
				return vrgather_vx_i64m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.nxv1i8.i32(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vrgather_vv_u8mf8(vuint8mf8_t op1, vuint8mf8_t index,
				size_t vl) {
				return vrgather_vv_u8mf8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.nxv1i8.i32(<vscale x 1 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vrgather_vx_u8mf8(vuint8mf8_t op1, size_t index, size_t vl) {
				return vrgather_vx_u8mf8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.nxv2i8.i32(<vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i8> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i8> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vrgather_vv_u8mf4(vuint8mf4_t op1, vuint8mf4_t index,
				size_t vl) {
				return vrgather_vv_u8mf4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.nxv2i8.i32(<vscale x 2 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vrgather_vx_u8mf4(vuint8mf4_t op1, size_t index, size_t vl) {
				return vrgather_vx_u8mf4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.nxv4i8.i32(<vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i8> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i8> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vrgather_vv_u8mf2(vuint8mf2_t op1, vuint8mf2_t index,
				size_t vl) {
				return vrgather_vv_u8mf2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.nxv4i8.i32(<vscale x 4 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vrgather_vx_u8mf2(vuint8mf2_t op1, size_t index, size_t vl) {
				return vrgather_vx_u8mf2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.nxv8i8.i32(<vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i8> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i8> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vrgather_vv_u8m1(vuint8m1_t op1, vuint8m1_t index, size_t vl) {
				return vrgather_vv_u8m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.nxv8i8.i32(<vscale x 8 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vrgather_vx_u8m1(vuint8m1_t op1, size_t index, size_t vl) {
				return vrgather_vx_u8m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.nxv16i8.i32(<vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i8> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i8> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vrgather_vv_u8m2(vuint8m2_t op1, vuint8m2_t index, size_t vl) {
				return vrgather_vv_u8m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.nxv16i8.i32(<vscale x 16 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vrgather_vx_u8m2(vuint8m2_t op1, size_t index, size_t vl) {
				return vrgather_vx_u8m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.nxv32i8.i32(<vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i8> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i8> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vrgather_vv_u8m4(vuint8m4_t op1, vuint8m4_t index, size_t vl) {
				return vrgather_vv_u8m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.nxv32i8.i32(<vscale x 32 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vrgather_vx_u8m4(vuint8m4_t op1, size_t index, size_t vl) {
				return vrgather_vx_u8m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.nxv64i8.i32(<vscale x 64 x i8> [[OP1:%.]], <vscale x 64 x i8> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.nxv64i8.i64(<vscale x 64 x i8> [[OP1:%.]], <vscale x 64 x i8> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vrgather_vv_u8m8(vuint8m8_t op1, vuint8m8_t index, size_t vl) {
				return vrgather_vv_u8m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.nxv64i8.i32(<vscale x 64 x i8> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.nxv64i8.i64(<vscale x 64 x i8> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vrgather_vx_u8m8(vuint8m8_t op1, size_t index, size_t vl) {
				return vrgather_vx_u8m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.nxv1i16.i32(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vrgather_vv_u16mf4(vuint16mf4_t op1, vuint16mf4_t index,
				size_t vl) {
				return vrgather_vv_u16mf4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.nxv1i16.i32(<vscale x 1 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vrgather_vx_u16mf4(vuint16mf4_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_u16mf4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.nxv2i16.i32(<vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vrgather_vv_u16mf2(vuint16mf2_t op1, vuint16mf2_t index,
				size_t vl) {
				return vrgather_vv_u16mf2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.nxv2i16.i32(<vscale x 2 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vrgather_vx_u16mf2(vuint16mf2_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_u16mf2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.nxv4i16.i32(<vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vrgather_vv_u16m1(vuint16m1_t op1, vuint16m1_t index,
				size_t vl) {
				return vrgather_vv_u16m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.nxv4i16.i32(<vscale x 4 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vrgather_vx_u16m1(vuint16m1_t op1, size_t index, size_t vl) {
				return vrgather_vx_u16m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.nxv8i16.i32(<vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vrgather_vv_u16m2(vuint16m2_t op1, vuint16m2_t index,
				size_t vl) {
				return vrgather_vv_u16m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.nxv8i16.i32(<vscale x 8 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vrgather_vx_u16m2(vuint16m2_t op1, size_t index, size_t vl) {
				return vrgather_vx_u16m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.nxv16i16.i32(<vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vrgather_vv_u16m4(vuint16m4_t op1, vuint16m4_t index,
				size_t vl) {
				return vrgather_vv_u16m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.nxv16i16.i32(<vscale x 16 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vrgather_vx_u16m4(vuint16m4_t op1, size_t index, size_t vl) {
				return vrgather_vx_u16m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.nxv32i16.i32(<vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.nxv32i16.i64(<vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vrgather_vv_u16m8(vuint16m8_t op1, vuint16m8_t index,
				size_t vl) {
				return vrgather_vv_u16m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.nxv32i16.i32(<vscale x 32 x i16> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.nxv32i16.i64(<vscale x 32 x i16> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vrgather_vx_u16m8(vuint16m8_t op1, size_t index, size_t vl) {
				return vrgather_vx_u16m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.nxv1i32.i32(<vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vrgather_vv_u32mf2(vuint32mf2_t op1, vuint32mf2_t index,
				size_t vl) {
				return vrgather_vv_u32mf2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.nxv1i32.i32(<vscale x 1 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vrgather_vx_u32mf2(vuint32mf2_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_u32mf2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.nxv2i32.i32(<vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vrgather_vv_u32m1(vuint32m1_t op1, vuint32m1_t index,
				size_t vl) {
				return vrgather_vv_u32m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.nxv2i32.i32(<vscale x 2 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vrgather_vx_u32m1(vuint32m1_t op1, size_t index, size_t vl) {
				return vrgather_vx_u32m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.nxv4i32.i32(<vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vrgather_vv_u32m2(vuint32m2_t op1, vuint32m2_t index,
				size_t vl) {
				return vrgather_vv_u32m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.i32(<vscale x 4 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vrgather_vx_u32m2(vuint32m2_t op1, size_t index, size_t vl) {
				return vrgather_vx_u32m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.nxv8i32.i32(<vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vrgather_vv_u32m4(vuint32m4_t op1, vuint32m4_t index,
				size_t vl) {
				return vrgather_vv_u32m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.nxv8i32.i32(<vscale x 8 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vrgather_vx_u32m4(vuint32m4_t op1, size_t index, size_t vl) {
				return vrgather_vx_u32m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.nxv16i32.i32(<vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.nxv16i32.i64(<vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vrgather_vv_u32m8(vuint32m8_t op1, vuint32m8_t index,
				size_t vl) {
				return vrgather_vv_u32m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.nxv16i32.i32(<vscale x 16 x i32> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.nxv16i32.i64(<vscale x 16 x i32> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vrgather_vx_u32m8(vuint32m8_t op1, size_t index, size_t vl) {
				return vrgather_vx_u32m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.nxv1i64.i32(<vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.nxv1i64.i64(<vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vrgather_vv_u64m1(vuint64m1_t op1, vuint64m1_t index,
				size_t vl) {
				return vrgather_vv_u64m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.nxv1i64.i32(<vscale x 1 x i64> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.nxv1i64.i64(<vscale x 1 x i64> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vrgather_vx_u64m1(vuint64m1_t op1, size_t index, size_t vl) {
				return vrgather_vx_u64m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.nxv2i64.i32(<vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.nxv2i64.i64(<vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vrgather_vv_u64m2(vuint64m2_t op1, vuint64m2_t index,
				size_t vl) {
				return vrgather_vv_u64m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.nxv2i64.i32(<vscale x 2 x i64> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.nxv2i64.i64(<vscale x 2 x i64> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vrgather_vx_u64m2(vuint64m2_t op1, size_t index, size_t vl) {
				return vrgather_vx_u64m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.nxv4i64.i32(<vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.nxv4i64.i64(<vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vrgather_vv_u64m4(vuint64m4_t op1, vuint64m4_t index,
				size_t vl) {
				return vrgather_vv_u64m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.nxv4i64.i32(<vscale x 4 x i64> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.nxv4i64.i64(<vscale x 4 x i64> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vrgather_vx_u64m4(vuint64m4_t op1, size_t index, size_t vl) {
				return vrgather_vx_u64m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.nxv8i64.i32(<vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.nxv8i64.i64(<vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vrgather_vv_u64m8(vuint64m8_t op1, vuint64m8_t index,
				size_t vl) {
				return vrgather_vv_u64m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.nxv8i64.i32(<vscale x 8 x i64> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.nxv8i64.i64(<vscale x 8 x i64> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vrgather_vx_u64m8(vuint64m8_t op1, size_t index, size_t vl) {
				return vrgather_vx_u64m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgather.vv.nxv1f32.i32(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgather.vv.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vrgather_vv_f32mf2(vfloat32mf2_t op1, vuint32mf2_t index,
				size_t vl) {
				return vrgather_vv_f32mf2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.nxv1f32.i32(<vscale x 1 x float> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vrgather_vx_f32mf2(vfloat32mf2_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_f32mf2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgather.vv.nxv2f32.i32(<vscale x 2 x float> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgather.vv.nxv2f32.i64(<vscale x 2 x float> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vrgather_vv_f32m1(vfloat32m1_t op1, vuint32m1_t index,
				size_t vl) {
				return vrgather_vv_f32m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i32(<vscale x 2 x float> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i64(<vscale x 2 x float> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vrgather_vx_f32m1(vfloat32m1_t op1, size_t index, size_t vl) {
				return vrgather_vx_f32m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgather.vv.nxv4f32.i32(<vscale x 4 x float> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgather.vv.nxv4f32.i64(<vscale x 4 x float> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vrgather_vv_f32m2(vfloat32m2_t op1, vuint32m2_t index,
				size_t vl) {
				return vrgather_vv_f32m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.nxv4f32.i32(<vscale x 4 x float> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.nxv4f32.i64(<vscale x 4 x float> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vrgather_vx_f32m2(vfloat32m2_t op1, size_t index, size_t vl) {
				return vrgather_vx_f32m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgather.vv.nxv8f32.i32(<vscale x 8 x float> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgather.vv.nxv8f32.i64(<vscale x 8 x float> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vrgather_vv_f32m4(vfloat32m4_t op1, vuint32m4_t index,
				size_t vl) {
				return vrgather_vv_f32m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.nxv8f32.i32(<vscale x 8 x float> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.nxv8f32.i64(<vscale x 8 x float> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vrgather_vx_f32m4(vfloat32m4_t op1, size_t index, size_t vl) {
				return vrgather_vx_f32m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgather.vv.nxv16f32.i32(<vscale x 16 x float> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgather.vv.nxv16f32.i64(<vscale x 16 x float> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vrgather_vv_f32m8(vfloat32m8_t op1, vuint32m8_t index,
				size_t vl) {
				return vrgather_vv_f32m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgather.vx.nxv16f32.i32(<vscale x 16 x float> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgather.vx.nxv16f32.i64(<vscale x 16 x float> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vrgather_vx_f32m8(vfloat32m8_t op1, size_t index, size_t vl) {
				return vrgather_vx_f32m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgather.vv.nxv1f64.i32(<vscale x 1 x double> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgather.vv.nxv1f64.i64(<vscale x 1 x double> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vrgather_vv_f64m1(vfloat64m1_t op1, vuint64m1_t index,
				size_t vl) {
				return vrgather_vv_f64m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.nxv1f64.i32(<vscale x 1 x double> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.nxv1f64.i64(<vscale x 1 x double> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vrgather_vx_f64m1(vfloat64m1_t op1, size_t index, size_t vl) {
				return vrgather_vx_f64m1(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgather.vv.nxv2f64.i32(<vscale x 2 x double> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgather.vv.nxv2f64.i64(<vscale x 2 x double> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vrgather_vv_f64m2(vfloat64m2_t op1, vuint64m2_t index,
				size_t vl) {
				return vrgather_vv_f64m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.nxv2f64.i32(<vscale x 2 x double> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.nxv2f64.i64(<vscale x 2 x double> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vrgather_vx_f64m2(vfloat64m2_t op1, size_t index, size_t vl) {
				return vrgather_vx_f64m2(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgather.vv.nxv4f64.i32(<vscale x 4 x double> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgather.vv.nxv4f64.i64(<vscale x 4 x double> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vrgather_vv_f64m4(vfloat64m4_t op1, vuint64m4_t index,
				size_t vl) {
				return vrgather_vv_f64m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.nxv4f64.i32(<vscale x 4 x double> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.nxv4f64.i64(<vscale x 4 x double> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vrgather_vx_f64m4(vfloat64m4_t op1, size_t index, size_t vl) {
				return vrgather_vx_f64m4(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgather.vv.nxv8f64.i32(<vscale x 8 x double> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgather.vv.nxv8f64.i64(<vscale x 8 x double> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vrgather_vv_f64m8(vfloat64m8_t op1, vuint64m8_t index,
				size_t vl) {
				return vrgather_vv_f64m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgather.vx.nxv8f64.i32(<vscale x 8 x double> [[OP1:%.]], i32 [[INDEX:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgather.vx.nxv8f64.i64(<vscale x 8 x double> [[OP1:%.]], i64 [[INDEX:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vrgather_vx_f64m8(vfloat64m8_t op1, size_t index, size_t vl) {
				return vrgather_vx_f64m8(op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.nxv1i8.i32(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vrgatherei16_vv_i8mf8(vint8mf8_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_i8mf8(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.nxv2i8.i32(<vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vrgatherei16_vv_i8mf4(vint8mf4_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_i8mf4(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.nxv4i8.i32(<vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vrgatherei16_vv_i8mf2(vint8mf2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_i8mf2(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i32(<vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vrgatherei16_vv_i8m1(vint8m1_t op1, vuint16m2_t op2, size_t vl) {
				return vrgatherei16_vv_i8m1(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.nxv16i8.i32(<vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vrgatherei16_vv_i8m2(vint8m2_t op1, vuint16m4_t op2, size_t vl) {
				return vrgatherei16_vv_i8m2(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.nxv32i8.i32(<vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vrgatherei16_vv_i8m4(vint8m4_t op1, vuint16m8_t op2, size_t vl) {
				return vrgatherei16_vv_i8m4(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.nxv1i16.i32(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vrgatherei16_vv_i16mf4(vint16mf4_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_i16mf4(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.nxv2i16.i32(<vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vrgatherei16_vv_i16mf2(vint16mf2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_i16mf2(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.nxv4i16.i32(<vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vrgatherei16_vv_i16m1(vint16m1_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_i16m1(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.nxv8i16.i32(<vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vrgatherei16_vv_i16m2(vint16m2_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_i16m2(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.nxv16i16.i32(<vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vrgatherei16_vv_i16m4(vint16m4_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16_vv_i16m4(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.nxv32i16.i32(<vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.nxv32i16.i64(<vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vrgatherei16_vv_i16m8(vint16m8_t op1, vuint16m8_t op2,
				size_t vl) {
				return vrgatherei16_vv_i16m8(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.nxv1i32.i32(<vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vrgatherei16_vv_i32mf2(vint32mf2_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_i32mf2(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgatherei16.vv.nxv2i32.i32(<vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgatherei16.vv.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vrgatherei16_vv_i32m1(vint32m1_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_i32m1(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.nxv4i32.i32(<vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vrgatherei16_vv_i32m2(vint32m2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_i32m2(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.nxv8i32.i32(<vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vrgatherei16_vv_i32m4(vint32m4_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_i32m4(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.nxv16i32.i32(<vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.nxv16i32.i64(<vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vrgatherei16_vv_i32m8(vint32m8_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16_vv_i32m8(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgatherei16.vv.nxv1i64.i32(<vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgatherei16.vv.nxv1i64.i64(<vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vrgatherei16_vv_i64m1(vint64m1_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_i64m1(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgatherei16.vv.nxv2i64.i32(<vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgatherei16.vv.nxv2i64.i64(<vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vrgatherei16_vv_i64m2(vint64m2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_i64m2(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.nxv4i64.i32(<vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.nxv4i64.i64(<vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vrgatherei16_vv_i64m4(vint64m4_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_i64m4(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.nxv8i64.i32(<vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.nxv8i64.i64(<vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vrgatherei16_vv_i64m8(vint64m8_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_i64m8(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.nxv1i8.i32(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vrgatherei16_vv_u8mf8(vuint8mf8_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_u8mf8(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.nxv2i8.i32(<vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vrgatherei16_vv_u8mf4(vuint8mf4_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_u8mf4(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.nxv4i8.i32(<vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vrgatherei16_vv_u8mf2(vuint8mf2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_u8mf2(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i32(<vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vrgatherei16_vv_u8m1(vuint8m1_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_u8m1(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.nxv16i8.i32(<vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vrgatherei16_vv_u8m2(vuint8m2_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16_vv_u8m2(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.nxv32i8.i32(<vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vrgatherei16_vv_u8m4(vuint8m4_t op1, vuint16m8_t op2,
				size_t vl) {
				return vrgatherei16_vv_u8m4(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.nxv1i16.i32(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vrgatherei16_vv_u16mf4(vuint16mf4_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_u16mf4(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.nxv2i16.i32(<vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vrgatherei16_vv_u16mf2(vuint16mf2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_u16mf2(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.nxv4i16.i32(<vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vrgatherei16_vv_u16m1(vuint16m1_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_u16m1(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.nxv8i16.i32(<vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vrgatherei16_vv_u16m2(vuint16m2_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_u16m2(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.nxv16i16.i32(<vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vrgatherei16_vv_u16m4(vuint16m4_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16_vv_u16m4(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.nxv32i16.i32(<vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.nxv32i16.i64(<vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vrgatherei16_vv_u16m8(vuint16m8_t op1, vuint16m8_t op2,
				size_t vl) {
				return vrgatherei16_vv_u16m8(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.nxv1i32.i32(<vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vrgatherei16_vv_u32mf2(vuint32mf2_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_u32mf2(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgatherei16.vv.nxv2i32.i32(<vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgatherei16.vv.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vrgatherei16_vv_u32m1(vuint32m1_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_u32m1(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.nxv4i32.i32(<vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vrgatherei16_vv_u32m2(vuint32m2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_u32m2(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.nxv8i32.i32(<vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vrgatherei16_vv_u32m4(vuint32m4_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_u32m4(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.nxv16i32.i32(<vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.nxv16i32.i64(<vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vrgatherei16_vv_u32m8(vuint32m8_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16_vv_u32m8(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgatherei16.vv.nxv1i64.i32(<vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgatherei16.vv.nxv1i64.i64(<vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vrgatherei16_vv_u64m1(vuint64m1_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_u64m1(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgatherei16.vv.nxv2i64.i32(<vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgatherei16.vv.nxv2i64.i64(<vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vrgatherei16_vv_u64m2(vuint64m2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_u64m2(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.nxv4i64.i32(<vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.nxv4i64.i64(<vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vrgatherei16_vv_u64m4(vuint64m4_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_u64m4(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.nxv8i64.i32(<vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.nxv8i64.i64(<vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vrgatherei16_vv_u64m8(vuint64m8_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_u64m8(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i32(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vrgatherei16_vv_f32mf2(vfloat32mf2_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_f32mf2(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i32(<vscale x 2 x float> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vrgatherei16_vv_f32m1(vfloat32m1_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_f32m1(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i32(<vscale x 4 x float> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vrgatherei16_vv_f32m2(vfloat32m2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_f32m2(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.nxv8f32.i32(<vscale x 8 x float> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.nxv8f32.i64(<vscale x 8 x float> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vrgatherei16_vv_f32m4(vfloat32m4_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_f32m4(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.nxv16f32.i32(<vscale x 16 x float> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.nxv16f32.i64(<vscale x 16 x float> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vrgatherei16_vv_f32m8(vfloat32m8_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16_vv_f32m8(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgatherei16.vv.nxv1f64.i32(<vscale x 1 x double> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgatherei16.vv.nxv1f64.i64(<vscale x 1 x double> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vrgatherei16_vv_f64m1(vfloat64m1_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_f64m1(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgatherei16.vv.nxv2f64.i32(<vscale x 2 x double> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgatherei16.vv.nxv2f64.i64(<vscale x 2 x double> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vrgatherei16_vv_f64m2(vfloat64m2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_f64m2(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.nxv4f64.i32(<vscale x 4 x double> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.nxv4f64.i64(<vscale x 4 x double> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vrgatherei16_vv_f64m4(vfloat64m4_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_f64m4(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.nxv8f64.i32(<vscale x 8 x double> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.nxv8f64.i64(<vscale x 8 x double> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vrgatherei16_vv_f64m8(vfloat64m8_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_f64m8(op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vrgather_vv_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff,
				vint8mf8_t op1, vuint8mf8_t index,
				size_t vl) {
				return vrgather_vv_i8mf8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vrgather_vx_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff,
				vint8mf8_t op1, size_t index, size_t vl) {
				return vrgather_vx_i8mf8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.mask.nxv2i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i8> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i8> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vrgather_vv_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff,
				vint8mf4_t op1, vuint8mf4_t index,
				size_t vl) {
				return vrgather_vv_i8mf4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.mask.nxv2i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vrgather_vx_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff,
				vint8mf4_t op1, size_t index, size_t vl) {
				return vrgather_vx_i8mf4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.mask.nxv4i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i8> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i8> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vrgather_vv_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff,
				vint8mf2_t op1, vuint8mf2_t index,
				size_t vl) {
				return vrgather_vv_i8mf2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.mask.nxv4i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vrgather_vx_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff,
				vint8mf2_t op1, size_t index, size_t vl) {
				return vrgather_vx_i8mf2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.mask.nxv8i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i8> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i8> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vrgather_vv_i8m1_m(vbool8_t mask, vint8m1_t maskedoff,
				vint8m1_t op1, vuint8m1_t index, size_t vl) {
				return vrgather_vv_i8m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.mask.nxv8i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vrgather_vx_i8m1_m(vbool8_t mask, vint8m1_t maskedoff,
				vint8m1_t op1, size_t index, size_t vl) {
				return vrgather_vx_i8m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.mask.nxv16i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i8> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i8> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vrgather_vv_i8m2_m(vbool4_t mask, vint8m2_t maskedoff,
				vint8m2_t op1, vuint8m2_t index, size_t vl) {
				return vrgather_vv_i8m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.mask.nxv16i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vrgather_vx_i8m2_m(vbool4_t mask, vint8m2_t maskedoff,
				vint8m2_t op1, size_t index, size_t vl) {
				return vrgather_vx_i8m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.mask.nxv32i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i8> [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i8> [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vrgather_vv_i8m4_m(vbool2_t mask, vint8m4_t maskedoff,
				vint8m4_t op1, vuint8m4_t index, size_t vl) {
				return vrgather_vv_i8m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.mask.nxv32i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vrgather_vx_i8m4_m(vbool2_t mask, vint8m4_t maskedoff,
				vint8m4_t op1, size_t index, size_t vl) {
				return vrgather_vx_i8m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.mask.nxv64i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[OP1:%.]], <vscale x 64 x i8> [[INDEX:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[OP1:%.]], <vscale x 64 x i8> [[INDEX:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vrgather_vv_i8m8_m(vbool1_t mask, vint8m8_t maskedoff,
				vint8m8_t op1, vuint8m8_t index, size_t vl) {
				return vrgather_vv_i8m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.mask.nxv64i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vrgather_vx_i8m8_m(vbool1_t mask, vint8m8_t maskedoff,
				vint8m8_t op1, size_t index, size_t vl) {
				return vrgather_vx_i8m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.mask.nxv1i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vrgather_vv_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff,
				vint16mf4_t op1, vuint16mf4_t index,
				size_t vl) {
				return vrgather_vv_i16mf4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.mask.nxv1i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vrgather_vx_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff,
				vint16mf4_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_i16mf4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.mask.nxv2i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vrgather_vv_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff,
				vint16mf2_t op1, vuint16mf2_t index,
				size_t vl) {
				return vrgather_vv_i16mf2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.mask.nxv2i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vrgather_vx_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff,
				vint16mf2_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_i16mf2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.mask.nxv4i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vrgather_vv_i16m1_m(vbool16_t mask, vint16m1_t maskedoff,
				vint16m1_t op1, vuint16m1_t index,
				size_t vl) {
				return vrgather_vv_i16m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.mask.nxv4i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vrgather_vx_i16m1_m(vbool16_t mask, vint16m1_t maskedoff,
				vint16m1_t op1, size_t index, size_t vl) {
				return vrgather_vx_i16m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.mask.nxv8i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vrgather_vv_i16m2_m(vbool8_t mask, vint16m2_t maskedoff,
				vint16m2_t op1, vuint16m2_t index,
				size_t vl) {
				return vrgather_vv_i16m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.mask.nxv8i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vrgather_vx_i16m2_m(vbool8_t mask, vint16m2_t maskedoff,
				vint16m2_t op1, size_t index, size_t vl) {
				return vrgather_vx_i16m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.mask.nxv16i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vrgather_vv_i16m4_m(vbool4_t mask, vint16m4_t maskedoff,
				vint16m4_t op1, vuint16m4_t index,
				size_t vl) {
				return vrgather_vv_i16m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.mask.nxv16i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vrgather_vx_i16m4_m(vbool4_t mask, vint16m4_t maskedoff,
				vint16m4_t op1, size_t index, size_t vl) {
				return vrgather_vx_i16m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.mask.nxv32i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vrgather_vv_i16m8_m(vbool2_t mask, vint16m8_t maskedoff,
				vint16m8_t op1, vuint16m8_t index,
				size_t vl) {
				return vrgather_vv_i16m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.mask.nxv32i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vrgather_vx_i16m8_m(vbool2_t mask, vint16m8_t maskedoff,
				vint16m8_t op1, size_t index, size_t vl) {
				return vrgather_vx_i16m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.mask.nxv1i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vrgather_vv_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff,
				vint32mf2_t op1, vuint32mf2_t index,
				size_t vl) {
				return vrgather_vv_i32mf2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.mask.nxv1i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vrgather_vx_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff,
				vint32mf2_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_i32mf2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.mask.nxv2i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vrgather_vv_i32m1_m(vbool32_t mask, vint32m1_t maskedoff,
				vint32m1_t op1, vuint32m1_t index,
				size_t vl) {
				return vrgather_vv_i32m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.mask.nxv2i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vrgather_vx_i32m1_m(vbool32_t mask, vint32m1_t maskedoff,
				vint32m1_t op1, size_t index, size_t vl) {
				return vrgather_vx_i32m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.mask.nxv4i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vrgather_vv_i32m2_m(vbool16_t mask, vint32m2_t maskedoff,
				vint32m2_t op1, vuint32m2_t index,
				size_t vl) {
				return vrgather_vv_i32m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.mask.nxv4i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vrgather_vx_i32m2_m(vbool16_t mask, vint32m2_t maskedoff,
				vint32m2_t op1, size_t index, size_t vl) {
				return vrgather_vx_i32m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.mask.nxv8i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vrgather_vv_i32m4_m(vbool8_t mask, vint32m4_t maskedoff,
				vint32m4_t op1, vuint32m4_t index,
				size_t vl) {
				return vrgather_vv_i32m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.mask.nxv8i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vrgather_vx_i32m4_m(vbool8_t mask, vint32m4_t maskedoff,
				vint32m4_t op1, size_t index, size_t vl) {
				return vrgather_vx_i32m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.mask.nxv16i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vrgather_vv_i32m8_m(vbool4_t mask, vint32m8_t maskedoff,
				vint32m8_t op1, vuint32m8_t index,
				size_t vl) {
				return vrgather_vv_i32m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.mask.nxv16i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vrgather_vx_i32m8_m(vbool4_t mask, vint32m8_t maskedoff,
				vint32m8_t op1, size_t index, size_t vl) {
				return vrgather_vx_i32m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.mask.nxv1i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vrgather_vv_i64m1_m(vbool64_t mask, vint64m1_t maskedoff,
				vint64m1_t op1, vuint64m1_t index,
				size_t vl) {
				return vrgather_vv_i64m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.mask.nxv1i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vrgather_vx_i64m1_m(vbool64_t mask, vint64m1_t maskedoff,
				vint64m1_t op1, size_t index, size_t vl) {
				return vrgather_vx_i64m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.mask.nxv2i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vrgather_vv_i64m2_m(vbool32_t mask, vint64m2_t maskedoff,
				vint64m2_t op1, vuint64m2_t index,
				size_t vl) {
				return vrgather_vv_i64m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.mask.nxv2i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vrgather_vx_i64m2_m(vbool32_t mask, vint64m2_t maskedoff,
				vint64m2_t op1, size_t index, size_t vl) {
				return vrgather_vx_i64m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.mask.nxv4i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vrgather_vv_i64m4_m(vbool16_t mask, vint64m4_t maskedoff,
				vint64m4_t op1, vuint64m4_t index,
				size_t vl) {
				return vrgather_vv_i64m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.mask.nxv4i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vrgather_vx_i64m4_m(vbool16_t mask, vint64m4_t maskedoff,
				vint64m4_t op1, size_t index, size_t vl) {
				return vrgather_vx_i64m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_i64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.mask.nxv8i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_i64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vrgather_vv_i64m8_m(vbool8_t mask, vint64m8_t maskedoff,
				vint64m8_t op1, vuint64m8_t index,
				size_t vl) {
				return vrgather_vv_i64m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_i64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.mask.nxv8i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_i64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vrgather_vx_i64m8_m(vbool8_t mask, vint64m8_t maskedoff,
				vint64m8_t op1, size_t index, size_t vl) {
				return vrgather_vx_i64m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i8> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vrgather_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff,
				vuint8mf8_t op1, vuint8mf8_t index,
				size_t vl) {
				return vrgather_vv_u8mf8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vrgather_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff,
				vuint8mf8_t op1, size_t index, size_t vl) {
				return vrgather_vx_u8mf8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.mask.nxv2i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i8> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i8> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vrgather_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff,
				vuint8mf4_t op1, vuint8mf4_t index,
				size_t vl) {
				return vrgather_vv_u8mf4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.mask.nxv2i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vrgather_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff,
				vuint8mf4_t op1, size_t index, size_t vl) {
				return vrgather_vx_u8mf4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.mask.nxv4i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i8> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i8> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vrgather_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff,
				vuint8mf2_t op1, vuint8mf2_t index,
				size_t vl) {
				return vrgather_vv_u8mf2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.mask.nxv4i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vrgather_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff,
				vuint8mf2_t op1, size_t index, size_t vl) {
				return vrgather_vx_u8mf2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.mask.nxv8i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i8> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i8> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vrgather_vv_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff,
				vuint8m1_t op1, vuint8m1_t index,
				size_t vl) {
				return vrgather_vv_u8m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.mask.nxv8i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vrgather_vx_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff,
				vuint8m1_t op1, size_t index, size_t vl) {
				return vrgather_vx_u8m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.mask.nxv16i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i8> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i8> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vrgather_vv_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff,
				vuint8m2_t op1, vuint8m2_t index,
				size_t vl) {
				return vrgather_vv_u8m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.mask.nxv16i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vrgather_vx_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff,
				vuint8m2_t op1, size_t index, size_t vl) {
				return vrgather_vx_u8m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.mask.nxv32i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i8> [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i8> [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vrgather_vv_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff,
				vuint8m4_t op1, vuint8m4_t index,
				size_t vl) {
				return vrgather_vv_u8m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.mask.nxv32i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vrgather_vx_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff,
				vuint8m4_t op1, size_t index, size_t vl) {
				return vrgather_vx_u8m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.mask.nxv64i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[OP1:%.]], <vscale x 64 x i8> [[INDEX:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[OP1:%.]], <vscale x 64 x i8> [[INDEX:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vrgather_vv_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff,
				vuint8m8_t op1, vuint8m8_t index,
				size_t vl) {
				return vrgather_vv_u8m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.mask.nxv64i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.mask.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vrgather_vx_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff,
				vuint8m8_t op1, size_t index, size_t vl) {
				return vrgather_vx_u8m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.mask.nxv1i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vrgather_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff,
				vuint16mf4_t op1, vuint16mf4_t index,
				size_t vl) {
				return vrgather_vv_u16mf4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.mask.nxv1i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vrgather_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff,
				vuint16mf4_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_u16mf4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.mask.nxv2i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vrgather_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff,
				vuint16mf2_t op1, vuint16mf2_t index,
				size_t vl) {
				return vrgather_vv_u16mf2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.mask.nxv2i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vrgather_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff,
				vuint16mf2_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_u16mf2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.mask.nxv4i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vrgather_vv_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff,
				vuint16m1_t op1, vuint16m1_t index,
				size_t vl) {
				return vrgather_vv_u16m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.mask.nxv4i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vrgather_vx_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff,
				vuint16m1_t op1, size_t index, size_t vl) {
				return vrgather_vx_u16m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.mask.nxv8i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vrgather_vv_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff,
				vuint16m2_t op1, vuint16m2_t index,
				size_t vl) {
				return vrgather_vv_u16m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.mask.nxv8i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vrgather_vx_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff,
				vuint16m2_t op1, size_t index, size_t vl) {
				return vrgather_vx_u16m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.mask.nxv16i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vrgather_vv_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff,
				vuint16m4_t op1, vuint16m4_t index,
				size_t vl) {
				return vrgather_vv_u16m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.mask.nxv16i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vrgather_vx_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff,
				vuint16m4_t op1, size_t index, size_t vl) {
				return vrgather_vx_u16m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.mask.nxv32i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vrgather_vv_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff,
				vuint16m8_t op1, vuint16m8_t index,
				size_t vl) {
				return vrgather_vv_u16m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.mask.nxv32i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vrgather_vx_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff,
				vuint16m8_t op1, size_t index, size_t vl) {
				return vrgather_vx_u16m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.mask.nxv1i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vrgather_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff,
				vuint32mf2_t op1, vuint32mf2_t index,
				size_t vl) {
				return vrgather_vv_u32mf2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.mask.nxv1i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vrgather_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff,
				vuint32mf2_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_u32mf2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.mask.nxv2i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vrgather_vv_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff,
				vuint32m1_t op1, vuint32m1_t index,
				size_t vl) {
				return vrgather_vv_u32m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.mask.nxv2i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vrgather_vx_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff,
				vuint32m1_t op1, size_t index, size_t vl) {
				return vrgather_vx_u32m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.mask.nxv4i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vrgather_vv_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff,
				vuint32m2_t op1, vuint32m2_t index,
				size_t vl) {
				return vrgather_vv_u32m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.mask.nxv4i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vrgather_vx_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff,
				vuint32m2_t op1, size_t index, size_t vl) {
				return vrgather_vx_u32m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.mask.nxv8i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vrgather_vv_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff,
				vuint32m4_t op1, vuint32m4_t index,
				size_t vl) {
				return vrgather_vv_u32m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.mask.nxv8i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vrgather_vx_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff,
				vuint32m4_t op1, size_t index, size_t vl) {
				return vrgather_vx_u32m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.mask.nxv16i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vrgather_vv_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff,
				vuint32m8_t op1, vuint32m8_t index,
				size_t vl) {
				return vrgather_vv_u32m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.mask.nxv16i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vrgather_vx_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff,
				vuint32m8_t op1, size_t index, size_t vl) {
				return vrgather_vx_u32m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.mask.nxv1i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vrgather_vv_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff,
				vuint64m1_t op1, vuint64m1_t index,
				size_t vl) {
				return vrgather_vv_u64m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.mask.nxv1i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vrgather_vx_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff,
				vuint64m1_t op1, size_t index, size_t vl) {
				return vrgather_vx_u64m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.mask.nxv2i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vrgather_vv_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff,
				vuint64m2_t op1, vuint64m2_t index,
				size_t vl) {
				return vrgather_vv_u64m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.mask.nxv2i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vrgather_vx_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff,
				vuint64m2_t op1, size_t index, size_t vl) {
				return vrgather_vx_u64m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.mask.nxv4i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vrgather_vv_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff,
				vuint64m4_t op1, vuint64m4_t index,
				size_t vl) {
				return vrgather_vv_u64m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.mask.nxv4i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vrgather_vx_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff,
				vuint64m4_t op1, size_t index, size_t vl) {
				return vrgather_vx_u64m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_u64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.mask.nxv8i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_u64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vrgather_vv_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff,
				vuint64m8_t op1, vuint64m8_t index,
				size_t vl) {
				return vrgather_vv_u64m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_u64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.mask.nxv8i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_u64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vrgather_vx_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff,
				vuint64m8_t op1, size_t index, size_t vl) {
				return vrgather_vx_u64m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgather.vv.mask.nxv1f32.i32(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgather.vv.mask.nxv1f32.i64(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x i32> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vrgather_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t maskedoff,
				vfloat32mf2_t op1, vuint32mf2_t index,
				size_t vl) {
				return vrgather_vv_f32mf2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.mask.nxv1f32.i32(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.mask.nxv1f32.i64(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vrgather_vx_f32mf2_m(vbool64_t mask, vfloat32mf2_t maskedoff,
				vfloat32mf2_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_f32mf2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgather.vv.mask.nxv2f32.i32(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgather.vv.mask.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[OP1:%.]], <vscale x 2 x i32> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vrgather_vv_f32m1_m(vbool32_t mask, vfloat32m1_t maskedoff,
				vfloat32m1_t op1, vuint32m1_t index,
				size_t vl) {
				return vrgather_vv_f32m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.mask.nxv2f32.i32(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.mask.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vrgather_vx_f32m1_m(vbool32_t mask, vfloat32m1_t maskedoff,
				vfloat32m1_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_f32m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgather.vv.mask.nxv4f32.i32(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgather.vv.mask.nxv4f32.i64(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[OP1:%.]], <vscale x 4 x i32> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vrgather_vv_f32m2_m(vbool16_t mask, vfloat32m2_t maskedoff,
				vfloat32m2_t op1, vuint32m2_t index,
				size_t vl) {
				return vrgather_vv_f32m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.mask.nxv4f32.i32(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.mask.nxv4f32.i64(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vrgather_vx_f32m2_m(vbool16_t mask, vfloat32m2_t maskedoff,
				vfloat32m2_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_f32m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgather.vv.mask.nxv8f32.i32(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgather.vv.mask.nxv8f32.i64(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[OP1:%.]], <vscale x 8 x i32> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vrgather_vv_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff,
				vfloat32m4_t op1, vuint32m4_t index,
				size_t vl) {
				return vrgather_vv_f32m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.mask.nxv8f32.i32(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.mask.nxv8f32.i64(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vrgather_vx_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff,
				vfloat32m4_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_f32m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgather.vv.mask.nxv16f32.i32(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgather.vv.mask.nxv16f32.i64(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[OP1:%.]], <vscale x 16 x i32> [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vrgather_vv_f32m8_m(vbool4_t mask, vfloat32m8_t maskedoff,
				vfloat32m8_t op1, vuint32m8_t index,
				size_t vl) {
				return vrgather_vv_f32m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgather.vx.mask.nxv16f32.i32(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgather.vx.mask.nxv16f32.i64(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vrgather_vx_f32m8_m(vbool4_t mask, vfloat32m8_t maskedoff,
				vfloat32m8_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_f32m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgather.vv.mask.nxv1f64.i32(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgather.vv.mask.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[OP1:%.]], <vscale x 1 x i64> [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vrgather_vv_f64m1_m(vbool64_t mask, vfloat64m1_t maskedoff,
				vfloat64m1_t op1, vuint64m1_t index,
				size_t vl) {
				return vrgather_vv_f64m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.mask.nxv1f64.i32(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.mask.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vrgather_vx_f64m1_m(vbool64_t mask, vfloat64m1_t maskedoff,
				vfloat64m1_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_f64m1_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgather.vv.mask.nxv2f64.i32(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgather.vv.mask.nxv2f64.i64(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[OP1:%.]], <vscale x 2 x i64> [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vrgather_vv_f64m2_m(vbool32_t mask, vfloat64m2_t maskedoff,
				vfloat64m2_t op1, vuint64m2_t index,
				size_t vl) {
				return vrgather_vv_f64m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.mask.nxv2f64.i32(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.mask.nxv2f64.i64(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vrgather_vx_f64m2_m(vbool32_t mask, vfloat64m2_t maskedoff,
				vfloat64m2_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_f64m2_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgather.vv.mask.nxv4f64.i32(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgather.vv.mask.nxv4f64.i64(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[OP1:%.]], <vscale x 4 x i64> [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vrgather_vv_f64m4_m(vbool16_t mask, vfloat64m4_t maskedoff,
				vfloat64m4_t op1, vuint64m4_t index,
				size_t vl) {
				return vrgather_vv_f64m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.mask.nxv4f64.i32(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.mask.nxv4f64.i64(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vrgather_vx_f64m4_m(vbool16_t mask, vfloat64m4_t maskedoff,
				vfloat64m4_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_f64m4_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vv_f64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgather.vv.mask.nxv8f64.i32(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vv_f64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgather.vv.mask.nxv8f64.i64(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], <vscale x 8 x i64> [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vrgather_vv_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
				vfloat64m8_t op1, vuint64m8_t index,
				size_t vl) {
				return vrgather_vv_f64m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgather_vx_f64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgather.vx.mask.nxv8f64.i32(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], i32 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgather_vx_f64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgather.vx.mask.nxv8f64.i64(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], i64 [[INDEX:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vrgather_vx_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
				vfloat64m8_t op1, size_t index,
				size_t vl) {
				return vrgather_vx_f64m8_m(mask, maskedoff, op1, index, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vrgatherei16_vv_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff,
				vint8mf8_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_i8mf8_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv2i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vrgatherei16_vv_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff,
				vint8mf4_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_i8mf4_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv4i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vrgatherei16_vv_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff,
				vint8mf2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_i8mf2_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv8i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vrgatherei16_vv_i8m1_m(vbool8_t mask, vint8m1_t maskedoff,
				vint8m1_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_i8m1_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv16i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vrgatherei16_vv_i8m2_m(vbool4_t mask, vint8m2_t maskedoff,
				vint8m2_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16_vv_i8m2_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv32i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vrgatherei16_vv_i8m4_m(vbool2_t mask, vint8m4_t maskedoff,
				vint8m4_t op1, vuint16m8_t op2,
				size_t vl) {
				return vrgatherei16_vv_i8m4_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv1i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vrgatherei16_vv_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff,
				vint16mf4_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_i16mf4_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv2i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vrgatherei16_vv_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff,
				vint16mf2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_i16mf2_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv4i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vrgatherei16_vv_i16m1_m(vbool16_t mask, vint16m1_t maskedoff,
				vint16m1_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_i16m1_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv8i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vrgatherei16_vv_i16m2_m(vbool8_t mask, vint16m2_t maskedoff,
				vint16m2_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_i16m2_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv16i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vrgatherei16_vv_i16m4_m(vbool4_t mask, vint16m4_t maskedoff,
				vint16m4_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16_vv_i16m4_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv32i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vrgatherei16_vv_i16m8_m(vbool2_t mask, vint16m8_t maskedoff,
				vint16m8_t op1, vuint16m8_t op2,
				size_t vl) {
				return vrgatherei16_vv_i16m8_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv1i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vrgatherei16_vv_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff,
				vint32mf2_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_i32mf2_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv2i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vrgatherei16_vv_i32m1_m(vbool32_t mask, vint32m1_t maskedoff,
				vint32m1_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_i32m1_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv4i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vrgatherei16_vv_i32m2_m(vbool16_t mask, vint32m2_t maskedoff,
				vint32m2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_i32m2_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv8i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vrgatherei16_vv_i32m4_m(vbool8_t mask, vint32m4_t maskedoff,
				vint32m4_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_i32m4_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv16i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vrgatherei16_vv_i32m8_m(vbool4_t mask, vint32m8_t maskedoff,
				vint32m8_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16_vv_i32m8_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv1i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vrgatherei16_vv_i64m1_m(vbool64_t mask, vint64m1_t maskedoff,
				vint64m1_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_i64m1_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv2i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vrgatherei16_vv_i64m2_m(vbool32_t mask, vint64m2_t maskedoff,
				vint64m2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_i64m2_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv4i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vrgatherei16_vv_i64m4_m(vbool16_t mask, vint64m4_t maskedoff,
				vint64m4_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_i64m4_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_i64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv8i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_i64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vrgatherei16_vv_i64m8_m(vbool8_t mask, vint64m8_t maskedoff,
				vint64m8_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_i64m8_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vrgatherei16_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff,
				vuint8mf8_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_u8mf8_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv2i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vrgatherei16_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff,
				vuint8mf4_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_u8mf4_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv4i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vrgatherei16_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff,
				vuint8mf2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_u8mf2_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv8i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vrgatherei16_vv_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff,
				vuint8m1_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_u8m1_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv16i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vrgatherei16_vv_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff,
				vuint8m2_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16_vv_u8m2_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv32i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vrgatherei16_vv_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff,
				vuint8m4_t op1, vuint16m8_t op2,
				size_t vl) {
				return vrgatherei16_vv_u8m4_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv1i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vrgatherei16_vv_u16mf4_m(vbool64_t mask,
				vuint16mf4_t maskedoff,
				vuint16mf4_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_u16mf4_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv2i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vrgatherei16_vv_u16mf2_m(vbool32_t mask,
				vuint16mf2_t maskedoff,
				vuint16mf2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_u16mf2_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv4i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vrgatherei16_vv_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff,
				vuint16m1_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_u16m1_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv8i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vrgatherei16_vv_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff,
				vuint16m2_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_u16m2_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv16i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vrgatherei16_vv_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff,
				vuint16m4_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16_vv_u16m4_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv32i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[OP1:%.]], <vscale x 32 x i16> [[OP2:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vrgatherei16_vv_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff,
				vuint16m8_t op1, vuint16m8_t op2,
				size_t vl) {
				return vrgatherei16_vv_u16m8_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv1i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vrgatherei16_vv_u32mf2_m(vbool64_t mask,
				vuint32mf2_t maskedoff,
				vuint32mf2_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_u32mf2_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv2i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vrgatherei16_vv_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff,
				vuint32m1_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_u32m1_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv4i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vrgatherei16_vv_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff,
				vuint32m2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_u32m2_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv8i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vrgatherei16_vv_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff,
				vuint32m4_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_u32m4_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv16i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vrgatherei16_vv_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff,
				vuint32m8_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16_vv_u32m8_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv1i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vrgatherei16_vv_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff,
				vuint64m1_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_u64m1_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv2i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vrgatherei16_vv_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff,
				vuint64m2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_u64m2_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv4i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vrgatherei16_vv_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff,
				vuint64m4_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_u64m4_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_u64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv8i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_u64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vrgatherei16_vv_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff,
				vuint64m8_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_u64m8_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv1f32.i32(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv1f32.i64(<vscale x 1 x float> [[MASKEDOFF:%.]], <vscale x 1 x float> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vrgatherei16_vv_f32mf2_m(vbool64_t mask,
				vfloat32mf2_t maskedoff,
				vfloat32mf2_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_f32mf2_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv2f32.i32(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF:%.]], <vscale x 2 x float> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vrgatherei16_vv_f32m1_m(vbool32_t mask,
				vfloat32m1_t maskedoff,
				vfloat32m1_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_f32m1_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv4f32.i32(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv4f32.i64(<vscale x 4 x float> [[MASKEDOFF:%.]], <vscale x 4 x float> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vrgatherei16_vv_f32m2_m(vbool16_t mask,
				vfloat32m2_t maskedoff,
				vfloat32m2_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_f32m2_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv8f32.i32(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv8f32.i64(<vscale x 8 x float> [[MASKEDOFF:%.]], <vscale x 8 x float> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vrgatherei16_vv_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff,
				vfloat32m4_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_f32m4_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv16f32.i32(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv16f32.i64(<vscale x 16 x float> [[MASKEDOFF:%.]], <vscale x 16 x float> [[OP1:%.]], <vscale x 16 x i16> [[OP2:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vrgatherei16_vv_f32m8_m(vbool4_t mask, vfloat32m8_t maskedoff,
				vfloat32m8_t op1, vuint16m4_t op2,
				size_t vl) {
				return vrgatherei16_vv_f32m8_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv1f64.i32(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF:%.]], <vscale x 1 x double> [[OP1:%.]], <vscale x 1 x i16> [[OP2:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vrgatherei16_vv_f64m1_m(vbool64_t mask,
				vfloat64m1_t maskedoff,
				vfloat64m1_t op1, vuint16mf4_t op2,
				size_t vl) {
				return vrgatherei16_vv_f64m1_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv2f64.i32(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv2f64.i64(<vscale x 2 x double> [[MASKEDOFF:%.]], <vscale x 2 x double> [[OP1:%.]], <vscale x 2 x i16> [[OP2:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vrgatherei16_vv_f64m2_m(vbool32_t mask,
				vfloat64m2_t maskedoff,
				vfloat64m2_t op1, vuint16mf2_t op2,
				size_t vl) {
				return vrgatherei16_vv_f64m2_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv4f64.i32(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv4f64.i64(<vscale x 4 x double> [[MASKEDOFF:%.]], <vscale x 4 x double> [[OP1:%.]], <vscale x 4 x i16> [[OP2:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vrgatherei16_vv_f64m4_m(vbool16_t mask,
				vfloat64m4_t maskedoff,
				vfloat64m4_t op1, vuint16m1_t op2,
				size_t vl) {
				return vrgatherei16_vv_f64m4_m(mask, maskedoff, op1, op2, vl);
				}

				// CHECK-RV32-LABEL: @test_vrgatherei16_vv_f64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv8f64.i32(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vrgatherei16_vv_f64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv8f64.i64(<vscale x 8 x double> [[MASKEDOFF:%.]], <vscale x 8 x double> [[OP1:%.]], <vscale x 8 x i16> [[OP2:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vrgatherei16_vv_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
				vfloat64m8_t op1, vuint16m2_t op2,
				size_t vl) {
				return vrgatherei16_vv_f64m8_m(mask, maskedoff, op1, op2, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1down.c

This file was added.

				// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
				// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 \| FileCheck --check-prefix=ASM --allow-empty %s

				// ASM-NOT: warning
				#include <riscv_vector.h>

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i32(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vslide1down_vx_i8mf8(vint8mf8_t src, int8_t value, size_t vl) {
				return vslide1down_vx_i8mf8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i32(<vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vslide1down_vx_i8mf4(vint8mf4_t src, int8_t value, size_t vl) {
				return vslide1down_vx_i8mf4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i32(<vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vslide1down_vx_i8mf2(vint8mf2_t src, int8_t value, size_t vl) {
				return vslide1down_vx_i8mf2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i32(<vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vslide1down_vx_i8m1(vint8m1_t src, int8_t value, size_t vl) {
				return vslide1down_vx_i8m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i32(<vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vslide1down_vx_i8m2(vint8m2_t src, int8_t value, size_t vl) {
				return vslide1down_vx_i8m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i32(<vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vslide1down_vx_i8m4(vint8m4_t src, int8_t value, size_t vl) {
				return vslide1down_vx_i8m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i32(<vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vslide1down_vx_i8m8(vint8m8_t src, int8_t value, size_t vl) {
				return vslide1down_vx_i8m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i32(<vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vslide1down_vx_i16mf4(vint16mf4_t src, int16_t value,
				size_t vl) {
				return vslide1down_vx_i16mf4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i32(<vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vslide1down_vx_i16mf2(vint16mf2_t src, int16_t value,
				size_t vl) {
				return vslide1down_vx_i16mf2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i32(<vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vslide1down_vx_i16m1(vint16m1_t src, int16_t value, size_t vl) {
				return vslide1down_vx_i16m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1down.nxv8i16.i16.i32(<vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1down.nxv8i16.i16.i64(<vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vslide1down_vx_i16m2(vint16m2_t src, int16_t value, size_t vl) {
				return vslide1down_vx_i16m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1down.nxv16i16.i16.i32(<vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1down.nxv16i16.i16.i64(<vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vslide1down_vx_i16m4(vint16m4_t src, int16_t value, size_t vl) {
				return vslide1down_vx_i16m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1down.nxv32i16.i16.i32(<vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1down.nxv32i16.i16.i64(<vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vslide1down_vx_i16m8(vint16m8_t src, int16_t value, size_t vl) {
				return vslide1down_vx_i16m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1down.nxv1i32.i32.i32(<vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1down.nxv1i32.i32.i64(<vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vslide1down_vx_i32mf2(vint32mf2_t src, int32_t value,
				size_t vl) {
				return vslide1down_vx_i32mf2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1down.nxv2i32.i32.i32(<vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1down.nxv2i32.i32.i64(<vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vslide1down_vx_i32m1(vint32m1_t src, int32_t value, size_t vl) {
				return vslide1down_vx_i32m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32.i32(<vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32.i64(<vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vslide1down_vx_i32m2(vint32m2_t src, int32_t value, size_t vl) {
				return vslide1down_vx_i32m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1down.nxv8i32.i32.i32(<vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1down.nxv8i32.i32.i64(<vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vslide1down_vx_i32m4(vint32m4_t src, int32_t value, size_t vl) {
				return vslide1down_vx_i32m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1down.nxv16i32.i32.i32(<vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1down.nxv16i32.i32.i64(<vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vslide1down_vx_i32m8(vint32m8_t src, int32_t value, size_t vl) {
				return vslide1down_vx_i32m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64.i32(<vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64.i64(<vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vslide1down_vx_i64m1(vint64m1_t src, int64_t value, size_t vl) {
				return vslide1down_vx_i64m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1down.nxv2i64.i64.i32(<vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1down.nxv2i64.i64.i64(<vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vslide1down_vx_i64m2(vint64m2_t src, int64_t value, size_t vl) {
				return vslide1down_vx_i64m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1down.nxv4i64.i64.i32(<vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1down.nxv4i64.i64.i64(<vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vslide1down_vx_i64m4(vint64m4_t src, int64_t value, size_t vl) {
				return vslide1down_vx_i64m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1down.nxv8i64.i64.i32(<vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1down.nxv8i64.i64.i64(<vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vslide1down_vx_i64m8(vint64m8_t src, int64_t value, size_t vl) {
				return vslide1down_vx_i64m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i32(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vslide1down_vx_u8mf8(vuint8mf8_t src, uint8_t value,
				size_t vl) {
				return vslide1down_vx_u8mf8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i32(<vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vslide1down_vx_u8mf4(vuint8mf4_t src, uint8_t value,
				size_t vl) {
				return vslide1down_vx_u8mf4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i32(<vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vslide1down_vx_u8mf2(vuint8mf2_t src, uint8_t value,
				size_t vl) {
				return vslide1down_vx_u8mf2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i32(<vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vslide1down_vx_u8m1(vuint8m1_t src, uint8_t value, size_t vl) {
				return vslide1down_vx_u8m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i32(<vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vslide1down_vx_u8m2(vuint8m2_t src, uint8_t value, size_t vl) {
				return vslide1down_vx_u8m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i32(<vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vslide1down_vx_u8m4(vuint8m4_t src, uint8_t value, size_t vl) {
				return vslide1down_vx_u8m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i32(<vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vslide1down_vx_u8m8(vuint8m8_t src, uint8_t value, size_t vl) {
				return vslide1down_vx_u8m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i32(<vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vslide1down_vx_u16mf4(vuint16mf4_t src, uint16_t value,
				size_t vl) {
				return vslide1down_vx_u16mf4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i32(<vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vslide1down_vx_u16mf2(vuint16mf2_t src, uint16_t value,
				size_t vl) {
				return vslide1down_vx_u16mf2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i32(<vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vslide1down_vx_u16m1(vuint16m1_t src, uint16_t value,
				size_t vl) {
				return vslide1down_vx_u16m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1down.nxv8i16.i16.i32(<vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1down.nxv8i16.i16.i64(<vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vslide1down_vx_u16m2(vuint16m2_t src, uint16_t value,
				size_t vl) {
				return vslide1down_vx_u16m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1down.nxv16i16.i16.i32(<vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1down.nxv16i16.i16.i64(<vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vslide1down_vx_u16m4(vuint16m4_t src, uint16_t value,
				size_t vl) {
				return vslide1down_vx_u16m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1down.nxv32i16.i16.i32(<vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1down.nxv32i16.i16.i64(<vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vslide1down_vx_u16m8(vuint16m8_t src, uint16_t value,
				size_t vl) {
				return vslide1down_vx_u16m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1down.nxv1i32.i32.i32(<vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1down.nxv1i32.i32.i64(<vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vslide1down_vx_u32mf2(vuint32mf2_t src, uint32_t value,
				size_t vl) {
				return vslide1down_vx_u32mf2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1down.nxv2i32.i32.i32(<vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1down.nxv2i32.i32.i64(<vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vslide1down_vx_u32m1(vuint32m1_t src, uint32_t value,
				size_t vl) {
				return vslide1down_vx_u32m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32.i32(<vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32.i64(<vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vslide1down_vx_u32m2(vuint32m2_t src, uint32_t value,
				size_t vl) {
				return vslide1down_vx_u32m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1down.nxv8i32.i32.i32(<vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1down.nxv8i32.i32.i64(<vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vslide1down_vx_u32m4(vuint32m4_t src, uint32_t value,
				size_t vl) {
				return vslide1down_vx_u32m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1down.nxv16i32.i32.i32(<vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1down.nxv16i32.i32.i64(<vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vslide1down_vx_u32m8(vuint32m8_t src, uint32_t value,
				size_t vl) {
				return vslide1down_vx_u32m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64.i32(<vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64.i64(<vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vslide1down_vx_u64m1(vuint64m1_t src, uint64_t value,
				size_t vl) {
				return vslide1down_vx_u64m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1down.nxv2i64.i64.i32(<vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1down.nxv2i64.i64.i64(<vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vslide1down_vx_u64m2(vuint64m2_t src, uint64_t value,
				size_t vl) {
				return vslide1down_vx_u64m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1down.nxv4i64.i64.i32(<vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1down.nxv4i64.i64.i64(<vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vslide1down_vx_u64m4(vuint64m4_t src, uint64_t value,
				size_t vl) {
				return vslide1down_vx_u64m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1down.nxv8i64.i64.i32(<vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1down.nxv8i64.i64.i64(<vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vslide1down_vx_u64m8(vuint64m8_t src, uint64_t value,
				size_t vl) {
				return vslide1down_vx_u64m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.mask.nxv1i8.i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vslide1down_vx_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff,
				vint8mf8_t src, int8_t value,
				size_t vl) {
				return vslide1down_vx_i8mf8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1down.mask.nxv2i8.i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1down.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vslide1down_vx_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff,
				vint8mf4_t src, int8_t value,
				size_t vl) {
				return vslide1down_vx_i8mf4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1down.mask.nxv4i8.i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1down.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vslide1down_vx_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff,
				vint8mf2_t src, int8_t value,
				size_t vl) {
				return vslide1down_vx_i8mf2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1down.mask.nxv8i8.i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1down.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vslide1down_vx_i8m1_m(vbool8_t mask, vint8m1_t maskedoff,
				vint8m1_t src, int8_t value, size_t vl) {
				return vslide1down_vx_i8m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1down.mask.nxv16i8.i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1down.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vslide1down_vx_i8m2_m(vbool4_t mask, vint8m2_t maskedoff,
				vint8m2_t src, int8_t value, size_t vl) {
				return vslide1down_vx_i8m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1down.mask.nxv32i8.i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1down.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vslide1down_vx_i8m4_m(vbool2_t mask, vint8m4_t maskedoff,
				vint8m4_t src, int8_t value, size_t vl) {
				return vslide1down_vx_i8m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1down.mask.nxv64i8.i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1down.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vslide1down_vx_i8m8_m(vbool1_t mask, vint8m8_t maskedoff,
				vint8m8_t src, int8_t value, size_t vl) {
				return vslide1down_vx_i8m8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1down.mask.nxv1i16.i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1down.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vslide1down_vx_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff,
				vint16mf4_t src, int16_t value,
				size_t vl) {
				return vslide1down_vx_i16mf4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1down.mask.nxv2i16.i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1down.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vslide1down_vx_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff,
				vint16mf2_t src, int16_t value,
				size_t vl) {
				return vslide1down_vx_i16mf2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1down.mask.nxv4i16.i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1down.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vslide1down_vx_i16m1_m(vbool16_t mask, vint16m1_t maskedoff,
				vint16m1_t src, int16_t value,
				size_t vl) {
				return vslide1down_vx_i16m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1down.mask.nxv8i16.i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1down.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vslide1down_vx_i16m2_m(vbool8_t mask, vint16m2_t maskedoff,
				vint16m2_t src, int16_t value,
				size_t vl) {
				return vslide1down_vx_i16m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1down.mask.nxv16i16.i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1down.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vslide1down_vx_i16m4_m(vbool4_t mask, vint16m4_t maskedoff,
				vint16m4_t src, int16_t value,
				size_t vl) {
				return vslide1down_vx_i16m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1down.mask.nxv32i16.i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1down.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vslide1down_vx_i16m8_m(vbool2_t mask, vint16m8_t maskedoff,
				vint16m8_t src, int16_t value,
				size_t vl) {
				return vslide1down_vx_i16m8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1down.mask.nxv1i32.i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1down.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vslide1down_vx_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff,
				vint32mf2_t src, int32_t value,
				size_t vl) {
				return vslide1down_vx_i32mf2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1down.mask.nxv2i32.i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1down.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vslide1down_vx_i32m1_m(vbool32_t mask, vint32m1_t maskedoff,
				vint32m1_t src, int32_t value,
				size_t vl) {
				return vslide1down_vx_i32m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1down.mask.nxv4i32.i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1down.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vslide1down_vx_i32m2_m(vbool16_t mask, vint32m2_t maskedoff,
				vint32m2_t src, int32_t value,
				size_t vl) {
				return vslide1down_vx_i32m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1down.mask.nxv8i32.i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1down.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vslide1down_vx_i32m4_m(vbool8_t mask, vint32m4_t maskedoff,
				vint32m4_t src, int32_t value,
				size_t vl) {
				return vslide1down_vx_i32m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1down.mask.nxv16i32.i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1down.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vslide1down_vx_i32m8_m(vbool4_t mask, vint32m8_t maskedoff,
				vint32m8_t src, int32_t value,
				size_t vl) {
				return vslide1down_vx_i32m8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vslide1down_vx_i64m1_m(vbool64_t mask, vint64m1_t maskedoff,
				vint64m1_t src, int64_t value,
				size_t vl) {
				return vslide1down_vx_i64m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1down.mask.nxv2i64.i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1down.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vslide1down_vx_i64m2_m(vbool32_t mask, vint64m2_t maskedoff,
				vint64m2_t src, int64_t value,
				size_t vl) {
				return vslide1down_vx_i64m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1down.mask.nxv4i64.i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1down.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vslide1down_vx_i64m4_m(vbool16_t mask, vint64m4_t maskedoff,
				vint64m4_t src, int64_t value,
				size_t vl) {
				return vslide1down_vx_i64m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_i64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1down.mask.nxv8i64.i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_i64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1down.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vslide1down_vx_i64m8_m(vbool8_t mask, vint64m8_t maskedoff,
				vint64m8_t src, int64_t value,
				size_t vl) {
				return vslide1down_vx_i64m8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.mask.nxv1i8.i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1down.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vslide1down_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff,
				vuint8mf8_t src, uint8_t value,
				size_t vl) {
				return vslide1down_vx_u8mf8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1down.mask.nxv2i8.i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1down.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vslide1down_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff,
				vuint8mf4_t src, uint8_t value,
				size_t vl) {
				return vslide1down_vx_u8mf4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1down.mask.nxv4i8.i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1down.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vslide1down_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff,
				vuint8mf2_t src, uint8_t value,
				size_t vl) {
				return vslide1down_vx_u8mf2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1down.mask.nxv8i8.i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1down.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vslide1down_vx_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff,
				vuint8m1_t src, uint8_t value,
				size_t vl) {
				return vslide1down_vx_u8m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1down.mask.nxv16i8.i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1down.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vslide1down_vx_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff,
				vuint8m2_t src, uint8_t value,
				size_t vl) {
				return vslide1down_vx_u8m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1down.mask.nxv32i8.i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1down.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vslide1down_vx_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff,
				vuint8m4_t src, uint8_t value,
				size_t vl) {
				return vslide1down_vx_u8m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1down.mask.nxv64i8.i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1down.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vslide1down_vx_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff,
				vuint8m8_t src, uint8_t value,
				size_t vl) {
				return vslide1down_vx_u8m8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1down.mask.nxv1i16.i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1down.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vslide1down_vx_u16mf4_m(vbool64_t mask,
				vuint16mf4_t maskedoff,
				vuint16mf4_t src, uint16_t value,
				size_t vl) {
				return vslide1down_vx_u16mf4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1down.mask.nxv2i16.i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1down.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vslide1down_vx_u16mf2_m(vbool32_t mask,
				vuint16mf2_t maskedoff,
				vuint16mf2_t src, uint16_t value,
				size_t vl) {
				return vslide1down_vx_u16mf2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1down.mask.nxv4i16.i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1down.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vslide1down_vx_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff,
				vuint16m1_t src, uint16_t value,
				size_t vl) {
				return vslide1down_vx_u16m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1down.mask.nxv8i16.i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1down.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vslide1down_vx_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff,
				vuint16m2_t src, uint16_t value,
				size_t vl) {
				return vslide1down_vx_u16m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1down.mask.nxv16i16.i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1down.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vslide1down_vx_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff,
				vuint16m4_t src, uint16_t value,
				size_t vl) {
				return vslide1down_vx_u16m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1down.mask.nxv32i16.i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1down.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vslide1down_vx_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff,
				vuint16m8_t src, uint16_t value,
				size_t vl) {
				return vslide1down_vx_u16m8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1down.mask.nxv1i32.i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1down.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vslide1down_vx_u32mf2_m(vbool64_t mask,
				vuint32mf2_t maskedoff,
				vuint32mf2_t src, uint32_t value,
				size_t vl) {
				return vslide1down_vx_u32mf2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1down.mask.nxv2i32.i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1down.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vslide1down_vx_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff,
				vuint32m1_t src, uint32_t value,
				size_t vl) {
				return vslide1down_vx_u32m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1down.mask.nxv4i32.i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1down.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vslide1down_vx_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff,
				vuint32m2_t src, uint32_t value,
				size_t vl) {
				return vslide1down_vx_u32m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1down.mask.nxv8i32.i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1down.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vslide1down_vx_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff,
				vuint32m4_t src, uint32_t value,
				size_t vl) {
				return vslide1down_vx_u32m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1down.mask.nxv16i32.i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1down.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vslide1down_vx_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff,
				vuint32m8_t src, uint32_t value,
				size_t vl) {
				return vslide1down_vx_u32m8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vslide1down_vx_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff,
				vuint64m1_t src, uint64_t value,
				size_t vl) {
				return vslide1down_vx_u64m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1down.mask.nxv2i64.i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1down.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vslide1down_vx_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff,
				vuint64m2_t src, uint64_t value,
				size_t vl) {
				return vslide1down_vx_u64m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1down.mask.nxv4i64.i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1down.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vslide1down_vx_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff,
				vuint64m4_t src, uint64_t value,
				size_t vl) {
				return vslide1down_vx_u64m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1down_vx_u64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1down.mask.nxv8i64.i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1down_vx_u64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1down.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vslide1down_vx_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff,
				vuint64m8_t src, uint64_t value,
				size_t vl) {
				return vslide1down_vx_u64m8_m(mask, maskedoff, src, value, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1up.c

This file was added.

				// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
				// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 \| FileCheck --check-prefix=ASM --allow-empty %s

				// ASM-NOT: warning
				#include <riscv_vector.h>

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i32(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vslide1up_vx_i8mf8(vint8mf8_t src, int8_t value, size_t vl) {
				return vslide1up_vx_i8mf8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i32(<vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vslide1up_vx_i8mf4(vint8mf4_t src, int8_t value, size_t vl) {
				return vslide1up_vx_i8mf4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i32(<vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vslide1up_vx_i8mf2(vint8mf2_t src, int8_t value, size_t vl) {
				return vslide1up_vx_i8mf2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i32(<vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vslide1up_vx_i8m1(vint8m1_t src, int8_t value, size_t vl) {
				return vslide1up_vx_i8m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i32(<vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vslide1up_vx_i8m2(vint8m2_t src, int8_t value, size_t vl) {
				return vslide1up_vx_i8m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i32(<vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vslide1up_vx_i8m4(vint8m4_t src, int8_t value, size_t vl) {
				return vslide1up_vx_i8m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i32(<vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vslide1up_vx_i8m8(vint8m8_t src, int8_t value, size_t vl) {
				return vslide1up_vx_i8m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i32(<vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vslide1up_vx_i16mf4(vint16mf4_t src, int16_t value,
				size_t vl) {
				return vslide1up_vx_i16mf4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i32(<vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vslide1up_vx_i16mf2(vint16mf2_t src, int16_t value,
				size_t vl) {
				return vslide1up_vx_i16mf2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i32(<vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vslide1up_vx_i16m1(vint16m1_t src, int16_t value, size_t vl) {
				return vslide1up_vx_i16m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1up.nxv8i16.i16.i32(<vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1up.nxv8i16.i16.i64(<vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vslide1up_vx_i16m2(vint16m2_t src, int16_t value, size_t vl) {
				return vslide1up_vx_i16m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1up.nxv16i16.i16.i32(<vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1up.nxv16i16.i16.i64(<vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vslide1up_vx_i16m4(vint16m4_t src, int16_t value, size_t vl) {
				return vslide1up_vx_i16m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1up.nxv32i16.i16.i32(<vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1up.nxv32i16.i16.i64(<vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vslide1up_vx_i16m8(vint16m8_t src, int16_t value, size_t vl) {
				return vslide1up_vx_i16m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1up.nxv1i32.i32.i32(<vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1up.nxv1i32.i32.i64(<vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vslide1up_vx_i32mf2(vint32mf2_t src, int32_t value,
				size_t vl) {
				return vslide1up_vx_i32mf2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1up.nxv2i32.i32.i32(<vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1up.nxv2i32.i32.i64(<vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vslide1up_vx_i32m1(vint32m1_t src, int32_t value, size_t vl) {
				return vslide1up_vx_i32m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1up.nxv4i32.i32.i32(<vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1up.nxv4i32.i32.i64(<vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vslide1up_vx_i32m2(vint32m2_t src, int32_t value, size_t vl) {
				return vslide1up_vx_i32m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1up.nxv8i32.i32.i32(<vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1up.nxv8i32.i32.i64(<vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vslide1up_vx_i32m4(vint32m4_t src, int32_t value, size_t vl) {
				return vslide1up_vx_i32m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1up.nxv16i32.i32.i32(<vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1up.nxv16i32.i32.i64(<vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vslide1up_vx_i32m8(vint32m8_t src, int32_t value, size_t vl) {
				return vslide1up_vx_i32m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64.i32(<vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64.i64(<vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vslide1up_vx_i64m1(vint64m1_t src, int64_t value, size_t vl) {
				return vslide1up_vx_i64m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1up.nxv2i64.i64.i32(<vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1up.nxv2i64.i64.i64(<vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vslide1up_vx_i64m2(vint64m2_t src, int64_t value, size_t vl) {
				return vslide1up_vx_i64m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1up.nxv4i64.i64.i32(<vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1up.nxv4i64.i64.i64(<vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vslide1up_vx_i64m4(vint64m4_t src, int64_t value, size_t vl) {
				return vslide1up_vx_i64m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1up.nxv8i64.i64.i32(<vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1up.nxv8i64.i64.i64(<vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vslide1up_vx_i64m8(vint64m8_t src, int64_t value, size_t vl) {
				return vslide1up_vx_i64m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i32(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vslide1up_vx_u8mf8(vuint8mf8_t src, uint8_t value, size_t vl) {
				return vslide1up_vx_u8mf8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i32(<vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vslide1up_vx_u8mf4(vuint8mf4_t src, uint8_t value, size_t vl) {
				return vslide1up_vx_u8mf4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i32(<vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vslide1up_vx_u8mf2(vuint8mf2_t src, uint8_t value, size_t vl) {
				return vslide1up_vx_u8mf2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i32(<vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vslide1up_vx_u8m1(vuint8m1_t src, uint8_t value, size_t vl) {
				return vslide1up_vx_u8m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i32(<vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vslide1up_vx_u8m2(vuint8m2_t src, uint8_t value, size_t vl) {
				return vslide1up_vx_u8m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i32(<vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vslide1up_vx_u8m4(vuint8m4_t src, uint8_t value, size_t vl) {
				return vslide1up_vx_u8m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i32(<vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vslide1up_vx_u8m8(vuint8m8_t src, uint8_t value, size_t vl) {
				return vslide1up_vx_u8m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i32(<vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vslide1up_vx_u16mf4(vuint16mf4_t src, uint16_t value,
				size_t vl) {
				return vslide1up_vx_u16mf4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i32(<vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vslide1up_vx_u16mf2(vuint16mf2_t src, uint16_t value,
				size_t vl) {
				return vslide1up_vx_u16mf2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i32(<vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vslide1up_vx_u16m1(vuint16m1_t src, uint16_t value,
				size_t vl) {
				return vslide1up_vx_u16m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1up.nxv8i16.i16.i32(<vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1up.nxv8i16.i16.i64(<vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vslide1up_vx_u16m2(vuint16m2_t src, uint16_t value,
				size_t vl) {
				return vslide1up_vx_u16m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1up.nxv16i16.i16.i32(<vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1up.nxv16i16.i16.i64(<vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vslide1up_vx_u16m4(vuint16m4_t src, uint16_t value,
				size_t vl) {
				return vslide1up_vx_u16m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1up.nxv32i16.i16.i32(<vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1up.nxv32i16.i16.i64(<vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vslide1up_vx_u16m8(vuint16m8_t src, uint16_t value,
				size_t vl) {
				return vslide1up_vx_u16m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1up.nxv1i32.i32.i32(<vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1up.nxv1i32.i32.i64(<vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vslide1up_vx_u32mf2(vuint32mf2_t src, uint32_t value,
				size_t vl) {
				return vslide1up_vx_u32mf2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1up.nxv2i32.i32.i32(<vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1up.nxv2i32.i32.i64(<vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vslide1up_vx_u32m1(vuint32m1_t src, uint32_t value,
				size_t vl) {
				return vslide1up_vx_u32m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1up.nxv4i32.i32.i32(<vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1up.nxv4i32.i32.i64(<vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vslide1up_vx_u32m2(vuint32m2_t src, uint32_t value,
				size_t vl) {
				return vslide1up_vx_u32m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1up.nxv8i32.i32.i32(<vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1up.nxv8i32.i32.i64(<vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vslide1up_vx_u32m4(vuint32m4_t src, uint32_t value,
				size_t vl) {
				return vslide1up_vx_u32m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1up.nxv16i32.i32.i32(<vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1up.nxv16i32.i32.i64(<vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vslide1up_vx_u32m8(vuint32m8_t src, uint32_t value,
				size_t vl) {
				return vslide1up_vx_u32m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64.i32(<vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64.i64(<vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vslide1up_vx_u64m1(vuint64m1_t src, uint64_t value,
				size_t vl) {
				return vslide1up_vx_u64m1(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1up.nxv2i64.i64.i32(<vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1up.nxv2i64.i64.i64(<vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vslide1up_vx_u64m2(vuint64m2_t src, uint64_t value,
				size_t vl) {
				return vslide1up_vx_u64m2(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1up.nxv4i64.i64.i32(<vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1up.nxv4i64.i64.i64(<vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vslide1up_vx_u64m4(vuint64m4_t src, uint64_t value,
				size_t vl) {
				return vslide1up_vx_u64m4(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1up.nxv8i64.i64.i32(<vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1up.nxv8i64.i64.i64(<vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vslide1up_vx_u64m8(vuint64m8_t src, uint64_t value,
				size_t vl) {
				return vslide1up_vx_u64m8(src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.mask.nxv1i8.i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vslide1up_vx_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff,
				vint8mf8_t src, int8_t value, size_t vl) {
				return vslide1up_vx_i8mf8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1up.mask.nxv2i8.i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1up.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vslide1up_vx_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff,
				vint8mf4_t src, int8_t value, size_t vl) {
				return vslide1up_vx_i8mf4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1up.mask.nxv4i8.i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1up.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vslide1up_vx_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff,
				vint8mf2_t src, int8_t value, size_t vl) {
				return vslide1up_vx_i8mf2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1up.mask.nxv8i8.i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1up.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vslide1up_vx_i8m1_m(vbool8_t mask, vint8m1_t maskedoff,
				vint8m1_t src, int8_t value, size_t vl) {
				return vslide1up_vx_i8m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1up.mask.nxv16i8.i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1up.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vslide1up_vx_i8m2_m(vbool4_t mask, vint8m2_t maskedoff,
				vint8m2_t src, int8_t value, size_t vl) {
				return vslide1up_vx_i8m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1up.mask.nxv32i8.i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1up.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vslide1up_vx_i8m4_m(vbool2_t mask, vint8m4_t maskedoff,
				vint8m4_t src, int8_t value, size_t vl) {
				return vslide1up_vx_i8m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1up.mask.nxv64i8.i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1up.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vslide1up_vx_i8m8_m(vbool1_t mask, vint8m8_t maskedoff,
				vint8m8_t src, int8_t value, size_t vl) {
				return vslide1up_vx_i8m8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1up.mask.nxv1i16.i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1up.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vslide1up_vx_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff,
				vint16mf4_t src, int16_t value,
				size_t vl) {
				return vslide1up_vx_i16mf4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1up.mask.nxv2i16.i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1up.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vslide1up_vx_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff,
				vint16mf2_t src, int16_t value,
				size_t vl) {
				return vslide1up_vx_i16mf2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1up.mask.nxv4i16.i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1up.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vslide1up_vx_i16m1_m(vbool16_t mask, vint16m1_t maskedoff,
				vint16m1_t src, int16_t value, size_t vl) {
				return vslide1up_vx_i16m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1up.mask.nxv8i16.i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1up.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vslide1up_vx_i16m2_m(vbool8_t mask, vint16m2_t maskedoff,
				vint16m2_t src, int16_t value, size_t vl) {
				return vslide1up_vx_i16m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1up.mask.nxv16i16.i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1up.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vslide1up_vx_i16m4_m(vbool4_t mask, vint16m4_t maskedoff,
				vint16m4_t src, int16_t value, size_t vl) {
				return vslide1up_vx_i16m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1up.mask.nxv32i16.i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1up.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vslide1up_vx_i16m8_m(vbool2_t mask, vint16m8_t maskedoff,
				vint16m8_t src, int16_t value, size_t vl) {
				return vslide1up_vx_i16m8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1up.mask.nxv1i32.i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1up.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vslide1up_vx_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff,
				vint32mf2_t src, int32_t value,
				size_t vl) {
				return vslide1up_vx_i32mf2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1up.mask.nxv2i32.i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1up.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vslide1up_vx_i32m1_m(vbool32_t mask, vint32m1_t maskedoff,
				vint32m1_t src, int32_t value, size_t vl) {
				return vslide1up_vx_i32m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1up.mask.nxv4i32.i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1up.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vslide1up_vx_i32m2_m(vbool16_t mask, vint32m2_t maskedoff,
				vint32m2_t src, int32_t value, size_t vl) {
				return vslide1up_vx_i32m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1up.mask.nxv8i32.i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1up.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vslide1up_vx_i32m4_m(vbool8_t mask, vint32m4_t maskedoff,
				vint32m4_t src, int32_t value, size_t vl) {
				return vslide1up_vx_i32m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1up.mask.nxv16i32.i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1up.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vslide1up_vx_i32m8_m(vbool4_t mask, vint32m8_t maskedoff,
				vint32m8_t src, int32_t value, size_t vl) {
				return vslide1up_vx_i32m8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1up.mask.nxv1i64.i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1up.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vslide1up_vx_i64m1_m(vbool64_t mask, vint64m1_t maskedoff,
				vint64m1_t src, int64_t value, size_t vl) {
				return vslide1up_vx_i64m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1up.mask.nxv2i64.i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1up.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vslide1up_vx_i64m2_m(vbool32_t mask, vint64m2_t maskedoff,
				vint64m2_t src, int64_t value, size_t vl) {
				return vslide1up_vx_i64m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1up.mask.nxv4i64.i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1up.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vslide1up_vx_i64m4_m(vbool16_t mask, vint64m4_t maskedoff,
				vint64m4_t src, int64_t value, size_t vl) {
				return vslide1up_vx_i64m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_i64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1up.mask.nxv8i64.i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_i64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1up.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vslide1up_vx_i64m8_m(vbool8_t mask, vint64m8_t maskedoff,
				vint64m8_t src, int64_t value, size_t vl) {
				return vslide1up_vx_i64m8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.mask.nxv1i8.i8.i32(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslide1up.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.]], <vscale x 1 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vslide1up_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff,
				vuint8mf8_t src, uint8_t value,
				size_t vl) {
				return vslide1up_vx_u8mf8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1up.mask.nxv2i8.i8.i32(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslide1up.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.]], <vscale x 2 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vslide1up_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff,
				vuint8mf4_t src, uint8_t value,
				size_t vl) {
				return vslide1up_vx_u8mf4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1up.mask.nxv4i8.i8.i32(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslide1up.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.]], <vscale x 4 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vslide1up_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff,
				vuint8mf2_t src, uint8_t value,
				size_t vl) {
				return vslide1up_vx_u8mf2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1up.mask.nxv8i8.i8.i32(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslide1up.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.]], <vscale x 8 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vslide1up_vx_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff,
				vuint8m1_t src, uint8_t value, size_t vl) {
				return vslide1up_vx_u8m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1up.mask.nxv16i8.i8.i32(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslide1up.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.]], <vscale x 16 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vslide1up_vx_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff,
				vuint8m2_t src, uint8_t value, size_t vl) {
				return vslide1up_vx_u8m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1up.mask.nxv32i8.i8.i32(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslide1up.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.]], <vscale x 32 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vslide1up_vx_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff,
				vuint8m4_t src, uint8_t value, size_t vl) {
				return vslide1up_vx_u8m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1up.mask.nxv64i8.i8.i32(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslide1up.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.]], <vscale x 64 x i8> [[SRC:%.]], i8 [[VALUE:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vslide1up_vx_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff,
				vuint8m8_t src, uint8_t value, size_t vl) {
				return vslide1up_vx_u8m8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1up.mask.nxv1i16.i16.i32(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslide1up.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.]], <vscale x 1 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vslide1up_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff,
				vuint16mf4_t src, uint16_t value,
				size_t vl) {
				return vslide1up_vx_u16mf4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1up.mask.nxv2i16.i16.i32(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslide1up.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.]], <vscale x 2 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vslide1up_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff,
				vuint16mf2_t src, uint16_t value,
				size_t vl) {
				return vslide1up_vx_u16mf2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1up.mask.nxv4i16.i16.i32(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslide1up.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.]], <vscale x 4 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vslide1up_vx_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff,
				vuint16m1_t src, uint16_t value,
				size_t vl) {
				return vslide1up_vx_u16m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1up.mask.nxv8i16.i16.i32(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslide1up.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.]], <vscale x 8 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vslide1up_vx_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff,
				vuint16m2_t src, uint16_t value,
				size_t vl) {
				return vslide1up_vx_u16m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1up.mask.nxv16i16.i16.i32(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslide1up.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.]], <vscale x 16 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vslide1up_vx_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff,
				vuint16m4_t src, uint16_t value,
				size_t vl) {
				return vslide1up_vx_u16m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1up.mask.nxv32i16.i16.i32(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslide1up.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.]], <vscale x 32 x i16> [[SRC:%.]], i16 [[VALUE:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vslide1up_vx_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff,
				vuint16m8_t src, uint16_t value,
				size_t vl) {
				return vslide1up_vx_u16m8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1up.mask.nxv1i32.i32.i32(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslide1up.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vslide1up_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff,
				vuint32mf2_t src, uint32_t value,
				size_t vl) {
				return vslide1up_vx_u32mf2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1up.mask.nxv2i32.i32.i32(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslide1up.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vslide1up_vx_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff,
				vuint32m1_t src, uint32_t value,
				size_t vl) {
				return vslide1up_vx_u32m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1up.mask.nxv4i32.i32.i32(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslide1up.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vslide1up_vx_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff,
				vuint32m2_t src, uint32_t value,
				size_t vl) {
				return vslide1up_vx_u32m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1up.mask.nxv8i32.i32.i32(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslide1up.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vslide1up_vx_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff,
				vuint32m4_t src, uint32_t value,
				size_t vl) {
				return vslide1up_vx_u32m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1up.mask.nxv16i32.i32.i32(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslide1up.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[VALUE:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vslide1up_vx_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff,
				vuint32m8_t src, uint32_t value,
				size_t vl) {
				return vslide1up_vx_u32m8_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1up.mask.nxv1i64.i64.i32(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslide1up.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vslide1up_vx_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff,
				vuint64m1_t src, uint64_t value,
				size_t vl) {
				return vslide1up_vx_u64m1_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1up.mask.nxv2i64.i64.i32(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslide1up.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vslide1up_vx_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff,
				vuint64m2_t src, uint64_t value,
				size_t vl) {
				return vslide1up_vx_u64m2_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1up.mask.nxv4i64.i64.i32(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslide1up.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vslide1up_vx_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff,
				vuint64m4_t src, uint64_t value,
				size_t vl) {
				return vslide1up_vx_u64m4_m(mask, maskedoff, src, value, vl);
				}

				// CHECK-RV32-LABEL: @test_vslide1up_vx_u64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1up.mask.nxv8i64.i64.i32(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslide1up_vx_u64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslide1up.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[VALUE:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vslide1up_vx_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff,
				vuint64m8_t src, uint64_t value,
				size_t vl) {
				return vslide1up_vx_u64m8_m(mask, maskedoff, src, value, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c

This file was added.

				// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
				// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 \| FileCheck --check-prefix=ASM --allow-empty %s

				// ASM-NOT: warning
				#include <riscv_vector.h>

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i32(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vslidedown_vx_i8mf8(vint8mf8_t dst, vint8mf8_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i8mf8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8.i32(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vslidedown_vx_i8mf4(vint8mf4_t dst, vint8mf4_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i8mf4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8.i32(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vslidedown_vx_i8mf2(vint8mf2_t dst, vint8mf2_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i8mf2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8.i32(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vslidedown_vx_i8m1(vint8m1_t dst, vint8m1_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i8m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8.i32(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vslidedown_vx_i8m2(vint8m2_t dst, vint8m2_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i8m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8.i32(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vslidedown_vx_i8m4(vint8m4_t dst, vint8m4_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i8m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.nxv64i8.i32(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vslidedown_vx_i8m8(vint8m8_t dst, vint8m8_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i8m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16.i32(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vslidedown_vx_i16mf4(vint16mf4_t dst, vint16mf4_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i16mf4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16.i32(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vslidedown_vx_i16mf2(vint16mf2_t dst, vint16mf2_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i16mf2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16.i32(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vslidedown_vx_i16m1(vint16m1_t dst, vint16m1_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i16m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16.i32(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vslidedown_vx_i16m2(vint16m2_t dst, vint16m2_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i16m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16.i32(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vslidedown_vx_i16m4(vint16m4_t dst, vint16m4_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i16m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.nxv32i16.i32(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vslidedown_vx_i16m8(vint16m8_t dst, vint16m8_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i16m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32.i32(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vslidedown_vx_i32mf2(vint32mf2_t dst, vint32mf2_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i32mf2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32.i32(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vslidedown_vx_i32m1(vint32m1_t dst, vint32m1_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i32m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32.i32(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vslidedown_vx_i32m2(vint32m2_t dst, vint32m2_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i32m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32.i32(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vslidedown_vx_i32m4(vint32m4_t dst, vint32m4_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i32m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.nxv16i32.i32(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vslidedown_vx_i32m8(vint32m8_t dst, vint32m8_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i32m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64.i32(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vslidedown_vx_i64m1(vint64m1_t dst, vint64m1_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i64m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64.i32(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vslidedown_vx_i64m2(vint64m2_t dst, vint64m2_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i64m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64.i32(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vslidedown_vx_i64m4(vint64m4_t dst, vint64m4_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i64m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.nxv8i64.i32(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vslidedown_vx_i64m8(vint64m8_t dst, vint64m8_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i64m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i32(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vslidedown_vx_u8mf8(vuint8mf8_t dst, vuint8mf8_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u8mf8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8.i32(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vslidedown_vx_u8mf4(vuint8mf4_t dst, vuint8mf4_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u8mf4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8.i32(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vslidedown_vx_u8mf2(vuint8mf2_t dst, vuint8mf2_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u8mf2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8.i32(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vslidedown_vx_u8m1(vuint8m1_t dst, vuint8m1_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u8m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8.i32(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vslidedown_vx_u8m2(vuint8m2_t dst, vuint8m2_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u8m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8.i32(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vslidedown_vx_u8m4(vuint8m4_t dst, vuint8m4_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u8m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.nxv64i8.i32(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vslidedown_vx_u8m8(vuint8m8_t dst, vuint8m8_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u8m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16.i32(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vslidedown_vx_u16mf4(vuint16mf4_t dst, vuint16mf4_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u16mf4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16.i32(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vslidedown_vx_u16mf2(vuint16mf2_t dst, vuint16mf2_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u16mf2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16.i32(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vslidedown_vx_u16m1(vuint16m1_t dst, vuint16m1_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u16m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16.i32(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vslidedown_vx_u16m2(vuint16m2_t dst, vuint16m2_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u16m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16.i32(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vslidedown_vx_u16m4(vuint16m4_t dst, vuint16m4_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u16m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.nxv32i16.i32(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vslidedown_vx_u16m8(vuint16m8_t dst, vuint16m8_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u16m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32.i32(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vslidedown_vx_u32mf2(vuint32mf2_t dst, vuint32mf2_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u32mf2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32.i32(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vslidedown_vx_u32m1(vuint32m1_t dst, vuint32m1_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u32m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32.i32(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vslidedown_vx_u32m2(vuint32m2_t dst, vuint32m2_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u32m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32.i32(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vslidedown_vx_u32m4(vuint32m4_t dst, vuint32m4_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u32m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.nxv16i32.i32(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vslidedown_vx_u32m8(vuint32m8_t dst, vuint32m8_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u32m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64.i32(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vslidedown_vx_u64m1(vuint64m1_t dst, vuint64m1_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u64m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64.i32(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vslidedown_vx_u64m2(vuint64m2_t dst, vuint64m2_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u64m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64.i32(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vslidedown_vx_u64m4(vuint64m4_t dst, vuint64m4_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u64m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.nxv8i64.i32(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vslidedown_vx_u64m8(vuint64m8_t dst, vuint64m8_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_u64m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i32(<vscale x 1 x float> [[DST:%.]], <vscale x 1 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> [[DST:%.]], <vscale x 1 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vslidedown_vx_f32mf2(vfloat32mf2_t dst, vfloat32mf2_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_f32mf2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i32(<vscale x 2 x float> [[DST:%.]], <vscale x 2 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 2 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vslidedown_vx_f32m1(vfloat32m1_t dst, vfloat32m1_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_f32m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i32(<vscale x 4 x float> [[DST:%.]], <vscale x 4 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float> [[DST:%.]], <vscale x 4 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vslidedown_vx_f32m2(vfloat32m2_t dst, vfloat32m2_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_f32m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i32(<vscale x 8 x float> [[DST:%.]], <vscale x 8 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float> [[DST:%.]], <vscale x 8 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vslidedown_vx_f32m4(vfloat32m4_t dst, vfloat32m4_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_f32m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vslidedown.nxv16f32.i32(<vscale x 16 x float> [[DST:%.]], <vscale x 16 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vslidedown.nxv16f32.i64(<vscale x 16 x float> [[DST:%.]], <vscale x 16 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vslidedown_vx_f32m8(vfloat32m8_t dst, vfloat32m8_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_f32m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64.i32(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x double> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x double> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vslidedown_vx_f64m1(vfloat64m1_t dst, vfloat64m1_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_f64m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64.i32(<vscale x 2 x double> [[DST:%.]], <vscale x 2 x double> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64.i64(<vscale x 2 x double> [[DST:%.]], <vscale x 2 x double> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vslidedown_vx_f64m2(vfloat64m2_t dst, vfloat64m2_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_f64m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64.i32(<vscale x 4 x double> [[DST:%.]], <vscale x 4 x double> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64.i64(<vscale x 4 x double> [[DST:%.]], <vscale x 4 x double> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vslidedown_vx_f64m4(vfloat64m4_t dst, vfloat64m4_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_f64m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vslidedown.nxv8f64.i32(<vscale x 8 x double> [[DST:%.]], <vscale x 8 x double> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vslidedown.nxv8f64.i64(<vscale x 8 x double> [[DST:%.]], <vscale x 8 x double> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vslidedown_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_f64m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8.i32(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vslidedown_vx_i8mf8_m(vbool64_t mask, vint8mf8_t dst,
				vint8mf8_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i8mf8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8.i32(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vslidedown_vx_i8mf4_m(vbool32_t mask, vint8mf4_t dst,
				vint8mf4_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i8mf4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8.i32(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vslidedown_vx_i8mf2_m(vbool16_t mask, vint8mf2_t dst,
				vint8mf2_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i8mf2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8.i32(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vslidedown_vx_i8m1_m(vbool8_t mask, vint8m1_t dst, vint8m1_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i8m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8.i32(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vslidedown_vx_i8m2_m(vbool4_t mask, vint8m2_t dst, vint8m2_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i8m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8.i32(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vslidedown_vx_i8m4_m(vbool2_t mask, vint8m4_t dst, vint8m4_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i8m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.mask.nxv64i8.i32(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vslidedown_vx_i8m8_m(vbool1_t mask, vint8m8_t dst, vint8m8_t src,
				size_t offset, size_t vl) {
				return vslidedown_vx_i8m8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16.i32(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vslidedown_vx_i16mf4_m(vbool64_t mask, vint16mf4_t dst,
				vint16mf4_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i16mf4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16.i32(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vslidedown_vx_i16mf2_m(vbool32_t mask, vint16mf2_t dst,
				vint16mf2_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i16mf2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16.i32(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vslidedown_vx_i16m1_m(vbool16_t mask, vint16m1_t dst,
				vint16m1_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i16m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16.i32(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vslidedown_vx_i16m2_m(vbool8_t mask, vint16m2_t dst,
				vint16m2_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i16m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16.i32(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vslidedown_vx_i16m4_m(vbool4_t mask, vint16m4_t dst,
				vint16m4_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i16m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.mask.nxv32i16.i32(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vslidedown_vx_i16m8_m(vbool2_t mask, vint16m8_t dst,
				vint16m8_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i16m8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32.i32(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vslidedown_vx_i32mf2_m(vbool64_t mask, vint32mf2_t dst,
				vint32mf2_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i32mf2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32.i32(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vslidedown_vx_i32m1_m(vbool32_t mask, vint32m1_t dst,
				vint32m1_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i32m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32.i32(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vslidedown_vx_i32m2_m(vbool16_t mask, vint32m2_t dst,
				vint32m2_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i32m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32.i32(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vslidedown_vx_i32m4_m(vbool8_t mask, vint32m4_t dst,
				vint32m4_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i32m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.mask.nxv16i32.i32(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vslidedown_vx_i32m8_m(vbool4_t mask, vint32m8_t dst,
				vint32m8_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i32m8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64.i32(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vslidedown_vx_i64m1_m(vbool64_t mask, vint64m1_t dst,
				vint64m1_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i64m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64.i32(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vslidedown_vx_i64m2_m(vbool32_t mask, vint64m2_t dst,
				vint64m2_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i64m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64.i32(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vslidedown_vx_i64m4_m(vbool16_t mask, vint64m4_t dst,
				vint64m4_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i64m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_i64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.mask.nxv8i64.i32(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vslidedown_vx_i64m8_m(vbool8_t mask, vint64m8_t dst,
				vint64m8_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_i64m8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8.i32(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vslidedown_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t dst,
				vuint8mf8_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_u8mf8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8.i32(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vslidedown_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t dst,
				vuint8mf4_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_u8mf4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8.i32(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vslidedown_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t dst,
				vuint8mf2_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_u8mf2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8.i32(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vslidedown_vx_u8m1_m(vbool8_t mask, vuint8m1_t dst,
				vuint8m1_t src, size_t offset, size_t vl) {
				return vslidedown_vx_u8m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8.i32(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vslidedown_vx_u8m2_m(vbool4_t mask, vuint8m2_t dst,
				vuint8m2_t src, size_t offset, size_t vl) {
				return vslidedown_vx_u8m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8.i32(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vslidedown_vx_u8m4_m(vbool2_t mask, vuint8m4_t dst,
				vuint8m4_t src, size_t offset, size_t vl) {
				return vslidedown_vx_u8m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.mask.nxv64i8.i32(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vslidedown_vx_u8m8_m(vbool1_t mask, vuint8m8_t dst,
				vuint8m8_t src, size_t offset, size_t vl) {
				return vslidedown_vx_u8m8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16.i32(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vslidedown_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t dst,
				vuint16mf4_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_u16mf4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16.i32(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vslidedown_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t dst,
				vuint16mf2_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_u16mf2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16.i32(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vslidedown_vx_u16m1_m(vbool16_t mask, vuint16m1_t dst,
				vuint16m1_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_u16m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16.i32(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vslidedown_vx_u16m2_m(vbool8_t mask, vuint16m2_t dst,
				vuint16m2_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_u16m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16.i32(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vslidedown_vx_u16m4_m(vbool4_t mask, vuint16m4_t dst,
				vuint16m4_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_u16m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.mask.nxv32i16.i32(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vslidedown_vx_u16m8_m(vbool2_t mask, vuint16m8_t dst,
				vuint16m8_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_u16m8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32.i32(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vslidedown_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t dst,
				vuint32mf2_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_u32mf2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32.i32(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vslidedown_vx_u32m1_m(vbool32_t mask, vuint32m1_t dst,
				vuint32m1_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_u32m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32.i32(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vslidedown_vx_u32m2_m(vbool16_t mask, vuint32m2_t dst,
				vuint32m2_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_u32m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32.i32(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vslidedown_vx_u32m4_m(vbool8_t mask, vuint32m4_t dst,
				vuint32m4_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_u32m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.mask.nxv16i32.i32(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vslidedown_vx_u32m8_m(vbool4_t mask, vuint32m8_t dst,
				vuint32m8_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_u32m8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64.i32(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vslidedown_vx_u64m1_m(vbool64_t mask, vuint64m1_t dst,
				vuint64m1_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_u64m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64.i32(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vslidedown_vx_u64m2_m(vbool32_t mask, vuint64m2_t dst,
				vuint64m2_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_u64m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64.i32(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vslidedown_vx_u64m4_m(vbool16_t mask, vuint64m4_t dst,
				vuint64m4_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_u64m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_u64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.mask.nxv8i64.i32(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vslidedown_vx_u64m8_m(vbool8_t mask, vuint64m8_t dst,
				vuint64m8_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_u64m8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32.i32(<vscale x 1 x float> [[DST:%.]], <vscale x 1 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32.i64(<vscale x 1 x float> [[DST:%.]], <vscale x 1 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vslidedown_vx_f32mf2_m(vbool64_t mask, vfloat32mf2_t dst,
				vfloat32mf2_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_f32mf2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32.i32(<vscale x 2 x float> [[DST:%.]], <vscale x 2 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 2 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vslidedown_vx_f32m1_m(vbool32_t mask, vfloat32m1_t dst,
				vfloat32m1_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_f32m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32.i32(<vscale x 4 x float> [[DST:%.]], <vscale x 4 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32.i64(<vscale x 4 x float> [[DST:%.]], <vscale x 4 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vslidedown_vx_f32m2_m(vbool16_t mask, vfloat32m2_t dst,
				vfloat32m2_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_f32m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32.i32(<vscale x 8 x float> [[DST:%.]], <vscale x 8 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32.i64(<vscale x 8 x float> [[DST:%.]], <vscale x 8 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vslidedown_vx_f32m4_m(vbool8_t mask, vfloat32m4_t dst,
				vfloat32m4_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_f32m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vslidedown.mask.nxv16f32.i32(<vscale x 16 x float> [[DST:%.]], <vscale x 16 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vslidedown.mask.nxv16f32.i64(<vscale x 16 x float> [[DST:%.]], <vscale x 16 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vslidedown_vx_f32m8_m(vbool4_t mask, vfloat32m8_t dst,
				vfloat32m8_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_f32m8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64.i32(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x double> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x double> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vslidedown_vx_f64m1_m(vbool64_t mask, vfloat64m1_t dst,
				vfloat64m1_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_f64m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64.i32(<vscale x 2 x double> [[DST:%.]], <vscale x 2 x double> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64.i64(<vscale x 2 x double> [[DST:%.]], <vscale x 2 x double> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vslidedown_vx_f64m2_m(vbool32_t mask, vfloat64m2_t dst,
				vfloat64m2_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_f64m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64.i32(<vscale x 4 x double> [[DST:%.]], <vscale x 4 x double> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64.i64(<vscale x 4 x double> [[DST:%.]], <vscale x 4 x double> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vslidedown_vx_f64m4_m(vbool16_t mask, vfloat64m4_t dst,
				vfloat64m4_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_f64m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslidedown_vx_f64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vslidedown.mask.nxv8f64.i32(<vscale x 8 x double> [[DST:%.]], <vscale x 8 x double> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vslidedown.mask.nxv8f64.i64(<vscale x 8 x double> [[DST:%.]], <vscale x 8 x double> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vslidedown_vx_f64m8_m(vbool8_t mask, vfloat64m8_t dst,
				vfloat64m8_t src, size_t offset,
				size_t vl) {
				return vslidedown_vx_f64m8_m(mask, dst, src, offset, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c

This file was added.

				// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
				// REQUIRES: riscv-registered-target
				// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV32 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -disable-O0-optnone -emit-llvm %s -o - \| opt -S -mem2reg \| FileCheck --check-prefix=CHECK-RV64 %s
				// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
				// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 \| FileCheck --check-prefix=ASM --allow-empty %s

				// ASM-NOT: warning
				#include <riscv_vector.h>

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i32(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vslideup_vx_i8mf8(vint8mf8_t dst, vint8mf8_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i8mf8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i32(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vslideup_vx_i8mf4(vint8mf4_t dst, vint8mf4_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i8mf4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i32(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vslideup_vx_i8mf2(vint8mf2_t dst, vint8mf2_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i8mf2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i32(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vslideup_vx_i8m1(vint8m1_t dst, vint8m1_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i8m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i32(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vslideup_vx_i8m2(vint8m2_t dst, vint8m2_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i8m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i32(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vslideup_vx_i8m4(vint8m4_t dst, vint8m4_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i8m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i32(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vslideup_vx_i8m8(vint8m8_t dst, vint8m8_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i8m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i32(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vslideup_vx_i16mf4(vint16mf4_t dst, vint16mf4_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_i16mf4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i32(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vslideup_vx_i16mf2(vint16mf2_t dst, vint16mf2_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_i16mf2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i32(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vslideup_vx_i16m1(vint16m1_t dst, vint16m1_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i16m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i32(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vslideup_vx_i16m2(vint16m2_t dst, vint16m2_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i16m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i32(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vslideup_vx_i16m4(vint16m4_t dst, vint16m4_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i16m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i32(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vslideup_vx_i16m8(vint16m8_t dst, vint16m8_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i16m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i32(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vslideup_vx_i32mf2(vint32mf2_t dst, vint32mf2_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_i32mf2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i32(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vslideup_vx_i32m1(vint32m1_t dst, vint32m1_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i32m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i32(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vslideup_vx_i32m2(vint32m2_t dst, vint32m2_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i32m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i32(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vslideup_vx_i32m4(vint32m4_t dst, vint32m4_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i32m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i32(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vslideup_vx_i32m8(vint32m8_t dst, vint32m8_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i32m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i32(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vslideup_vx_i64m1(vint64m1_t dst, vint64m1_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i64m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i32(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vslideup_vx_i64m2(vint64m2_t dst, vint64m2_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i64m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i32(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vslideup_vx_i64m4(vint64m4_t dst, vint64m4_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i64m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i32(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vslideup_vx_i64m8(vint64m8_t dst, vint64m8_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i64m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8mf8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i32(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vslideup_vx_u8mf8(vuint8mf8_t dst, vuint8mf8_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_u8mf8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i32(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vslideup_vx_u8mf4(vuint8mf4_t dst, vuint8mf4_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_u8mf4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i32(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vslideup_vx_u8mf2(vuint8mf2_t dst, vuint8mf2_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_u8mf2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i32(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vslideup_vx_u8m1(vuint8m1_t dst, vuint8m1_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u8m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i32(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vslideup_vx_u8m2(vuint8m2_t dst, vuint8m2_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u8m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i32(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vslideup_vx_u8m4(vuint8m4_t dst, vuint8m4_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u8m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i32(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vslideup_vx_u8m8(vuint8m8_t dst, vuint8m8_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u8m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16mf4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i32(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vslideup_vx_u16mf4(vuint16mf4_t dst, vuint16mf4_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_u16mf4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i32(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vslideup_vx_u16mf2(vuint16mf2_t dst, vuint16mf2_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_u16mf2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i32(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vslideup_vx_u16m1(vuint16m1_t dst, vuint16m1_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_u16m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i32(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vslideup_vx_u16m2(vuint16m2_t dst, vuint16m2_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_u16m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i32(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vslideup_vx_u16m4(vuint16m4_t dst, vuint16m4_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_u16m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i32(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vslideup_vx_u16m8(vuint16m8_t dst, vuint16m8_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_u16m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i32(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vslideup_vx_u32mf2(vuint32mf2_t dst, vuint32mf2_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_u32mf2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i32(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vslideup_vx_u32m1(vuint32m1_t dst, vuint32m1_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_u32m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i32(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vslideup_vx_u32m2(vuint32m2_t dst, vuint32m2_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_u32m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i32(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vslideup_vx_u32m4(vuint32m4_t dst, vuint32m4_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_u32m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i32(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vslideup_vx_u32m8(vuint32m8_t dst, vuint32m8_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_u32m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i32(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vslideup_vx_u64m1(vuint64m1_t dst, vuint64m1_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_u64m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i32(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vslideup_vx_u64m2(vuint64m2_t dst, vuint64m2_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_u64m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i32(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vslideup_vx_u64m4(vuint64m4_t dst, vuint64m4_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_u64m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i32(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vslideup_vx_u64m8(vuint64m8_t dst, vuint64m8_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_u64m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32mf2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i32(<vscale x 1 x float> [[DST:%.]], <vscale x 1 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32mf2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> [[DST:%.]], <vscale x 1 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vslideup_vx_f32mf2(vfloat32mf2_t dst, vfloat32mf2_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_f32mf2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i32(<vscale x 2 x float> [[DST:%.]], <vscale x 2 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 2 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vslideup_vx_f32m1(vfloat32m1_t dst, vfloat32m1_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_f32m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32.i32(<vscale x 4 x float> [[DST:%.]], <vscale x 4 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32.i64(<vscale x 4 x float> [[DST:%.]], <vscale x 4 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vslideup_vx_f32m2(vfloat32m2_t dst, vfloat32m2_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_f32m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32.i32(<vscale x 8 x float> [[DST:%.]], <vscale x 8 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32.i64(<vscale x 8 x float> [[DST:%.]], <vscale x 8 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vslideup_vx_f32m4(vfloat32m4_t dst, vfloat32m4_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_f32m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vslideup.nxv16f32.i32(<vscale x 16 x float> [[DST:%.]], <vscale x 16 x float> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vslideup.nxv16f32.i64(<vscale x 16 x float> [[DST:%.]], <vscale x 16 x float> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vslideup_vx_f32m8(vfloat32m8_t dst, vfloat32m8_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_f32m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f64m1(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64.i32(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x double> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f64m1(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x double> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vslideup_vx_f64m1(vfloat64m1_t dst, vfloat64m1_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_f64m1(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f64m2(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64.i32(<vscale x 2 x double> [[DST:%.]], <vscale x 2 x double> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f64m2(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64.i64(<vscale x 2 x double> [[DST:%.]], <vscale x 2 x double> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vslideup_vx_f64m2(vfloat64m2_t dst, vfloat64m2_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_f64m2(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f64m4(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64.i32(<vscale x 4 x double> [[DST:%.]], <vscale x 4 x double> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f64m4(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64.i64(<vscale x 4 x double> [[DST:%.]], <vscale x 4 x double> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vslideup_vx_f64m4(vfloat64m4_t dst, vfloat64m4_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_f64m4(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f64m8(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vslideup.nxv8f64.i32(<vscale x 8 x double> [[DST:%.]], <vscale x 8 x double> [[SRC:%.]], i32 [[OFFSET:%.]], i32 [[VL:%.*]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f64m8(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vslideup.nxv8f64.i64(<vscale x 8 x double> [[DST:%.]], <vscale x 8 x double> [[SRC:%.]], i64 [[OFFSET:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vslideup_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_f64m8(dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8.i32(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vint8mf8_t test_vslideup_vx_i8mf8_m(vbool64_t mask, vint8mf8_t dst,
				vint8mf8_t src, size_t offset, size_t vl) {
				return vslideup_vx_i8mf8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8.i32(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vint8mf4_t test_vslideup_vx_i8mf4_m(vbool32_t mask, vint8mf4_t dst,
				vint8mf4_t src, size_t offset, size_t vl) {
				return vslideup_vx_i8mf4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8.i32(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vint8mf2_t test_vslideup_vx_i8mf2_m(vbool16_t mask, vint8mf2_t dst,
				vint8mf2_t src, size_t offset, size_t vl) {
				return vslideup_vx_i8mf2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8.i32(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vint8m1_t test_vslideup_vx_i8m1_m(vbool8_t mask, vint8m1_t dst, vint8m1_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_i8m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8.i32(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vint8m2_t test_vslideup_vx_i8m2_m(vbool4_t mask, vint8m2_t dst, vint8m2_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_i8m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8.i32(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vint8m4_t test_vslideup_vx_i8m4_m(vbool2_t mask, vint8m4_t dst, vint8m4_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_i8m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.mask.nxv64i8.i32(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vint8m8_t test_vslideup_vx_i8m8_m(vbool1_t mask, vint8m8_t dst, vint8m8_t src,
				size_t offset, size_t vl) {
				return vslideup_vx_i8m8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16.i32(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vint16mf4_t test_vslideup_vx_i16mf4_m(vbool64_t mask, vint16mf4_t dst,
				vint16mf4_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i16mf4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16.i32(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vint16mf2_t test_vslideup_vx_i16mf2_m(vbool32_t mask, vint16mf2_t dst,
				vint16mf2_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i16mf2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16.i32(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vint16m1_t test_vslideup_vx_i16m1_m(vbool16_t mask, vint16m1_t dst,
				vint16m1_t src, size_t offset, size_t vl) {
				return vslideup_vx_i16m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16.i32(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vint16m2_t test_vslideup_vx_i16m2_m(vbool8_t mask, vint16m2_t dst,
				vint16m2_t src, size_t offset, size_t vl) {
				return vslideup_vx_i16m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16.i32(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vint16m4_t test_vslideup_vx_i16m4_m(vbool4_t mask, vint16m4_t dst,
				vint16m4_t src, size_t offset, size_t vl) {
				return vslideup_vx_i16m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.mask.nxv32i16.i32(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vint16m8_t test_vslideup_vx_i16m8_m(vbool2_t mask, vint16m8_t dst,
				vint16m8_t src, size_t offset, size_t vl) {
				return vslideup_vx_i16m8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32.i32(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vint32mf2_t test_vslideup_vx_i32mf2_m(vbool64_t mask, vint32mf2_t dst,
				vint32mf2_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_i32mf2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32.i32(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vslideup_vx_i32m1_m(vbool32_t mask, vint32m1_t dst,
				vint32m1_t src, size_t offset, size_t vl) {
				return vslideup_vx_i32m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32.i32(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vint32m2_t test_vslideup_vx_i32m2_m(vbool16_t mask, vint32m2_t dst,
				vint32m2_t src, size_t offset, size_t vl) {
				return vslideup_vx_i32m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32.i32(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vint32m4_t test_vslideup_vx_i32m4_m(vbool8_t mask, vint32m4_t dst,
				vint32m4_t src, size_t offset, size_t vl) {
				return vslideup_vx_i32m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.mask.nxv16i32.i32(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vint32m8_t test_vslideup_vx_i32m8_m(vbool4_t mask, vint32m8_t dst,
				vint32m8_t src, size_t offset, size_t vl) {
				return vslideup_vx_i32m8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64.i32(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vslideup_vx_i64m1_m(vbool64_t mask, vint64m1_t dst,
				vint64m1_t src, size_t offset, size_t vl) {
				return vslideup_vx_i64m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64.i32(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vint64m2_t test_vslideup_vx_i64m2_m(vbool32_t mask, vint64m2_t dst,
				vint64m2_t src, size_t offset, size_t vl) {
				return vslideup_vx_i64m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64.i32(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vint64m4_t test_vslideup_vx_i64m4_m(vbool16_t mask, vint64m4_t dst,
				vint64m4_t src, size_t offset, size_t vl) {
				return vslideup_vx_i64m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_i64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.mask.nxv8i64.i32(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_i64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vint64m8_t test_vslideup_vx_i64m8_m(vbool8_t mask, vint64m8_t dst,
				vint64m8_t src, size_t offset, size_t vl) {
				return vslideup_vx_i64m8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8mf8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8.i32(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.]], <vscale x 1 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
				//
				vuint8mf8_t test_vslideup_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t dst,
				vuint8mf8_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u8mf8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8.i32(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.]], <vscale x 2 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
				//
				vuint8mf4_t test_vslideup_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t dst,
				vuint8mf4_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u8mf4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8.i32(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.]], <vscale x 4 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
				//
				vuint8mf2_t test_vslideup_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t dst,
				vuint8mf2_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u8mf2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8.i32(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.]], <vscale x 8 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
				//
				vuint8m1_t test_vslideup_vx_u8m1_m(vbool8_t mask, vuint8m1_t dst,
				vuint8m1_t src, size_t offset, size_t vl) {
				return vslideup_vx_u8m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8.i32(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.]], <vscale x 16 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
				//
				vuint8m2_t test_vslideup_vx_u8m2_m(vbool4_t mask, vuint8m2_t dst,
				vuint8m2_t src, size_t offset, size_t vl) {
				return vslideup_vx_u8m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8.i32(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.]], <vscale x 32 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
				//
				vuint8m4_t test_vslideup_vx_u8m4_m(vbool2_t mask, vuint8m4_t dst,
				vuint8m4_t src, size_t offset, size_t vl) {
				return vslideup_vx_u8m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u8m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.mask.nxv64i8.i32(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 64 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u8m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.mask.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.]], <vscale x 64 x i8> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 64 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
				//
				vuint8m8_t test_vslideup_vx_u8m8_m(vbool1_t mask, vuint8m8_t dst,
				vuint8m8_t src, size_t offset, size_t vl) {
				return vslideup_vx_u8m8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16mf4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16.i32(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.]], <vscale x 1 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
				//
				vuint16mf4_t test_vslideup_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t dst,
				vuint16mf4_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u16mf4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16.i32(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.]], <vscale x 2 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
				//
				vuint16mf2_t test_vslideup_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t dst,
				vuint16mf2_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u16mf2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16.i32(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.]], <vscale x 4 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
				//
				vuint16m1_t test_vslideup_vx_u16m1_m(vbool16_t mask, vuint16m1_t dst,
				vuint16m1_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u16m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16.i32(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.]], <vscale x 8 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
				//
				vuint16m2_t test_vslideup_vx_u16m2_m(vbool8_t mask, vuint16m2_t dst,
				vuint16m2_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u16m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16.i32(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.]], <vscale x 16 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
				//
				vuint16m4_t test_vslideup_vx_u16m4_m(vbool4_t mask, vuint16m4_t dst,
				vuint16m4_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u16m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u16m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.mask.nxv32i16.i32(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u16m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.mask.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.]], <vscale x 32 x i16> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
				//
				vuint16m8_t test_vslideup_vx_u16m8_m(vbool2_t mask, vuint16m8_t dst,
				vuint16m8_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u16m8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32.i32(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.]], <vscale x 1 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
				//
				vuint32mf2_t test_vslideup_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t dst,
				vuint32mf2_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u32mf2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32.i32(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.]], <vscale x 2 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vslideup_vx_u32m1_m(vbool32_t mask, vuint32m1_t dst,
				vuint32m1_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u32m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32.i32(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.]], <vscale x 4 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
				//
				vuint32m2_t test_vslideup_vx_u32m2_m(vbool16_t mask, vuint32m2_t dst,
				vuint32m2_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u32m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32.i32(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.]], <vscale x 8 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
				//
				vuint32m4_t test_vslideup_vx_u32m4_m(vbool8_t mask, vuint32m4_t dst,
				vuint32m4_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u32m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.mask.nxv16i32.i32(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.mask.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.]], <vscale x 16 x i32> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
				//
				vuint32m8_t test_vslideup_vx_u32m8_m(vbool4_t mask, vuint32m8_t dst,
				vuint32m8_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u32m8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64.i32(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 1 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vslideup_vx_u64m1_m(vbool64_t mask, vuint64m1_t dst,
				vuint64m1_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u64m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64.i32(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.]], <vscale x 2 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
				//
				vuint64m2_t test_vslideup_vx_u64m2_m(vbool32_t mask, vuint64m2_t dst,
				vuint64m2_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u64m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64.i32(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.]], <vscale x 4 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
				//
				vuint64m4_t test_vslideup_vx_u64m4_m(vbool16_t mask, vuint64m4_t dst,
				vuint64m4_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u64m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_u64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.mask.nxv8i64.i32(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_u64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.mask.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.]], <vscale x 8 x i64> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
				//
				vuint64m8_t test_vslideup_vx_u64m8_m(vbool8_t mask, vuint64m8_t dst,
				vuint64m8_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_u64m8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32mf2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32.i32(<vscale x 1 x float> [[DST:%.]], <vscale x 1 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32mf2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32.i64(<vscale x 1 x float> [[DST:%.]], <vscale x 1 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
				//
				vfloat32mf2_t test_vslideup_vx_f32mf2_m(vbool64_t mask, vfloat32mf2_t dst,
				vfloat32mf2_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_f32mf2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32.i32(<vscale x 2 x float> [[DST:%.]], <vscale x 2 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32.i64(<vscale x 2 x float> [[DST:%.]], <vscale x 2 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vslideup_vx_f32m1_m(vbool32_t mask, vfloat32m1_t dst,
				vfloat32m1_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_f32m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32.i32(<vscale x 4 x float> [[DST:%.]], <vscale x 4 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32.i64(<vscale x 4 x float> [[DST:%.]], <vscale x 4 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
				//
				vfloat32m2_t test_vslideup_vx_f32m2_m(vbool16_t mask, vfloat32m2_t dst,
				vfloat32m2_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_f32m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32.i32(<vscale x 8 x float> [[DST:%.]], <vscale x 8 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32.i64(<vscale x 8 x float> [[DST:%.]], <vscale x 8 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
				//
				vfloat32m4_t test_vslideup_vx_f32m4_m(vbool8_t mask, vfloat32m4_t dst,
				vfloat32m4_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_f32m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f32m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vslideup.mask.nxv16f32.i32(<vscale x 16 x float> [[DST:%.]], <vscale x 16 x float> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f32m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 16 x float> @llvm.riscv.vslideup.mask.nxv16f32.i64(<vscale x 16 x float> [[DST:%.]], <vscale x 16 x float> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
				//
				vfloat32m8_t test_vslideup_vx_f32m8_m(vbool4_t mask, vfloat32m8_t dst,
				vfloat32m8_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_f32m8_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f64m1_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64.i32(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x double> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f64m1_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 1 x double> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vslideup_vx_f64m1_m(vbool64_t mask, vfloat64m1_t dst,
				vfloat64m1_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_f64m1_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f64m2_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64.i32(<vscale x 2 x double> [[DST:%.]], <vscale x 2 x double> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f64m2_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64.i64(<vscale x 2 x double> [[DST:%.]], <vscale x 2 x double> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 2 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
				//
				vfloat64m2_t test_vslideup_vx_f64m2_m(vbool32_t mask, vfloat64m2_t dst,
				vfloat64m2_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_f64m2_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f64m4_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64.i32(<vscale x 4 x double> [[DST:%.]], <vscale x 4 x double> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f64m4_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64.i64(<vscale x 4 x double> [[DST:%.]], <vscale x 4 x double> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 4 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
				//
				vfloat64m4_t test_vslideup_vx_f64m4_m(vbool16_t mask, vfloat64m4_t dst,
				vfloat64m4_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_f64m4_m(mask, dst, src, offset, vl);
				}

				// CHECK-RV32-LABEL: @test_vslideup_vx_f64m8_m(
				// CHECK-RV32-NEXT: entry:
				// CHECK-RV32-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vslideup.mask.nxv8f64.i32(<vscale x 8 x double> [[DST:%.]], <vscale x 8 x double> [[SRC:%.]], i32 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i32 [[VL:%.]])
				// CHECK-RV32-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				// CHECK-RV64-LABEL: @test_vslideup_vx_f64m8_m(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 8 x double> @llvm.riscv.vslideup.mask.nxv8f64.i64(<vscale x 8 x double> [[DST:%.]], <vscale x 8 x double> [[SRC:%.]], i64 [[OFFSET:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
				//
				vfloat64m8_t test_vslideup_vx_f64m8_m(vbool8_t mask, vfloat64m8_t dst,
				vfloat64m8_t src, size_t offset,
				size_t vl) {
				return vslideup_vx_f64m8_m(mask, dst, src, offset, vl);
				}

This is an archive of the discontinued LLVM Phabricator instance.

[RISCV][Clang] Add some RVV Permutation intrinsic functions.ClosedPublic

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Diff 336725

clang/include/clang/Basic/riscv_vector.td

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1down.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1up.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c

[RISCV][Clang] Add some RVV Permutation intrinsic functions.
ClosedPublic