[mlir] Rename AVX512 dialect to X86Vector

[cota]

Summary

We will soon be adding non-AVX512 operations to MLIR, such as AVX's rsqrt. In https://reviews.llvm.org/D99818 several possibilities were discussed, namely to (1) add non-AVX512 ops to the AVX512 dialect, (2) add more dialects (e.g. AVX dialect for AVX rsqrt), and (3) expand the scope of the AVX512 to include these SIMD x86 ops, thereby renaming the dialect to something more accurate such as X86Vector.

Consensus was reached on option (3), which this patch implements.

[cota]

Context: https://reviews.llvm.org/D99818

[aartbik]

I don't think we have so many clients that renaming isn't possible, do we? We have done that before with much more heavily used files.
It's not a super big deal, but this way we lose the revision history of all copied files.

So unless there is a very strong reason to do it this way (or I am wrong in revision history), can we just move the files?

[cota]

• [mlir] Rename AVX512 dialect to X86Vector

[cota]

The previous push used a different diffbase than the original push,
which messed up the diff. Push a diff with the original diffbase now.

[bondhugula]

There isn't a commit summary at all. It'd be good to explain the rationale for the renaming.

[cota]

In D100119#2678531, @bondhugula wrote:

There isn't a commit summary at all. It'd be good to explain the rationale for the renaming.

Added context for this change, thanks.

[ftynse]

mlir/include/mlir/Dialect/X86Vector/X86Vector.td

1

Please fix the comment overflow

mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp

1–2

Please fix the comment overflow

[cota]

Fix overly long comments

[aartbik]

mlir/include/mlir/Dialect/X86Vector/Transforms.h

2

Just curious, why does this file (and the cmake) still show up as delete/add pair

[cota]

mlir/include/mlir/Dialect/X86Vector/Transforms.h

2

That depends on the similarity index that git uses:

$ git diff help
[...]
-M[<n>], --find-renames[=<n>]
           Detect renames. If n is specified, it is a threshold on the similarity index (i.e. amount of addition/deletions compared to the file’s size). For example,
           -M90% means Git should consider a delete/add pair to be a rename if more than 90% of the file hasn’t changed. Without a % sign, the number is to be read as a
           fraction, with a decimal point before it. I.e., -M5 becomes 0.5, and is thus the same as -M50%. Similarly, -M05 is the same as -M5%. To limit detection to
           exact renames, use -M100%. The default similarity index is 50%.

For instance with -M4 this file is detected as a rename. The CMake file has all of its non-whitespace lines changed so it cannot be detected as a rename even with -M1.

[aartbik]

mlir/include/mlir/Dialect/X86Vector/Transforms.h

2

Makes sense. Thanks.

[bondhugula]

We will soon be adding non-AVX512 operations to MLIR, such as AVX's rsqrt. In https://reviews.llvm.org/D99818 several possibilities were discussed, namely to (1) add non-AVX512 ops to
the AVX512 dialect, (2) add more dialects (e.g. AVX dialect for AVX rsqrt), and (3) expand the scope of the AVX512 to include these SIMD x86 ops, thereby renaming the dialect to
something more accurate such as X86Vector.
Consensus was reached on option (3), which this patch implements.

Are you sure about adding non AVX ops to this, i.e., renaming this to X86Vector vs just to AVX? It was a bit confusing without the reference to the rsqrt revision, which would still keep this dialect to AVX. I see that there was a consensus on D99818 to call this X86Vector, but it's always confusing when the renaming is done before any actual non-AVX ops are added or even a plan for that. Is there a proposal for the first non AVX op to be added to this and which one it would be? I also see @ftynse suggested going with AVX there.

[tschuett]

Maybe a child diff with the new op?

[ftynse]

In D100119#2681022, @bondhugula wrote:

Is there a proposal for the first non AVX op to be added to this and which one it would be?

There is a patch, D99818, which triggered the discussion about renaming. That patch adds an AVX op. I am highly supportive of renaming the dialect in a separate patch.

I also see @ftynse suggested going with AVX there.

You must be misreading, I did not suggest this. This will be equally confusing to have AVX512 ops in the AVX dialect and AVX ops in the AVX512 dialect; these are two different instruction sets.

[bondhugula]

In D100119#2681293, @ftynse wrote:

In D100119#2681022, @bondhugula wrote:

Is there a proposal for the first non AVX op to be added to this and which one it would be?

There is a patch, D99818, which triggered the discussion about renaming. That patch adds an AVX op. I am highly supportive of renaming the dialect in a separate patch.

I was asking about a "non AVX op" - as you point out, that's adding an AVX op. (I was aware of D99818 after Aart referred to that above.)

I also see @ftynse suggested going with AVX there.

You must be misreading, I did not suggest this. This will be equally confusing to have AVX512 ops in the AVX dialect and AVX ops in the AVX512 dialect; these are two different

I might have misread the multiply nested context; looks like it was someone else.

[cota]

So far I only have immediate plans of adding avx.rsqrt to the dialect. I'd expect AVX, AVX512 and SSE ops to be added to this dialect in the future.

I think AVX is an OK name although if we end up adding SSE ops then AVX could be confusing.

Furthermore, if we prefix the ops with the dialect's name, which AFAICT seems to be the convention in MLIR, then naming the dialect AVX might be confusing/ugly. For example, we'd have avx.avx.rsqrt and avx.avx512.rsqrt$width; I'd rather have something else in the prefix or just drop the prefix and call those ops avx.rsqrt and avx512.rsqrt.

I don't feel strongly about this, so if you want me to proceed with AVX (I presume by dropping avx as a prefix for all ops) I'll happily do that.

[ftynse]

I have expressed by concerns about the dialect AVX here and in the previous discussion. We will have to rename it the moment somebody wants SSE! I don't understand what is blocking here, the renamed dialect intends to contain ops related to X86 vectors. It does not yet, but this should not preclude us from stating the intent and proceeding. If somebody fills super-strongly about the name, I can waste my time to add a random SSE op once its landed...

[nicolasvasilache]

x86vector is fine for now.

As we evolve we may want to get into e.g. x86.avx.xyz and x86.avx512.pqr but we can easily iterate in-tree as we grow the number of use cases.

mlir/include/mlir/Conversion/Passes.td

def ConvertVectorToLLVM : Pass<"convert-vector-to-llvm", "ModuleOp"> {
   let summary = "Lower the operations from the vector dialect into the LLVM "
                 "dialect";
   let description = [{
 
     Convert operations from the vector dialect into the LLVM IR dialect
     operations. The lowering pass provides several options to control
     the kinds of optimizations that are allowed. It also provides options
     that enable the use of one or more architectural-specific dialects
-    (AMX, AVX512, ArmNeon, ArmSVE, etc.) in combination with the
+    (AMX, X86Vector, ArmNeon, ArmSVE, etc.) in combination with the
     architectural-neutral vector dialect lowering.
 
   }];
   let constructor = "mlir::createConvertVectorToLLVMPass()";
   // Override explicitly in C++ to allow conditional dialect dependence.
   // let dependentDialects;
   let options = [
     Option<"reassociateFPReductions", "reassociate-fp-reductions",
            "bool", /*default=*/"false",
            "Allows llvm to reassociate floating-point reductions for speed">,
     Option<"enableIndexOptimizations", "enable-index-optimizations",
            "bool", /*default=*/"true",
            "Allows compiler to assume indices fit in 32-bit if that yields "
      "faster code">,
     Option<"enableAMX", "enable-amx",
            "bool", /*default=*/"false",
            "Enables the use of AMX dialect while lowering the vector "
      "dialect.">,
-    Option<"enableAVX512", "enable-avx512",
-           "bool", /*default=*/"false",
-           "Enables the use of AVX512 dialect while lowering the vector "
-     "dialect.">,
     Option<"enableArmNeon", "enable-arm-neon",
            "bool", /*default=*/"false",
            "Enables the use of ArmNeon dialect while lowering the vector "
      "dialect.">,
     Option<"enableArmSVE", "enable-arm-sve",
            "bool", /*default=*/"false",
            "Enables the use of ArmSVE dialect while lowering the vector "
-       "dialect.">
+       "dialect.">,
+    Option<"enableX86Vector", "enable-x86vector",
+           "bool", /*default=*/"false",
+           "Enables the use of X86Vector dialect while lowering the vector "
+     "dialect.">
   ];
 }
 
 //===----------------------------------------------------------------------===//
 // VectorToROCDL
 //===----------------------------------------------------------------------===//
 
 def ConvertVectorToROCDL : Pass<"convert-vector-to-rocdl", "ModuleOp"> {

mlir/include/mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h

 /// Options to control Vector to LLVM lowering.
 ///
 /// This should kept in sync with VectorToLLVM options defined for the
 /// ConvertVectorToLLVM pass in include/mlir/Conversion/Passes.td
 struct LowerVectorToLLVMOptions {
   LowerVectorToLLVMOptions()
       : reassociateFPReductions(false), enableIndexOptimizations(true),
         enableArmNeon(false), enableArmSVE(false), enableAMX(false),
-        enableAVX512(false) {}
+        enableX86Vector(false) {}
 
   LowerVectorToLLVMOptions &setReassociateFPReductions(bool b) {
     reassociateFPReductions = b;
     return *this;
   }
   LowerVectorToLLVMOptions &setEnableIndexOptimizations(bool b) {
     enableIndexOptimizations = b;
     return *this;
   }
   LowerVectorToLLVMOptions &setEnableArmNeon(bool b) {
     enableArmNeon = b;
     return *this;
   }
   LowerVectorToLLVMOptions &setEnableArmSVE(bool b) {
     enableArmSVE = b;
     return *this;
   }
   LowerVectorToLLVMOptions &setEnableAMX(bool b) {
     enableAMX = b;
     return *this;
   }
-  LowerVectorToLLVMOptions &setEnableAVX512(bool b) {
-    enableAVX512 = b;
+  LowerVectorToLLVMOptions &setEnableX86Vector(bool b) {
+    enableX86Vector = b;
     return *this;
   }
 
   bool reassociateFPReductions;
   bool enableIndexOptimizations;
   bool enableArmNeon;
   bool enableArmSVE;
   bool enableAMX;
-  bool enableAVX512;
+  bool enableX86Vector;
 };
 
 /// Collect a set of patterns to convert from Vector contractions to LLVM Matrix
 /// Intrinsics. To lower to assembly, the LLVM flag -lower-matrix-intrinsics
 /// will be needed when invoking LLVM.
 void populateVectorToLLVMMatrixConversionPatterns(LLVMTypeConverter &converter,
                                                   RewritePatternSet &patterns);
 

mlir/include/mlir/Dialect/AVX512/CMakeLists.txt

-add_mlir_dialect(AVX512 avx512)
-add_mlir_doc(AVX512 -gen-dialect-doc AVX512 Dialects/)
-
-set(LLVM_TARGET_DEFINITIONS AVX512.td)
-mlir_tablegen(AVX512Conversions.inc -gen-llvmir-conversions)
-add_public_tablegen_target(MLIRAVX512ConversionsIncGen)

mlir/include/mlir/Dialect/AVX512/Transforms.h

-//===- Transforms.h - AVX512 Dialect Transformation Entrypoints -*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef MLIR_DIALECT_AVX512_TRANSFORMS_H
-#define MLIR_DIALECT_AVX512_TRANSFORMS_H
-
-namespace mlir {
-
-class LLVMConversionTarget;
-class LLVMTypeConverter;
-class RewritePatternSet;
-using OwningRewritePatternList = RewritePatternSet;
-
-/// Collect a set of patterns to lower AVX512 ops to ops that map to LLVM
-/// intrinsics.
-void populateAVX512LegalizeForLLVMExportPatterns(LLVMTypeConverter &converter,
-                                                 RewritePatternSet &patterns);
-
-/// Configure the target to support lowering AVX512 ops to ops that map to LLVM
-/// intrinsics.
-void configureAVX512LegalizeForExportTarget(LLVMConversionTarget &target);
-
-} // namespace mlir
-
-#endif // MLIR_DIALECT_AVX512_TRANSFORMS_H

mlir/include/mlir/Dialect/CMakeLists.txt

 add_subdirectory(Affine)
 add_subdirectory(Async)
 add_subdirectory(ArmNeon)
 add_subdirectory(ArmSVE)
 add_subdirectory(AMX)
-add_subdirectory(AVX512)
 add_subdirectory(Complex)
 add_subdirectory(DLTI)
 add_subdirectory(GPU)
 add_subdirectory(Math)
 add_subdirectory(Linalg)
 add_subdirectory(LLVMIR)
 add_subdirectory(MemRef)
 add_subdirectory(OpenACC)
 add_subdirectory(OpenMP)
 add_subdirectory(PDL)
 add_subdirectory(PDLInterp)
 add_subdirectory(Quant)
 add_subdirectory(SCF)
 add_subdirectory(Shape)
 add_subdirectory(SPIRV)
 add_subdirectory(StandardOps)
 add_subdirectory(Tensor)
 add_subdirectory(Tosa)
 add_subdirectory(Vector)
+add_subdirectory(X86Vector)

mlir/include/mlir/Dialect/X86Vector/CMakeLists.txt

+add_mlir_dialect(X86Vector x86vector)
+add_mlir_doc(X86Vector -gen-dialect-doc X86Vector Dialects/)
+
+set(LLVM_TARGET_DEFINITIONS X86Vector.td)
+mlir_tablegen(X86VectorConversions.inc -gen-llvmir-conversions)
+add_public_tablegen_target(MLIRX86VectorConversionsIncGen)

mlir/include/mlir/Dialect/X86Vector/Transforms.h

+//=- Transforms.h - X86Vector Dialect Transformation Entrypoints -*- C++ -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_X86VECTOR_TRANSFORMS_H
+#define MLIR_DIALECT_X86VECTOR_TRANSFORMS_H
+
+namespace mlir {
+
+class LLVMConversionTarget;
+class LLVMTypeConverter;
+class RewritePatternSet;
+using OwningRewritePatternList = RewritePatternSet;
+
+/// Collect a set of patterns to lower X86Vector ops to ops that map to LLVM
+/// intrinsics.
+void populateX86VectorLegalizeForLLVMExportPatterns(
+    LLVMTypeConverter &converter, RewritePatternSet &patterns);
+
+/// Configure the target to support lowering X86Vector ops to ops that map to
+/// LLVM intrinsics.
+void configureX86VectorLegalizeForExportTarget(LLVMConversionTarget &target);
+
+} // namespace mlir
+
+#endif // MLIR_DIALECT_X86VECTOR_TRANSFORMS_H

mlir/include/mlir/Dialect/X86Vector/X86Vector.td

-//===-- AVX512Ops.td - AVX512 dialect operation definitions *- tablegen -*-===//
+//===-- X86VectorOps.td - X86Vector dialect operation definitions *- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-// This file defines the basic operations for the AVX512 dialect.
+// This file defines the basic operations for the X86Vector dialect.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef AVX512_OPS
-#define AVX512_OPS
+#ifndef X86VECTOR_OPS
+#define X86VECTOR_OPS
 
 include "mlir/Interfaces/SideEffectInterfaces.td"
 include "mlir/Dialect/LLVMIR/LLVMOpBase.td"
 
 //===----------------------------------------------------------------------===//
-// AVX512 dialect definition
+// X86Vector dialect definition
 //===----------------------------------------------------------------------===//
 
-def AVX512_Dialect : Dialect {
-  let name = "avx512";
-  let cppNamespace = "::mlir::avx512";
+def X86Vector_Dialect : Dialect {
+  let name = "x86vector";
+  let cppNamespace = "::mlir::x86vector";
 }
 
 //===----------------------------------------------------------------------===//
 // AVX512 op definitions
 //===----------------------------------------------------------------------===//
 
 class AVX512_Op<string mnemonic, list<OpTrait> traits = []> :
-  Op<AVX512_Dialect, mnemonic, traits> {}
+  Op<X86Vector_Dialect, "avx512." # mnemonic, traits> {}
 
 class AVX512_IntrOp<string mnemonic, int numResults, list<OpTrait> traits = []> :
-  LLVM_IntrOpBase<AVX512_Dialect, "intr." # mnemonic,
+  LLVM_IntrOpBase<X86Vector_Dialect, "avx512.intr." # mnemonic,
                   "x86_avx512_" # !subst(".", "_", mnemonic),
                   [], [], traits, numResults>;
 
 // Defined by first result overload. May have to be extended for other
 // instructions in the future.
 class AVX512_IntrOverloadedOp<string mnemonic,
                               list<OpTrait> traits = []> :
-  LLVM_IntrOpBase<AVX512_Dialect, "intr." # mnemonic,
+  LLVM_IntrOpBase<X86Vector_Dialect, "avx512.intr." # mnemonic,
                   "x86_avx512_" # !subst(".", "_", mnemonic),
                   /*list<int> overloadedResults=*/[0],
                   /*list<int> overloadedOperands=*/[],
                   traits, /*numResults=*/1>;
 //----------------------------------------------------------------------------//
 // MaskCompressOp
 //----------------------------------------------------------------------------//
 

 }
 
 def Vp2IntersectQIntrOp : AVX512_IntrOp<"vp2intersect.q.512", 2, [
   NoSideEffect]> {
   let arguments = (ins VectorOfLengthAndType<[8], [I64]>:$a,
                    VectorOfLengthAndType<[8], [I64]>:$b);
 }
 
-#endif // AVX512_OPS
+#endif // X86VECTOR_OPS

mlir/include/mlir/Dialect/X86Vector/X86VectorDialect.h

-//===- AVX512Dialect.h - MLIR Dialect for AVX512 ----------------*- C++ -*-===//
+//===- X86VectorDialect.h - MLIR Dialect for X86Vector ----------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-// This file declares the Target dialect for AVX512 in MLIR.
+// This file declares the Target dialect for X86Vector in MLIR.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef MLIR_DIALECT_AVX512_AVX512DIALECT_H_
-#define MLIR_DIALECT_AVX512_AVX512DIALECT_H_
+#ifndef MLIR_DIALECT_X86VECTOR_X86VECTORDIALECT_H_
+#define MLIR_DIALECT_X86VECTOR_X86VECTORDIALECT_H_
 
 #include "mlir/IR/BuiltinTypes.h"
 #include "mlir/IR/Dialect.h"
 #include "mlir/IR/OpDefinition.h"
 #include "mlir/IR/OpImplementation.h"
 #include "mlir/Interfaces/SideEffectInterfaces.h"
 
-#include "mlir/Dialect/AVX512/AVX512Dialect.h.inc"
+#include "mlir/Dialect/X86Vector/X86VectorDialect.h.inc"
 
 #define GET_OP_CLASSES
-#include "mlir/Dialect/AVX512/AVX512.h.inc"
+#include "mlir/Dialect/X86Vector/X86Vector.h.inc"
 
-#endif // MLIR_DIALECT_AVX512_AVX512DIALECT_H_
+#endif // MLIR_DIALECT_X86VECTOR_X86VECTORDIALECT_H_

mlir/include/mlir/InitAllDialects.h

 // passes to the system.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef MLIR_INITALLDIALECTS_H_
 #define MLIR_INITALLDIALECTS_H_
 
 #include "mlir/Dialect/AMX/AMXDialect.h"
-#include "mlir/Dialect/AVX512/AVX512Dialect.h"
 #include "mlir/Dialect/Affine/IR/AffineOps.h"
 #include "mlir/Dialect/ArmNeon/ArmNeonDialect.h"
 #include "mlir/Dialect/ArmSVE/ArmSVEDialect.h"
 #include "mlir/Dialect/Async/IR/Async.h"
 #include "mlir/Dialect/Complex/IR/Complex.h"
 #include "mlir/Dialect/DLTI/DLTI.h"
 #include "mlir/Dialect/GPU/GPUDialect.h"
 #include "mlir/Dialect/LLVMIR/LLVMArmSVEDialect.h"

 #include "mlir/Dialect/SCF/SCF.h"
 #include "mlir/Dialect/SDBM/SDBMDialect.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVDialect.h"
 #include "mlir/Dialect/Shape/IR/Shape.h"
 #include "mlir/Dialect/StandardOps/IR/Ops.h"
 #include "mlir/Dialect/Tensor/IR/Tensor.h"
 #include "mlir/Dialect/Tosa/IR/TosaOps.h"
 #include "mlir/Dialect/Vector/VectorOps.h"
+#include "mlir/Dialect/X86Vector/X86VectorDialect.h"
 #include "mlir/IR/Dialect.h"
 
 namespace mlir {
 
 /// Add all the MLIR dialects to the provided registry.
 inline void registerAllDialects(DialectRegistry &registry) {
   // clang-format off
   registry.insert<acc::OpenACCDialect,
                   AffineDialect,
                   amx::AMXDialect,
                   arm_neon::ArmNeonDialect,
                   async::AsyncDialect,
-                  avx512::AVX512Dialect,
                   complex::ComplexDialect,
                   DLTIDialect,
                   gpu::GPUDialect,
                   LLVM::LLVMDialect,
                   LLVM::LLVMArmSVEDialect,
                   linalg::LinalgDialect,
                   math::MathDialect,
                   memref::MemRefDialect,
                   scf::SCFDialect,
                   omp::OpenMPDialect,
                   pdl::PDLDialect,
                   pdl_interp::PDLInterpDialect,
                   quant::QuantizationDialect,
                   spirv::SPIRVDialect,
                   StandardOpsDialect,
                   arm_sve::ArmSVEDialect,
                   vector::VectorDialect,
                   NVVM::NVVMDialect,
                   ROCDL::ROCDLDialect,
                   SDBMDialect,
                   shape::ShapeDialect,
                   tensor::TensorDialect,
-                  tosa::TosaDialect>();
+                  tosa::TosaDialect,
+                  x86vector::X86VectorDialect>();
   // clang-format on
 }
 
 /// Append all the MLIR dialects to the registry contained in the given context.
 inline void registerAllDialects(MLIRContext &context) {
   DialectRegistry registry;
   registerAllDialects(registry);
   context.appendDialectRegistry(registry);
 }
 
 } // namespace mlir
 
 #endif // MLIR_INITALLDIALECTS_H_

mlir/include/mlir/Target/LLVMIR/Dialect/AVX512/AVX512ToLLVMIRTranslation.h

-//===- AVX512ToLLVMIRTranslation.h - AVX512 to LLVM IR ----------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This provides registration calls for AVX512 dialect to LLVM IR
-// translation.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef MLIR_TARGET_LLVMIR_DIALECT_AVX512_AVX512TOLLVMIRTRANSLATION_H
-#define MLIR_TARGET_LLVMIR_DIALECT_AVX512_AVX512TOLLVMIRTRANSLATION_H
-
-namespace mlir {
-
-class DialectRegistry;
-class MLIRContext;
-
-/// Register the AVX512 dialect and the translation from it to the LLVM IR
-/// in the given registry;
-void registerAVX512DialectTranslation(DialectRegistry &registry);
-
-/// Register the AVX512 dialect and the translation from it in the registry
-/// associated with the given context.
-void registerAVX512DialectTranslation(MLIRContext &context);
-
-} // namespace mlir
-
-#endif // MLIR_TARGET_LLVMIR_DIALECT_AVX512_AVX512TOLLVMIRTRANSLATION_H

mlir/include/mlir/Target/LLVMIR/Dialect/All.h

 // dialects to LLVM IR.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef MLIR_TARGET_LLVMIR_DIALECT_ALL_H
 #define MLIR_TARGET_LLVMIR_DIALECT_ALL_H
 
 #include "mlir/Target/LLVMIR/Dialect/AMX/AMXToLLVMIRTranslation.h"
-#include "mlir/Target/LLVMIR/Dialect/AVX512/AVX512ToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/ArmNeon/ArmNeonToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/LLVMArmSVE/LLVMArmSVEToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/ROCDL/ROCDLToLLVMIRTranslation.h"
+#include "mlir/Target/LLVMIR/Dialect/X86Vector/X86VectorToLLVMIRTranslation.h"
 
 namespace mlir {
 class DialectRegistry;
 
 /// Registers all dialects that can be translated to LLVM IR and the
 /// corresponding translation interfaces.
 static inline void registerAllToLLVMIRTranslations(DialectRegistry &registry) {
   registerArmNeonDialectTranslation(registry);
   registerAMXDialectTranslation(registry);
-  registerAVX512DialectTranslation(registry);
   registerLLVMArmSVEDialectTranslation(registry);
   registerLLVMDialectTranslation(registry);
   registerNVVMDialectTranslation(registry);
   registerOpenMPDialectTranslation(registry);
   registerROCDLDialectTranslation(registry);
+  registerX86VectorDialectTranslation(registry);
 }
 } // namespace mlir
 
 #endif // MLIR_TARGET_LLVMIR_DIALECT_ALL_H

mlir/include/mlir/Target/LLVMIR/Dialect/X86Vector/X86VectorToLLVMIRTranslation.h

+//===- X86VectorToLLVMIRTranslation.h - X86Vector to LLVM IR ----*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This provides registration calls for X86Vector dialect to LLVM IR
+// translation.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_TARGET_LLVMIR_DIALECT_X86VECTOR_X86VECTORTOLLVMIRTRANSLATION_H
+#define MLIR_TARGET_LLVMIR_DIALECT_X86VECTOR_X86VECTORTOLLVMIRTRANSLATION_H
+
+namespace mlir {
+
+class DialectRegistry;
+class MLIRContext;
+
+/// Register the X86Vector dialect and the translation from it to the LLVM IR
+/// in the given registry;
+void registerX86VectorDialectTranslation(DialectRegistry &registry);
+
+/// Register the X86Vector dialect and the translation from it in the registry
+/// associated with the given context.
+void registerX86VectorDialectTranslation(MLIRContext &context);
+
+} // namespace mlir
+
+#endif // MLIR_TARGET_LLVMIR_DIALECT_X86VECTOR_X86VECTORTOLLVMIRTRANSLATION_H

mlir/lib/Conversion/VectorToLLVM/CMakeLists.txt

add_mlir_conversion_library(MLIRVectorToLLVM
 
   LINK_COMPONENTS
   Core
 
   LINK_LIBS PUBLIC
   MLIRArmNeon
   MLIRAMX
   MLIRAMXTransforms
-  MLIRAVX512
-  MLIRAVX512Transforms
   MLIRArmSVE
   MLIRArmSVEToLLVM
   MLIRLLVMArmSVE
   MLIRLLVMIR
   MLIRMemRef
   MLIRStandardToLLVM
   MLIRTargetLLVMIRExport
   MLIRTransforms
   MLIRVector
+  MLIRX86Vector
+  MLIRX86VectorTransforms
   )

mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVMPass.cpp

 
 #include "../PassDetail.h"
 
 #include "mlir/Conversion/ArmSVEToLLVM/ArmSVEToLLVM.h"
 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h"
 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h"
 #include "mlir/Dialect/AMX/AMXDialect.h"
 #include "mlir/Dialect/AMX/Transforms.h"
-#include "mlir/Dialect/AVX512/AVX512Dialect.h"
-#include "mlir/Dialect/AVX512/Transforms.h"
 #include "mlir/Dialect/ArmNeon/ArmNeonDialect.h"
 #include "mlir/Dialect/ArmSVE/ArmSVEDialect.h"
 #include "mlir/Dialect/LLVMIR/LLVMArmSVEDialect.h"
 #include "mlir/Dialect/LLVMIR/LLVMDialect.h"
 #include "mlir/Dialect/MemRef/IR/MemRef.h"
 #include "mlir/Dialect/StandardOps/IR/Ops.h"
 #include "mlir/Dialect/Vector/VectorOps.h"
+#include "mlir/Dialect/X86Vector/Transforms.h"
+#include "mlir/Dialect/X86Vector/X86VectorDialect.h"
 #include "mlir/Transforms/GreedyPatternRewriteDriver.h"
 
 using namespace mlir;
 using namespace mlir::vector;
 
 namespace {
 struct LowerVectorToLLVMPass
     : public ConvertVectorToLLVMBase<LowerVectorToLLVMPass> {
   LowerVectorToLLVMPass(const LowerVectorToLLVMOptions &options) {
     this->reassociateFPReductions = options.reassociateFPReductions;
     this->enableIndexOptimizations = options.enableIndexOptimizations;
     this->enableArmNeon = options.enableArmNeon;
     this->enableArmSVE = options.enableArmSVE;
     this->enableAMX = options.enableAMX;
-    this->enableAVX512 = options.enableAVX512;
+    this->enableX86Vector = options.enableX86Vector;
   }
   // Override explicitly to allow conditional dialect dependence.
   void getDependentDialects(DialectRegistry &registry) const override {
     registry.insert<LLVM::LLVMDialect>();
     registry.insert<memref::MemRefDialect>();
     if (enableArmNeon)
       registry.insert<arm_neon::ArmNeonDialect>();
     if (enableArmSVE)
       registry.insert<LLVM::LLVMArmSVEDialect>();
     if (enableAMX)
       registry.insert<amx::AMXDialect>();
-    if (enableAVX512)
-      registry.insert<avx512::AVX512Dialect>();
+    if (enableX86Vector)
+      registry.insert<x86vector::X86VectorDialect>();
   }
   void runOnOperation() override;
 };
 } // namespace
 
 void LowerVectorToLLVMPass::runOnOperation() {
   // Perform progressive lowering of operations on slices and
   // all contraction operations. Also applies folding and DCE.
target.addDynamicallyLegalOp<CallOp, CallIndirectOp, ReturnOp>(
                  !hasScalableVectorType(op->getResultTypes());
         });
     populateArmSVEToLLVMConversionPatterns(converter, patterns);
   }
   if (enableAMX) {
     configureAMXLegalizeForExportTarget(target);
     populateAMXLegalizeForLLVMExportPatterns(converter, patterns);
   }
-  if (enableAVX512) {
-    configureAVX512LegalizeForExportTarget(target);
-    populateAVX512LegalizeForLLVMExportPatterns(converter, patterns);
+  if (enableX86Vector) {
+    configureX86VectorLegalizeForExportTarget(target);
+    populateX86VectorLegalizeForLLVMExportPatterns(converter, patterns);
   }
 
   if (failed(
           applyPartialConversion(getOperation(), target, std::move(patterns))))
     signalPassFailure();
 }
 
 std::unique_ptr<OperationPass<ModuleOp>>
 mlir::createConvertVectorToLLVMPass(const LowerVectorToLLVMOptions &options) {
   return std::make_unique<LowerVectorToLLVMPass>(options);
 }

mlir/lib/Dialect/AVX512/IR/CMakeLists.txt

-add_mlir_dialect_library(MLIRAVX512
-  AVX512Dialect.cpp
-
-  ADDITIONAL_HEADER_DIRS
-  ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/AVX512
-
-  DEPENDS
-  MLIRAVX512IncGen
-
-  LINK_LIBS PUBLIC
-  MLIRIR
-  MLIRLLVMIR
-  MLIRSideEffectInterfaces
-  )

mlir/lib/Dialect/CMakeLists.txt

 add_subdirectory(Affine)
 add_subdirectory(ArmNeon)
 add_subdirectory(ArmSVE)
 add_subdirectory(Async)
 add_subdirectory(AMX)
-add_subdirectory(AVX512)
 add_subdirectory(Complex)
 add_subdirectory(DLTI)
 add_subdirectory(GPU)
 add_subdirectory(Linalg)
 add_subdirectory(LLVMIR)
 add_subdirectory(Math)
 add_subdirectory(MemRef)
 add_subdirectory(OpenACC)
 add_subdirectory(OpenMP)
 add_subdirectory(PDL)
 add_subdirectory(PDLInterp)
 add_subdirectory(Quant)
 add_subdirectory(SCF)
 add_subdirectory(SDBM)
 add_subdirectory(Shape)
 add_subdirectory(SPIRV)
 add_subdirectory(StandardOps)
 add_subdirectory(Tensor)
 add_subdirectory(Tosa)
 add_subdirectory(Utils)
 add_subdirectory(Vector)
+add_subdirectory(X86Vector)
 
 set(LLVM_OPTIONAL_SOURCES
   Traits.cpp
 )
 
 add_mlir_library(MLIRDialect
   Traits.cpp
 
   ADDITIONAL_HEADER_DIRS
   ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect
 
   LINK_LIBS PUBLIC
   MLIRIR
   )

mlir/lib/Dialect/X86Vector/CMakeLists.txt

 add_subdirectory(IR)
 add_subdirectory(Transforms)

mlir/lib/Dialect/X86Vector/IR/CMakeLists.txt

+add_mlir_dialect_library(MLIRX86Vector
+  X86VectorDialect.cpp
+
+  ADDITIONAL_HEADER_DIRS
+  ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/X86Vector
+
+  DEPENDS
+  MLIRX86VectorIncGen
+
+  LINK_LIBS PUBLIC
+  MLIRIR
+  MLIRLLVMIR
+  MLIRSideEffectInterfaces
+  )

mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp

-//===- AVX512Ops.cpp - MLIR AVX512 ops implementation ---------------------===//
+//===- X86VectorDialect.cpp - MLIR X86Vector ops implementation -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements the AVX512 dialect and its operations.
+// This file implements the X86Vector dialect and its operations.
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Dialect/AVX512/AVX512Dialect.h"
+#include "mlir/Dialect/X86Vector/X86VectorDialect.h"
 #include "mlir/Dialect/LLVMIR/LLVMTypes.h"
 #include "mlir/IR/Builders.h"
 #include "mlir/IR/OpImplementation.h"
 #include "mlir/IR/TypeUtilities.h"
 
 using namespace mlir;
 
-void avx512::AVX512Dialect::initialize() {
+void x86vector::X86VectorDialect::initialize() {
   addOperations<
 #define GET_OP_LIST
-#include "mlir/Dialect/AVX512/AVX512.cpp.inc"
+#include "mlir/Dialect/X86Vector/X86Vector.cpp.inc"
       >();
 }
 
-static LogicalResult verify(avx512::MaskCompressOp op) {
+static LogicalResult verify(x86vector::MaskCompressOp op) {
   if (op.src() && op.constant_src())
     return emitError(op.getLoc(), "cannot use both src and constant_src");
 
   if (op.src() && (op.src().getType() != op.dst().getType()))
     return emitError(op.getLoc(),
                      "failed to verify that src and dst have same type");
 
   if (op.constant_src() && (op.constant_src()->getType() != op.dst().getType()))
     return emitError(
         op.getLoc(),
         "failed to verify that constant_src and dst have same type");
 
   return success();
 }
 
 #define GET_OP_CLASSES
-#include "mlir/Dialect/AVX512/AVX512.cpp.inc"
+#include "mlir/Dialect/X86Vector/X86Vector.cpp.inc"

mlir/lib/Dialect/X86Vector/Transforms/CMakeLists.txt

-add_mlir_dialect_library(MLIRAVX512Transforms
+add_mlir_dialect_library(MLIRX86VectorTransforms
   LegalizeForLLVMExport.cpp
 
   DEPENDS
-  MLIRAVX512ConversionsIncGen
+  MLIRX86VectorConversionsIncGen
 
   LINK_LIBS PUBLIC
-  MLIRAVX512
+  MLIRX86Vector
   MLIRIR
   MLIRLLVMIR
   MLIRStandardToLLVM
   )

mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp

-//===- LegalizeForLLVMExport.cpp - Prepare AVX512 for LLVM translation ----===//
+//===- LegalizeForLLVMExport.cpp - Prepare X86Vector for LLVM translation
+//----===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Dialect/AVX512/Transforms.h"
+#include "mlir/Dialect/X86Vector/Transforms.h"
 
 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h"
-#include "mlir/Dialect/AVX512/AVX512Dialect.h"
 #include "mlir/Dialect/LLVMIR/LLVMDialect.h"
 #include "mlir/Dialect/StandardOps/IR/Ops.h"
+#include "mlir/Dialect/X86Vector/X86VectorDialect.h"
 #include "mlir/IR/BuiltinOps.h"
 #include "mlir/IR/PatternMatch.h"
 
 using namespace mlir;
-using namespace mlir::avx512;
+using namespace mlir::x86vector;
 
-/// Extracts the "main" vector element type from the given AVX512 operation.
+/// Extracts the "main" vector element type from the given X86Vector operation.
 template <typename OpTy>
 static Type getSrcVectorElementType(OpTy op) {
   return op.src().getType().template cast<VectorType>().getElementType();
 }
 template <>
 Type getSrcVectorElementType(Vp2IntersectOp op) {
   return op.a().getType().template cast<VectorType>().getElementType();
 }
 
 namespace {
+
 /// Base conversion for AVX512 ops that can be lowered to one of the two
 /// intrinsics based on the bitwidth of their "main" vector element type. This
 /// relies on the to-LLVM-dialect conversion helpers to correctly pack the
 /// results of multi-result intrinsic ops.
 template <typename OpTy, typename Intr32OpTy, typename Intr64OpTy>
 struct LowerToIntrinsic : public OpConversionPattern<OpTy> {
   explicit LowerToIntrinsic(LLVMTypeConverter &converter)
       : OpConversionPattern<OpTy>(converter, &converter.getContext()) {}

 
 using Registry = RegistryImpl<
     RegEntry<MaskRndScaleOp, MaskRndScalePSIntrOp, MaskRndScalePDIntrOp>,
     RegEntry<MaskScaleFOp, MaskScaleFPSIntrOp, MaskScaleFPDIntrOp>,
     RegEntry<Vp2IntersectOp, Vp2IntersectDIntrOp, Vp2IntersectQIntrOp>>;
 
 } // namespace
 
-/// Populate the given list with patterns that convert from AVX512 to LLVM.
-void mlir::populateAVX512LegalizeForLLVMExportPatterns(
+/// Populate the given list with patterns that convert from X86Vector to LLVM.
+void mlir::populateX86VectorLegalizeForLLVMExportPatterns(
     LLVMTypeConverter &converter, RewritePatternSet &patterns) {
   Registry::registerPatterns(converter, patterns);
   patterns.add<MaskCompressOpConversion>(converter);
 }
 
-void mlir::configureAVX512LegalizeForExportTarget(
+void mlir::configureX86VectorLegalizeForExportTarget(
     LLVMConversionTarget &target) {
   Registry::configureTarget(target);
   target.addLegalOp<MaskCompressIntrOp>();
   target.addIllegalOp<MaskCompressOp>();
 }

mlir/lib/Target/LLVMIR/CMakeLists.txt

add_mlir_translation_library(MLIRTargetLLVMIRExport
   )
 
 add_mlir_translation_library(MLIRToLLVMIRTranslationRegistration
   ConvertToLLVMIR.cpp
 
   LINK_LIBS PUBLIC
   MLIRArmNeonToLLVMIRTranslation
   MLIRAMXToLLVMIRTranslation
-  MLIRAVX512ToLLVMIRTranslation
+  MLIRX86VectorToLLVMIRTranslation
   MLIRLLVMArmSVEToLLVMIRTranslation
   MLIRLLVMToLLVMIRTranslation
   MLIRNVVMToLLVMIRTranslation
   MLIROpenMPToLLVMIRTranslation
   MLIRROCDLToLLVMIRTranslation
   )
 
 add_mlir_translation_library(MLIRTargetLLVMIRImport

mlir/lib/Target/LLVMIR/Dialect/AVX512/CMakeLists.txt

-add_mlir_translation_library(MLIRAVX512ToLLVMIRTranslation
-  AVX512ToLLVMIRTranslation.cpp
-
-  DEPENDS
-  MLIRAVX512ConversionsIncGen
-
-  LINK_COMPONENTS
-  Core
-
-  LINK_LIBS PUBLIC
-  MLIRIR
-  MLIRAVX512
-  MLIRLLVMIR
-  MLIRSupport
-  MLIRTargetLLVMIRExport
-  )

mlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt

 add_subdirectory(ArmNeon)
 add_subdirectory(AMX)
-add_subdirectory(AVX512)
 add_subdirectory(LLVMArmSVE)
 add_subdirectory(LLVMIR)
 add_subdirectory(NVVM)
 add_subdirectory(OpenMP)
 add_subdirectory(ROCDL)
+add_subdirectory(X86Vector)

mlir/lib/Target/LLVMIR/Dialect/X86Vector/CMakeLists.txt

+add_mlir_translation_library(MLIRX86VectorToLLVMIRTranslation
+  X86VectorToLLVMIRTranslation.cpp
+
+  DEPENDS
+  MLIRX86VectorConversionsIncGen
+
+  LINK_COMPONENTS
+  Core
+
+  LINK_LIBS PUBLIC
+  MLIRIR
+  MLIRX86Vector
+  MLIRLLVMIR
+  MLIRSupport
+  MLIRTargetLLVMIRExport
+  )

mlir/lib/Target/LLVMIR/Dialect/X86Vector/X86VectorToLLVMIRTranslation.cpp

-//===- AVX512ToLLVMIRTranslation.cpp - Translate AVX512 to LLVM IR---------===//
+//===- X86VectorToLLVMIRTranslation.cpp - Translate X86Vector to LLVM IR---===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements a translation between the MLIR AVX512 dialect and
+// This file implements a translation between the MLIR X86Vector dialect and
 // LLVM IR.
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Target/LLVMIR/Dialect/AVX512/AVX512ToLLVMIRTranslation.h"
-#include "mlir/Dialect/AVX512/AVX512Dialect.h"
+#include "mlir/Target/LLVMIR/Dialect/X86Vector/X86VectorToLLVMIRTranslation.h"
+#include "mlir/Dialect/X86Vector/X86VectorDialect.h"
 #include "mlir/IR/Operation.h"
 #include "mlir/Target/LLVMIR/ModuleTranslation.h"
 
 #include "llvm/IR/IRBuilder.h"
 #include "llvm/IR/IntrinsicsX86.h"
 
 using namespace mlir;
 using namespace mlir::LLVM;
 
 namespace {
 /// Implementation of the dialect interface that converts operations belonging
-/// to the AVX512 dialect to LLVM IR.
-class AVX512DialectLLVMIRTranslationInterface
+/// to the X86Vector dialect to LLVM IR.
+class X86VectorDialectLLVMIRTranslationInterface
     : public LLVMTranslationDialectInterface {
 public:
   using LLVMTranslationDialectInterface::LLVMTranslationDialectInterface;
 
   /// Translates the given operation to LLVM IR using the provided IR builder
   /// and saving the state in `moduleTranslation`.
   LogicalResult
   convertOperation(Operation *op, llvm::IRBuilderBase &builder,
                    LLVM::ModuleTranslation &moduleTranslation) const final {
     Operation &opInst = *op;
-#include "mlir/Dialect/AVX512/AVX512Conversions.inc"
+#include "mlir/Dialect/X86Vector/X86VectorConversions.inc"
 
     return failure();
   }
 };
 } // end namespace
 
-void mlir::registerAVX512DialectTranslation(DialectRegistry &registry) {
-  registry.insert<avx512::AVX512Dialect>();
-  registry.addDialectInterface<avx512::AVX512Dialect,
-                               AVX512DialectLLVMIRTranslationInterface>();
+void mlir::registerX86VectorDialectTranslation(DialectRegistry &registry) {
+  registry.insert<x86vector::X86VectorDialect>();
+  registry.addDialectInterface<x86vector::X86VectorDialect,
+                               X86VectorDialectLLVMIRTranslationInterface>();
 }
 
-void mlir::registerAVX512DialectTranslation(MLIRContext &context) {
+void mlir::registerX86VectorDialectTranslation(MLIRContext &context) {
   DialectRegistry registry;
-  registerAVX512DialectTranslation(registry);
+  registerX86VectorDialectTranslation(registry);
   context.appendDialectRegistry(registry);
 }

mlir/test/CMakeLists.txt

 # for the mlir spirv / vulkan runner tests.
 set(MLIR_SPIRV_WRAPPER_LIBRARY_DIR ${CMAKE_LIBRARY_OUTPUT_DIRECTORY})
 set(MLIR_VULKAN_WRAPPER_LIBRARY_DIR ${CMAKE_LIBRARY_OUTPUT_DIRECTORY})
 
 if (MLIR_INCLUDE_INTEGRATION_TESTS)
   set(INTEL_SDE_EXECUTABLE "" CACHE STRING
       "If set, arch-specific integration tests are run with Intel SDE.")
   option(MLIR_RUN_AMX_TESTS "Run AMX tests.")
-  option(MLIR_RUN_AVX512_TESTS "Run AVX512 tests.")
+  option(MLIR_RUN_X86VECTOR_TESTS "Run X86Vector tests.")
   # Passed to lit.site.cfg.py.in to set up the path where to find the libraries.
   set(MLIR_INTEGRATION_TEST_DIR ${CMAKE_LIBRARY_OUTPUT_DIRECTORY})
 
   # Copy test data over.
   file(COPY ${CMAKE_CURRENT_SOURCE_DIR}/Integration/data/test.mtx
             ${CMAKE_CURRENT_SOURCE_DIR}/Integration/data/test.tns
             ${CMAKE_CURRENT_SOURCE_DIR}/Integration/data/wide.mtx
           DESTINATION ${MLIR_INTEGRATION_TEST_DIR}/data/)

mlir/test/Dialect/AVX512/legalize-for-llvm.mlir

-// RUN: mlir-opt %s -convert-vector-to-llvm="enable-avx512" | mlir-opt | FileCheck %s
-
-func @avx512_mask_rndscale(%a: vector<16xf32>, %b: vector<8xf64>, %i32: i32, %i16: i16, %i8: i8)
-  -> (vector<16xf32>, vector<8xf64>, vector<16xf32>, vector<8xf64>)
-{
-  // CHECK: avx512.intr.mask.rndscale.ps.512
-  %0 = avx512.mask.rndscale %a, %i32, %a, %i16, %i32: vector<16xf32>
-  // CHECK: avx512.intr.mask.rndscale.pd.512
-  %1 = avx512.mask.rndscale %b, %i32, %b, %i8, %i32: vector<8xf64>
-
-  // CHECK: avx512.intr.mask.scalef.ps.512
-  %2 = avx512.mask.scalef %a, %a, %a, %i16, %i32: vector<16xf32>
-  // CHECK: avx512.intr.mask.scalef.pd.512
-  %3 = avx512.mask.scalef %b, %b, %b, %i8, %i32: vector<8xf64>
-
-  // Keep results alive.
-  return %0, %1, %2, %3 : vector<16xf32>, vector<8xf64>, vector<16xf32>, vector<8xf64>
-}
-
-func @avx512_mask_compress(%k1: vector<16xi1>, %a1: vector<16xf32>,
-                           %k2: vector<8xi1>, %a2: vector<8xi64>)
-  -> (vector<16xf32>, vector<16xf32>, vector<8xi64>)
-{
-  // CHECK: avx512.intr.mask.compress
-  %0 = avx512.mask.compress %k1, %a1 : vector<16xf32>
-  // CHECK: avx512.intr.mask.compress
-  %1 = avx512.mask.compress %k1, %a1 {constant_src = dense<5.0> : vector<16xf32>} : vector<16xf32>
-  // CHECK: avx512.intr.mask.compress
-  %2 = avx512.mask.compress %k2, %a2, %a2 : vector<8xi64>, vector<8xi64>
-  return %0, %1, %2 : vector<16xf32>, vector<16xf32>, vector<8xi64>
-}
-
-func @avx512_vp2intersect(%a: vector<16xi32>, %b: vector<8xi64>)
-  -> (vector<16xi1>, vector<16xi1>, vector<8xi1>, vector<8xi1>)
-{
-  // CHECK: avx512.intr.vp2intersect.d.512
-  %0, %1 = avx512.vp2intersect %a, %a : vector<16xi32>
-  // CHECK: avx512.intr.vp2intersect.q.512
-  %2, %3 = avx512.vp2intersect %b, %b : vector<8xi64>
-  return %0, %1, %2, %3 : vector<16xi1>, vector<16xi1>, vector<8xi1>, vector<8xi1>
-}

mlir/test/Dialect/AVX512/roundtrip.mlir

-// RUN: mlir-opt -verify-diagnostics %s | mlir-opt | FileCheck %s
-
-func @avx512_mask_rndscale(%a: vector<16xf32>, %b: vector<8xf64>, %i32: i32, %i16: i16, %i8: i8)
-  -> (vector<16xf32>, vector<8xf64>)
-{
-  // CHECK: avx512.mask.rndscale {{.*}}: vector<16xf32>
-  %0 = avx512.mask.rndscale %a, %i32, %a, %i16, %i32 : vector<16xf32>
-  // CHECK: avx512.mask.rndscale {{.*}}: vector<8xf64>
-  %1 = avx512.mask.rndscale %b, %i32, %b, %i8, %i32 : vector<8xf64>
-  return %0, %1: vector<16xf32>, vector<8xf64>
-}
-
-func @avx512_scalef(%a: vector<16xf32>, %b: vector<8xf64>, %i32: i32, %i16: i16, %i8: i8)
-  -> (vector<16xf32>, vector<8xf64>)
-{
-  // CHECK: avx512.mask.scalef {{.*}}: vector<16xf32>
-  %0 = avx512.mask.scalef %a, %a, %a, %i16, %i32: vector<16xf32>
-  // CHECK: avx512.mask.scalef {{.*}}: vector<8xf64>
-  %1 = avx512.mask.scalef %b, %b, %b, %i8, %i32 : vector<8xf64>
-  return %0, %1: vector<16xf32>, vector<8xf64>
-}
-
-func @avx512_vp2intersect(%a: vector<16xi32>, %b: vector<8xi64>)
-  -> (vector<16xi1>, vector<16xi1>, vector<8xi1>, vector<8xi1>)
-{
-  // CHECK: avx512.vp2intersect {{.*}} : vector<16xi32>
-  %0, %1 = avx512.vp2intersect %a, %a : vector<16xi32>
-  // CHECK: avx512.vp2intersect {{.*}} : vector<8xi64>
-  %2, %3 = avx512.vp2intersect %b, %b : vector<8xi64>
-  return %0, %1, %2, %3 : vector<16xi1>, vector<16xi1>, vector<8xi1>, vector<8xi1>
-}
-
-func @avx512_mask_compress(%k1: vector<16xi1>, %a1: vector<16xf32>,
-                           %k2: vector<8xi1>, %a2: vector<8xi64>)
-  -> (vector<16xf32>, vector<16xf32>, vector<8xi64>)
-{
-  // CHECK: avx512.mask.compress {{.*}} : vector<16xf32>
-  %0 = avx512.mask.compress %k1, %a1 : vector<16xf32>
-  // CHECK: avx512.mask.compress {{.*}} : vector<16xf32>
-  %1 = avx512.mask.compress %k1, %a1 {constant_src = dense<5.0> : vector<16xf32>} : vector<16xf32>
-  // CHECK: avx512.mask.compress {{.*}} : vector<8xi64>
-  %2 = avx512.mask.compress %k2, %a2, %a2 : vector<8xi64>, vector<8xi64>
-  return %0, %1, %2 : vector<16xf32>, vector<16xf32>, vector<8xi64>
-}

mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir

+// RUN: mlir-opt %s -convert-vector-to-llvm="enable-x86vector" | mlir-opt | FileCheck %s
+
+// CHECK-LABEL: func @avx512_mask_rndscale
+func @avx512_mask_rndscale(%a: vector<16xf32>, %b: vector<8xf64>, %i32: i32, %i16: i16, %i8: i8)
+  -> (vector<16xf32>, vector<8xf64>, vector<16xf32>, vector<8xf64>)
+{
+  // CHECK: x86vector.avx512.intr.mask.rndscale.ps.512
+  %0 = x86vector.avx512.mask.rndscale %a, %i32, %a, %i16, %i32: vector<16xf32>
+  // CHECK: x86vector.avx512.intr.mask.rndscale.pd.512
+  %1 = x86vector.avx512.mask.rndscale %b, %i32, %b, %i8, %i32: vector<8xf64>
+
+  // CHECK: x86vector.avx512.intr.mask.scalef.ps.512
+  %2 = x86vector.avx512.mask.scalef %a, %a, %a, %i16, %i32: vector<16xf32>
+  // CHECK: x86vector.avx512.intr.mask.scalef.pd.512
+  %3 = x86vector.avx512.mask.scalef %b, %b, %b, %i8, %i32: vector<8xf64>
+
+  // Keep results alive.
+  return %0, %1, %2, %3 : vector<16xf32>, vector<8xf64>, vector<16xf32>, vector<8xf64>
+}
+
+// CHECK-LABEL: func @avx512_mask_compress
+func @avx512_mask_compress(%k1: vector<16xi1>, %a1: vector<16xf32>,
+                           %k2: vector<8xi1>, %a2: vector<8xi64>)
+  -> (vector<16xf32>, vector<16xf32>, vector<8xi64>)
+{
+  // CHECK: x86vector.avx512.intr.mask.compress
+  %0 = x86vector.avx512.mask.compress %k1, %a1 : vector<16xf32>
+  // CHECK: x86vector.avx512.intr.mask.compress
+  %1 = x86vector.avx512.mask.compress %k1, %a1 {constant_src = dense<5.0> : vector<16xf32>} : vector<16xf32>
+  // CHECK: x86vector.avx512.intr.mask.compress
+  %2 = x86vector.avx512.mask.compress %k2, %a2, %a2 : vector<8xi64>, vector<8xi64>
+  return %0, %1, %2 : vector<16xf32>, vector<16xf32>, vector<8xi64>
+}
+
+// CHECK-LABEL: func @avx512_vp2intersect
+func @avx512_vp2intersect(%a: vector<16xi32>, %b: vector<8xi64>)
+  -> (vector<16xi1>, vector<16xi1>, vector<8xi1>, vector<8xi1>)
+{
+  // CHECK: x86vector.avx512.intr.vp2intersect.d.512
+  %0, %1 = x86vector.avx512.vp2intersect %a, %a : vector<16xi32>
+  // CHECK: x86vector.avx512.intr.vp2intersect.q.512
+  %2, %3 = x86vector.avx512.vp2intersect %b, %b : vector<8xi64>
+  return %0, %1, %2, %3 : vector<16xi1>, vector<16xi1>, vector<8xi1>, vector<8xi1>
+}

mlir/test/Dialect/X86Vector/roundtrip.mlir

+// RUN: mlir-opt -verify-diagnostics %s | mlir-opt | FileCheck %s
+
+// CHECK-LABEL: func @avx512_mask_rndscale
+func @avx512_mask_rndscale(%a: vector<16xf32>, %b: vector<8xf64>, %i32: i32, %i16: i16, %i8: i8)
+  -> (vector<16xf32>, vector<8xf64>)
+{
+  // CHECK: x86vector.avx512.mask.rndscale {{.*}}: vector<16xf32>
+  %0 = x86vector.avx512.mask.rndscale %a, %i32, %a, %i16, %i32 : vector<16xf32>
+  // CHECK: x86vector.avx512.mask.rndscale {{.*}}: vector<8xf64>
+  %1 = x86vector.avx512.mask.rndscale %b, %i32, %b, %i8, %i32 : vector<8xf64>
+  return %0, %1: vector<16xf32>, vector<8xf64>
+}
+
+// CHECK-LABEL: func @avx512_scalef
+func @avx512_scalef(%a: vector<16xf32>, %b: vector<8xf64>, %i32: i32, %i16: i16, %i8: i8)
+  -> (vector<16xf32>, vector<8xf64>)
+{
+  // CHECK: x86vector.avx512.mask.scalef {{.*}}: vector<16xf32>
+  %0 = x86vector.avx512.mask.scalef %a, %a, %a, %i16, %i32: vector<16xf32>
+  // CHECK: x86vector.avx512.mask.scalef {{.*}}: vector<8xf64>
+  %1 = x86vector.avx512.mask.scalef %b, %b, %b, %i8, %i32 : vector<8xf64>
+  return %0, %1: vector<16xf32>, vector<8xf64>
+}
+
+// CHECK-LABEL: func @avx512_vp2intersect
+func @avx512_vp2intersect(%a: vector<16xi32>, %b: vector<8xi64>)
+  -> (vector<16xi1>, vector<16xi1>, vector<8xi1>, vector<8xi1>)
+{
+  // CHECK: x86vector.avx512.vp2intersect {{.*}} : vector<16xi32>
+  %0, %1 = x86vector.avx512.vp2intersect %a, %a : vector<16xi32>
+  // CHECK: x86vector.avx512.vp2intersect {{.*}} : vector<8xi64>
+  %2, %3 = x86vector.avx512.vp2intersect %b, %b : vector<8xi64>
+  return %0, %1, %2, %3 : vector<16xi1>, vector<16xi1>, vector<8xi1>, vector<8xi1>
+}
+
+// CHECK-LABEL: func @avx512_mask_compress
+func @avx512_mask_compress(%k1: vector<16xi1>, %a1: vector<16xf32>,
+                           %k2: vector<8xi1>, %a2: vector<8xi64>)
+  -> (vector<16xf32>, vector<16xf32>, vector<8xi64>)
+{
+  // CHECK: x86vector.avx512.mask.compress {{.*}} : vector<16xf32>
+  %0 = x86vector.avx512.mask.compress %k1, %a1 : vector<16xf32>
+  // CHECK: x86vector.avx512.mask.compress {{.*}} : vector<16xf32>
+  %1 = x86vector.avx512.mask.compress %k1, %a1 {constant_src = dense<5.0> : vector<16xf32>} : vector<16xf32>
+  // CHECK: x86vector.avx512.mask.compress {{.*}} : vector<8xi64>
+  %2 = x86vector.avx512.mask.compress %k2, %a2, %a2 : vector<8xi64>, vector<8xi64>
+  return %0, %1, %2 : vector<16xf32>, vector<16xf32>, vector<8xi64>
+}

mlir/test/Integration/Dialect/Vector/CPU/X86Vector/lit.local.cfg

 import sys
 
-# AVX512 tests must be enabled via build flag.
-if config.mlir_run_avx512_tests != 'ON':
+# X86Vector tests must be enabled via build flag.
+if config.mlir_run_x86vector_tests != 'ON':
     config.unsupported = True
 
 # No JIT on win32.
 if sys.platform == 'win32':
     config.unsupported = True
 
 if config.intel_sde_executable:
     # Run test in emulator (Intel SDE).
     config.substitutions.append(('%lli', config.intel_sde_executable + ' -tgl -- lli'))
 else:
     config.substitutions.append(('%lli', 'lli'))

mlir/test/Integration/Dialect/Vector/CPU/X86Vector/test-mask-compress.mlir

-// RUN: mlir-opt %s -convert-scf-to-std -convert-vector-to-llvm="enable-avx512" -convert-std-to-llvm  | \
+// RUN: mlir-opt %s -convert-scf-to-std -convert-vector-to-llvm="enable-x86vector" -convert-std-to-llvm  | \
 // RUN: mlir-translate  --mlir-to-llvmir | \
 // RUN: %lli --entry-function=entry --mattr="avx512bw" --dlopen=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \
 // RUN: FileCheck %s
 
 func @entry() -> i32 {
   %i0 = constant 0 : i32
 
   %a = std.constant dense<[1., 0., 0., 2., 4., 3., 5., 7., 8., 1., 5., 5., 3., 1., 0., 7.]> : vector<16xf32>
   %k = std.constant dense<[1,  0,  1,  1,  1,  0,  0,  0,  0,  0,  1,  1,  1,  1,  1,  0]> : vector<16xi1>
-  %r1 = avx512.mask.compress %k, %a : vector<16xf32>
-  %r2 = avx512.mask.compress %k, %a {constant_src = dense<5.0> : vector<16xf32>} : vector<16xf32>
+  %r1 = x86vector.avx512.mask.compress %k, %a : vector<16xf32>
+  %r2 = x86vector.avx512.mask.compress %k, %a {constant_src = dense<5.0> : vector<16xf32>} : vector<16xf32>
 
   vector.print %r1 : vector<16xf32>
   // CHECK: ( 1, 0, 2, 4, 5, 5, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0 )
 
   vector.print %r2 : vector<16xf32>
   // CHECK: ( 1, 0, 2, 4, 5, 5, 3, 1, 0, 5, 5, 5, 5, 5, 5, 5 )
 
   %src = std.constant dense<[0., 2., 1., 8., 6., 4., 4., 3., 2., 8., 5., 6., 3., 7., 6., 9.]> : vector<16xf32>
-  %r3 = avx512.mask.compress %k, %a, %src : vector<16xf32>, vector<16xf32>
+  %r3 = x86vector.avx512.mask.compress %k, %a, %src : vector<16xf32>, vector<16xf32>
 
   vector.print %r3 : vector<16xf32>
   // CHECK: ( 1, 0, 2, 4, 5, 5, 3, 1, 0, 8, 5, 6, 3, 7, 6, 9 )
 
   return %i0 : i32
 }

mlir/test/Integration/Dialect/Vector/CPU/X86Vector/test-sparse-dot-product.mlir

-// RUN: mlir-opt %s -convert-scf-to-std -convert-vector-to-llvm="enable-avx512" -convert-std-to-llvm  | \
+// RUN: mlir-opt %s -convert-scf-to-std -convert-vector-to-llvm="enable-x86vector" -convert-std-to-llvm  | \
 // RUN: mlir-translate  --mlir-to-llvmir | \
 // RUN: %lli --entry-function=entry --mattr="avx512bw,avx512vp2intersect" --dlopen=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \
 // RUN: FileCheck %s
 
 // This test shows how to implement a sparse vector-vector dot product with
 // AVX512. It uses vp2intersect, mask.compress and vector.contract to compute
 // the dot product of two sparse HW vectors of 8 float64 elements ("segment").
 // Each sparse vector is represented by an index memref (A or C) and by a data
#contraction_trait = {
   indexing_maps = #contraction_accesses,
   iterator_types = ["reduction"]
 }
 
 // Sparse vector dot product of two vectors.
 func @vector_dot(%v_A : vector<8xi64>, %v_B : vector<8xf64>,
                  %v_C : vector<8xi64>, %v_D : vector<8xf64>) -> f64 {
   // Compute intersection of indices.
-  %k0, %k1 = avx512.vp2intersect %v_A, %v_C : vector<8xi64>
+  %k0, %k1 = x86vector.avx512.vp2intersect %v_A, %v_C : vector<8xi64>
 
   // Filter out values without match and compress vector.
-  %p0 = avx512.mask.compress %k0, %v_B : vector<8xf64>
-  %p1 = avx512.mask.compress %k1, %v_D : vector<8xf64>
+  %p0 = x86vector.avx512.mask.compress %k0, %v_B : vector<8xf64>
+  %p1 = x86vector.avx512.mask.compress %k1, %v_D : vector<8xf64>
 
   // Dense vector dot product.
   %acc = std.constant 0.0 : f64
   %r = vector.contract #contraction_trait %p0, %p1, %acc
       : vector<8xf64>, vector<8xf64> into f64
 
   return %r : f64
 }

mlir/test/Integration/Dialect/Vector/CPU/X86Vector/test-vp2intersect-i32.mlir

-// RUN: mlir-opt %s -convert-scf-to-std -convert-vector-to-llvm="enable-avx512" -convert-std-to-llvm  | \
+// RUN: mlir-opt %s -convert-scf-to-std -convert-vector-to-llvm="enable-x86vector" -convert-std-to-llvm  | \
 // RUN: mlir-translate  --mlir-to-llvmir | \
 // RUN: %lli --entry-function=entry --mattr="avx512bw,avx512vp2intersect" --dlopen=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \
 // RUN: FileCheck %s
 
 // Note: To run this test, your CPU must support AVX512 vp2intersect.
 
 func @entry() -> i32 {
   %i0 = constant 0 : i32
func @entry() -> i32 {
   %w5 = vector.insert %i4, %w4[10] : i32 into vector<16xi32>
   %w6 = vector.insert %i0, %w5[11] : i32 into vector<16xi32>
   %w7 = vector.insert %i0, %w6[12] : i32 into vector<16xi32>
   %w8 = vector.insert %i0, %w7[13] : i32 into vector<16xi32>
   %w9 = vector.insert %i0, %w8[15] : i32 into vector<16xi32>
   vector.print %w9 : vector<16xi32>
   // CHECK: ( 1, 1, 1, 1, 2, 1, 1, -219, 12, 12, 12, 0, 0, 0, 1, 0 )
 
-  %k1, %k2 = avx512.vp2intersect %v9, %w9 : vector<16xi32>
+  %k1, %k2 = x86vector.avx512.vp2intersect %v9, %w9 : vector<16xi32>
 
   vector.print %k1 : vector<16xi1>
   // CHECK: ( 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1 )
 
   vector.print %k2 : vector<16xi1>
   // CHECK: ( 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1 )
 
   return %i0 : i32
 }

mlir/test/Target/LLVMIR/x86vector.mlir

 // RUN: mlir-translate --mlir-to-llvmir %s | FileCheck %s
 
 // CHECK-LABEL: define <16 x float> @LLVM_x86_avx512_mask_ps_512
 llvm.func @LLVM_x86_avx512_mask_ps_512(%a: vector<16 x f32>,
                                        %c: i16)
   -> (vector<16 x f32>)
 {
   %b = llvm.mlir.constant(42 : i32) : i32
   // CHECK: call <16 x float> @llvm.x86.avx512.mask.rndscale.ps.512(<16 x float>
-  %0 = "avx512.intr.mask.rndscale.ps.512"(%a, %b, %a, %c, %b) :
+  %0 = "x86vector.avx512.intr.mask.rndscale.ps.512"(%a, %b, %a, %c, %b) :
     (vector<16 x f32>, i32, vector<16 x f32>, i16, i32) -> vector<16 x f32>
   // CHECK: call <16 x float> @llvm.x86.avx512.mask.scalef.ps.512(<16 x float>
-  %1 = "avx512.intr.mask.scalef.ps.512"(%a, %a, %a, %c, %b) :
+  %1 = "x86vector.avx512.intr.mask.scalef.ps.512"(%a, %a, %a, %c, %b) :
     (vector<16 x f32>, vector<16 x f32>, vector<16 x f32>, i16, i32) -> vector<16 x f32>
   llvm.return %1: vector<16 x f32>
 }
 
 // CHECK-LABEL: define <8 x double> @LLVM_x86_avx512_mask_pd_512
 llvm.func @LLVM_x86_avx512_mask_pd_512(%a: vector<8xf64>,
                                        %c: i8)
   -> (vector<8xf64>)
 {
   %b = llvm.mlir.constant(42 : i32) : i32
   // CHECK: call <8 x double> @llvm.x86.avx512.mask.rndscale.pd.512(<8 x double>
-  %0 = "avx512.intr.mask.rndscale.pd.512"(%a, %b, %a, %c, %b) :
+  %0 = "x86vector.avx512.intr.mask.rndscale.pd.512"(%a, %b, %a, %c, %b) :
     (vector<8xf64>, i32, vector<8xf64>, i8, i32) -> vector<8xf64>
   // CHECK: call <8 x double> @llvm.x86.avx512.mask.scalef.pd.512(<8 x double>
-  %1 = "avx512.intr.mask.scalef.pd.512"(%a, %a, %a, %c, %b) :
+  %1 = "x86vector.avx512.intr.mask.scalef.pd.512"(%a, %a, %a, %c, %b) :
     (vector<8xf64>, vector<8xf64>, vector<8xf64>, i8, i32) -> vector<8xf64>
   llvm.return %1: vector<8xf64>
 }
 
 // CHECK-LABEL: define <16 x float> @LLVM_x86_mask_compress
 llvm.func @LLVM_x86_mask_compress(%k: vector<16xi1>, %a: vector<16xf32>)
   -> vector<16xf32>
 {
   // CHECK: call <16 x float> @llvm.x86.avx512.mask.compress.v16f32(
-  %0 = "avx512.intr.mask.compress"(%a, %a, %k) :
+  %0 = "x86vector.avx512.intr.mask.compress"(%a, %a, %k) :
     (vector<16xf32>, vector<16xf32>, vector<16xi1>) -> vector<16xf32>
   llvm.return %0 : vector<16xf32>
 }
 
 // CHECK-LABEL: define { <16 x i1>, <16 x i1> } @LLVM_x86_vp2intersect_d_512
 llvm.func @LLVM_x86_vp2intersect_d_512(%a: vector<16xi32>, %b: vector<16xi32>)
   -> !llvm.struct<(vector<16 x i1>, vector<16 x i1>)>
 {
   // CHECK: call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32>
-  %0 = "avx512.intr.vp2intersect.d.512"(%a, %b) :
+  %0 = "x86vector.avx512.intr.vp2intersect.d.512"(%a, %b) :
     (vector<16xi32>, vector<16xi32>) -> !llvm.struct<(vector<16 x i1>, vector<16 x i1>)>
   llvm.return %0 : !llvm.struct<(vector<16 x i1>, vector<16 x i1>)>
 }
 
 // CHECK-LABEL: define { <8 x i1>, <8 x i1> } @LLVM_x86_vp2intersect_q_512
 llvm.func @LLVM_x86_vp2intersect_q_512(%a: vector<8xi64>, %b: vector<8xi64>)
   -> !llvm.struct<(vector<8 x i1>, vector<8 x i1>)>
 {
   // CHECK: call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.q.512(<8 x i64>
-  %0 = "avx512.intr.vp2intersect.q.512"(%a, %b) :
+  %0 = "x86vector.avx512.intr.vp2intersect.q.512"(%a, %b) :
     (vector<8xi64>, vector<8xi64>) -> !llvm.struct<(vector<8 x i1>, vector<8 x i1>)>
   llvm.return %0 : !llvm.struct<(vector<8 x i1>, vector<8 x i1>)>
 }

mlir/test/lit.site.cfg.py.in

 config.spirv_wrapper_library_dir = "@MLIR_SPIRV_WRAPPER_LIBRARY_DIR@"
 config.enable_spirv_cpu_runner = @MLIR_SPIRV_CPU_RUNNER_ENABLED@
 config.vulkan_wrapper_library_dir = "@MLIR_VULKAN_WRAPPER_LIBRARY_DIR@"
 config.enable_vulkan_runner = @MLIR_VULKAN_RUNNER_ENABLED@
 config.enable_bindings_python = @MLIR_BINDINGS_PYTHON_ENABLED@
 config.mlir_integration_test_dir = "@MLIR_INTEGRATION_TEST_DIR@"
 config.intel_sde_executable = "@INTEL_SDE_EXECUTABLE@"
 config.mlir_run_amx_tests = "@MLIR_RUN_AMX_TESTS@"
-config.mlir_run_avx512_tests = "@MLIR_RUN_AVX512_TESTS@"
+config.mlir_run_x86vector_tests = "@MLIR_RUN_X86VECTOR_TESTS@"
 config.mlir_include_integration_tests = "@MLIR_INCLUDE_INTEGRATION_TESTS@"
 
 # Support substitution of the tools_dir with user parameters. This is
 # used when we can't determine the tool dir at configuration time.
 try:
     config.llvm_tools_dir = config.llvm_tools_dir % lit_config.params
     config.llvm_lib_dir = config.llvm_lib_dir % lit_config.params
     config.llvm_shlib_dir = config.llvm_shlib_dir % lit_config.params

mlir/test/mlir-opt/commandline.mlir

 // RUN: mlir-opt --show-dialects | FileCheck %s
 // CHECK: Available Dialects:
 // CHECK-NEXT: acc
 // CHECK-NEXT: affine
 // CHECK-NEXT: amx
 // CHECK-NEXT: arm_neon
 // CHECK-NEXT: arm_sve
 // CHECK-NEXT: async
-// CHECK-NEXT: avx512
 // CHECK-NEXT: complex
 // CHECK-NEXT: dlti
 // CHECK-NEXT: gpu
 // CHECK-NEXT: linalg
 // CHECK-NEXT: llvm
 // CHECK-NEXT: llvm_arm_sve
 // CHECK-NEXT: math
 // CHECK-NEXT: memref
 // CHECK-NEXT: nvvm
 // CHECK-NEXT: omp
 // CHECK-NEXT: pdl
 // CHECK-NEXT: pdl_interp
 // CHECK-NEXT: quant
 // CHECK-NEXT: rocdl
 // CHECK-NEXT: scf
 // CHECK-NEXT: sdbm
 // CHECK-NEXT: shape
 // CHECK-NEXT: spv
 // CHECK-NEXT: std
 // CHECK-NEXT: tensor
 // CHECK-NEXT: test
 // CHECK-NEXT: tosa
 // CHECK-NEXT: vector
+// CHECK-NEXT: x86vector