riscv-v-spec-0.10 page 59
The fourth case of instruction description is added
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[RISCV] Add missing part of instruction vmsge {u}. VX ClosedPublic Authored by joker881 on Apr 8 2021, 8:28 AM.
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Diff Detail Event TimelineHerald added subscribers: frasercrmck, luismarques, apazos and 19 others. · View Herald TranscriptApr 8 2021, 8:28 AM lebedev.ri retitled this revision from Add missing part of instruction vmsge {u}. VX to [RISCV] Add missing part of instruction vmsge {u}. VX.Apr 8 2021, 9:32 AM Herald added subscribers: vkmr, evandro, benna and 3 others. · View Herald TranscriptApr 8 2021, 9:32 AM Comment Actions Upload patches with full context using git diff -U99999 as documented here https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface
Comment Actions Do we need this case? Case 4 is any vd. It means (vd == v0) || (vd != v0), right? These two cases are already covered by case 2 and case 3. Comment Actions
I think this is the case that a temp register is provided and the destination isn't v0. The user probably should use case 2 by not providing the temp register. But if they give the temp register should we accept it and match the spec or error for the destination not being v0(what we currently do)? joker881 marked 2 inline comments as done. Comment Actions
If the destination is not v0, case 2 is better than case 4. There should be no need to provide the temp register. I think the case 4 is useful when we could not determine vd is v0 or not, but it should not be the case in AsmParser. The registers in MCInst should be physical registers. joker881 marked 2 inline comments as not done. joker881 marked 2 inline comments as done. Comment Actions
Ok, I have finished it. B97933: Diff 336392. Comment Actions
What does the GNU assembler do? Can someone write inline assembly that requires this? If they let the compiler allocate the registers for the inline assembly we would need to support any register. Comment Actions
Got it. Maybe we need this pattern for inline asm. I have no strong opinion to oppose this patch. Just curious when we need it. This revision is now accepted and ready to land.Apr 12 2021, 10:09 AM Comment Actions Your commit description was not formatted correctly. You can read other commits for references. Differential Revision: was not on a new line so the differential was not automatically closed when you pushed the commit.
Revision Contents
Diff 336392 llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/test/MC/RISCV/rvv/compare.s
llvm/test/MC/RISCV/rvv/invalid.s
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