Refactor: Simplify boolean conditional return statements in lib/Target/AArch64

[LegalizeAdulthood]

Summary

Use clang-tidy to simplify boolean conditional return statements

[craig.topper]

lib/Target/AArch64/AArch64AddressTypePromotion.cpp

205

Push negate through

lib/Target/AArch64/AArch64FrameLowering.cpp

133

Push negate through

527

Push negate through

lib/Target/AArch64/AArch64PromoteConstant.cpp

288

Push negate through

[LegalizeAdulthood]

lib/Target/AArch64/AArch64AddressTypePromotion.cpp

205

Fixed.

lib/Target/AArch64/AArch64FrameLowering.cpp

133

Fixed.

527

Fixed.

lib/Target/AArch64/AArch64PromoteConstant.cpp

288

Fixed.

[LegalizeAdulthood]

Update from comments, clang-format

[• HaoLiu]

Hi Richard,

I think it's good refactor. LGTM.

Thanks,
-Hao

[LegalizeAdulthood]

I do not have commit access, so someone else will need to commit this. Let me know if it needs rebasing.

Patch by Richard Thomson.

[LegalizeAdulthood]

I do not have commit access, so someone else will need to commit this. Let me know if it needs rebasing.

Patch by Richard Thomson.

[echristo]

It does need rebasing if you wouldn't mind. I'll commit it after.

Thanks!

-eric

[LegalizeAdulthood]

make check-all passes in release

[echristo]

Committed thusly:

dzur:~/sources/llvm> git svn dcommit
Committing to https://llvm.org/svn/llvm-project/llvm/trunk ...
M lib/Target/AArch64/AArch64AddressTypePromotion.cpp
M lib/Target/AArch64/AArch64FastISel.cpp
M lib/Target/AArch64/AArch64FrameLowering.cpp
M lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M lib/Target/AArch64/AArch64ISelLowering.cpp
M lib/Target/AArch64/AArch64PromoteConstant.cpp
M lib/Target/AArch64/AArch64RegisterInfo.cpp
Committed r262266

lib/Target/AArch64/AArch64AddressTypePromotion.cpp

bool AArch64AddressTypePromotion::shouldGetThrough(const Instruction *Inst) {
   // useless.
   if (isa<TruncInst>(Inst))
     return true;
 
   // If both operands are not constant, a new sext will be created here.
   // Current heuristic is: each step should be profitable.
   // Therefore we don't allow to increase the number of sext even if it may
   // be profitable later on.
-  if (isa<BinaryOperator>(Inst) && isa<ConstantInt>(Inst->getOperand(1)))
-    return true;
-
-  return false;
+  return isa<BinaryOperator>(Inst) && isa<ConstantInt>(Inst->getOperand(1));
 }
 
 static bool shouldSExtOperand(const Instruction *Inst, int OpIdx) {
-  if (isa<SelectInst>(Inst) && OpIdx == 0)
-    return false;
-  return true;
+  return !(isa<SelectInst>(Inst) && OpIdx == 0);
 }
 
 bool
 AArch64AddressTypePromotion::shouldConsiderSExt(const Instruction *SExt) const {
   if (SExt->getType() != ConsideredSExtType)
     return false;
 
   for (const User *U : SExt->users()) {

lib/Target/AArch64/AArch64FastISel.cpp

bool AArch64FastISel::isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed) {
   if (Ty->isVectorTy() && !IsVectorAllowed)
     return false;
 
   if (isTypeLegal(Ty, VT))
     return true;
 
   // If this is a type than can be sign or zero-extended to a basic operation
   // go ahead and accept it now.
-  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
-    return true;
-
-  return false;
+  return VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16;
 }
 
 bool AArch64FastISel::isValueAvailable(const Value *V) const {
   if (!isa<Instruction>(V))
     return true;
 
   const auto *I = cast<Instruction>(V);
-  if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
-    return true;
-
-  return false;
+  return FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB;
 }
 
 bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) {
   unsigned ScaleFactor = getImplicitScaleFactor(VT);
   if (!ScaleFactor)
     return false;
 
   bool ImmediateOffsetNeedsLowering = false;
bool AArch64FastISel::selectStore(const Instruction *I) {
   if (!SrcReg)
     return false;
 
   // See if we can handle this address.
   Address Addr;
   if (!computeAddress(I->getOperand(1), Addr, I->getOperand(0)->getType()))
     return false;
 
-  if (!emitStore(VT, SrcReg, Addr, createMachineMemOperandFor(I)))
-    return false;
-  return true;
+  return emitStore(VT, SrcReg, Addr, createMachineMemOperandFor(I));
 }
 
 static AArch64CC::CondCode getCompareCC(CmpInst::Predicate Pred) {
   switch (Pred) {
   case CmpInst::FCMP_ONE:
   case CmpInst::FCMP_UEQ:
   default:
     // AL is our "false" for now. The other two need more compares.

lib/Target/AArch64/AArch64FrameLowering.cpp

bool AArch64FrameLowering::canUseRedZone(const MachineFunction &MF) const {
 
   const MachineFrameInfo *MFI = MF.getFrameInfo();
   const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
   unsigned NumBytes = AFI->getLocalStackSize();
 
   // Note: currently hasFP() is always true for hasCalls(), but that's an
   // implementation detail of the current code, not a strict requirement,
   // so stay safe here and check both.
-  if (MFI->hasCalls() || hasFP(MF) || NumBytes > 128)
-    return false;
-  return true;
+  return !(MFI->hasCalls() || hasFP(MF) || NumBytes > 128);
 }
 
 /// hasFP - Return true if the specified function should have a dedicated frame
 /// pointer register.
 bool AArch64FrameLowering::hasFP(const MachineFunction &MF) const {
   const MachineFrameInfo *MFI = MF.getFrameInfo();
   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
   return (MFI->hasCalls() || MFI->hasVarSizedObjects() ||
static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) {
   unsigned RtIdx = 0;
   if (MI->getOpcode() == AArch64::LDPXpost ||
       MI->getOpcode() == AArch64::LDPDpost)
     RtIdx = 1;
 
   if (MI->getOpcode() == AArch64::LDPXpost ||
       MI->getOpcode() == AArch64::LDPDpost ||
       MI->getOpcode() == AArch64::LDPXi || MI->getOpcode() == AArch64::LDPDi) {
-    if (!isCalleeSavedRegister(MI->getOperand(RtIdx).getReg(), CSRegs) ||
+    return !(!isCalleeSavedRegister(MI->getOperand(RtIdx).getReg(), CSRegs) ||
         !isCalleeSavedRegister(MI->getOperand(RtIdx + 1).getReg(), CSRegs) ||
-        MI->getOperand(RtIdx + 2).getReg() != AArch64::SP)
-      return false;
-    return true;
+        MI->getOperand(RtIdx + 2).getReg() != AArch64::SP);
   }
 
   return false;
 }
 
 void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
                                         MachineBasicBlock &MBB) const {
   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();

lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

case ISD::ROTR:
     return AArch64_AM::ROR;
   }
 }
 
 /// \brief Determine whether it is worth to fold V into an extended register.
 bool AArch64DAGToDAGISel::isWorthFolding(SDValue V) const {
   // it hurts if the value is used at least twice, unless we are optimizing
   // for code size.
-  if (ForCodeSize || V.hasOneUse())
-    return true;
-  return false;
+  return ForCodeSize || V.hasOneUse();
 }
 
 /// SelectShiftedRegister - Select a "shifted register" operand.  If the value
 /// is not shifted, set the Shift operand to default of "LSL 0".  The logical
 /// instructions allow the shifted register to be rotated, but the arithmetic
 /// instructions do not.  The AllowROR parameter specifies whether ROR is
 /// supported.
 bool AArch64DAGToDAGISel::SelectShiftedRegister(SDValue N, bool AllowROR,
bool AArch64DAGToDAGISel::SelectExtendedSHL(SDValue N, unsigned Size,
   }
 
   unsigned LegalShiftVal = Log2_32(Size);
   unsigned ShiftVal = CSD->getZExtValue();
 
   if (ShiftVal != 0 && ShiftVal != LegalShiftVal)
     return false;
 
-  if (isWorthFolding(N))
-    return true;
-
-  return false;
+  return isWorthFolding(N);
 }
 
 bool AArch64DAGToDAGISel::SelectAddrModeWRO(SDValue N, unsigned Size,
                                             SDValue &Base, SDValue &Offset,
                                             SDValue &SignExtend,
                                             SDValue &DoShift) {
   if (N.getOpcode() != ISD::ADD)
     return false;

lib/Target/AArch64/AArch64ISelLowering.cpp

static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
   }
   return DAG.getNode(ISD::BUILD_VECTOR, dl,
                      MVT::getVectorVT(TruncVT, NumElts), Ops);
 }
 
 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
   if (N->getOpcode() == ISD::SIGN_EXTEND)
     return true;
-  if (isExtendedBUILD_VECTOR(N, DAG, true))
-    return true;
-  return false;
+  return isExtendedBUILD_VECTOR(N, DAG, true);
 }
 
 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
   if (N->getOpcode() == ISD::ZERO_EXTEND)
     return true;
-  if (isExtendedBUILD_VECTOR(N, DAG, false))
-    return true;
-  return false;
+  return isExtendedBUILD_VECTOR(N, DAG, false);
 }
 
 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
   unsigned Opcode = N->getOpcode();
   if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
     SDNode *N0 = N->getOperand(0).getNode();
     SDNode *N1 = N->getOperand(1).getNode();
     return N0->hasOneUse() && N1->hasOneUse() &&
bool AArch64TargetLowering::isEligibleForTailCallOptimization(
   // X86) but less efficient and uglier in LowerCall.
   for (Function::const_arg_iterator i = CallerF->arg_begin(),
                                     e = CallerF->arg_end();
        i != e; ++i)
     if (i->hasByValAttr())
       return false;
 
   if (getTargetMachine().Options.GuaranteedTailCallOpt) {
-    if (IsTailCallConvention(CalleeCC) && CCMatch)
-      return true;
-    return false;
+    return IsTailCallConvention(CalleeCC) && CCMatch;
   }
 
   // Externally-defined functions with weak linkage should not be
   // tail-called on AArch64 when the OS does not support dynamic
   // pre-emption of symbols, as the AAELF spec requires normal calls
   // to undefined weak functions to be replaced with a NOP or jump to the
   // next instruction. The behaviour of branch instructions in this
   // situation (as used for tail calls) is implementation-defined, so we
bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
   if (User &&
       !(User->getOpcode() == Instruction::FSub ||
         User->getOpcode() == Instruction::FAdd))
     return true;
 
   const TargetOptions &Options = getTargetMachine().Options;
   EVT VT = getValueType(User->getOperand(0)->getType());
 
-  if (isFMAFasterThanFMulAndFAdd(VT) &&
+  return !(isFMAFasterThanFMulAndFAdd(VT) &&
       isOperationLegalOrCustom(ISD::FMA, VT) &&
-      (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath))
-    return false;
-
-  return true;
+      (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath));
 }
 
 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
 // 64-bit GPR.
 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
   if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
     return false;
   unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
if (Size >= 4 &&
        (allowsMisalignedMemoryAccesses(MVT::i32, 0, 1, &Fast) && Fast)))
     return MVT::i32;
 
   return MVT::Other;
 }
 
 // 12-bit optionally shifted immediates are legal for adds.
 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
-  if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
-    return true;
-  return false;
+  return (Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0);
 }
 
 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
 // immediates is the same as for an add or a sub.
 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
   if (Immed < 0)
     Immed *= -1;
   return isLegalAddImmediate(Immed);
if (!AM.Scale) {
     int64_t Offset = AM.BaseOffs;
 
     // 9-bit signed offset
     if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
       return true;
 
     // 12-bit unsigned offset
     unsigned shift = Log2_64(NumBytes);
-    if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
+    return NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
         // Must be a multiple of NumBytes (NumBytes is a power of 2)
-        (Offset >> shift) << shift == Offset)
-      return true;
-    return false;
+        (Offset >> shift) << shift == Offset;
   }
 
   // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
 
-  if (!AM.Scale || AM.Scale == 1 ||
-      (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
-    return true;
-  return false;
+  return !AM.Scale || AM.Scale == 1 ||
+      (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes);
 }
 
 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
                                                 Type *Ty) const {
   // Scaling factors are not free at all.
   // Operands                     | Rt Latency
   // -------------------------------------------
   // Rt, [Xn, Xm]                 | 4
if ((TypeNode->getVT() == MVT::i8 && width == 8)
        || (TypeNode->getVT() == MVT::i16 && width == 16)) {
       ExtType = ISD::ZEXTLOAD;
       return true;
     }
     return false;
   }
   case ISD::Constant:
   case ISD::TargetConstant: {
-    if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
-        1LL << (width - 1))
-      return true;
-    return false;
+    return std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
+        1LL << (width - 1);
   }
   }
 
   return true;
 }
 
 // This function does a whole lot of voodoo to determine if the tests are
 // equivalent without and with a mask. Essentially what happens is that given a
bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
   return true;
 }
 
 // Return whether the an instruction can potentially be optimized to a tail
 // call. This will cause the optimizers to attempt to move, or duplicate,
 // return instructions to help enable tail call optimizations for this
 // instruction.
 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
-  if (!CI->isTailCall())
-    return false;
-
-  return true;
+  return CI->isTailCall();
 }
 
 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
                                                    SDValue &Offset,
                                                    ISD::MemIndexedMode &AM,
                                                    bool &IsInc,
                                                    SelectionDAG &DAG) const {
   if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)

lib/Target/AArch64/AArch64InstrInfo.cpp

assert(MI->getNumOperands() >= 4 && MI->getOperand(0).isReg() &&
          MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
          MI->getOperand(3).isReg() && "MAdd/MSub must have a least 4 regs");
 
   // The third input reg must be zero.
   if (MI->getOperand(3).getReg() != ZeroReg)
     return false;
 
   // Must only used by the user we combine with.
-  if (!MRI.hasOneNonDBGUse(MI->getOperand(0).getReg()))
-    return false;
-
-  return true;
+  return MRI.hasOneNonDBGUse(MI->getOperand(0).getReg());
 }
 
 /// hasPattern - return true when there is potentially a faster code sequence
 /// for an instruction chain ending in \p Root. All potential patterns are
 /// listed
 /// in the \p Pattern vector. Pattern should be sorted in priority order since
 /// the pattern evaluator stops checking as soon as it finds a faster sequence.
 

lib/Target/AArch64/AArch64PromoteConstant.cpp

if (isa<const IndirectBrInst>(Instr))
     return false;
 
   // Do not mess with intrinsics.
   if (isa<const IntrinsicInst>(Instr))
     return false;
 
   // Do not mess with inline asm.
   const CallInst *CI = dyn_cast<const CallInst>(Instr);
-  if (CI && isa<const InlineAsm>(CI->getCalledValue()))
-    return false;
-
-  return true;
+  return !(CI && isa<const InlineAsm>(CI->getCalledValue()));
 }
 
 /// Check if the given Cst should be converted into
 /// a load of a global variable initialized with Cst.
 /// A constant should be converted if it is likely that the materialization of
 /// the constant will be tricky. Thus, we give up on zero or undef values.
 ///
 /// \todo Currently, accept only vector related types.

lib/Target/AArch64/AArch64RegisterInfo.cpp

if (needsStackRealignment(MF))
       return true;
     // Conservatively estimate whether the negative offset from the frame
     // pointer will be sufficient to reach. If a function has a smallish
     // frame, it's less likely to have lots of spills and callee saved
     // space, so it's all more likely to be within range of the frame pointer.
     // If it's wrong, we'll materialize the constant and still get to the
     // object; it's just suboptimal. Negative offsets use the unscaled
     // load/store instructions, which have a 9-bit signed immediate.
-    if (MFI->getLocalFrameSize() < 256)
-      return false;
-    return true;
+    return MFI->getLocalFrameSize() >= 256;
   }
 
   return false;
 }
 
 bool AArch64RegisterInfo::canRealignStack(const MachineFunction &MF) const {
 
-  if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
-    return false;
-
-  return true;
+  return !MF.getFunction()->hasFnAttribute("no-realign-stack");
 }
 
 // FIXME: share this with other backends with identical implementation?
 bool
 AArch64RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
   const MachineFrameInfo *MFI = MF.getFrameInfo();
   const Function *F = MF.getFunction();
   unsigned StackAlign = MF.getTarget()