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Nov 21 2013, 2:25 AM (299 w, 4 d)

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Jun 26 2015

HaoLiu added a comment to D10533: [AArch64][ARM] Match interleaved memory accesses into ldN/stN/vldN/vstN intrinsics..

I committed this patch separately in r240751, r240754 and r240755. Thanks again for your review comments.

Jun 26 2015, 12:13 AM

Jun 25 2015

HaoLiu committed rL240760: [InterleavedAccess] Fix failures "undefined type 'llvm::raw_ostream'" on….
[InterleavedAccess] Fix failures "undefined type 'llvm::raw_ostream'" on…
Jun 25 2015, 9:38 PM
HaoLiu committed rL240755: [ARM] Lower interleaved memory accesses to vldN/vstN intrinsics..
[ARM] Lower interleaved memory accesses to vldN/vstN intrinsics.
Jun 25 2015, 7:45 PM
HaoLiu committed rL240754: [AArch64] Lower interleaved memory accesses to ldN/stN intrinsics. This patch….
[AArch64] Lower interleaved memory accesses to ldN/stN intrinsics. This patch…
Jun 25 2015, 7:32 PM
HaoLiu committed rL240751: [InterleavedAccess] Add a pass InterleavedAccess to identify interleaved memory….
[InterleavedAccess] Add a pass InterleavedAccess to identify interleaved memory…
Jun 25 2015, 7:10 PM
HaoLiu closed D10533: [AArch64][ARM] Match interleaved memory accesses into ldN/stN/vldN/vstN intrinsics. by committing rL240751: [InterleavedAccess] Add a pass InterleavedAccess to identify interleaved memory….
Jun 25 2015, 7:10 PM
HaoLiu updated the diff for D10533: [AArch64][ARM] Match interleaved memory accesses into ldN/stN/vldN/vstN intrinsics..
Jun 25 2015, 12:25 AM
HaoLiu added a comment to D10533: [AArch64][ARM] Match interleaved memory accesses into ldN/stN/vldN/vstN intrinsics..

I refactored the patch according to Michael's comments. As well as inline comments to answer questions from Renato and Michael.

Jun 25 2015, 12:19 AM
HaoLiu updated the diff for D10533: [AArch64][ARM] Match interleaved memory accesses into ldN/stN/vldN/vstN intrinsics..
Jun 25 2015, 12:06 AM

Jun 24 2015

HaoLiu added a comment to D10533: [AArch64][ARM] Match interleaved memory accesses into ldN/stN/vldN/vstN intrinsics..

ping...

Jun 24 2015, 12:52 AM

Jun 23 2015

HaoLiu added a comment to D10533: [AArch64][ARM] Match interleaved memory accesses into ldN/stN/vldN/vstN intrinsics..

Updated a patch according to Renato's comments.

Jun 23 2015, 12:09 AM
HaoLiu updated the diff for D10533: [AArch64][ARM] Match interleaved memory accesses into ldN/stN/vldN/vstN intrinsics..
Jun 23 2015, 12:07 AM

Jun 18 2015

HaoLiu added a comment to D10533: [AArch64][ARM] Match interleaved memory accesses into ldN/stN/vldN/vstN intrinsics..

Updated a new patch refactored according to Silviu's comment.

Jun 18 2015, 10:54 PM
HaoLiu updated the diff for D10533: [AArch64][ARM] Match interleaved memory accesses into ldN/stN/vldN/vstN intrinsics..
Jun 18 2015, 10:53 PM
HaoLiu abandoned D10335: [AArch64] Match interleaved memory accesses into ldN/stN instructions..

I've created a new patch to share code between ARM and AArch64 backends. Abondon this patch.

Jun 18 2015, 3:09 AM
HaoLiu retitled D10533: [AArch64][ARM] Match interleaved memory accesses into ldN/stN/vldN/vstN intrinsics. from to [AArch64][ARM] Match interleaved memory accesses into ldN/stN/vldN/vstN intrinsics..
Jun 18 2015, 3:08 AM

Jun 17 2015

HaoLiu added a comment to D10335: [AArch64] Match interleaved memory accesses into ldN/stN instructions..

Do you guys have any idea about sharing the matchInterleavedLoad()/matchInterleavedStore()?

Jun 17 2015, 1:12 AM

Jun 15 2015

HaoLiu added a comment to D10335: [AArch64] Match interleaved memory accesses into ldN/stN instructions..

I've refactored the patch according to comments from Michael and Silviu.

Jun 15 2015, 1:13 AM
HaoLiu updated the diff for D10335: [AArch64] Match interleaved memory accesses into ldN/stN instructions..
Jun 15 2015, 12:41 AM

Jun 14 2015

HaoLiu committed rL239715: [AArch64] Delete two empty files, which should be removed by r239713..
[AArch64] Delete two empty files, which should be removed by r239713.
Jun 14 2015, 8:01 PM
HaoLiu committed rL239713: [AArch64] Revert r239711 again. We need to discuss how to share code between….
[AArch64] Revert r239711 again. We need to discuss how to share code between…
Jun 14 2015, 7:01 PM
HaoLiu committed rL239711: [AArch64] Match interleaved memory accesses into ldN/stN instructions..
[AArch64] Match interleaved memory accesses into ldN/stN instructions.
Jun 14 2015, 6:40 PM

Jun 11 2015

HaoLiu committed rL239515: [LoopVectorize] Revert the enabling of interleaved memory access in Loop….
[LoopVectorize] Revert the enabling of interleaved memory access in Loop…
Jun 11 2015, 2:22 AM
HaoLiu committed rL239514: [AArch64] Match interleaved memory accesses into ldN/stN instructions..
[AArch64] Match interleaved memory accesses into ldN/stN instructions.
Jun 11 2015, 2:09 AM

Jun 10 2015

HaoLiu added a comment to D10335: [AArch64] Match interleaved memory accesses into ldN/stN instructions..

Hi James,

Jun 10 2015, 11:46 PM
HaoLiu updated the diff for D10335: [AArch64] Match interleaved memory accesses into ldN/stN instructions..
Jun 10 2015, 11:07 PM

Jun 9 2015

HaoLiu updated the diff for D10335: [AArch64] Match interleaved memory accesses into ldN/stN instructions..

Update a patch fixes a typo.

Jun 9 2015, 2:18 AM
HaoLiu retitled D10335: [AArch64] Match interleaved memory accesses into ldN/stN instructions. from to [AArch64] Match interleaved memory accesses into ldN/stN instructions..
Jun 9 2015, 2:13 AM

Jun 8 2015

HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Committed in r239285 (Code about LoopAccessAnalysis) and r239291 (Code about LoopVectorize).

Jun 8 2015, 1:58 AM

Jun 7 2015

HaoLiu committed rL239291: [LoopVectorize] Teach Loop Vectorizor about interleaved memory accesses..
[LoopVectorize] Teach Loop Vectorizor about interleaved memory accesses.
Jun 7 2015, 11:44 PM
HaoLiu committed rL239285: [LoopAccessAnalysis] Teach LAA to check the memory dependence between strided….
[LoopAccessAnalysis] Teach LAA to check the memory dependence between strided…
Jun 7 2015, 9:52 PM
HaoLiu closed D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access by committing rL239285: [LoopAccessAnalysis] Teach LAA to check the memory dependence between strided….
Jun 7 2015, 9:52 PM

Jun 4 2015

HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

I've updated the patch according to Michael's comments. My comments are inline.

Jun 4 2015, 10:52 PM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
Jun 4 2015, 10:44 PM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
Jun 4 2015, 1:48 AM
HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Hi Adam,

Jun 4 2015, 1:30 AM

Jun 3 2015

HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Hi Adam,

Jun 3 2015, 6:39 PM

Jun 2 2015

HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

To my understanding, if a load has to wait until the store is committed, it is store-load forwarding.
For the case:

A[i] = a;     (1)
b = A[i];     (2)

(2) has to waite (1) to be committed. It is store-load forwarding. After vectoring such case, it is still store-load forwarding.

From comment in couldPreventStoreLoadForward, I think it means to prevent generating store-load forwarding by vectorization. If that is ture. The difference for this case is that it is original store-load forwarding. Do you mean that we could vectorize the cases that are original store-load forwarding?

The problem is not whether we can vectorize or not but because we can. It's whether the resulting vector store and load will be subject to the processor's store-to-load forwarding optimization. In this case the store does not have to get fully retired before the load could start executing (assuming an OOO core) but the memory unit will forward the value of the store to the load (and check whether there are intervening stores that make this invalid).

This is easy for the processor to figure out if both operations use the same address. However if they are only partially overlapping it's hard.

Jun 2 2015, 6:15 PM
HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Hi Adam,

Jun 2 2015, 12:32 AM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
Jun 2 2015, 12:31 AM

Jun 1 2015

HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

I also found a bug that write after load to the same location like:

A[i] = a;
b = A[i];

is not looked as store-load forwarding currently. As this could affect the correctness, I fixed this with slight modification. 2 new test cases are added.

Why do you think that this is bug? In this case because the vectorized loads and stores are aligned with each other, there should be no problem for the memory unit to figure out store-to-load forwarding. See the big comment in MemoryDepChecker::couldPreventStoreLoadForward.

Jun 1 2015, 11:49 PM
HaoLiu removed a reviewer for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access: HaoLiu.
Jun 1 2015, 3:16 AM
HaoLiu requested review of D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
Jun 1 2015, 3:16 AM

May 31 2015

HaoLiu accepted D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Refactored the patch according to Adam's comments.

May 31 2015, 11:55 PM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 31 2015, 11:52 PM

May 27 2015

HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Updated a new patch with slight modifications.

May 27 2015, 11:19 PM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 27 2015, 11:13 PM
HaoLiu accepted D9979: Refactor: Simplify boolean conditional return statements in lib/Target/AArch64.

Hi Richard,

May 27 2015, 7:01 PM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 27 2015, 4:10 AM
HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Updated a new patch refactored the LoopAccessAnalysis about dependence check on strided accesses.

May 27 2015, 4:04 AM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 27 2015, 3:52 AM

May 26 2015

HaoLiu updated subscribers of D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 26 2015, 12:10 AM
HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

I met a bug in Phabricator. It automatically removed all reviewers when I uploading a new patch. Now I've added reviewers back.

May 26 2015, 12:09 AM
HaoLiu added reviewers for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access: mzolotukhin, anemet, rengolin.
May 26 2015, 12:08 AM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 26 2015, 12:05 AM

May 25 2015

HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Updated a new patch refactored according to Michael and Adam.
There are two main changes:

(1) Add a threshold MaxInterleaveStride to avoid analyzing accesses with too large stride.
(2) Move the code about analyzing interleaved accesses in LoopAccessAnalysis to LoopVectorizer.
May 25 2015, 3:31 AM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 25 2015, 3:23 AM

May 24 2015

HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

I think LoopAccessAnalysis is a specific analysis for LV, so it's reasonable to put interleaved access analysis in an analysis specific for LV. If LoopAccessAnalysis is not specific for LV, I agree that we should not put it here. Currently I don't have idea about how other clients could use such interleave information.

But I still wonder how "other" clients use this analysis, as it has a lot of LV specific code like "CanVecMem, force-vector-width, force-vector-interleave", .... I wonder how "other" clients could use such analysis. Adam, do you have any example about other clients using LoopAccessAnalysis?

Sure, I already mentioned both clients: Transforms/Scalar/LoopDistribute.cpp and the still pending Ashutosh's Loop versioning pass in D9151.

Regarding your first specific question on CanVecMem, the basic design principle for splitting out LAA fron LV was to continue to provide the high-level LV-specific answers (i.e. CanVecMem) but also provide more lower-level/generic information about the dependences and run-time checks so that other passes could also use them (see APIs like: getInterestingDependences, getMemoryInstructions, getRuntimeChecks and getInstructionsForAccess).

Your other question was about force-vector-width, etc. These influence what dependences are acceptable for LV for its specific view of the dependence information. The solution here was to provide subtypes like *Vectorizable (see Dependence::DepType). These "subtypes" provide further classification of the dependence. LV uses these to allow vectorization of certain Backward dependences.

Loop Distribution does not use this classification since it only cares about forward vs. backward dependences.

Thus the difference is exposed to the clients and they can chose to treat these types differently or uniformly.

Adam

May 24 2015, 6:28 PM
HaoLiu added inline comments to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 24 2015, 7:43 AM
HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

It's easy to move such analysis to LV, but I think it reasonable to analyze interleaved accesses in LoopAccessAnalysis:

(1) Regarding the name "LoopAccessAnalysis", which is responsible for analyzing accesses in a loop. The interleaved access group is a special kind of access in loop.

True, I named it LAA because it’s a parallel dependence analysis framework to DependenceAnalysis but the focus is the same: dependence analysis plus run-time alias check generation for may-alias accesses.

I don’t have a problem adding things to the analysis that are free to compute even if it’s only used by a single client of the analysis pass (consider Ashutosh’s recent StoreToInvariantAddress changes). Here however we’re adding a potentially costly new analysis only required by a single client.

(2) For clients other than LV, it could disable or enable such analysis. Or we could disable it by default and LV calls function like "analyzeInterleaving()" to do analysis. To achieve this is easy.

Not really. This is an analysis pass, transform passes may depend on it and the pipeline manager will run this pass depending on transform pass requirements and possibly rerun it if it got invalidated by prior transformations.

As an example, consider this scenario. LAA is performed because of Loop Distribution. We end up not distributing the loop so the result of the analysis is intact and won’t be rerun. Then comes LV but the analysis is lacking the interleaved access analysis part.

Admittedly, we currently have a hack in LAA with regard to symbolic strides which would be similar to what you’re proposing. That however is more of shortcoming of how LAA was split out from LV rather than an example to follow.

(3) For other clients, I think we may also need to modify the memory dependence analysis, which is now dedicated to analyze dependences for loop vectorizer.

I am not sure I understand this point. Can you please elaborate?

May 24 2015, 7:35 AM

May 22 2015

HaoLiu added inline comments to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 22 2015, 12:47 AM

May 21 2015

HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Thinking about this a bit more, why are we collecting the InterLeaveGroups in LAA? LAA provides loop dependence information and computing this additional, unrelated information comes at a cost. Clients other than LV would pay for this without using it. I think that the InterLeaveGroups analysis should probably live in LV.

What do you think? Let me know if I am missing something from an earlier discussion.

Adam

May 21 2015, 11:59 PM
HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

I've updated a new patch refactored according to Michael's comments.

May 21 2015, 11:45 PM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 21 2015, 11:20 PM
HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Hi Hao,

Thanks for updating the patch, another bunch of comments from me inline.

Also, sorry for that I give the feedback in parts - it's hard to find enough time to review the entire patch all at once. I know that it might be a bit frustrating sometimes, but in fact I really appreciate your work and see how things converge:)

Thanks,
Michael

May 21 2015, 2:10 AM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 21 2015, 2:08 AM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 21 2015, 12:54 AM

May 20 2015

HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Michael, I agree with you and I'll separate the patch when committing.

Unless you can guarantee that trunk will work with just the first patch (ie. you have tested both equally), I don't think it's a good idea to split the patch. The analysis does nothing without the actual vectorisation, and vice versa.

It's a big patch, yes, but also this is a big change. I don't see what splitting the patches would gain us.

The patch now looks more like what we had planned in the beginning, so as long as all comments are addressed, and all tests pass, I'm happy.

Thank you for the effort of bringing this up again.

cheers,
--renato

May 20 2015, 6:13 PM

May 19 2015

HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Also, I think it's a good idea to separate the part for LoopAccessAnalysis part into a separate patch. I think it's fine to keep it in one patch during review (to keep the history), but I'd suggest committing it separately when they are ready. It'll help tracking down any potential issues that could be exposed later.

Michael, I agree with you and I'll separate the patch when committing.

May 19 2015, 11:52 PM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 19 2015, 11:50 PM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 19 2015, 11:16 PM
HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

I've updated a new patch according to the comments from Renato and Adam. This patch adds a new class InterleavedAccessInfo to handle the analysis about interleaved accesses.

May 19 2015, 3:45 AM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 19 2015, 3:36 AM

May 18 2015

HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Updated a new patch according to Renato's comments.

May 18 2015, 2:49 AM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 18 2015, 2:45 AM

May 15 2015

HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

I update a new patch according to the comments from Michael and the patch in PR17677 by Renato.

May 15 2015, 3:57 AM

May 14 2015

HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

I find it could break the Write After Write dependeces for cases like:

void waw(int *A) {
  short *T = (short *)A;
  T++;
  int *B = (int *)T;
  for (unsigned i = 0; i < 1024; i+=2)  {
    A[i+1] = i + 1;      // (1)
    B[i] = i;            // (2)
    A[i] = i;            // (3)
  }
}

The combine of "(1) + (3)" will be inserted after (2). As pointer B and A can calculate the distance, and all Writes are the same size and share the same stride, it can indeed pass the memory dependence check.

May 14 2015, 1:03 AM

May 13 2015

HaoLiu closed D2297: [PATCH][AArch64]Add missing floating point convert, round and misc intrinsics.
May 13 2015, 7:57 PM
HaoLiu closed D2239: [PATCH][AArch64] Fix the bug about Load/Store a vector type and bitcast between i64 and a vector type .
May 13 2015, 7:57 PM
HaoLiu closed D2249: [PATCH][AArch64] Fix the bug about disassembling incorrect lanes for post-indx of load/store single element instructions..
May 13 2015, 7:57 PM
HaoLiu closed D2298: [PATCH][AArch64]Add missing ACLE intrinsics mapping to general arithmetic operation from VFP instructions .
May 13 2015, 7:57 PM
HaoLiu closed D2299: [PATCH][AArch64]Add missing ACLE pair intrinsics.
May 13 2015, 7:56 PM
HaoLiu closed D2473: [AArch64]Add support to copy vector list registers such as DPair, DTriple... in copyPhyReg.
May 13 2015, 7:56 PM
HaoLiu closed D2502: Fix a bug in Instruction Combine when optimizing shuffle vector and insert element.
May 13 2015, 7:56 PM
HaoLiu closed D3740: [ARM64] Implement NEON post-increment LD1 (lane) and post-increment LD1R.
May 13 2015, 7:55 PM
HaoLiu closed D4417: [AArch64]Fix an assertion failure about concating two build_vector in DAG Combiner.
May 13 2015, 7:54 PM
HaoLiu closed D4322: [AArch64] Change default legalization behavior of v1i32 to be widen to v2i32 instead of scalarization .
May 13 2015, 7:53 PM
HaoLiu closed D5864: [AArch64] Improve and enable the SeparateConstOffsetFromGEP for AArch64 backend..
May 13 2015, 7:52 PM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 13 2015, 4:13 AM
HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Hi all the reviews,

May 13 2015, 4:03 AM
HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

I've attached a patch refactored according to the comments from Elena, Renato and Michael.

May 13 2015, 3:47 AM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 13 2015, 3:46 AM

May 12 2015

HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Hi Renato,

May 12 2015, 5:35 AM

May 7 2015

HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Do you have any ideas how can we remove unnecessary checks?

No much ideas. The memory check in Loop Vectorizer is much complex than SLP.

May 7 2015, 11:59 PM
HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Hi Hao,

First of all, thanks for working on this!
Below is the first round of comments from me, I'll get back to it again to dig into more interesting parts.

BTW, what are the problems that prevents us from getting performance benefits?

May 7 2015, 11:23 PM
HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Hao,

About the redundant code with SLP and others, there is a new loop library in lib/Transform/Utils/LoopUtils.cpp which you can use. If it's not a loop utility, please find the best appropriate place in the same directory and remove it from SLP and others.

cheers,
--renato

May 7 2015, 10:48 PM
HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

I've attached a new patch Diff25284 according to the comments from Michael and Renato.

May 7 2015, 10:46 PM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 7 2015, 10:30 PM
HaoLiu updated the diff for D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.
May 7 2015, 10:16 PM

May 6 2015

HaoLiu added a comment to D9368: [LoopVectorize]Teach Loop Vectorizer about interleaved memory access.

Thanks very much for the code review.
I've updated the code according to most of the comments.
I just can not complete the following two comments by the end of today:

(1) To add a new cost model function in BasicTTIImpl.h
(2) To handle the redundant load/store case.

I'll do in the next patch.

May 6 2015, 4:09 AM