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Differential D99036

GlobalISel: Constant fold FP bin ops in MIRBuilder
ClosedPublic

Authored by arsenm on Mar 21 2021, 7:06 AM.

Details

Reviewers
aemerson
paquette
bogner
dsanders
aditya_nandakumar
Summary

Might as well handle these if we're going to handle the integer ops here.

Diff Detail

Revision Contents

PathSize
llvm/
lib/
CodeGen/
GlobalISel/
20 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
72 lines

Diff 332156

llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp

Show First 20 Lines • Show All 191 Lines • ▼ Show 20 Lines case TargetOpcode::G_UMAX: {
// Try to constant fold these. // Try to constant fold these.
assert(SrcOps.size() == 2 && "Invalid sources"); assert(SrcOps.size() == 2 && "Invalid sources");
assert(DstOps.size() == 1 && "Invalid dsts"); assert(DstOps.size() == 1 && "Invalid dsts");
if (Optional<APInt> Cst = ConstantFoldBinOp(Opc, SrcOps[0].getReg(), if (Optional<APInt> Cst = ConstantFoldBinOp(Opc, SrcOps[0].getReg(),
SrcOps[1].getReg(), *getMRI())) SrcOps[1].getReg(), *getMRI()))
return buildConstant(DstOps[0], *Cst); return buildConstant(DstOps[0], *Cst);
break; break;
} }
case TargetOpcode::G_FADD:
case TargetOpcode::G_FSUB:
case TargetOpcode::G_FMUL:
case TargetOpcode::G_FDIV:
case TargetOpcode::G_FREM:
case TargetOpcode::G_FMINNUM:
case TargetOpcode::G_FMAXNUM:
case TargetOpcode::G_FMINNUM_IEEE:
case TargetOpcode::G_FMAXNUM_IEEE:
case TargetOpcode::G_FMINIMUM:
case TargetOpcode::G_FMAXIMUM:
case TargetOpcode::G_FCOPYSIGN: {
// Try to constant fold these.
assert(SrcOps.size() == 2 && "Invalid sources");
assert(DstOps.size() == 1 && "Invalid dsts");
if (Optional<APFloat> Cst = ConstantFoldFPBinOp(
Opc, SrcOps[0].getReg(), SrcOps[1].getReg(), *getMRI()))
return buildFConstant(DstOps[0], *Cst);
break;
}
case TargetOpcode::G_SEXT_INREG: { case TargetOpcode::G_SEXT_INREG: {
assert(DstOps.size() == 1 && "Invalid dst ops"); assert(DstOps.size() == 1 && "Invalid dst ops");
assert(SrcOps.size() == 2 && "Invalid src ops"); assert(SrcOps.size() == 2 && "Invalid src ops");
const DstOp &Dst = DstOps[0]; const DstOp &Dst = DstOps[0];
const SrcOp &Src0 = SrcOps[0]; const SrcOp &Src0 = SrcOps[0];
const SrcOp &Src1 = SrcOps[1]; const SrcOp &Src1 = SrcOps[1];
if (auto MaybeCst = if (auto MaybeCst =
ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI())) ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI()))
▲ Show 20 Lines • Show All 83 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir

Show First 20 Lines • Show All 996 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: fold_fadd_into_select_s32_0 ; CHECK-LABEL: name: fold_fadd_into_select_s32_0
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: %reg:_(s32) = COPY $vgpr0 ; CHECK: %reg:_(s32) = COPY $vgpr0
; CHECK: %zero:_(s32) = G_CONSTANT i32 0 ; CHECK: %zero:_(s32) = G_CONSTANT i32 0
; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.800000e+01
; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+01
; CHECK: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01 ; CHECK: %fadd:_(s32) = nnan G_SELECT %cond(s1), [[C]], [[C1]]
; CHECK: [[FADD:%[0-9]+]]:_(s32) = G_FADD %two, %sixteen
; CHECK: [[FADD1:%[0-9]+]]:_(s32) = G_FADD %four, %sixteen
; CHECK: %fadd:_(s32) = nnan G_SELECT %cond(s1), [[FADD]], [[FADD1]]
; CHECK: S_ENDPGM 0, implicit %fadd(s32) ; CHECK: S_ENDPGM 0, implicit %fadd(s32)
%reg:_(s32) = COPY $vgpr0 %reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0 %zero:_(s32) = G_CONSTANT i32 0
%cond:_(s1) = G_ICMP intpred(eq), %reg, %zero %cond:_(s1) = G_ICMP intpred(eq), %reg, %zero
%two:_(s32) = G_FCONSTANT float 2.0 %two:_(s32) = G_FCONSTANT float 2.0
%four:_(s32) = G_FCONSTANT float 4.0 %four:_(s32) = G_FCONSTANT float 4.0
%select:_(s32) = G_SELECT %cond, %two, %four %select:_(s32) = G_SELECT %cond, %two, %four
%sixteen:_(s32) = G_FCONSTANT float 16.0 %sixteen:_(s32) = G_FCONSTANT float 16.0
%fadd:_(s32) = nnan G_FADD %select, %sixteen %fadd:_(s32) = nnan G_FADD %select, %sixteen
S_ENDPGM 0, implicit %fadd S_ENDPGM 0, implicit %fadd
... ...
--- ---
name: fold_fadd_into_select_s32_1 name: fold_fadd_into_select_s32_1
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: fold_fadd_into_select_s32_1 ; CHECK-LABEL: name: fold_fadd_into_select_s32_1
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: %reg:_(s32) = COPY $vgpr0 ; CHECK: %reg:_(s32) = COPY $vgpr0
; CHECK: %zero:_(s32) = G_CONSTANT i32 0 ; CHECK: %zero:_(s32) = G_CONSTANT i32 0
; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.800000e+01
; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+01
; CHECK: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01 ; CHECK: %fadd:_(s32) = nnan G_SELECT %cond(s1), [[C]], [[C1]]
; CHECK: [[FADD:%[0-9]+]]:_(s32) = G_FADD %sixteen, %two
; CHECK: [[FADD1:%[0-9]+]]:_(s32) = G_FADD %sixteen, %four
; CHECK: %fadd:_(s32) = nnan G_SELECT %cond(s1), [[FADD]], [[FADD1]]
; CHECK: S_ENDPGM 0, implicit %fadd(s32) ; CHECK: S_ENDPGM 0, implicit %fadd(s32)
%reg:_(s32) = COPY $vgpr0 %reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0 %zero:_(s32) = G_CONSTANT i32 0
%cond:_(s1) = G_ICMP intpred(eq), %reg, %zero %cond:_(s1) = G_ICMP intpred(eq), %reg, %zero
%two:_(s32) = G_FCONSTANT float 2.0 %two:_(s32) = G_FCONSTANT float 2.0
%four:_(s32) = G_FCONSTANT float 4.0 %four:_(s32) = G_FCONSTANT float 4.0
%select:_(s32) = G_SELECT %cond, %two, %four %select:_(s32) = G_SELECT %cond, %two, %four
%sixteen:_(s32) = G_FCONSTANT float 16.0 %sixteen:_(s32) = G_FCONSTANT float 16.0
%fadd:_(s32) = nnan G_FADD %sixteen, %select %fadd:_(s32) = nnan G_FADD %sixteen, %select
S_ENDPGM 0, implicit %fadd S_ENDPGM 0, implicit %fadd
... ...
--- ---
name: fold_fsub_into_select_s32_0 name: fold_fsub_into_select_s32_0
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: fold_fsub_into_select_s32_0 ; CHECK-LABEL: name: fold_fsub_into_select_s32_0
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: %reg:_(s32) = COPY $vgpr0 ; CHECK: %reg:_(s32) = COPY $vgpr0
; CHECK: %zero:_(s32) = G_CONSTANT i32 0 ; CHECK: %zero:_(s32) = G_CONSTANT i32 0
; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.400000e+01
; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.200000e+01
; CHECK: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01 ; CHECK: %fsub:_(s32) = nnan G_SELECT %cond(s1), [[C]], [[C1]]
; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB %two, %sixteen
; CHECK: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB %four, %sixteen
; CHECK: %fsub:_(s32) = nnan G_SELECT %cond(s1), [[FSUB]], [[FSUB1]]
; CHECK: S_ENDPGM 0, implicit %fsub(s32) ; CHECK: S_ENDPGM 0, implicit %fsub(s32)
%reg:_(s32) = COPY $vgpr0 %reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0 %zero:_(s32) = G_CONSTANT i32 0
%cond:_(s1) = G_ICMP intpred(eq), %reg, %zero %cond:_(s1) = G_ICMP intpred(eq), %reg, %zero
%two:_(s32) = G_FCONSTANT float 2.0 %two:_(s32) = G_FCONSTANT float 2.0
%four:_(s32) = G_FCONSTANT float 4.0 %four:_(s32) = G_FCONSTANT float 4.0
%select:_(s32) = G_SELECT %cond, %two, %four %select:_(s32) = G_SELECT %cond, %two, %four
%sixteen:_(s32) = G_FCONSTANT float 16.0 %sixteen:_(s32) = G_FCONSTANT float 16.0
%fsub:_(s32) = nnan G_FSUB %select, %sixteen %fsub:_(s32) = nnan G_FSUB %select, %sixteen
S_ENDPGM 0, implicit %fsub S_ENDPGM 0, implicit %fsub
... ...
--- ---
name: fold_fmul_into_select_s32_0 name: fold_fmul_into_select_s32_0
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: fold_fmul_into_select_s32_0 ; CHECK-LABEL: name: fold_fmul_into_select_s32_0
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: %reg:_(s32) = COPY $vgpr0 ; CHECK: %reg:_(s32) = COPY $vgpr0
; CHECK: %zero:_(s32) = G_CONSTANT i32 0 ; CHECK: %zero:_(s32) = G_CONSTANT i32 0
; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.400000e+01
; CHECK: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01 ; CHECK: %fmul:_(s32) = nnan G_SELECT %cond(s1), [[C]], [[C1]]
; CHECK: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL %two, %sixteen
; CHECK: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL %four, %sixteen
; CHECK: %fmul:_(s32) = nnan G_SELECT %cond(s1), [[FMUL]], [[FMUL1]]
; CHECK: S_ENDPGM 0, implicit %fmul(s32) ; CHECK: S_ENDPGM 0, implicit %fmul(s32)
%reg:_(s32) = COPY $vgpr0 %reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0 %zero:_(s32) = G_CONSTANT i32 0
%cond:_(s1) = G_ICMP intpred(eq), %reg, %zero %cond:_(s1) = G_ICMP intpred(eq), %reg, %zero
%two:_(s32) = G_FCONSTANT float 2.0 %two:_(s32) = G_FCONSTANT float 2.0
%four:_(s32) = G_FCONSTANT float 4.0 %four:_(s32) = G_FCONSTANT float 4.0
%select:_(s32) = G_SELECT %cond, %two, %four %select:_(s32) = G_SELECT %cond, %two, %four
%sixteen:_(s32) = G_FCONSTANT float 16.0 %sixteen:_(s32) = G_FCONSTANT float 16.0
%fmul:_(s32) = nnan G_FMUL %select, %sixteen %fmul:_(s32) = nnan G_FMUL %select, %sixteen
S_ENDPGM 0, implicit %fmul S_ENDPGM 0, implicit %fmul
... ...
--- ---
name: fold_fdiv_into_select_s32_0 name: fold_fdiv_into_select_s32_0
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: fold_fdiv_into_select_s32_0 ; CHECK-LABEL: name: fold_fdiv_into_select_s32_0
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: %reg:_(s32) = COPY $vgpr0 ; CHECK: %reg:_(s32) = COPY $vgpr0
; CHECK: %zero:_(s32) = G_CONSTANT i32 0 ; CHECK: %zero:_(s32) = G_CONSTANT i32 0
; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.250000e-01
; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.500000e-01
; CHECK: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01 ; CHECK: %fdiv:_(s32) = nnan G_SELECT %cond(s1), [[C]], [[C1]]
; CHECK: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV %two, %sixteen
; CHECK: [[FDIV1:%[0-9]+]]:_(s32) = G_FDIV %four, %sixteen
; CHECK: %fdiv:_(s32) = nnan G_SELECT %cond(s1), [[FDIV]], [[FDIV1]]
; CHECK: S_ENDPGM 0, implicit %fdiv(s32) ; CHECK: S_ENDPGM 0, implicit %fdiv(s32)
%reg:_(s32) = COPY $vgpr0 %reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0 %zero:_(s32) = G_CONSTANT i32 0
%cond:_(s1) = G_ICMP intpred(eq), %reg, %zero %cond:_(s1) = G_ICMP intpred(eq), %reg, %zero
%two:_(s32) = G_FCONSTANT float 2.0 %two:_(s32) = G_FCONSTANT float 2.0
%four:_(s32) = G_FCONSTANT float 4.0 %four:_(s32) = G_FCONSTANT float 4.0
%select:_(s32) = G_SELECT %cond, %two, %four %select:_(s32) = G_SELECT %cond, %two, %four
%sixteen:_(s32) = G_FCONSTANT float 16.0 %sixteen:_(s32) = G_FCONSTANT float 16.0
Show All 9 Lines bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: fold_frem_into_select_s32_0 ; CHECK-LABEL: name: fold_frem_into_select_s32_0
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: %reg:_(s32) = COPY $vgpr0 ; CHECK: %reg:_(s32) = COPY $vgpr0
; CHECK: %zero:_(s32) = G_CONSTANT i32 0 ; CHECK: %zero:_(s32) = G_CONSTANT i32 0
; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00 ; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00
; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00 ; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00
; CHECK: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01 ; CHECK: %frem:_(s32) = nnan G_SELECT %cond(s1), %two, %four
; CHECK: [[FREM:%[0-9]+]]:_(s32) = G_FREM %two, %sixteen
; CHECK: [[FREM1:%[0-9]+]]:_(s32) = G_FREM %four, %sixteen
; CHECK: %frem:_(s32) = nnan G_SELECT %cond(s1), [[FREM]], [[FREM1]]
; CHECK: S_ENDPGM 0, implicit %frem(s32) ; CHECK: S_ENDPGM 0, implicit %frem(s32)
%reg:_(s32) = COPY $vgpr0 %reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0 %zero:_(s32) = G_CONSTANT i32 0
%cond:_(s1) = G_ICMP intpred(eq), %reg, %zero %cond:_(s1) = G_ICMP intpred(eq), %reg, %zero
%two:_(s32) = G_FCONSTANT float 2.0 %two:_(s32) = G_FCONSTANT float 2.0
%four:_(s32) = G_FCONSTANT float 4.0 %four:_(s32) = G_FCONSTANT float 4.0
%select:_(s32) = G_SELECT %cond, %two, %four %select:_(s32) = G_SELECT %cond, %two, %four
%sixteen:_(s32) = G_FCONSTANT float 16.0 %sixteen:_(s32) = G_FCONSTANT float 16.0
Show All 38 Lines bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: fold_fminnum_into_select_s32_0 ; CHECK-LABEL: name: fold_fminnum_into_select_s32_0
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: %reg:_(s32) = COPY $vgpr0 ; CHECK: %reg:_(s32) = COPY $vgpr0
; CHECK: %zero:_(s32) = G_CONSTANT i32 0 ; CHECK: %zero:_(s32) = G_CONSTANT i32 0
; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00 ; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00
; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00 ; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00
; CHECK: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01 ; CHECK: %fminnum:_(s32) = nnan G_SELECT %cond(s1), %two, %four
; CHECK: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM %two, %sixteen
; CHECK: [[FMINNUM1:%[0-9]+]]:_(s32) = G_FMINNUM %four, %sixteen
; CHECK: %fminnum:_(s32) = nnan G_SELECT %cond(s1), [[FMINNUM]], [[FMINNUM1]]
; CHECK: S_ENDPGM 0, implicit %fminnum(s32) ; CHECK: S_ENDPGM 0, implicit %fminnum(s32)
%reg:_(s32) = COPY $vgpr0 %reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0 %zero:_(s32) = G_CONSTANT i32 0
%cond:_(s1) = G_ICMP intpred(eq), %reg, %zero %cond:_(s1) = G_ICMP intpred(eq), %reg, %zero
%two:_(s32) = G_FCONSTANT float 2.0 %two:_(s32) = G_FCONSTANT float 2.0
%four:_(s32) = G_FCONSTANT float 4.0 %four:_(s32) = G_FCONSTANT float 4.0
%select:_(s32) = G_SELECT %cond, %two, %four %select:_(s32) = G_SELECT %cond, %two, %four
%sixteen:_(s32) = G_FCONSTANT float 16.0 %sixteen:_(s32) = G_FCONSTANT float 16.0
Show All 36 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: fold_fmaxnum_into_select_s32_0 ; CHECK-LABEL: name: fold_fmaxnum_into_select_s32_0
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: %reg:_(s32) = COPY $vgpr0 ; CHECK: %reg:_(s32) = COPY $vgpr0
; CHECK: %zero:_(s32) = G_CONSTANT i32 0 ; CHECK: %zero:_(s32) = G_CONSTANT i32 0
; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00
; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00 ; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00
; CHECK: %select:_(s32) = G_SELECT %cond(s1), %two, %four
; CHECK: %three:_(s32) = G_FCONSTANT float 3.000000e+00 ; CHECK: %three:_(s32) = G_FCONSTANT float 3.000000e+00
; CHECK: %fmaxnum:_(s32) = nnan G_FMAXNUM %select, %three ; CHECK: %fmaxnum:_(s32) = nnan G_SELECT %cond(s1), %three, %four
; CHECK: S_ENDPGM 0, implicit %fmaxnum(s32) ; CHECK: S_ENDPGM 0, implicit %fmaxnum(s32)
%reg:_(s32) = COPY $vgpr0 %reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0 %zero:_(s32) = G_CONSTANT i32 0
%cond:_(s1) = G_ICMP intpred(eq), %reg, %zero %cond:_(s1) = G_ICMP intpred(eq), %reg, %zero
%two:_(s32) = G_FCONSTANT float 2.0 %two:_(s32) = G_FCONSTANT float 2.0
%four:_(s32) = G_FCONSTANT float 4.0 %four:_(s32) = G_FCONSTANT float 4.0
%select:_(s32) = G_SELECT %cond, %two, %four %select:_(s32) = G_SELECT %cond, %two, %four
%three:_(s32) = G_FCONSTANT float 3.0 %three:_(s32) = G_FCONSTANT float 3.0
Show All 9 Lines bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: fold_fmaxnum_ieee_into_select_s32_0 ; CHECK-LABEL: name: fold_fmaxnum_ieee_into_select_s32_0
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: %reg:_(s32) = COPY $vgpr0 ; CHECK: %reg:_(s32) = COPY $vgpr0
; CHECK: %zero:_(s32) = G_CONSTANT i32 0 ; CHECK: %zero:_(s32) = G_CONSTANT i32 0
; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00 ; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00
; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00 ; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00
; CHECK: %select:_(s32) = G_SELECT %cond(s1), %two, %four
; CHECK: %three:_(s32) = G_FCONSTANT float 3.000000e+00 ; CHECK: %three:_(s32) = G_FCONSTANT float 3.000000e+00
; CHECK: %fmaxnum_ieee:_(s32) = nnan G_FMAXNUM_IEEE %select, %three ; CHECK: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE %two, %three
; CHECK: [[FMAXNUM_IEEE1:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE %four, %three
; CHECK: %fmaxnum_ieee:_(s32) = nnan G_SELECT %cond(s1), [[FMAXNUM_IEEE]], [[FMAXNUM_IEEE1]]
; CHECK: S_ENDPGM 0, implicit %fmaxnum_ieee(s32) ; CHECK: S_ENDPGM 0, implicit %fmaxnum_ieee(s32)
%reg:_(s32) = COPY $vgpr0 %reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0 %zero:_(s32) = G_CONSTANT i32 0
%cond:_(s1) = G_ICMP intpred(eq), %reg, %zero %cond:_(s1) = G_ICMP intpred(eq), %reg, %zero
%two:_(s32) = G_FCONSTANT float 2.0 %two:_(s32) = G_FCONSTANT float 2.0
%four:_(s32) = G_FCONSTANT float 4.0 %four:_(s32) = G_FCONSTANT float 4.0
%select:_(s32) = G_SELECT %cond, %two, %four %select:_(s32) = G_SELECT %cond, %two, %four
%three:_(s32) = G_FCONSTANT float 3.0 %three:_(s32) = G_FCONSTANT float 3.0
Show All 9 Lines bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: fold_fminimum_into_select_s32_0 ; CHECK-LABEL: name: fold_fminimum_into_select_s32_0
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: %reg:_(s32) = COPY $vgpr0 ; CHECK: %reg:_(s32) = COPY $vgpr0
; CHECK: %zero:_(s32) = G_CONSTANT i32 0 ; CHECK: %zero:_(s32) = G_CONSTANT i32 0
; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00 ; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00
; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00 ; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00
; CHECK: %select:_(s32) = G_SELECT %cond(s1), %two, %four ; CHECK: %fminimum:_(s32) = nnan G_SELECT %cond(s1), %two, %four
; CHECK: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
; CHECK: %fminimum:_(s32) = nnan G_FMINIMUM %select, %sixteen
; CHECK: S_ENDPGM 0, implicit %fminimum(s32) ; CHECK: S_ENDPGM 0, implicit %fminimum(s32)
%reg:_(s32) = COPY $vgpr0 %reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0 %zero:_(s32) = G_CONSTANT i32 0
%cond:_(s1) = G_ICMP intpred(eq), %reg, %zero %cond:_(s1) = G_ICMP intpred(eq), %reg, %zero
%two:_(s32) = G_FCONSTANT float 2.0 %two:_(s32) = G_FCONSTANT float 2.0
%four:_(s32) = G_FCONSTANT float 4.0 %four:_(s32) = G_FCONSTANT float 4.0
%select:_(s32) = G_SELECT %cond, %two, %four %select:_(s32) = G_SELECT %cond, %two, %four
%sixteen:_(s32) = G_FCONSTANT float 16.0 %sixteen:_(s32) = G_FCONSTANT float 16.0
%fminimum:_(s32) = nnan G_FMINIMUM %select, %sixteen %fminimum:_(s32) = nnan G_FMINIMUM %select, %sixteen
S_ENDPGM 0, implicit %fminimum S_ENDPGM 0, implicit %fminimum
... ...
--- ---
name: fold_fmaximum_into_select_s32_0 name: fold_fmaximum_into_select_s32_0
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: fold_fmaximum_into_select_s32_0 ; CHECK-LABEL: name: fold_fmaximum_into_select_s32_0
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: %reg:_(s32) = COPY $vgpr0 ; CHECK: %reg:_(s32) = COPY $vgpr0
; CHECK: %zero:_(s32) = G_CONSTANT i32 0 ; CHECK: %zero:_(s32) = G_CONSTANT i32 0
; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero ; CHECK: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
; CHECK: %two:_(s32) = G_FCONSTANT float 2.000000e+00
; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00 ; CHECK: %four:_(s32) = G_FCONSTANT float 4.000000e+00
; CHECK: %select:_(s32) = G_SELECT %cond(s1), %two, %four
; CHECK: %three:_(s32) = G_FCONSTANT float 3.000000e+00 ; CHECK: %three:_(s32) = G_FCONSTANT float 3.000000e+00
; CHECK: %fmaximum:_(s32) = nnan G_FMAXIMUM %select, %three ; CHECK: %fmaximum:_(s32) = nnan G_SELECT %cond(s1), %three, %four
; CHECK: S_ENDPGM 0, implicit %fmaximum(s32) ; CHECK: S_ENDPGM 0, implicit %fmaximum(s32)
%reg:_(s32) = COPY $vgpr0 %reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0 %zero:_(s32) = G_CONSTANT i32 0
%cond:_(s1) = G_ICMP intpred(eq), %reg, %zero %cond:_(s1) = G_ICMP intpred(eq), %reg, %zero
%two:_(s32) = G_FCONSTANT float 2.0 %two:_(s32) = G_FCONSTANT float 2.0
%four:_(s32) = G_FCONSTANT float 4.0 %four:_(s32) = G_FCONSTANT float 4.0
%select:_(s32) = G_SELECT %cond, %two, %four %select:_(s32) = G_SELECT %cond, %two, %four
%three:_(s32) = G_FCONSTANT float 3.0 %three:_(s32) = G_FCONSTANT float 3.0
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