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Differential D104528

[GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder
ClosedPublic

Authored by foad on Jun 18 2021, 6:01 AM.

Details

Reviewers
arsenm
paquette
aemerson
jroelofs
Commits
rGdc4ca0dbbcef: [GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder

Diff Detail

Event Timeline

foad created this revision.Jun 18 2021, 6:01 AM
Herald added subscribers: kerbowa, hiraditya, rovka and 2 others. · View Herald TranscriptJun 18 2021, 6:01 AM
foad requested review of this revision.Jun 18 2021, 6:01 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 18 2021, 6:01 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
jroelofs accepted this revision.Jun 18 2021, 9:40 AM

LGTM

This revision is now accepted and ready to land.Jun 18 2021, 9:40 AM
Harbormaster completed remote builds in B109916: Diff 352987.Jun 18 2021, 8:34 PM
foad mentioned this in D105525: [GISel] Add fpext/fptrunc combines.Jul 8 2021, 3:35 AM
jroelofs added a comment.Jul 26 2021, 10:41 AM

@foad were you going to land this? Seems worthwhile.

foad added a comment.Jul 26 2021, 12:29 PM
In D104528#2904886, @jroelofs wrote:

@foad were you going to land this? Seems worthwhile.

Sure, will do. I think I was waiting for D99036 to go in first, but I see now there's no real dependency.

This revision was landed with ongoing or failed builds.Jul 27 2021, 3:28 AM
Closed by commit rGdc4ca0dbbcef: [GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder (authored by foad). · Explain Why
This revision was automatically updated to reflect the committed changes.
foad added a commit: rGdc4ca0dbbcef: [GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder.

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
4 lines
lib/
CodeGen/
GlobalISel/
10 lines
13 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
3 lines
24 lines
148 lines
144 lines
126 lines
61 lines

Diff 361962

llvm/include/llvm/CodeGen/GlobalISel/Utils.h

Show First 20 Lines • Show All 251 Lines • ▼ Show 20 LinesOptional<APInt> ConstantFoldBinOp(unsigned Opcode, const Register Op1,
const MachineRegisterInfo &MRI); const MachineRegisterInfo &MRI);
Optional<APFloat> ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, Optional<APFloat> ConstantFoldFPBinOp(unsigned Opcode, const Register Op1,
const Register Op2, const Register Op2,
const MachineRegisterInfo &MRI); const MachineRegisterInfo &MRI);
Optional<APInt> ConstantFoldExtOp(unsigned Opcode, const Register Op1, Optional<APInt> ConstantFoldExtOp(unsigned Opcode, const Register Op1,
uint64_t Imm, const MachineRegisterInfo &MRI); uint64_t Imm, const MachineRegisterInfo &MRI);
Optional<APFloat> ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy,
Register Src,
const MachineRegisterInfo &MRI);
/// Test if the given value is known to have exactly one bit set. This differs /// Test if the given value is known to have exactly one bit set. This differs
/// from computeKnownBits in that it doesn't necessarily determine which bit is /// from computeKnownBits in that it doesn't necessarily determine which bit is
/// set. /// set.
bool isKnownToBeAPowerOfTwo(Register Val, const MachineRegisterInfo &MRI, bool isKnownToBeAPowerOfTwo(Register Val, const MachineRegisterInfo &MRI,
GISelKnownBits *KnownBits = nullptr); GISelKnownBits *KnownBits = nullptr);
/// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is true, /// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is true,
/// this returns if \p Val can be assumed to never be a signaling NaN. /// this returns if \p Val can be assumed to never be a signaling NaN.
▲ Show 20 Lines • Show All 131 Lines • Show Last 20 Lines

llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp

Show First 20 Lines • Show All 197 Lines • ▼ Show 20 Lines case TargetOpcode::G_SEXT_INREG: {
const DstOp &Dst = DstOps[0]; const DstOp &Dst = DstOps[0];
const SrcOp &Src0 = SrcOps[0]; const SrcOp &Src0 = SrcOps[0];
const SrcOp &Src1 = SrcOps[1]; const SrcOp &Src1 = SrcOps[1];
if (auto MaybeCst = if (auto MaybeCst =
ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI())) ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI()))
return buildConstant(Dst, *MaybeCst); return buildConstant(Dst, *MaybeCst);
break; break;
} }
case TargetOpcode::G_SITOFP:
case TargetOpcode::G_UITOFP: {
// Try to constant fold these.
assert(SrcOps.size() == 1 && "Invalid sources");
assert(DstOps.size() == 1 && "Invalid dsts");
if (Optional<APFloat> Cst = ConstantFoldIntToFloat(
Opc, DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getReg(), *getMRI()))
return buildFConstant(DstOps[0], *Cst);
break;
}
} }
bool CanCopy = checkCopyToDefsPossible(DstOps); bool CanCopy = checkCopyToDefsPossible(DstOps);
if (!canPerformCSEForOpc(Opc)) if (!canPerformCSEForOpc(Opc))
return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag);
// If we can CSE this instruction, but involves generating copies to multiple // If we can CSE this instruction, but involves generating copies to multiple
// regs, give up. This frequently happens to UNMERGEs. // regs, give up. This frequently happens to UNMERGEs.
if (!CanCopy) { if (!CanCopy) {
auto MIB = MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); auto MIB = MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag);
▲ Show 20 Lines • Show All 72 Lines • Show Last 20 Lines

llvm/lib/CodeGen/GlobalISel/Utils.cpp

Show First 20 Lines • Show All 667 Lines • ▼ Show 20 Lines case TargetOpcode::G_SEXT_INREG: {
LLT Ty = MRI.getType(Op1); LLT Ty = MRI.getType(Op1);
return MaybeOp1Cst->trunc(Imm).sext(Ty.getScalarSizeInBits()); return MaybeOp1Cst->trunc(Imm).sext(Ty.getScalarSizeInBits());
} }
} }
} }
return None; return None;
} }
Optional<APFloat> llvm::ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy,
Register Src,
const MachineRegisterInfo &MRI) {
assert(Opcode == TargetOpcode::G_SITOFP || Opcode == TargetOpcode::G_UITOFP);
if (auto MaybeSrcVal = getConstantVRegVal(Src, MRI)) {
APFloat DstVal(getFltSemanticForLLT(DstTy));
DstVal.convertFromAPInt(*MaybeSrcVal, Opcode == TargetOpcode::G_SITOFP,
APFloat::rmNearestTiesToEven);
return DstVal;
}
return None;
}
bool llvm::isKnownToBeAPowerOfTwo(Register Reg, const MachineRegisterInfo &MRI, bool llvm::isKnownToBeAPowerOfTwo(Register Reg, const MachineRegisterInfo &MRI,
GISelKnownBits *KB) { GISelKnownBits *KB) {
Optional<DefinitionAndSourceRegister> DefSrcReg = Optional<DefinitionAndSourceRegister> DefSrcReg =
getDefSrcRegIgnoringCopies(Reg, MRI); getDefSrcRegIgnoringCopies(Reg, MRI);
if (!DefSrcReg) if (!DefSrcReg)
return false; return false;
const MachineInstr &MI = *DefSrcReg->MI; const MachineInstr &MI = *DefSrcReg->MI;
▲ Show 20 Lines • Show All 317 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll

Show First 20 Lines • Show All 683 Lines • ▼ Show 20 Lines; GFX6-NEXT: s_endpgm
%ashr = ashr i32 %shl, 8 %ashr = ashr i32 %shl, 8
store i32 %ashr, i32 addrspace(1)* %out, align 4 store i32 %ashr, i32 addrspace(1)* %out, align 4
ret void ret void
} }
define amdgpu_kernel void @simplify_demanded_bfe_sdiv(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { define amdgpu_kernel void @simplify_demanded_bfe_sdiv(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
; GFX6-LABEL: simplify_demanded_bfe_sdiv: ; GFX6-LABEL: simplify_demanded_bfe_sdiv:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 2 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, 2.0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb ; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_load_dword s2, s[2:3], 0x0 ; GFX6-NEXT: s_load_dword s2, s[2:3], 0x0
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
▲ Show 20 Lines • Show All 287 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines; GCN-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 1) %res = call float @llvm.powi.f32.i32(float %l, i32 1)
ret float %res ret float %res
} }
define float @v_powi_neg1_f32(float %l) { define float @v_powi_neg1_f32(float %l) {
; GCN-LABEL: v_powi_neg1_f32: ; GCN-LABEL: v_powi_neg1_f32:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cvt_f32_i32_e32 v1, -1
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GCN-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 ; GCN-NEXT: v_mul_legacy_f32_e32 v0, -1.0, v0
; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GCN-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 -1) %res = call float @llvm.powi.f32.i32(float %l, i32 -1)
ret float %res ret float %res
} }
define float @v_powi_2_f32(float %l) { define float @v_powi_2_f32(float %l) {
; GCN-LABEL: v_powi_2_f32: ; GCN-LABEL: v_powi_2_f32:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GCN-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_cvt_f32_ubyte0_e32 v1, 2 ; GCN-NEXT: v_mul_legacy_f32_e32 v0, 2.0, v0
; GCN-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GCN-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 2) %res = call float @llvm.powi.f32.i32(float %l, i32 2)
ret float %res ret float %res
} }
define float @v_powi_neg2_f32(float %l) { define float @v_powi_neg2_f32(float %l) {
; GCN-LABEL: v_powi_neg2_f32: ; GCN-LABEL: v_powi_neg2_f32:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cvt_f32_i32_e32 v1, -2
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GCN-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 ; GCN-NEXT: v_mul_legacy_f32_e32 v0, -2.0, v0
; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GCN-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 -2) %res = call float @llvm.powi.f32.i32(float %l, i32 -2)
ret float %res ret float %res
} }
define float @v_powi_4_f32(float %l) { define float @v_powi_4_f32(float %l) {
; GCN-LABEL: v_powi_4_f32: ; GCN-LABEL: v_powi_4_f32:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GCN-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_cvt_f32_ubyte0_e32 v1, 4 ; GCN-NEXT: v_mul_legacy_f32_e32 v0, 4.0, v0
; GCN-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GCN-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 4) %res = call float @llvm.powi.f32.i32(float %l, i32 4)
ret float %res ret float %res
} }
define float @v_powi_8_f32(float %l) { define float @v_powi_8_f32(float %l) {
; GCN-LABEL: v_powi_8_f32: ; GCN-LABEL: v_powi_8_f32:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GCN-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_cvt_f32_ubyte0_e32 v1, 8 ; GCN-NEXT: v_mul_legacy_f32_e32 v0, 0x41000000, v0
; GCN-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GCN-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 8) %res = call float @llvm.powi.f32.i32(float %l, i32 8)
ret float %res ret float %res
} }
define float @v_powi_16_f32(float %l) { define float @v_powi_16_f32(float %l) {
; GCN-LABEL: v_powi_16_f32: ; GCN-LABEL: v_powi_16_f32:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GCN-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_cvt_f32_ubyte0_e32 v1, 16 ; GCN-NEXT: v_mul_legacy_f32_e32 v0, 0x41800000, v0
; GCN-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GCN-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 16) %res = call float @llvm.powi.f32.i32(float %l, i32 16)
ret float %res ret float %res
} }
define float @v_powi_128_f32(float %l) { define float @v_powi_128_f32(float %l) {
; GCN-LABEL: v_powi_128_f32: ; GCN-LABEL: v_powi_128_f32:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GCN-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_cvt_f32_ubyte0_e32 v1, 0x80 ; GCN-NEXT: v_mul_legacy_f32_e32 v0, 0x43000000, v0
; GCN-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GCN-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 128) %res = call float @llvm.powi.f32.i32(float %l, i32 128)
ret float %res ret float %res
} }
define float @v_powi_neg128_f32(float %l) { define float @v_powi_neg128_f32(float %l) {
; GCN-LABEL: v_powi_neg128_f32: ; GCN-LABEL: v_powi_neg128_f32:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cvt_f32_i32_e32 v1, 0xffffff80
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GCN-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 ; GCN-NEXT: v_mul_legacy_f32_e32 v0, 0xc3000000, v0
; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GCN-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 -128) %res = call float @llvm.powi.f32.i32(float %l, i32 -128)
ret float %res ret float %res
} }
; FIXME: f64 broken ; FIXME: f64 broken
; define double @v_powi_f64(double %l, i32 %r) { ; define double @v_powi_f64(double %l, i32 %r) {
Show All 9 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll

Show First 20 Lines • Show All 290 Lines • ▼ Show 20 Lines
} }
define i32 @v_sdiv_i32_pow2k_denom(i32 %num) { define i32 @v_sdiv_i32_pow2k_denom(i32 %num) {
; CHECK-LABEL: v_sdiv_i32_pow2k_denom: ; CHECK-LABEL: v_sdiv_i32_pow2k_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_movk_i32 s6, 0x1000 ; CHECK-NEXT: s_movk_i32 s6, 0x1000
; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CHECK-NEXT: v_mov_b32_e32 v2, 0xfffff000 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, 0x45800000
; CHECK-NEXT: v_mov_b32_e32 v3, 0xfffff000
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_cvt_f32_u32_e32 v3, s6 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1 ; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1
; CHECK-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; CHECK-NEXT: v_mul_lo_u32 v3, v3, v2
; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3 ; CHECK-NEXT: v_mul_hi_u32 v3, v2, v3
; CHECK-NEXT: v_mul_lo_u32 v2, v2, v3 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CHECK-NEXT: v_mul_hi_u32 v2, v3, v2
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; CHECK-NEXT: v_mul_hi_u32 v2, v0, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v0, v2
; CHECK-NEXT: v_lshlrev_b32_e32 v3, 12, v2 ; CHECK-NEXT: v_lshlrev_b32_e32 v3, 12, v2
; CHECK-NEXT: v_add_i32_e32 v4, vcc, 1, v2 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, 1, v2
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
; CHECK-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; CHECK-NEXT: v_subrev_i32_e64 v3, s[4:5], s6, v0 ; CHECK-NEXT: v_subrev_i32_e64 v3, s[4:5], s6, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_xor_b32_e32 v1, v1, v3 ; GISEL-NEXT: v_xor_b32_e32 v1, v1, v3
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v3 ; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_sdiv_v2i32_pow2k_denom: ; CGP-LABEL: v_sdiv_v2i32_pow2k_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: s_movk_i32 s4, 0x1000 ; CGP-NEXT: s_movk_i32 s8, 0x1000
; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v0 ; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v0
; CGP-NEXT: v_mov_b32_e32 v3, 0x1000 ; CGP-NEXT: v_rcp_iflag_f32_e32 v3, 0x45800000
; CGP-NEXT: s_movk_i32 s5, 0xf000 ; CGP-NEXT: s_movk_i32 s4, 0xf000
; CGP-NEXT: v_mov_b32_e32 v4, 0xfffff000 ; CGP-NEXT: v_mov_b32_e32 v4, 0xfffff000
; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1 ; CGP-NEXT: v_mov_b32_e32 v5, 0x1000
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, 0x45800000
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v6, s4 ; CGP-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v5 ; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v6
; CGP-NEXT: v_cvt_f32_u32_e32 v7, v3
; CGP-NEXT: v_xor_b32_e32 v0, v0, v2
; CGP-NEXT: v_rcp_iflag_f32_e32 v6, v6
; CGP-NEXT: v_xor_b32_e32 v1, v1, v5
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v7
; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; CGP-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7 ; CGP-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6 ; CGP-NEXT: v_xor_b32_e32 v0, v0, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v3, v3
; CGP-NEXT: v_xor_b32_e32 v1, v1, v6
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
; CGP-NEXT: v_mul_lo_u32 v8, s5, v6 ; CGP-NEXT: v_mul_lo_u32 v8, s4, v3
; CGP-NEXT: v_mul_lo_u32 v4, v4, v7 ; CGP-NEXT: v_mul_lo_u32 v4, v4, v7
; CGP-NEXT: v_mul_hi_u32 v8, v6, v8 ; CGP-NEXT: v_mul_hi_u32 v8, v3, v8
; CGP-NEXT: v_mul_hi_u32 v4, v7, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v7, v4
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v8
; CGP-NEXT: v_add_i32_e32 v4, vcc, v7, v4 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; CGP-NEXT: v_mul_hi_u32 v6, v0, v6 ; CGP-NEXT: v_mul_hi_u32 v3, v0, v3
; CGP-NEXT: v_mul_hi_u32 v4, v1, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v1, v4
; CGP-NEXT: v_lshlrev_b32_e32 v7, 12, v6 ; CGP-NEXT: v_lshlrev_b32_e32 v7, 12, v3
; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v6 ; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v3
; CGP-NEXT: v_lshlrev_b32_e32 v9, 12, v4 ; CGP-NEXT: v_lshlrev_b32_e32 v9, 12, v4
; CGP-NEXT: v_add_i32_e32 v10, vcc, 1, v4 ; CGP-NEXT: v_add_i32_e32 v10, vcc, 1, v4
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v7 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v7
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v9 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v9
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; CGP-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; CGP-NEXT: v_subrev_i32_e64 v7, s[4:5], s4, v0 ; CGP-NEXT: v_subrev_i32_e64 v7, s[4:5], s8, v0
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v5
; CGP-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[4:5]
; CGP-NEXT: v_sub_i32_e64 v8, s[6:7], v1, v3 ; CGP-NEXT: v_sub_i32_e64 v8, s[6:7], v1, v5
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v6 ; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v3
; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[4:5]
; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; CGP-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5
; CGP-NEXT: v_cndmask_b32_e32 v1, v4, v8, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v4, v8, vcc
; CGP-NEXT: v_xor_b32_e32 v0, v0, v2 ; CGP-NEXT: v_xor_b32_e32 v0, v0, v2
; CGP-NEXT: v_xor_b32_e32 v1, v1, v5 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v6
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v5 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%result = sdiv <2 x i32> %num, <i32 4096, i32 4096> %result = sdiv <2 x i32> %num, <i32 4096, i32 4096>
ret <2 x i32> %result ret <2 x i32> %result
} }
define i32 @v_sdiv_i32_oddk_denom(i32 %num) { define i32 @v_sdiv_i32_oddk_denom(i32 %num) {
; CHECK-LABEL: v_sdiv_i32_oddk_denom: ; CHECK-LABEL: v_sdiv_i32_oddk_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_mov_b32 s6, 0x12d8fb ; CHECK-NEXT: s_mov_b32 s6, 0x12d8fb
; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CHECK-NEXT: v_mov_b32_e32 v2, 0xffed2705 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, 0x4996c7d8
; CHECK-NEXT: v_mov_b32_e32 v3, 0xffed2705
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_cvt_f32_u32_e32 v3, s6 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1 ; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1
; CHECK-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; CHECK-NEXT: v_mul_lo_u32 v3, v3, v2
; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3 ; CHECK-NEXT: v_mul_hi_u32 v3, v2, v3
; CHECK-NEXT: v_mul_lo_u32 v2, v2, v3 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CHECK-NEXT: v_mul_hi_u32 v2, v3, v2
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; CHECK-NEXT: v_mul_hi_u32 v2, v0, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v0, v2
; CHECK-NEXT: v_mul_lo_u32 v3, v2, s6 ; CHECK-NEXT: v_mul_lo_u32 v3, v2, s6
; CHECK-NEXT: v_add_i32_e32 v4, vcc, 1, v2 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, 1, v2
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
; CHECK-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; CHECK-NEXT: v_subrev_i32_e64 v3, s[4:5], s6, v0 ; CHECK-NEXT: v_subrev_i32_e64 v3, s[4:5], s6, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
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; GISEL-NEXT: v_xor_b32_e32 v1, v1, v3 ; GISEL-NEXT: v_xor_b32_e32 v1, v1, v3
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v3 ; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_sdiv_v2i32_oddk_denom: ; CGP-LABEL: v_sdiv_v2i32_oddk_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: s_mov_b32 s4, 0x12d8fb ; CGP-NEXT: s_mov_b32 s8, 0x12d8fb
; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v0 ; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v0
; CGP-NEXT: v_mov_b32_e32 v3, 0x12d8fb ; CGP-NEXT: v_rcp_iflag_f32_e32 v3, 0x4996c7d8
; CGP-NEXT: s_mov_b32 s5, 0xffed2705 ; CGP-NEXT: s_mov_b32 s4, 0xffed2705
; CGP-NEXT: v_mov_b32_e32 v4, 0xffed2705 ; CGP-NEXT: v_mov_b32_e32 v4, 0xffed2705
; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1 ; CGP-NEXT: v_mov_b32_e32 v5, 0x12d8fb
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, 0x4996c7d8
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v6, s4 ; CGP-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v5 ; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v6
; CGP-NEXT: v_cvt_f32_u32_e32 v7, v3
; CGP-NEXT: v_xor_b32_e32 v0, v0, v2
; CGP-NEXT: v_rcp_iflag_f32_e32 v6, v6
; CGP-NEXT: v_xor_b32_e32 v1, v1, v5
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v7
; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; CGP-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7 ; CGP-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6 ; CGP-NEXT: v_xor_b32_e32 v0, v0, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v3, v3
; CGP-NEXT: v_xor_b32_e32 v1, v1, v6
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
; CGP-NEXT: v_mul_lo_u32 v8, s5, v6 ; CGP-NEXT: v_mul_lo_u32 v8, s4, v3
; CGP-NEXT: v_mul_lo_u32 v4, v4, v7 ; CGP-NEXT: v_mul_lo_u32 v4, v4, v7
; CGP-NEXT: v_mul_hi_u32 v8, v6, v8 ; CGP-NEXT: v_mul_hi_u32 v8, v3, v8
; CGP-NEXT: v_mul_hi_u32 v4, v7, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v7, v4
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v8
; CGP-NEXT: v_add_i32_e32 v4, vcc, v7, v4 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; CGP-NEXT: v_mul_hi_u32 v6, v0, v6 ; CGP-NEXT: v_mul_hi_u32 v3, v0, v3
; CGP-NEXT: v_mul_hi_u32 v4, v1, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v1, v4
; CGP-NEXT: v_mul_lo_u32 v7, v6, s4 ; CGP-NEXT: v_mul_lo_u32 v7, v3, s8
; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v6 ; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v3
; CGP-NEXT: v_mul_lo_u32 v9, v4, v3 ; CGP-NEXT: v_mul_lo_u32 v9, v4, v5
; CGP-NEXT: v_add_i32_e32 v10, vcc, 1, v4 ; CGP-NEXT: v_add_i32_e32 v10, vcc, 1, v4
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v7 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v7
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v9 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v9
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; CGP-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; CGP-NEXT: v_subrev_i32_e64 v7, s[4:5], s4, v0 ; CGP-NEXT: v_subrev_i32_e64 v7, s[4:5], s8, v0
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v5
; CGP-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[4:5]
; CGP-NEXT: v_sub_i32_e64 v8, s[6:7], v1, v3 ; CGP-NEXT: v_sub_i32_e64 v8, s[6:7], v1, v5
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v6 ; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v3
; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[4:5]
; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; CGP-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5
; CGP-NEXT: v_cndmask_b32_e32 v1, v4, v8, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v4, v8, vcc
; CGP-NEXT: v_xor_b32_e32 v0, v0, v2 ; CGP-NEXT: v_xor_b32_e32 v0, v0, v2
; CGP-NEXT: v_xor_b32_e32 v1, v1, v5 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v6
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v5 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%result = sdiv <2 x i32> %num, <i32 1235195, i32 1235195> %result = sdiv <2 x i32> %num, <i32 1235195, i32 1235195>
ret <2 x i32> %result ret <2 x i32> %result
} }
define i32 @v_sdiv_i32_pow2_shl_denom(i32 %x, i32 %y) { define i32 @v_sdiv_i32_pow2_shl_denom(i32 %x, i32 %y) {
; CHECK-LABEL: v_sdiv_i32_pow2_shl_denom: ; CHECK-LABEL: v_sdiv_i32_pow2_shl_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
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llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll

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} }
define i32 @v_srem_i32_pow2k_denom(i32 %num) { define i32 @v_srem_i32_pow2k_denom(i32 %num) {
; CHECK-LABEL: v_srem_i32_pow2k_denom: ; CHECK-LABEL: v_srem_i32_pow2k_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_movk_i32 s4, 0x1000 ; CHECK-NEXT: s_movk_i32 s4, 0x1000
; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CHECK-NEXT: v_mov_b32_e32 v2, 0xfffff000 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, 0x45800000
; CHECK-NEXT: v_mov_b32_e32 v3, 0xfffff000
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_cvt_f32_u32_e32 v3, s4 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1 ; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1
; CHECK-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; CHECK-NEXT: v_mul_lo_u32 v3, v3, v2
; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3 ; CHECK-NEXT: v_mul_hi_u32 v3, v2, v3
; CHECK-NEXT: v_mul_lo_u32 v2, v2, v3 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CHECK-NEXT: v_mul_hi_u32 v2, v3, v2
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; CHECK-NEXT: v_mul_hi_u32 v2, v0, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v0, v2
; CHECK-NEXT: v_lshlrev_b32_e32 v2, 12, v2 ; CHECK-NEXT: v_lshlrev_b32_e32 v2, 12, v2
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0 ; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0 ; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
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; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v3 ; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_srem_v2i32_pow2k_denom: ; CGP-LABEL: v_srem_v2i32_pow2k_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: s_movk_i32 s4, 0x1000 ; CGP-NEXT: s_movk_i32 s4, 0x1000
; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v0 ; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v0
; CGP-NEXT: v_mov_b32_e32 v3, 0x1000 ; CGP-NEXT: v_rcp_iflag_f32_e32 v3, 0x45800000
; CGP-NEXT: s_movk_i32 s5, 0xf000 ; CGP-NEXT: s_movk_i32 s5, 0xf000
; CGP-NEXT: v_mov_b32_e32 v4, 0xfffff000 ; CGP-NEXT: v_mov_b32_e32 v4, 0xfffff000
; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1 ; CGP-NEXT: v_mov_b32_e32 v5, 0x1000
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, 0x45800000
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v6, s4 ; CGP-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v5 ; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v6
; CGP-NEXT: v_cvt_f32_u32_e32 v7, v3
; CGP-NEXT: v_xor_b32_e32 v0, v0, v2
; CGP-NEXT: v_rcp_iflag_f32_e32 v6, v6
; CGP-NEXT: v_xor_b32_e32 v1, v1, v5
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v7
; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; CGP-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7 ; CGP-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6 ; CGP-NEXT: v_xor_b32_e32 v0, v0, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v3, v3
; CGP-NEXT: v_xor_b32_e32 v1, v1, v6
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
; CGP-NEXT: v_mul_lo_u32 v8, s5, v6 ; CGP-NEXT: v_mul_lo_u32 v8, s5, v3
; CGP-NEXT: v_mul_lo_u32 v4, v4, v7 ; CGP-NEXT: v_mul_lo_u32 v4, v4, v7
; CGP-NEXT: v_mul_hi_u32 v8, v6, v8 ; CGP-NEXT: v_mul_hi_u32 v8, v3, v8
; CGP-NEXT: v_mul_hi_u32 v4, v7, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v7, v4
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v8
; CGP-NEXT: v_add_i32_e32 v4, vcc, v7, v4 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; CGP-NEXT: v_mul_hi_u32 v6, v0, v6 ; CGP-NEXT: v_mul_hi_u32 v3, v0, v3
; CGP-NEXT: v_mul_hi_u32 v4, v1, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v1, v4
; CGP-NEXT: v_lshlrev_b32_e32 v6, 12, v6 ; CGP-NEXT: v_lshlrev_b32_e32 v3, 12, v3
; CGP-NEXT: v_lshlrev_b32_e32 v4, 12, v4 ; CGP-NEXT: v_lshlrev_b32_e32 v4, 12, v4
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v6 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v4 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
; CGP-NEXT: v_subrev_i32_e32 v4, vcc, s4, v0 ; CGP-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
; CGP-NEXT: v_sub_i32_e32 v6, vcc, v1, v3 ; CGP-NEXT: v_sub_i32_e32 v4, vcc, v1, v5
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; CGP-NEXT: v_subrev_i32_e32 v4, vcc, s4, v0 ; CGP-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
; CGP-NEXT: v_sub_i32_e32 v6, vcc, v1, v3 ; CGP-NEXT: v_sub_i32_e32 v4, vcc, v1, v5
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; CGP-NEXT: v_xor_b32_e32 v0, v0, v2 ; CGP-NEXT: v_xor_b32_e32 v0, v0, v2
; CGP-NEXT: v_xor_b32_e32 v1, v1, v5 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v6
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v5 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%result = srem <2 x i32> %num, <i32 4096, i32 4096> %result = srem <2 x i32> %num, <i32 4096, i32 4096>
ret <2 x i32> %result ret <2 x i32> %result
} }
define i32 @v_srem_i32_oddk_denom(i32 %num) { define i32 @v_srem_i32_oddk_denom(i32 %num) {
; CHECK-LABEL: v_srem_i32_oddk_denom: ; CHECK-LABEL: v_srem_i32_oddk_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_mov_b32 s4, 0x12d8fb ; CHECK-NEXT: s_mov_b32 s4, 0x12d8fb
; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CHECK-NEXT: v_mov_b32_e32 v2, 0xffed2705 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, 0x4996c7d8
; CHECK-NEXT: v_mov_b32_e32 v3, 0xffed2705
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_cvt_f32_u32_e32 v3, s4 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1 ; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1
; CHECK-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; CHECK-NEXT: v_mul_lo_u32 v3, v3, v2
; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3 ; CHECK-NEXT: v_mul_hi_u32 v3, v2, v3
; CHECK-NEXT: v_mul_lo_u32 v2, v2, v3 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CHECK-NEXT: v_mul_hi_u32 v2, v3, v2
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; CHECK-NEXT: v_mul_hi_u32 v2, v0, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v0, v2
; CHECK-NEXT: v_mul_lo_u32 v2, v2, s4 ; CHECK-NEXT: v_mul_lo_u32 v2, v2, s4
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0 ; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0 ; CHECK-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
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; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v3 ; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_srem_v2i32_oddk_denom: ; CGP-LABEL: v_srem_v2i32_oddk_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: s_mov_b32 s4, 0x12d8fb ; CGP-NEXT: s_mov_b32 s4, 0x12d8fb
; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v0 ; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v0
; CGP-NEXT: v_mov_b32_e32 v3, 0x12d8fb ; CGP-NEXT: v_rcp_iflag_f32_e32 v3, 0x4996c7d8
; CGP-NEXT: s_mov_b32 s5, 0xffed2705 ; CGP-NEXT: s_mov_b32 s5, 0xffed2705
; CGP-NEXT: v_mov_b32_e32 v4, 0xffed2705 ; CGP-NEXT: v_mov_b32_e32 v4, 0xffed2705
; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1 ; CGP-NEXT: v_mov_b32_e32 v5, 0x12d8fb
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, 0x4996c7d8
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v6, s4 ; CGP-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v5 ; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v6
; CGP-NEXT: v_cvt_f32_u32_e32 v7, v3
; CGP-NEXT: v_xor_b32_e32 v0, v0, v2
; CGP-NEXT: v_rcp_iflag_f32_e32 v6, v6
; CGP-NEXT: v_xor_b32_e32 v1, v1, v5
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v7
; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; CGP-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7 ; CGP-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6 ; CGP-NEXT: v_xor_b32_e32 v0, v0, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v3, v3
; CGP-NEXT: v_xor_b32_e32 v1, v1, v6
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
; CGP-NEXT: v_mul_lo_u32 v8, s5, v6 ; CGP-NEXT: v_mul_lo_u32 v8, s5, v3
; CGP-NEXT: v_mul_lo_u32 v4, v4, v7 ; CGP-NEXT: v_mul_lo_u32 v4, v4, v7
; CGP-NEXT: v_mul_hi_u32 v8, v6, v8 ; CGP-NEXT: v_mul_hi_u32 v8, v3, v8
; CGP-NEXT: v_mul_hi_u32 v4, v7, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v7, v4
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v8
; CGP-NEXT: v_add_i32_e32 v4, vcc, v7, v4 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; CGP-NEXT: v_mul_hi_u32 v6, v0, v6 ; CGP-NEXT: v_mul_hi_u32 v3, v0, v3
; CGP-NEXT: v_mul_hi_u32 v4, v1, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v1, v4
; CGP-NEXT: v_mul_lo_u32 v6, v6, s4 ; CGP-NEXT: v_mul_lo_u32 v3, v3, s4
; CGP-NEXT: v_mul_lo_u32 v4, v4, v3 ; CGP-NEXT: v_mul_lo_u32 v4, v4, s4
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v6 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v4 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
; CGP-NEXT: v_subrev_i32_e32 v4, vcc, s4, v0 ; CGP-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
; CGP-NEXT: v_sub_i32_e32 v6, vcc, v1, v3 ; CGP-NEXT: v_sub_i32_e32 v4, vcc, v1, v5
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; CGP-NEXT: v_subrev_i32_e32 v4, vcc, s4, v0 ; CGP-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
; CGP-NEXT: v_sub_i32_e32 v6, vcc, v1, v3 ; CGP-NEXT: v_sub_i32_e32 v4, vcc, v1, v5
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; CGP-NEXT: v_xor_b32_e32 v0, v0, v2 ; CGP-NEXT: v_xor_b32_e32 v0, v0, v2
; CGP-NEXT: v_xor_b32_e32 v1, v1, v5 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v6
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v5 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%result = srem <2 x i32> %num, <i32 1235195, i32 1235195> %result = srem <2 x i32> %num, <i32 1235195, i32 1235195>
ret <2 x i32> %result ret <2 x i32> %result
} }
define i32 @v_srem_i32_pow2_shl_denom(i32 %x, i32 %y) { define i32 @v_srem_i32_pow2_shl_denom(i32 %x, i32 %y) {
; CHECK-LABEL: v_srem_i32_pow2_shl_denom: ; CHECK-LABEL: v_srem_i32_pow2_shl_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
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llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll

Show First 20 Lines • Show All 217 Lines • ▼ Show 20 Lines; CGP-NEXT: s_setpc_b64 s[30:31]
ret <2 x i32> %result ret <2 x i32> %result
} }
define i32 @v_udiv_i32_pow2k_denom(i32 %num) { define i32 @v_udiv_i32_pow2k_denom(i32 %num) {
; CHECK-LABEL: v_udiv_i32_pow2k_denom: ; CHECK-LABEL: v_udiv_i32_pow2k_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_movk_i32 s6, 0x1000 ; CHECK-NEXT: s_movk_i32 s6, 0x1000
; CHECK-NEXT: v_mov_b32_e32 v1, 0xfffff000 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v1, 0x45800000
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s6 ; CHECK-NEXT: v_mov_b32_e32 v2, 0xfffff000
; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CHECK-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; CHECK-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v1, v1
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_mul_lo_u32 v2, v2, v1
; CHECK-NEXT: v_mul_lo_u32 v1, v1, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
; CHECK-NEXT: v_mul_hi_u32 v1, v2, v1 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
; CHECK-NEXT: v_lshlrev_b32_e32 v2, 12, v1 ; CHECK-NEXT: v_lshlrev_b32_e32 v2, 12, v1
; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v1 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v1
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; CHECK-NEXT: v_subrev_i32_e64 v2, s[4:5], s6, v0 ; CHECK-NEXT: v_subrev_i32_e64 v2, s[4:5], s6, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
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; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
; GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_udiv_v2i32_pow2k_denom: ; CGP-LABEL: v_udiv_v2i32_pow2k_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: s_movk_i32 s4, 0x1000 ; CGP-NEXT: s_movk_i32 s8, 0x1000
; CGP-NEXT: v_mov_b32_e32 v2, 0x1000 ; CGP-NEXT: v_rcp_iflag_f32_e32 v2, 0x45800000
; CGP-NEXT: s_movk_i32 s5, 0xf000 ; CGP-NEXT: s_movk_i32 s4, 0xf000
; CGP-NEXT: v_mov_b32_e32 v3, 0xfffff000 ; CGP-NEXT: v_mov_b32_e32 v3, 0xfffff000
; CGP-NEXT: v_cvt_f32_u32_e32 v4, s4 ; CGP-NEXT: v_mov_b32_e32 v4, 0x1000
; CGP-NEXT: v_cvt_f32_u32_e32 v5, v2 ; CGP-NEXT: v_rcp_iflag_f32_e32 v5, 0x45800000
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v5
; CGP-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
; CGP-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5 ; CGP-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5
; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v5, v5 ; CGP-NEXT: v_cvt_u32_f32_e32 v5, v5
; CGP-NEXT: v_mul_lo_u32 v6, s5, v4 ; CGP-NEXT: v_mul_lo_u32 v6, s4, v2
; CGP-NEXT: v_mul_lo_u32 v3, v3, v5 ; CGP-NEXT: v_mul_lo_u32 v3, v3, v5
; CGP-NEXT: v_mul_hi_u32 v6, v4, v6 ; CGP-NEXT: v_mul_hi_u32 v6, v2, v6
; CGP-NEXT: v_mul_hi_u32 v3, v5, v3 ; CGP-NEXT: v_mul_hi_u32 v3, v5, v3
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CGP-NEXT: v_add_i32_e32 v3, vcc, v5, v3 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; CGP-NEXT: v_mul_hi_u32 v4, v0, v4 ; CGP-NEXT: v_mul_hi_u32 v2, v0, v2
; CGP-NEXT: v_mul_hi_u32 v3, v1, v3 ; CGP-NEXT: v_mul_hi_u32 v3, v1, v3
; CGP-NEXT: v_lshlrev_b32_e32 v5, 12, v4 ; CGP-NEXT: v_lshlrev_b32_e32 v5, 12, v2
; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v4 ; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v2
; CGP-NEXT: v_lshlrev_b32_e32 v7, 12, v3 ; CGP-NEXT: v_lshlrev_b32_e32 v7, 12, v3
; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v3 ; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v3
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v5 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v7 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v7
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; CGP-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; CGP-NEXT: v_subrev_i32_e64 v5, s[4:5], s4, v0 ; CGP-NEXT: v_subrev_i32_e64 v5, s[4:5], s8, v0
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v2 ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s8, v1
; CGP-NEXT: v_cndmask_b32_e64 v3, v3, v8, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v3, v3, v8, s[4:5]
; CGP-NEXT: v_sub_i32_e64 v6, s[6:7], v1, v2 ; CGP-NEXT: v_sub_i32_e64 v6, s[6:7], v1, v4
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; CGP-NEXT: v_add_i32_e32 v5, vcc, 1, v4 ; CGP-NEXT: v_add_i32_e32 v5, vcc, 1, v2
; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[4:5]
; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v3 ; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v3
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; CGP-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v4
; CGP-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%result = udiv <2 x i32> %num, <i32 4096, i32 4096> %result = udiv <2 x i32> %num, <i32 4096, i32 4096>
ret <2 x i32> %result ret <2 x i32> %result
} }
define i32 @v_udiv_i32_oddk_denom(i32 %num) { define i32 @v_udiv_i32_oddk_denom(i32 %num) {
; CHECK-LABEL: v_udiv_i32_oddk_denom: ; CHECK-LABEL: v_udiv_i32_oddk_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_mov_b32 s6, 0x12d8fb ; CHECK-NEXT: s_mov_b32 s6, 0x12d8fb
; CHECK-NEXT: v_mov_b32_e32 v1, 0xffed2705 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v1, 0x4996c7d8
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s6 ; CHECK-NEXT: v_mov_b32_e32 v2, 0xffed2705
; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CHECK-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; CHECK-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v1, v1
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_mul_lo_u32 v2, v2, v1
; CHECK-NEXT: v_mul_lo_u32 v1, v1, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
; CHECK-NEXT: v_mul_hi_u32 v1, v2, v1 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
; CHECK-NEXT: v_mul_lo_u32 v2, v1, s6 ; CHECK-NEXT: v_mul_lo_u32 v2, v1, s6
; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v1 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v1
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; CHECK-NEXT: v_subrev_i32_e64 v2, s[4:5], s6, v0 ; CHECK-NEXT: v_subrev_i32_e64 v2, s[4:5], s6, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
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; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
; GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_udiv_v2i32_oddk_denom: ; CGP-LABEL: v_udiv_v2i32_oddk_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: s_mov_b32 s4, 0x12d8fb ; CGP-NEXT: s_mov_b32 s8, 0x12d8fb
; CGP-NEXT: v_mov_b32_e32 v2, 0x12d8fb ; CGP-NEXT: v_rcp_iflag_f32_e32 v2, 0x4996c7d8
; CGP-NEXT: s_mov_b32 s5, 0xffed2705 ; CGP-NEXT: s_mov_b32 s4, 0xffed2705
; CGP-NEXT: v_cvt_f32_u32_e32 v3, s4 ; CGP-NEXT: v_mov_b32_e32 v3, 0x12d8fb
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2 ; CGP-NEXT: v_rcp_iflag_f32_e32 v4, 0x4996c7d8
; CGP-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; CGP-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4 ; CGP-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
; CGP-NEXT: v_cvt_u32_f32_e32 v3, v3 ; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
; CGP-NEXT: v_mul_lo_u32 v5, s5, v3 ; CGP-NEXT: v_mul_lo_u32 v5, s4, v2
; CGP-NEXT: v_mul_lo_u32 v6, s5, v4 ; CGP-NEXT: v_mul_lo_u32 v6, s4, v4
; CGP-NEXT: v_mul_hi_u32 v5, v3, v5 ; CGP-NEXT: v_mul_hi_u32 v5, v2, v5
; CGP-NEXT: v_mul_hi_u32 v6, v4, v6 ; CGP-NEXT: v_mul_hi_u32 v6, v4, v6
; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; CGP-NEXT: v_mul_hi_u32 v3, v0, v3 ; CGP-NEXT: v_mul_hi_u32 v2, v0, v2
; CGP-NEXT: v_mul_hi_u32 v4, v1, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v1, v4
; CGP-NEXT: v_mul_lo_u32 v5, v3, s4 ; CGP-NEXT: v_mul_lo_u32 v5, v2, s8
; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v3 ; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v2
; CGP-NEXT: v_mul_lo_u32 v7, v4, v2 ; CGP-NEXT: v_mul_lo_u32 v7, v4, s8
; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v5 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v7 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v7
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; CGP-NEXT: v_subrev_i32_e64 v5, s[4:5], s4, v0 ; CGP-NEXT: v_subrev_i32_e64 v5, s[4:5], s8, v0
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v2 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3
; CGP-NEXT: v_cndmask_b32_e64 v4, v4, v8, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v4, v4, v8, s[4:5]
; CGP-NEXT: v_sub_i32_e64 v6, s[6:7], v1, v2 ; CGP-NEXT: v_sub_i32_e64 v6, s[6:7], v1, v3
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; CGP-NEXT: v_add_i32_e32 v5, vcc, 1, v3 ; CGP-NEXT: v_add_i32_e32 v5, vcc, 1, v2
; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[4:5]
; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v4 ; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v4
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; CGP-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
; CGP-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%result = udiv <2 x i32> %num, <i32 1235195, i32 1235195> %result = udiv <2 x i32> %num, <i32 1235195, i32 1235195>
ret <2 x i32> %result ret <2 x i32> %result
} }
define i32 @v_udiv_i32_pow2_shl_denom(i32 %x, i32 %y) { define i32 @v_udiv_i32_pow2_shl_denom(i32 %x, i32 %y) {
; CHECK-LABEL: v_udiv_i32_pow2_shl_denom: ; CHECK-LABEL: v_udiv_i32_pow2_shl_denom:
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llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll

Show First 20 Lines • Show All 224 Lines • ▼ Show 20 Lines; CHECK-NEXT: s_setpc_b64 s[30:31]
ret <2 x i32> %result ret <2 x i32> %result
} }
define i32 @v_urem_i32_oddk_denom(i32 %num) { define i32 @v_urem_i32_oddk_denom(i32 %num) {
; CHECK-LABEL: v_urem_i32_oddk_denom: ; CHECK-LABEL: v_urem_i32_oddk_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_mov_b32 s4, 0x12d8fb ; CHECK-NEXT: s_mov_b32 s4, 0x12d8fb
; CHECK-NEXT: v_mov_b32_e32 v1, 0xffed2705 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v1, 0x4996c7d8
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s4 ; CHECK-NEXT: v_mov_b32_e32 v2, 0xffed2705
; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CHECK-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; CHECK-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v1, v1
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_mul_lo_u32 v2, v2, v1
; CHECK-NEXT: v_mul_lo_u32 v1, v1, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
; CHECK-NEXT: v_mul_hi_u32 v1, v2, v1 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
; CHECK-NEXT: v_mul_lo_u32 v1, v1, s4 ; CHECK-NEXT: v_mul_lo_u32 v1, v1, s4
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0 ; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0 ; CHECK-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
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; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_urem_v2i32_oddk_denom: ; CGP-LABEL: v_urem_v2i32_oddk_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: s_mov_b32 s4, 0x12d8fb ; CGP-NEXT: s_mov_b32 s4, 0x12d8fb
; CGP-NEXT: v_mov_b32_e32 v2, 0x12d8fb ; CGP-NEXT: v_rcp_iflag_f32_e32 v2, 0x4996c7d8
; CGP-NEXT: s_mov_b32 s5, 0xffed2705 ; CGP-NEXT: s_mov_b32 s5, 0xffed2705
; CGP-NEXT: v_cvt_f32_u32_e32 v3, s4 ; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; CGP-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; CGP-NEXT: v_mul_lo_u32 v3, s5, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v3, v3 ; CGP-NEXT: v_mul_hi_u32 v3, v2, v3
; CGP-NEXT: v_mul_lo_u32 v4, s5, v3 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CGP-NEXT: v_mul_hi_u32 v4, v3, v4 ; CGP-NEXT: v_mul_hi_u32 v3, v0, v2
; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v4 ; CGP-NEXT: v_mul_hi_u32 v2, v1, v2
; CGP-NEXT: v_mul_hi_u32 v4, v0, v3 ; CGP-NEXT: v_mul_lo_u32 v3, v3, s4
; CGP-NEXT: v_mul_hi_u32 v3, v1, v3 ; CGP-NEXT: v_mul_lo_u32 v2, v2, s4
; CGP-NEXT: v_mul_lo_u32 v4, v4, s4 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CGP-NEXT: v_mul_lo_u32 v3, v3, v2 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 ; CGP-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v3 ; CGP-NEXT: v_subrev_i32_e32 v3, vcc, s4, v1
; CGP-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
; CGP-NEXT: v_sub_i32_e32 v4, vcc, v1, v2
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; CGP-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0 ; CGP-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
; CGP-NEXT: v_sub_i32_e32 v4, vcc, v1, v2 ; CGP-NEXT: v_subrev_i32_e32 v3, vcc, 0x12d8fb, v1
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%result = urem <2 x i32> %num, <i32 1235195, i32 1235195> %result = urem <2 x i32> %num, <i32 1235195, i32 1235195>
ret <2 x i32> %result ret <2 x i32> %result
} }
define i32 @v_urem_i32_pow2_shl_denom(i32 %x, i32 %y) { define i32 @v_urem_i32_pow2_shl_denom(i32 %x, i32 %y) {
; CHECK-LABEL: v_urem_i32_pow2_shl_denom: ; CHECK-LABEL: v_urem_i32_pow2_shl_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
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