[RISCV] Add constraint for rvv indexed loads.

[khchen]

Summary

Add the constraint when destination EEW not equals the source EEW.

The RVV spec allow three overlap rules:

1. The destination EEW equals the source EEW.

2. The destination EEW is smaller than the source EEW and the overlap is in the lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi v0, v0, 3 is legal, but a destination of v1 is not).

3. The destination EEW is greater than the source EEW, the source EMUL is at least 1, and the overlap is in the highest-numbered part of the destination register group (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or v4 is not).

Currently I implement the first stricter constraint because I have no idea to
model other overlap rules.

[frasercrmck]

You'll need to update the mgather tests too. Those were probably merged while you were working on this.

[khchen]

Rebase, update mgather tests.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

673

Can we rename HasConstraints to EarlyClobber?

[frasercrmck]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

673

I agree, I think HasConstraints is too vague and is only likely to be used for earlyclobber anyways.

[khchen]

Rename HasConstraints to EarlyClobber.

[frasercrmck]

LGTM. As you say, constraints 2 and 3 are difficult to enforce, but we need this fix for correctness. So I think merging this and revisiting it later is the way to go.

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

class VPseudoSLoadMask<VReg RetClass, bits<7> EEW>:
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoILoadNoMask<VReg RetClass, VReg IdxClass, bits<7> EEW, bits<3> LMUL,
-                         bit Ordered>:
+                         bit Ordered, bit EarlyClobber>:
       Pseudo<(outs RetClass:$rd),
              (ins GPR:$rs1, IdxClass:$rs2, GPR:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLX</*Masked*/0, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasDummyMask = 1;
+  let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd", "");
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoILoadMask<VReg RetClass, VReg IdxClass, bits<7> EEW, bits<3> LMUL,
-                       bit Ordered>:
+                       bit Ordered, bit EarlyClobber>:
       Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
               (ins GetVRegNoV0<RetClass>.R:$merge,
                    GPR:$rs1, IdxClass:$rs2,
                    VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),[]>,
       RISCVVPseudo,
       RISCVVLX</*Masked*/1, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
-  let Constraints = "$rd = $merge";
+  let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $merge", "$rd = $merge");
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoUSStoreNoMask<VReg StClass, bits<7> EEW>:
foreach sew = EEWList in {
         // Calculate emul = eew * lmul / sew
         defvar octuple_emul = !srl(!mul(eew, octuple_lmul), shift_amount<sew>.val);
         if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
           defvar LInfo = lmul.MX;
           defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
           defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
           defvar Vreg = lmul.vrclass;
           defvar IdxVreg = idx_lmul.vrclass;
+          defvar HasConstraint = !ne(sew, eew);
           let VLMul = lmul.value in {
             def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo :
-              VPseudoILoadNoMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered>;
+              VPseudoILoadNoMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered, HasConstraint>;
             def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo # "_MASK" :
-              VPseudoILoadMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered>;
+              VPseudoILoadMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered, HasConstraint>;
           }
         }
       }
     }
   }
 }
 
 multiclass VPseudoUSStore {

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

; RV64-NEXT:    ret
   %v = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, i32 1, <4 x i1> %m, <4 x i8> %passthru)
   ret <4 x i8> %v
 }
 
 define <4 x i8> @mgather_truemask_v4i8(<4 x i8*> %ptrs, <4 x i8> %passthru) {
 ; RV32-LABEL: mgather_truemask_v4i8:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
-; RV32-NEXT:    vloxei32.v v8, (zero), v8
+; RV32-NEXT:    vloxei32.v v25, (zero), v8
+; RV32-NEXT:    vmv1r.v v8, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_truemask_v4i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 4, e8,mf4,ta,mu
-; RV64-NEXT:    vloxei64.v v8, (zero), v8
+; RV64-NEXT:    vloxei64.v v25, (zero), v8
+; RV64-NEXT:    vmv1r.v v8, v25
 ; RV64-NEXT:    ret
   %mhead = insertelement <4 x i1> undef, i1 1, i32 0
   %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
   %v = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, i32 1, <4 x i1> %mtrue, <4 x i8> %passthru)
   ret <4 x i8> %v
 }
 
 define <4 x i8> @mgather_falsemask_v4i8(<4 x i8*> %ptrs, <4 x i8> %passthru) {
; RV64-NEXT:    ret
   %v = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> %m, <4 x i16> %passthru)
   ret <4 x i16> %v
 }
 
 define <4 x i16> @mgather_truemask_v4i16(<4 x i16*> %ptrs, <4 x i16> %passthru) {
 ; RV32-LABEL: mgather_truemask_v4i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
-; RV32-NEXT:    vloxei32.v v8, (zero), v8
+; RV32-NEXT:    vloxei32.v v25, (zero), v8
+; RV32-NEXT:    vmv1r.v v8, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_truemask_v4i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
-; RV64-NEXT:    vloxei64.v v8, (zero), v8
+; RV64-NEXT:    vloxei64.v v25, (zero), v8
+; RV64-NEXT:    vmv1r.v v8, v25
 ; RV64-NEXT:    ret
   %mhead = insertelement <4 x i1> undef, i1 1, i32 0
   %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
   %v = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> %mtrue, <4 x i16> %passthru)
   ret <4 x i16> %v
 }
 
 define <4 x i16> @mgather_falsemask_v4i16(<4 x i16*> %ptrs, <4 x i16> %passthru) {

 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; RV32-NEXT:    vloxei32.v v8, (zero), v8
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_truemask_v4i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; RV64-NEXT:    vloxei64.v v8, (zero), v8
+; RV64-NEXT:    vloxei64.v v25, (zero), v8
+; RV64-NEXT:    vmv1r.v v8, v25
 ; RV64-NEXT:    ret
   %mhead = insertelement <4 x i1> undef, i1 1, i32 0
   %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
   %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> %mtrue, <4 x i32> %passthru)
   ret <4 x i32> %v
 }
 
 define <4 x i32> @mgather_falsemask_v4i32(<4 x i32*> %ptrs, <4 x i32> %passthru) {
; RV64-NEXT:    ret
   %v = call <4 x i64> @llvm.masked.gather.v4i64.v4p0i64(<4 x i64*> %ptrs, i32 8, <4 x i1> %m, <4 x i64> %passthru)
   ret <4 x i64> %v
 }
 
 define <4 x i64> @mgather_truemask_v4i64(<4 x i64*> %ptrs, <4 x i64> %passthru) {
 ; RV32-LABEL: mgather_truemask_v4i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
-; RV32-NEXT:    vloxei32.v v8, (zero), v8
+; RV32-NEXT:    vloxei32.v v26, (zero), v8
+; RV32-NEXT:    vmv2r.v v8, v26
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_truemask_v4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vloxei64.v v8, (zero), v8
 ; RV64-NEXT:    ret
   %mhead = insertelement <4 x i1> undef, i1 1, i32 0
; RV64-NEXT:    ret
   %v = call <4 x half> @llvm.masked.gather.v4f16.v4p0f16(<4 x half*> %ptrs, i32 2, <4 x i1> %m, <4 x half> %passthru)
   ret <4 x half> %v
 }
 
 define <4 x half> @mgather_truemask_v4f16(<4 x half*> %ptrs, <4 x half> %passthru) {
 ; RV32-LABEL: mgather_truemask_v4f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
-; RV32-NEXT:    vloxei32.v v8, (zero), v8
+; RV32-NEXT:    vloxei32.v v25, (zero), v8
+; RV32-NEXT:    vmv1r.v v8, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_truemask_v4f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 4, e16,mf2,ta,mu
-; RV64-NEXT:    vloxei64.v v8, (zero), v8
+; RV64-NEXT:    vloxei64.v v25, (zero), v8
+; RV64-NEXT:    vmv1r.v v8, v25
 ; RV64-NEXT:    ret
   %mhead = insertelement <4 x i1> undef, i1 1, i32 0
   %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
   %v = call <4 x half> @llvm.masked.gather.v4f16.v4p0f16(<4 x half*> %ptrs, i32 2, <4 x i1> %mtrue, <4 x half> %passthru)
   ret <4 x half> %v
 }
 
 define <4 x half> @mgather_falsemask_v4f16(<4 x half*> %ptrs, <4 x half> %passthru) {

 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
 ; RV32-NEXT:    vloxei32.v v8, (zero), v8
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_truemask_v4f32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 4, e32,m1,ta,mu
-; RV64-NEXT:    vloxei64.v v8, (zero), v8
+; RV64-NEXT:    vloxei64.v v25, (zero), v8
+; RV64-NEXT:    vmv1r.v v8, v25
 ; RV64-NEXT:    ret
   %mhead = insertelement <4 x i1> undef, i1 1, i32 0
   %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer
   %v = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %ptrs, i32 4, <4 x i1> %mtrue, <4 x float> %passthru)
   ret <4 x float> %v
 }
 
 define <4 x float> @mgather_falsemask_v4f32(<4 x float*> %ptrs, <4 x float> %passthru) {
; RV64-NEXT:    ret
   %v = call <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> %ptrs, i32 8, <4 x i1> %m, <4 x double> %passthru)
   ret <4 x double> %v
 }
 
 define <4 x double> @mgather_truemask_v4f64(<4 x double*> %ptrs, <4 x double> %passthru) {
 ; RV32-LABEL: mgather_truemask_v4f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
-; RV32-NEXT:    vloxei32.v v8, (zero), v8
+; RV32-NEXT:    vloxei32.v v26, (zero), v8
+; RV32-NEXT:    vmv2r.v v8, v26
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_truemask_v4f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vloxei64.v v8, (zero), v8
 ; RV64-NEXT:    ret
   %mhead = insertelement <4 x i1> undef, i1 1, i32 0

llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll

; RV64-NEXT:    ret
   %v = call <vscale x 4 x i8> @llvm.masked.gather.nxv4i8.nxv4p0i8(<vscale x 4 x i8*> %ptrs, i32 1, <vscale x 4 x i1> %m, <vscale x 4 x i8> %passthru)
   ret <vscale x 4 x i8> %v
 }
 
 define <vscale x 4 x i8> @mgather_truemask_nxv4i8(<vscale x 4 x i8*> %ptrs, <vscale x 4 x i8> %passthru) {
 ; RV32-LABEL: mgather_truemask_nxv4i8:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
-; RV32-NEXT:    vloxei32.v v8, (zero), v8
+; RV32-NEXT:    vloxei32.v v25, (zero), v8
+; RV32-NEXT:    vmv1r.v v8, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_truemask_nxv4i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
-; RV64-NEXT:    vloxei64.v v8, (zero), v8
+; RV64-NEXT:    vloxei64.v v25, (zero), v8
+; RV64-NEXT:    vmv1r.v v8, v25
 ; RV64-NEXT:    ret
   %mhead = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
   %mtrue = shufflevector <vscale x 4 x i1> %mhead, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
   %v = call <vscale x 4 x i8> @llvm.masked.gather.nxv4i8.nxv4p0i8(<vscale x 4 x i8*> %ptrs, i32 1, <vscale x 4 x i1> %mtrue, <vscale x 4 x i8> %passthru)
   ret <vscale x 4 x i8> %v
 }
 
 define <vscale x 4 x i8> @mgather_falsemask_nxv4i8(<vscale x 4 x i8*> %ptrs, <vscale x 4 x i8> %passthru) {
; RV64-NEXT:    ret
   %v = call <vscale x 4 x i16> @llvm.masked.gather.nxv4i16.nxv4p0i16(<vscale x 4 x i16*> %ptrs, i32 2, <vscale x 4 x i1> %m, <vscale x 4 x i16> %passthru)
   ret <vscale x 4 x i16> %v
 }
 
 define <vscale x 4 x i16> @mgather_truemask_nxv4i16(<vscale x 4 x i16*> %ptrs, <vscale x 4 x i16> %passthru) {
 ; RV32-LABEL: mgather_truemask_nxv4i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
-; RV32-NEXT:    vloxei32.v v8, (zero), v8
+; RV32-NEXT:    vloxei32.v v25, (zero), v8
+; RV32-NEXT:    vmv1r.v v8, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_truemask_nxv4i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
-; RV64-NEXT:    vloxei64.v v8, (zero), v8
+; RV64-NEXT:    vloxei64.v v25, (zero), v8
+; RV64-NEXT:    vmv1r.v v8, v25
 ; RV64-NEXT:    ret
   %mhead = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
   %mtrue = shufflevector <vscale x 4 x i1> %mhead, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
   %v = call <vscale x 4 x i16> @llvm.masked.gather.nxv4i16.nxv4p0i16(<vscale x 4 x i16*> %ptrs, i32 2, <vscale x 4 x i1> %mtrue, <vscale x 4 x i16> %passthru)
   ret <vscale x 4 x i16> %v
 }
 
 define <vscale x 4 x i16> @mgather_falsemask_nxv4i16(<vscale x 4 x i16*> %ptrs, <vscale x 4 x i16> %passthru) {

 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; RV32-NEXT:    vloxei32.v v8, (zero), v8
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_truemask_nxv4i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
-; RV64-NEXT:    vloxei64.v v8, (zero), v8
+; RV64-NEXT:    vloxei64.v v26, (zero), v8
+; RV64-NEXT:    vmv2r.v v8, v26
 ; RV64-NEXT:    ret
   %mhead = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
   %mtrue = shufflevector <vscale x 4 x i1> %mhead, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
   %v = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> %ptrs, i32 4, <vscale x 4 x i1> %mtrue, <vscale x 4 x i32> %passthru)
   ret <vscale x 4 x i32> %v
 }
 
 define <vscale x 4 x i32> @mgather_falsemask_nxv4i32(<vscale x 4 x i32*> %ptrs, <vscale x 4 x i32> %passthru) {
; RV64-NEXT:    ret
   %v = call <vscale x 4 x i64> @llvm.masked.gather.nxv4i64.nxv4p0i64(<vscale x 4 x i64*> %ptrs, i32 8, <vscale x 4 x i1> %m, <vscale x 4 x i64> %passthru)
   ret <vscale x 4 x i64> %v
 }
 
 define <vscale x 4 x i64> @mgather_truemask_nxv4i64(<vscale x 4 x i64*> %ptrs, <vscale x 4 x i64> %passthru) {
 ; RV32-LABEL: mgather_truemask_nxv4i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
-; RV32-NEXT:    vloxei32.v v8, (zero), v8
+; RV32-NEXT:    vloxei32.v v28, (zero), v8
+; RV32-NEXT:    vmv4r.v v8, v28
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_truemask_nxv4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; RV64-NEXT:    vloxei64.v v8, (zero), v8
 ; RV64-NEXT:    ret
   %mhead = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
; RV64-NEXT:    ret
   %v = call <vscale x 4 x half> @llvm.masked.gather.nxv4f16.nxv4p0f16(<vscale x 4 x half*> %ptrs, i32 2, <vscale x 4 x i1> %m, <vscale x 4 x half> %passthru)
   ret <vscale x 4 x half> %v
 }
 
 define <vscale x 4 x half> @mgather_truemask_nxv4f16(<vscale x 4 x half*> %ptrs, <vscale x 4 x half> %passthru) {
 ; RV32-LABEL: mgather_truemask_nxv4f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
-; RV32-NEXT:    vloxei32.v v8, (zero), v8
+; RV32-NEXT:    vloxei32.v v25, (zero), v8
+; RV32-NEXT:    vmv1r.v v8, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_truemask_nxv4f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
-; RV64-NEXT:    vloxei64.v v8, (zero), v8
+; RV64-NEXT:    vloxei64.v v25, (zero), v8
+; RV64-NEXT:    vmv1r.v v8, v25
 ; RV64-NEXT:    ret
   %mhead = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
   %mtrue = shufflevector <vscale x 4 x i1> %mhead, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
   %v = call <vscale x 4 x half> @llvm.masked.gather.nxv4f16.nxv4p0f16(<vscale x 4 x half*> %ptrs, i32 2, <vscale x 4 x i1> %mtrue, <vscale x 4 x half> %passthru)
   ret <vscale x 4 x half> %v
 }
 
 define <vscale x 4 x half> @mgather_falsemask_nxv4f16(<vscale x 4 x half*> %ptrs, <vscale x 4 x half> %passthru) {

 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; RV32-NEXT:    vloxei32.v v8, (zero), v8
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_truemask_nxv4f32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
-; RV64-NEXT:    vloxei64.v v8, (zero), v8
+; RV64-NEXT:    vloxei64.v v26, (zero), v8
+; RV64-NEXT:    vmv2r.v v8, v26
 ; RV64-NEXT:    ret
   %mhead = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
   %mtrue = shufflevector <vscale x 4 x i1> %mhead, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
   %v = call <vscale x 4 x float> @llvm.masked.gather.nxv4f32.nxv4p0f32(<vscale x 4 x float*> %ptrs, i32 4, <vscale x 4 x i1> %mtrue, <vscale x 4 x float> %passthru)
   ret <vscale x 4 x float> %v
 }
 
 define <vscale x 4 x float> @mgather_falsemask_nxv4f32(<vscale x 4 x float*> %ptrs, <vscale x 4 x float> %passthru) {
; RV64-NEXT:    ret
   %v = call <vscale x 4 x double> @llvm.masked.gather.nxv4f64.nxv4p0f64(<vscale x 4 x double*> %ptrs, i32 8, <vscale x 4 x i1> %m, <vscale x 4 x double> %passthru)
   ret <vscale x 4 x double> %v
 }
 
 define <vscale x 4 x double> @mgather_truemask_nxv4f64(<vscale x 4 x double*> %ptrs, <vscale x 4 x double> %passthru) {
 ; RV32-LABEL: mgather_truemask_nxv4f64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
-; RV32-NEXT:    vloxei32.v v8, (zero), v8
+; RV32-NEXT:    vloxei32.v v28, (zero), v8
+; RV32-NEXT:    vmv4r.v v8, v28
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_truemask_nxv4f64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; RV64-NEXT:    vloxei64.v v8, (zero), v8
 ; RV64-NEXT:    ret
   %mhead = insertelement <vscale x 4 x i1> undef, i1 1, i32 0

llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh,+f,+d -verify-machineinstrs \
 ; RUN:   --riscv-no-aliases < %s | FileCheck %s
 declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32(
   <vscale x 1 x i8>*,
   <vscale x 1 x i32>,
   i32);
 
 define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32(
     <vscale x 1 x i8>* %0,
     <vscale x 1 x i32> %1,
     i32 %2)
 
   ret <vscale x 1 x i8> %a
declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32(
   <vscale x 2 x i8>*,
   <vscale x 2 x i32>,
   i32);
 
 define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32(
     <vscale x 2 x i8>* %0,
     <vscale x 2 x i32> %1,
     i32 %2)
 
   ret <vscale x 2 x i8> %a
declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32(
   <vscale x 4 x i8>*,
   <vscale x 4 x i32>,
   i32);
 
 define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32(
     <vscale x 4 x i8>* %0,
     <vscale x 4 x i32> %1,
     i32 %2)
 
   ret <vscale x 4 x i8> %a
declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32(
   <vscale x 8 x i8>*,
   <vscale x 8 x i32>,
   i32);
 
 define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32(
     <vscale x 8 x i8>* %0,
     <vscale x 8 x i32> %1,
     i32 %2)
 
   ret <vscale x 8 x i8> %a
declare <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32(
   <vscale x 16 x i8>*,
   <vscale x 16 x i32>,
   i32);
 
 define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32(
     <vscale x 16 x i8>* %0,
     <vscale x 16 x i32> %1,
     i32 %2)
 
   ret <vscale x 16 x i8> %a
declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32(
   <vscale x 1 x i16>*,
   <vscale x 1 x i32>,
   i32);
 
 define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32(
     <vscale x 1 x i16>* %0,
     <vscale x 1 x i32> %1,
     i32 %2)
 
   ret <vscale x 1 x i16> %a
declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32(
   <vscale x 2 x i16>*,
   <vscale x 2 x i32>,
   i32);
 
 define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32(
     <vscale x 2 x i16>* %0,
     <vscale x 2 x i32> %1,
     i32 %2)
 
   ret <vscale x 2 x i16> %a
declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32(
   <vscale x 4 x i16>*,
   <vscale x 4 x i32>,
   i32);
 
 define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32(
     <vscale x 4 x i16>* %0,
     <vscale x 4 x i32> %1,
     i32 %2)
 
   ret <vscale x 4 x i16> %a
declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32(
   <vscale x 8 x i16>*,
   <vscale x 8 x i32>,
   i32);
 
 define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32(
     <vscale x 8 x i16>* %0,
     <vscale x 8 x i32> %1,
     i32 %2)
 
   ret <vscale x 8 x i16> %a
declare <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32(
   <vscale x 16 x i16>*,
   <vscale x 16 x i32>,
   i32);
 
 define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32(
     <vscale x 16 x i16>* %0,
     <vscale x 16 x i32> %1,
     i32 %2)
 
   ret <vscale x 16 x i16> %a
declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32(
   <vscale x 1 x half>*,
   <vscale x 1 x i32>,
   i32);
 
 define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32(
     <vscale x 1 x half>* %0,
     <vscale x 1 x i32> %1,
     i32 %2)
 
   ret <vscale x 1 x half> %a
declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32(
   <vscale x 2 x half>*,
   <vscale x 2 x i32>,
   i32);
 
 define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32(
     <vscale x 2 x half>* %0,
     <vscale x 2 x i32> %1,
     i32 %2)
 
   ret <vscale x 2 x half> %a
declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32(
   <vscale x 4 x half>*,
   <vscale x 4 x i32>,
   i32);
 
 define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32(
     <vscale x 4 x half>* %0,
     <vscale x 4 x i32> %1,
     i32 %2)
 
   ret <vscale x 4 x half> %a
declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32(
   <vscale x 8 x half>*,
   <vscale x 8 x i32>,
   i32);
 
 define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32(
     <vscale x 8 x half>* %0,
     <vscale x 8 x i32> %1,
     i32 %2)
 
   ret <vscale x 8 x half> %a
declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32(
   <vscale x 16 x half>*,
   <vscale x 16 x i32>,
   i32);
 
 define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32(
     <vscale x 16 x half>* %0,
     <vscale x 16 x i32> %1,
     i32 %2)
 
   ret <vscale x 16 x half> %a
declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32(
   <vscale x 1 x double>*,
   <vscale x 1 x i32>,
   i32);
 
 define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32(
     <vscale x 1 x double>* %0,
     <vscale x 1 x i32> %1,
     i32 %2)
 
   ret <vscale x 1 x double> %a
declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32(
   <vscale x 2 x double>*,
   <vscale x 2 x i32>,
   i32);
 
 define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32(
     <vscale x 2 x double>* %0,
     <vscale x 2 x i32> %1,
     i32 %2)
 
   ret <vscale x 2 x double> %a
declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32(
   <vscale x 4 x double>*,
   <vscale x 4 x i32>,
   i32);
 
 define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32(
     <vscale x 4 x double>* %0,
     <vscale x 4 x i32> %1,
     i32 %2)
 
   ret <vscale x 4 x double> %a
declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i32(
   <vscale x 8 x double>*,
   <vscale x 8 x i32>,
   i32);
 
 define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i32(
     <vscale x 8 x double>* %0,
     <vscale x 8 x i32> %1,
     i32 %2)
 
   ret <vscale x 8 x double> %a
declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16(
   <vscale x 1 x i8>*,
   <vscale x 1 x i16>,
   i32);
 
 define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16(
     <vscale x 1 x i8>* %0,
     <vscale x 1 x i16> %1,
     i32 %2)
 
   ret <vscale x 1 x i8> %a
declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16(
   <vscale x 2 x i8>*,
   <vscale x 2 x i16>,
   i32);
 
 define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16(
     <vscale x 2 x i8>* %0,
     <vscale x 2 x i16> %1,
     i32 %2)
 
   ret <vscale x 2 x i8> %a
declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16(
   <vscale x 4 x i8>*,
   <vscale x 4 x i16>,
   i32);
 
 define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16(
     <vscale x 4 x i8>* %0,
     <vscale x 4 x i16> %1,
     i32 %2)
 
   ret <vscale x 4 x i8> %a
declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16(
   <vscale x 8 x i8>*,
   <vscale x 8 x i16>,
   i32);
 
 define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16(
     <vscale x 8 x i8>* %0,
     <vscale x 8 x i16> %1,
     i32 %2)
 
   ret <vscale x 8 x i8> %a
declare <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16(
   <vscale x 16 x i8>*,
   <vscale x 16 x i16>,
   i32);
 
 define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16(
     <vscale x 16 x i8>* %0,
     <vscale x 16 x i16> %1,
     i32 %2)
 
   ret <vscale x 16 x i8> %a
declare <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16(
   <vscale x 32 x i8>*,
   <vscale x 32 x i16>,
   i32);
 
 define <vscale x 32 x i8> @intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8>* %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16(
     <vscale x 32 x i8>* %0,
     <vscale x 32 x i16> %1,
     i32 %2)
 
   ret <vscale x 32 x i8> %a
declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16(
   <vscale x 1 x i32>*,
   <vscale x 1 x i16>,
   i32);
 
 define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16(
     <vscale x 1 x i32>* %0,
     <vscale x 1 x i16> %1,
     i32 %2)
 
   ret <vscale x 1 x i32> %a
declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16(
   <vscale x 2 x i32>*,
   <vscale x 2 x i16>,
   i32);
 
 define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16(
     <vscale x 2 x i32>* %0,
     <vscale x 2 x i16> %1,
     i32 %2)
 
   ret <vscale x 2 x i32> %a
declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16(
   <vscale x 4 x i32>*,
   <vscale x 4 x i16>,
   i32);
 
 define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16(
     <vscale x 4 x i32>* %0,
     <vscale x 4 x i16> %1,
     i32 %2)
 
   ret <vscale x 4 x i32> %a
declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16(
   <vscale x 8 x i32>*,
   <vscale x 8 x i16>,
   i32);
 
 define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16(
     <vscale x 8 x i32>* %0,
     <vscale x 8 x i16> %1,
     i32 %2)
 
   ret <vscale x 8 x i32> %a
declare <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16(
   <vscale x 16 x i32>*,
   <vscale x 16 x i16>,
   i32);
 
 define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16(
     <vscale x 16 x i32>* %0,
     <vscale x 16 x i16> %1,
     i32 %2)
 
   ret <vscale x 16 x i32> %a
declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16(
   <vscale x 1 x float>*,
   <vscale x 1 x i16>,
   i32);
 
 define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16(
     <vscale x 1 x float>* %0,
     <vscale x 1 x i16> %1,
     i32 %2)
 
   ret <vscale x 1 x float> %a
declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16(
   <vscale x 2 x float>*,
   <vscale x 2 x i16>,
   i32);
 
 define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16(
     <vscale x 2 x float>* %0,
     <vscale x 2 x i16> %1,
     i32 %2)
 
   ret <vscale x 2 x float> %a
declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16(
   <vscale x 4 x float>*,
   <vscale x 4 x i16>,
   i32);
 
 define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16(
     <vscale x 4 x float>* %0,
     <vscale x 4 x i16> %1,
     i32 %2)
 
   ret <vscale x 4 x float> %a
declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16(
   <vscale x 8 x float>*,
   <vscale x 8 x i16>,
   i32);
 
 define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16(
     <vscale x 8 x float>* %0,
     <vscale x 8 x i16> %1,
     i32 %2)
 
   ret <vscale x 8 x float> %a
declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i16(
   <vscale x 16 x float>*,
   <vscale x 16 x i16>,
   i32);
 
 define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i16(
     <vscale x 16 x float>* %0,
     <vscale x 16 x i16> %1,
     i32 %2)
 
   ret <vscale x 16 x float> %a
declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16(
   <vscale x 1 x double>*,
   <vscale x 1 x i16>,
   i32);
 
 define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16(
     <vscale x 1 x double>* %0,
     <vscale x 1 x i16> %1,
     i32 %2)
 
   ret <vscale x 1 x double> %a
declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16(
   <vscale x 2 x double>*,
   <vscale x 2 x i16>,
   i32);
 
 define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16(
     <vscale x 2 x double>* %0,
     <vscale x 2 x i16> %1,
     i32 %2)
 
   ret <vscale x 2 x double> %a
declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16(
   <vscale x 4 x double>*,
   <vscale x 4 x i16>,
   i32);
 
 define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16(
     <vscale x 4 x double>* %0,
     <vscale x 4 x i16> %1,
     i32 %2)
 
   ret <vscale x 4 x double> %a
declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i16(
   <vscale x 8 x double>*,
   <vscale x 8 x i16>,
   i32);
 
 define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i16(
     <vscale x 8 x double>* %0,
     <vscale x 8 x i16> %1,
     i32 %2)
 
   ret <vscale x 8 x double> %a
declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8(
   <vscale x 1 x i16>*,
   <vscale x 1 x i8>,
   i32);
 
 define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8(
     <vscale x 1 x i16>* %0,
     <vscale x 1 x i8> %1,
     i32 %2)
 
   ret <vscale x 1 x i16> %a
declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8(
   <vscale x 2 x i16>*,
   <vscale x 2 x i8>,
   i32);
 
 define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8(
     <vscale x 2 x i16>* %0,
     <vscale x 2 x i8> %1,
     i32 %2)
 
   ret <vscale x 2 x i16> %a
declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8(
   <vscale x 4 x i16>*,
   <vscale x 4 x i8>,
   i32);
 
 define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8(
     <vscale x 4 x i16>* %0,
     <vscale x 4 x i8> %1,
     i32 %2)
 
   ret <vscale x 4 x i16> %a
declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8(
   <vscale x 8 x i16>*,
   <vscale x 8 x i8>,
   i32);
 
 define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8(
     <vscale x 8 x i16>* %0,
     <vscale x 8 x i8> %1,
     i32 %2)
 
   ret <vscale x 8 x i16> %a
declare <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8(
   <vscale x 16 x i16>*,
   <vscale x 16 x i8>,
   i32);
 
 define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8(
     <vscale x 16 x i16>* %0,
     <vscale x 16 x i8> %1,
     i32 %2)
 
   ret <vscale x 16 x i16> %a
declare <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8(
   <vscale x 32 x i16>*,
   <vscale x 32 x i8>,
   i32);
 
 define <vscale x 32 x i16> @intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m8,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8(
     <vscale x 32 x i16>* %0,
     <vscale x 32 x i8> %1,
     i32 %2)
 
   ret <vscale x 32 x i16> %a
declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8(
   <vscale x 1 x i32>*,
   <vscale x 1 x i8>,
   i32);
 
 define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8(
     <vscale x 1 x i32>* %0,
     <vscale x 1 x i8> %1,
     i32 %2)
 
   ret <vscale x 1 x i32> %a
declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8(
   <vscale x 2 x i32>*,
   <vscale x 2 x i8>,
   i32);
 
 define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8(
     <vscale x 2 x i32>* %0,
     <vscale x 2 x i8> %1,
     i32 %2)
 
   ret <vscale x 2 x i32> %a
declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8(
   <vscale x 4 x i32>*,
   <vscale x 4 x i8>,
   i32);
 
 define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8(
     <vscale x 4 x i32>* %0,
     <vscale x 4 x i8> %1,
     i32 %2)
 
   ret <vscale x 4 x i32> %a
declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8(
   <vscale x 8 x i32>*,
   <vscale x 8 x i8>,
   i32);
 
 define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8(
     <vscale x 8 x i32>* %0,
     <vscale x 8 x i8> %1,
     i32 %2)
 
   ret <vscale x 8 x i32> %a
declare <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8(
   <vscale x 16 x i32>*,
   <vscale x 16 x i8>,
   i32);
 
 define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8(
     <vscale x 16 x i32>* %0,
     <vscale x 16 x i8> %1,
     i32 %2)
 
   ret <vscale x 16 x i32> %a
declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8(
   <vscale x 1 x half>*,
   <vscale x 1 x i8>,
   i32);
 
 define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8(
     <vscale x 1 x half>* %0,
     <vscale x 1 x i8> %1,
     i32 %2)
 
   ret <vscale x 1 x half> %a
declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8(
   <vscale x 2 x half>*,
   <vscale x 2 x i8>,
   i32);
 
 define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8(
     <vscale x 2 x half>* %0,
     <vscale x 2 x i8> %1,
     i32 %2)
 
   ret <vscale x 2 x half> %a
declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8(
   <vscale x 4 x half>*,
   <vscale x 4 x i8>,
   i32);
 
 define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8(
     <vscale x 4 x half>* %0,
     <vscale x 4 x i8> %1,
     i32 %2)
 
   ret <vscale x 4 x half> %a
declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8(
   <vscale x 8 x half>*,
   <vscale x 8 x i8>,
   i32);
 
 define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8(
     <vscale x 8 x half>* %0,
     <vscale x 8 x i8> %1,
     i32 %2)
 
   ret <vscale x 8 x half> %a
declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8(
   <vscale x 16 x half>*,
   <vscale x 16 x i8>,
   i32);
 
 define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8(
     <vscale x 16 x half>* %0,
     <vscale x 16 x i8> %1,
     i32 %2)
 
   ret <vscale x 16 x half> %a
declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i8(
   <vscale x 32 x half>*,
   <vscale x 32 x i8>,
   i32);
 
 define <vscale x 32 x half> @intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m8,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i8(
     <vscale x 32 x half>* %0,
     <vscale x 32 x i8> %1,
     i32 %2)
 
   ret <vscale x 32 x half> %a
declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8(
   <vscale x 1 x float>*,
   <vscale x 1 x i8>,
   i32);
 
 define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8(
     <vscale x 1 x float>* %0,
     <vscale x 1 x i8> %1,
     i32 %2)
 
   ret <vscale x 1 x float> %a
declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8(
   <vscale x 2 x float>*,
   <vscale x 2 x i8>,
   i32);
 
 define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8(
     <vscale x 2 x float>* %0,
     <vscale x 2 x i8> %1,
     i32 %2)
 
   ret <vscale x 2 x float> %a
declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8(
   <vscale x 4 x float>*,
   <vscale x 4 x i8>,
   i32);
 
 define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8(
     <vscale x 4 x float>* %0,
     <vscale x 4 x i8> %1,
     i32 %2)
 
   ret <vscale x 4 x float> %a
declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8(
   <vscale x 8 x float>*,
   <vscale x 8 x i8>,
   i32);
 
 define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8(
     <vscale x 8 x float>* %0,
     <vscale x 8 x i8> %1,
     i32 %2)
 
   ret <vscale x 8 x float> %a
declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i8(
   <vscale x 16 x float>*,
   <vscale x 16 x i8>,
   i32);
 
 define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i8(
     <vscale x 16 x float>* %0,
     <vscale x 16 x i8> %1,
     i32 %2)
 
   ret <vscale x 16 x float> %a
declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8(
   <vscale x 1 x double>*,
   <vscale x 1 x i8>,
   i32);
 
 define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8(
     <vscale x 1 x double>* %0,
     <vscale x 1 x i8> %1,
     i32 %2)
 
   ret <vscale x 1 x double> %a
declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8(
   <vscale x 2 x double>*,
   <vscale x 2 x i8>,
   i32);
 
 define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8(
     <vscale x 2 x double>* %0,
     <vscale x 2 x i8> %1,
     i32 %2)
 
   ret <vscale x 2 x double> %a
declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8(
   <vscale x 4 x double>*,
   <vscale x 4 x i8>,
   i32);
 
 define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8(
     <vscale x 4 x double>* %0,
     <vscale x 4 x i8> %1,
     i32 %2)
 
   ret <vscale x 4 x double> %a
declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i8(
   <vscale x 8 x double>*,
   <vscale x 8 x i8>,
   i32);
 
 define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i8(
     <vscale x 8 x double>* %0,
     <vscale x 8 x i8> %1,
     i32 %2)
 
   ret <vscale x 8 x double> %a

llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh,+f,+d -verify-machineinstrs \
 ; RUN:   --riscv-no-aliases < %s | FileCheck %s
 declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64(
   <vscale x 1 x i8>*,
   <vscale x 1 x i64>,
   i64);
 
 define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i64(
     <vscale x 1 x i8>* %0,
     <vscale x 1 x i64> %1,
     i64 %2)
 
   ret <vscale x 1 x i8> %a
declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i64(
   <vscale x 2 x i8>*,
   <vscale x 2 x i64>,
   i64);
 
 define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i64(
     <vscale x 2 x i8>* %0,
     <vscale x 2 x i64> %1,
     i64 %2)
 
   ret <vscale x 2 x i8> %a
declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i64(
   <vscale x 4 x i8>*,
   <vscale x 4 x i64>,
   i64);
 
 define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i64(
     <vscale x 4 x i8>* %0,
     <vscale x 4 x i64> %1,
     i64 %2)
 
   ret <vscale x 4 x i8> %a
declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i64(
   <vscale x 8 x i8>*,
   <vscale x 8 x i64>,
   i64);
 
 define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i64(
     <vscale x 8 x i8>* %0,
     <vscale x 8 x i64> %1,
     i64 %2)
 
   ret <vscale x 8 x i8> %a
declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64(
   <vscale x 1 x i16>*,
   <vscale x 1 x i64>,
   i64);
 
 define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i64(
     <vscale x 1 x i16>* %0,
     <vscale x 1 x i64> %1,
     i64 %2)
 
   ret <vscale x 1 x i16> %a
declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i64(
   <vscale x 2 x i16>*,
   <vscale x 2 x i64>,
   i64);
 
 define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i64(
     <vscale x 2 x i16>* %0,
     <vscale x 2 x i64> %1,
     i64 %2)
 
   ret <vscale x 2 x i16> %a
declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i64(
   <vscale x 4 x i16>*,
   <vscale x 4 x i64>,
   i64);
 
 define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i64(
     <vscale x 4 x i16>* %0,
     <vscale x 4 x i64> %1,
     i64 %2)
 
   ret <vscale x 4 x i16> %a
declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i64(
   <vscale x 8 x i16>*,
   <vscale x 8 x i64>,
   i64);
 
 define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i64(
     <vscale x 8 x i16>* %0,
     <vscale x 8 x i64> %1,
     i64 %2)
 
   ret <vscale x 8 x i16> %a
declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64(
   <vscale x 1 x i32>*,
   <vscale x 1 x i64>,
   i64);
 
 define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i64(
     <vscale x 1 x i32>* %0,
     <vscale x 1 x i64> %1,
     i64 %2)
 
   ret <vscale x 1 x i32> %a
declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i64(
   <vscale x 2 x i32>*,
   <vscale x 2 x i64>,
   i64);
 
 define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i64(
     <vscale x 2 x i32>* %0,
     <vscale x 2 x i64> %1,
     i64 %2)
 
   ret <vscale x 2 x i32> %a
declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(
   <vscale x 4 x i32>*,
   <vscale x 4 x i64>,
   i64);
 
 define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i64(
     <vscale x 4 x i32>* %0,
     <vscale x 4 x i64> %1,
     i64 %2)
 
   ret <vscale x 4 x i32> %a
declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i64(
   <vscale x 8 x i32>*,
   <vscale x 8 x i64>,
   i64);
 
 define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i64(
     <vscale x 8 x i32>* %0,
     <vscale x 8 x i64> %1,
     i64 %2)
 
   ret <vscale x 8 x i32> %a
declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i64(
   <vscale x 1 x half>*,
   <vscale x 1 x i64>,
   i64);
 
 define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i64(
     <vscale x 1 x half>* %0,
     <vscale x 1 x i64> %1,
     i64 %2)
 
   ret <vscale x 1 x half> %a
declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i64(
   <vscale x 2 x half>*,
   <vscale x 2 x i64>,
   i64);
 
 define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i64(
     <vscale x 2 x half>* %0,
     <vscale x 2 x i64> %1,
     i64 %2)
 
   ret <vscale x 2 x half> %a
declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i64(
   <vscale x 4 x half>*,
   <vscale x 4 x i64>,
   i64);
 
 define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i64(
     <vscale x 4 x half>* %0,
     <vscale x 4 x i64> %1,
     i64 %2)
 
   ret <vscale x 4 x half> %a
declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i64(
   <vscale x 8 x half>*,
   <vscale x 8 x i64>,
   i64);
 
 define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i64(
     <vscale x 8 x half>* %0,
     <vscale x 8 x i64> %1,
     i64 %2)
 
   ret <vscale x 8 x half> %a
declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i64(
   <vscale x 1 x float>*,
   <vscale x 1 x i64>,
   i64);
 
 define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i64(
     <vscale x 1 x float>* %0,
     <vscale x 1 x i64> %1,
     i64 %2)
 
   ret <vscale x 1 x float> %a
declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i64(
   <vscale x 2 x float>*,
   <vscale x 2 x i64>,
   i64);
 
 define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i64(
     <vscale x 2 x float>* %0,
     <vscale x 2 x i64> %1,
     i64 %2)
 
   ret <vscale x 2 x float> %a
declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i64(
   <vscale x 4 x float>*,
   <vscale x 4 x i64>,
   i64);
 
 define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i64(
     <vscale x 4 x float>* %0,
     <vscale x 4 x i64> %1,
     i64 %2)
 
   ret <vscale x 4 x float> %a
declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i64(
   <vscale x 8 x float>*,
   <vscale x 8 x i64>,
   i64);
 
 define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v8
+; CHECK-NEXT:    vloxei64.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i64(
     <vscale x 8 x float>* %0,
     <vscale x 8 x i64> %1,
     i64 %2)
 
   ret <vscale x 8 x float> %a
declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32(
   <vscale x 1 x i8>*,
   <vscale x 1 x i32>,
   i64);
 
 define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32(
     <vscale x 1 x i8>* %0,
     <vscale x 1 x i32> %1,
     i64 %2)
 
   ret <vscale x 1 x i8> %a
declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32(
   <vscale x 2 x i8>*,
   <vscale x 2 x i32>,
   i64);
 
 define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32(
     <vscale x 2 x i8>* %0,
     <vscale x 2 x i32> %1,
     i64 %2)
 
   ret <vscale x 2 x i8> %a
declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32(
   <vscale x 4 x i8>*,
   <vscale x 4 x i32>,
   i64);
 
 define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32(
     <vscale x 4 x i8>* %0,
     <vscale x 4 x i32> %1,
     i64 %2)
 
   ret <vscale x 4 x i8> %a
declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32(
   <vscale x 8 x i8>*,
   <vscale x 8 x i32>,
   i64);
 
 define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32(
     <vscale x 8 x i8>* %0,
     <vscale x 8 x i32> %1,
     i64 %2)
 
   ret <vscale x 8 x i8> %a
declare <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32(
   <vscale x 16 x i8>*,
   <vscale x 16 x i32>,
   i64);
 
 define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32(
     <vscale x 16 x i8>* %0,
     <vscale x 16 x i32> %1,
     i64 %2)
 
   ret <vscale x 16 x i8> %a
declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32(
   <vscale x 1 x i16>*,
   <vscale x 1 x i32>,
   i64);
 
 define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32(
     <vscale x 1 x i16>* %0,
     <vscale x 1 x i32> %1,
     i64 %2)
 
   ret <vscale x 1 x i16> %a
declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32(
   <vscale x 2 x i16>*,
   <vscale x 2 x i32>,
   i64);
 
 define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32(
     <vscale x 2 x i16>* %0,
     <vscale x 2 x i32> %1,
     i64 %2)
 
   ret <vscale x 2 x i16> %a
declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32(
   <vscale x 4 x i16>*,
   <vscale x 4 x i32>,
   i64);
 
 define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32(
     <vscale x 4 x i16>* %0,
     <vscale x 4 x i32> %1,
     i64 %2)
 
   ret <vscale x 4 x i16> %a
declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32(
   <vscale x 8 x i16>*,
   <vscale x 8 x i32>,
   i64);
 
 define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32(
     <vscale x 8 x i16>* %0,
     <vscale x 8 x i32> %1,
     i64 %2)
 
   ret <vscale x 8 x i16> %a
declare <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32(
   <vscale x 16 x i16>*,
   <vscale x 16 x i32>,
   i64);
 
 define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32(
     <vscale x 16 x i16>* %0,
     <vscale x 16 x i32> %1,
     i64 %2)
 
   ret <vscale x 16 x i16> %a
declare <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32(
   <vscale x 1 x i64>*,
   <vscale x 1 x i32>,
   i64);
 
 define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32(
     <vscale x 1 x i64>* %0,
     <vscale x 1 x i32> %1,
     i64 %2)
 
   ret <vscale x 1 x i64> %a
declare <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32(
   <vscale x 2 x i64>*,
   <vscale x 2 x i32>,
   i64);
 
 define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32(
     <vscale x 2 x i64>* %0,
     <vscale x 2 x i32> %1,
     i64 %2)
 
   ret <vscale x 2 x i64> %a
declare <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32(
   <vscale x 4 x i64>*,
   <vscale x 4 x i32>,
   i64);
 
 define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32(
     <vscale x 4 x i64>* %0,
     <vscale x 4 x i32> %1,
     i64 %2)
 
   ret <vscale x 4 x i64> %a
declare <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32(
   <vscale x 8 x i64>*,
   <vscale x 8 x i32>,
   i64);
 
 define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32(
     <vscale x 8 x i64>* %0,
     <vscale x 8 x i32> %1,
     i64 %2)
 
   ret <vscale x 8 x i64> %a
declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32(
   <vscale x 1 x half>*,
   <vscale x 1 x i32>,
   i64);
 
 define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32(
     <vscale x 1 x half>* %0,
     <vscale x 1 x i32> %1,
     i64 %2)
 
   ret <vscale x 1 x half> %a
declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32(
   <vscale x 2 x half>*,
   <vscale x 2 x i32>,
   i64);
 
 define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32(
     <vscale x 2 x half>* %0,
     <vscale x 2 x i32> %1,
     i64 %2)
 
   ret <vscale x 2 x half> %a
declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32(
   <vscale x 4 x half>*,
   <vscale x 4 x i32>,
   i64);
 
 define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32(
     <vscale x 4 x half>* %0,
     <vscale x 4 x i32> %1,
     i64 %2)
 
   ret <vscale x 4 x half> %a
declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32(
   <vscale x 8 x half>*,
   <vscale x 8 x i32>,
   i64);
 
 define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32(
     <vscale x 8 x half>* %0,
     <vscale x 8 x i32> %1,
     i64 %2)
 
   ret <vscale x 8 x half> %a
declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32(
   <vscale x 16 x half>*,
   <vscale x 16 x i32>,
   i64);
 
 define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32(
     <vscale x 16 x half>* %0,
     <vscale x 16 x i32> %1,
     i64 %2)
 
   ret <vscale x 16 x half> %a
declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32(
   <vscale x 1 x double>*,
   <vscale x 1 x i32>,
   i64);
 
 define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32(
     <vscale x 1 x double>* %0,
     <vscale x 1 x i32> %1,
     i64 %2)
 
   ret <vscale x 1 x double> %a
declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32(
   <vscale x 2 x double>*,
   <vscale x 2 x i32>,
   i64);
 
 define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32(
     <vscale x 2 x double>* %0,
     <vscale x 2 x i32> %1,
     i64 %2)
 
   ret <vscale x 2 x double> %a
declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32(
   <vscale x 4 x double>*,
   <vscale x 4 x i32>,
   i64);
 
 define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32(
     <vscale x 4 x double>* %0,
     <vscale x 4 x i32> %1,
     i64 %2)
 
   ret <vscale x 4 x double> %a
declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i32(
   <vscale x 8 x double>*,
   <vscale x 8 x i32>,
   i64);
 
 define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxei32.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i32(
     <vscale x 8 x double>* %0,
     <vscale x 8 x i32> %1,
     i64 %2)
 
   ret <vscale x 8 x double> %a
declare <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16(
   <vscale x 1 x i8>*,
   <vscale x 1 x i16>,
   i64);
 
 define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16(
     <vscale x 1 x i8>* %0,
     <vscale x 1 x i16> %1,
     i64 %2)
 
   ret <vscale x 1 x i8> %a
declare <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16(
   <vscale x 2 x i8>*,
   <vscale x 2 x i16>,
   i64);
 
 define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16(
     <vscale x 2 x i8>* %0,
     <vscale x 2 x i16> %1,
     i64 %2)
 
   ret <vscale x 2 x i8> %a
declare <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16(
   <vscale x 4 x i8>*,
   <vscale x 4 x i16>,
   i64);
 
 define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16(
     <vscale x 4 x i8>* %0,
     <vscale x 4 x i16> %1,
     i64 %2)
 
   ret <vscale x 4 x i8> %a
declare <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16(
   <vscale x 8 x i8>*,
   <vscale x 8 x i16>,
   i64);
 
 define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16(
     <vscale x 8 x i8>* %0,
     <vscale x 8 x i16> %1,
     i64 %2)
 
   ret <vscale x 8 x i8> %a
declare <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16(
   <vscale x 16 x i8>*,
   <vscale x 16 x i16>,
   i64);
 
 define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16(
     <vscale x 16 x i8>* %0,
     <vscale x 16 x i16> %1,
     i64 %2)
 
   ret <vscale x 16 x i8> %a
declare <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16(
   <vscale x 32 x i8>*,
   <vscale x 32 x i16>,
   i64);
 
 define <vscale x 32 x i8> @intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8>* %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16(
     <vscale x 32 x i8>* %0,
     <vscale x 32 x i16> %1,
     i64 %2)
 
   ret <vscale x 32 x i8> %a
declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16(
   <vscale x 1 x i32>*,
   <vscale x 1 x i16>,
   i64);
 
 define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16(
     <vscale x 1 x i32>* %0,
     <vscale x 1 x i16> %1,
     i64 %2)
 
   ret <vscale x 1 x i32> %a
declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16(
   <vscale x 2 x i32>*,
   <vscale x 2 x i16>,
   i64);
 
 define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16(
     <vscale x 2 x i32>* %0,
     <vscale x 2 x i16> %1,
     i64 %2)
 
   ret <vscale x 2 x i32> %a
declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16(
   <vscale x 4 x i32>*,
   <vscale x 4 x i16>,
   i64);
 
 define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16(
     <vscale x 4 x i32>* %0,
     <vscale x 4 x i16> %1,
     i64 %2)
 
   ret <vscale x 4 x i32> %a
declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16(
   <vscale x 8 x i32>*,
   <vscale x 8 x i16>,
   i64);
 
 define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16(
     <vscale x 8 x i32>* %0,
     <vscale x 8 x i16> %1,
     i64 %2)
 
   ret <vscale x 8 x i32> %a
declare <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16(
   <vscale x 16 x i32>*,
   <vscale x 16 x i16>,
   i64);
 
 define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16(
     <vscale x 16 x i32>* %0,
     <vscale x 16 x i16> %1,
     i64 %2)
 
   ret <vscale x 16 x i32> %a
declare <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16(
   <vscale x 1 x i64>*,
   <vscale x 1 x i16>,
   i64);
 
 define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16(
     <vscale x 1 x i64>* %0,
     <vscale x 1 x i16> %1,
     i64 %2)
 
   ret <vscale x 1 x i64> %a
declare <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16(
   <vscale x 2 x i64>*,
   <vscale x 2 x i16>,
   i64);
 
 define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16(
     <vscale x 2 x i64>* %0,
     <vscale x 2 x i16> %1,
     i64 %2)
 
   ret <vscale x 2 x i64> %a
declare <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16(
   <vscale x 4 x i64>*,
   <vscale x 4 x i16>,
   i64);
 
 define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16(
     <vscale x 4 x i64>* %0,
     <vscale x 4 x i16> %1,
     i64 %2)
 
   ret <vscale x 4 x i64> %a
declare <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16(
   <vscale x 8 x i64>*,
   <vscale x 8 x i16>,
   i64);
 
 define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16(
     <vscale x 8 x i64>* %0,
     <vscale x 8 x i16> %1,
     i64 %2)
 
   ret <vscale x 8 x i64> %a
declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16(
   <vscale x 1 x float>*,
   <vscale x 1 x i16>,
   i64);
 
 define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16(
     <vscale x 1 x float>* %0,
     <vscale x 1 x i16> %1,
     i64 %2)
 
   ret <vscale x 1 x float> %a
declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16(
   <vscale x 2 x float>*,
   <vscale x 2 x i16>,
   i64);
 
 define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16(
     <vscale x 2 x float>* %0,
     <vscale x 2 x i16> %1,
     i64 %2)
 
   ret <vscale x 2 x float> %a
declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16(
   <vscale x 4 x float>*,
   <vscale x 4 x i16>,
   i64);
 
 define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16(
     <vscale x 4 x float>* %0,
     <vscale x 4 x i16> %1,
     i64 %2)
 
   ret <vscale x 4 x float> %a
declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16(
   <vscale x 8 x float>*,
   <vscale x 8 x i16>,
   i64);
 
 define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16(
     <vscale x 8 x float>* %0,
     <vscale x 8 x i16> %1,
     i64 %2)
 
   ret <vscale x 8 x float> %a
declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i16(
   <vscale x 16 x float>*,
   <vscale x 16 x i16>,
   i64);
 
 define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i16(
     <vscale x 16 x float>* %0,
     <vscale x 16 x i16> %1,
     i64 %2)
 
   ret <vscale x 16 x float> %a
declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16(
   <vscale x 1 x double>*,
   <vscale x 1 x i16>,
   i64);
 
 define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16(
     <vscale x 1 x double>* %0,
     <vscale x 1 x i16> %1,
     i64 %2)
 
   ret <vscale x 1 x double> %a
declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16(
   <vscale x 2 x double>*,
   <vscale x 2 x i16>,
   i64);
 
 define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16(
     <vscale x 2 x double>* %0,
     <vscale x 2 x i16> %1,
     i64 %2)
 
   ret <vscale x 2 x double> %a
declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16(
   <vscale x 4 x double>*,
   <vscale x 4 x i16>,
   i64);
 
 define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16(
     <vscale x 4 x double>* %0,
     <vscale x 4 x i16> %1,
     i64 %2)
 
   ret <vscale x 4 x double> %a
declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i16(
   <vscale x 8 x double>*,
   <vscale x 8 x i16>,
   i64);
 
 define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
-; CHECK-NEXT:    vloxei16.v v8, (a0), v8
+; CHECK-NEXT:    vloxei16.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i16(
     <vscale x 8 x double>* %0,
     <vscale x 8 x i16> %1,
     i64 %2)
 
   ret <vscale x 8 x double> %a
declare <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8(
   <vscale x 1 x i16>*,
   <vscale x 1 x i8>,
   i64);
 
 define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8(
     <vscale x 1 x i16>* %0,
     <vscale x 1 x i8> %1,
     i64 %2)
 
   ret <vscale x 1 x i16> %a
declare <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8(
   <vscale x 2 x i16>*,
   <vscale x 2 x i8>,
   i64);
 
 define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8(
     <vscale x 2 x i16>* %0,
     <vscale x 2 x i8> %1,
     i64 %2)
 
   ret <vscale x 2 x i16> %a
declare <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8(
   <vscale x 4 x i16>*,
   <vscale x 4 x i8>,
   i64);
 
 define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8(
     <vscale x 4 x i16>* %0,
     <vscale x 4 x i8> %1,
     i64 %2)
 
   ret <vscale x 4 x i16> %a
declare <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8(
   <vscale x 8 x i16>*,
   <vscale x 8 x i8>,
   i64);
 
 define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8(
     <vscale x 8 x i16>* %0,
     <vscale x 8 x i8> %1,
     i64 %2)
 
   ret <vscale x 8 x i16> %a
declare <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8(
   <vscale x 16 x i16>*,
   <vscale x 16 x i8>,
   i64);
 
 define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8(
     <vscale x 16 x i16>* %0,
     <vscale x 16 x i8> %1,
     i64 %2)
 
   ret <vscale x 16 x i16> %a
declare <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8(
   <vscale x 32 x i16>*,
   <vscale x 32 x i8>,
   i64);
 
 define <vscale x 32 x i16> @intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16>* %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m8,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8(
     <vscale x 32 x i16>* %0,
     <vscale x 32 x i8> %1,
     i64 %2)
 
   ret <vscale x 32 x i16> %a
declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8(
   <vscale x 1 x i32>*,
   <vscale x 1 x i8>,
   i64);
 
 define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8(
     <vscale x 1 x i32>* %0,
     <vscale x 1 x i8> %1,
     i64 %2)
 
   ret <vscale x 1 x i32> %a
declare <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8(
   <vscale x 2 x i32>*,
   <vscale x 2 x i8>,
   i64);
 
 define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8(
     <vscale x 2 x i32>* %0,
     <vscale x 2 x i8> %1,
     i64 %2)
 
   ret <vscale x 2 x i32> %a
declare <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8(
   <vscale x 4 x i32>*,
   <vscale x 4 x i8>,
   i64);
 
 define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8(
     <vscale x 4 x i32>* %0,
     <vscale x 4 x i8> %1,
     i64 %2)
 
   ret <vscale x 4 x i32> %a
declare <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8(
   <vscale x 8 x i32>*,
   <vscale x 8 x i8>,
   i64);
 
 define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8(
     <vscale x 8 x i32>* %0,
     <vscale x 8 x i8> %1,
     i64 %2)
 
   ret <vscale x 8 x i32> %a
declare <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8(
   <vscale x 16 x i32>*,
   <vscale x 16 x i8>,
   i64);
 
 define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8(
     <vscale x 16 x i32>* %0,
     <vscale x 16 x i8> %1,
     i64 %2)
 
   ret <vscale x 16 x i32> %a
declare <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8(
   <vscale x 1 x i64>*,
   <vscale x 1 x i8>,
   i64);
 
 define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8(
     <vscale x 1 x i64>* %0,
     <vscale x 1 x i8> %1,
     i64 %2)
 
   ret <vscale x 1 x i64> %a
declare <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8(
   <vscale x 2 x i64>*,
   <vscale x 2 x i8>,
   i64);
 
 define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8(
     <vscale x 2 x i64>* %0,
     <vscale x 2 x i8> %1,
     i64 %2)
 
   ret <vscale x 2 x i64> %a
declare <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8(
   <vscale x 4 x i64>*,
   <vscale x 4 x i8>,
   i64);
 
 define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8(
     <vscale x 4 x i64>* %0,
     <vscale x 4 x i8> %1,
     i64 %2)
 
   ret <vscale x 4 x i64> %a
declare <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8(
   <vscale x 8 x i64>*,
   <vscale x 8 x i8>,
   i64);
 
 define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8(
     <vscale x 8 x i64>* %0,
     <vscale x 8 x i8> %1,
     i64 %2)
 
   ret <vscale x 8 x i64> %a
declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8(
   <vscale x 1 x half>*,
   <vscale x 1 x i8>,
   i64);
 
 define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8(
     <vscale x 1 x half>* %0,
     <vscale x 1 x i8> %1,
     i64 %2)
 
   ret <vscale x 1 x half> %a
declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8(
   <vscale x 2 x half>*,
   <vscale x 2 x i8>,
   i64);
 
 define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8(
     <vscale x 2 x half>* %0,
     <vscale x 2 x i8> %1,
     i64 %2)
 
   ret <vscale x 2 x half> %a
declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8(
   <vscale x 4 x half>*,
   <vscale x 4 x i8>,
   i64);
 
 define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8(
     <vscale x 4 x half>* %0,
     <vscale x 4 x i8> %1,
     i64 %2)
 
   ret <vscale x 4 x half> %a
declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8(
   <vscale x 8 x half>*,
   <vscale x 8 x i8>,
   i64);
 
 define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8(
     <vscale x 8 x half>* %0,
     <vscale x 8 x i8> %1,
     i64 %2)
 
   ret <vscale x 8 x half> %a
declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8(
   <vscale x 16 x half>*,
   <vscale x 16 x i8>,
   i64);
 
 define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8(
     <vscale x 16 x half>* %0,
     <vscale x 16 x i8> %1,
     i64 %2)
 
   ret <vscale x 16 x half> %a
declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i8(
   <vscale x 32 x half>*,
   <vscale x 32 x i8>,
   i64);
 
 define <vscale x 32 x half> @intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half>* %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m8,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i8(
     <vscale x 32 x half>* %0,
     <vscale x 32 x i8> %1,
     i64 %2)
 
   ret <vscale x 32 x half> %a
declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8(
   <vscale x 1 x float>*,
   <vscale x 1 x i8>,
   i64);
 
 define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8(
     <vscale x 1 x float>* %0,
     <vscale x 1 x i8> %1,
     i64 %2)
 
   ret <vscale x 1 x float> %a
declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8(
   <vscale x 2 x float>*,
   <vscale x 2 x i8>,
   i64);
 
 define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8(
     <vscale x 2 x float>* %0,
     <vscale x 2 x i8> %1,
     i64 %2)
 
   ret <vscale x 2 x float> %a
declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8(
   <vscale x 4 x float>*,
   <vscale x 4 x i8>,
   i64);
 
 define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8(
     <vscale x 4 x float>* %0,
     <vscale x 4 x i8> %1,
     i64 %2)
 
   ret <vscale x 4 x float> %a
declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8(
   <vscale x 8 x float>*,
   <vscale x 8 x i8>,
   i64);
 
 define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8(
     <vscale x 8 x float>* %0,
     <vscale x 8 x i8> %1,
     i64 %2)
 
   ret <vscale x 8 x float> %a
declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i8(
   <vscale x 16 x float>*,
   <vscale x 16 x i8>,
   i64);
 
 define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i8(
     <vscale x 16 x float>* %0,
     <vscale x 16 x i8> %1,
     i64 %2)
 
   ret <vscale x 16 x float> %a
declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8(
   <vscale x 1 x double>*,
   <vscale x 1 x i8>,
   i64);
 
 define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8(
     <vscale x 1 x double>* %0,
     <vscale x 1 x i8> %1,
     i64 %2)
 
   ret <vscale x 1 x double> %a
declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8(
   <vscale x 2 x double>*,
   <vscale x 2 x i8>,
   i64);
 
 define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8(
     <vscale x 2 x double>* %0,
     <vscale x 2 x i8> %1,
     i64 %2)
 
   ret <vscale x 2 x double> %a
declare <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8(
   <vscale x 4 x double>*,
   <vscale x 4 x i8>,
   i64);
 
 define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8(
     <vscale x 4 x double>* %0,
     <vscale x 4 x i8> %1,
     i64 %2)
 
   ret <vscale x 4 x double> %a
declare <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i8(
   <vscale x 8 x double>*,
   <vscale x 8 x i8>,
   i64);
 
 define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
-; CHECK-NEXT:    vloxei8.v v8, (a0), v8
+; CHECK-NEXT:    vloxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i8(
     <vscale x 8 x double>* %0,
     <vscale x 8 x i8> %1,
     i64 %2)
 
   ret <vscale x 8 x double> %a

llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh,+f,+d -verify-machineinstrs \
 ; RUN:   --riscv-no-aliases < %s | FileCheck %s
 declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32(
   <vscale x 1 x i8>*,
   <vscale x 1 x i32>,
   i32);
 
 define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32(
     <vscale x 1 x i8>* %0,
     <vscale x 1 x i32> %1,
     i32 %2)
 
   ret <vscale x 1 x i8> %a
declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32(
   <vscale x 2 x i8>*,
   <vscale x 2 x i32>,
   i32);
 
 define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32(
     <vscale x 2 x i8>* %0,
     <vscale x 2 x i32> %1,
     i32 %2)
 
   ret <vscale x 2 x i8> %a
declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32(
   <vscale x 4 x i8>*,
   <vscale x 4 x i32>,
   i32);
 
 define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32(
     <vscale x 4 x i8>* %0,
     <vscale x 4 x i32> %1,
     i32 %2)
 
   ret <vscale x 4 x i8> %a
declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32(
   <vscale x 8 x i8>*,
   <vscale x 8 x i32>,
   i32);
 
 define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32(
     <vscale x 8 x i8>* %0,
     <vscale x 8 x i32> %1,
     i32 %2)
 
   ret <vscale x 8 x i8> %a
declare <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32(
   <vscale x 16 x i8>*,
   <vscale x 16 x i32>,
   i32);
 
 define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32(
     <vscale x 16 x i8>* %0,
     <vscale x 16 x i32> %1,
     i32 %2)
 
   ret <vscale x 16 x i8> %a
declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32(
   <vscale x 1 x i16>*,
   <vscale x 1 x i32>,
   i32);
 
 define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32(
     <vscale x 1 x i16>* %0,
     <vscale x 1 x i32> %1,
     i32 %2)
 
   ret <vscale x 1 x i16> %a
declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32(
   <vscale x 2 x i16>*,
   <vscale x 2 x i32>,
   i32);
 
 define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32(
     <vscale x 2 x i16>* %0,
     <vscale x 2 x i32> %1,
     i32 %2)
 
   ret <vscale x 2 x i16> %a
declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32(
   <vscale x 4 x i16>*,
   <vscale x 4 x i32>,
   i32);
 
 define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32(
     <vscale x 4 x i16>* %0,
     <vscale x 4 x i32> %1,
     i32 %2)
 
   ret <vscale x 4 x i16> %a
declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32(
   <vscale x 8 x i16>*,
   <vscale x 8 x i32>,
   i32);
 
 define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32(
     <vscale x 8 x i16>* %0,
     <vscale x 8 x i32> %1,
     i32 %2)
 
   ret <vscale x 8 x i16> %a
declare <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32(
   <vscale x 16 x i16>*,
   <vscale x 16 x i32>,
   i32);
 
 define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32(
     <vscale x 16 x i16>* %0,
     <vscale x 16 x i32> %1,
     i32 %2)
 
   ret <vscale x 16 x i16> %a
declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32(
   <vscale x 1 x half>*,
   <vscale x 1 x i32>,
   i32);
 
 define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32(
     <vscale x 1 x half>* %0,
     <vscale x 1 x i32> %1,
     i32 %2)
 
   ret <vscale x 1 x half> %a
declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32(
   <vscale x 2 x half>*,
   <vscale x 2 x i32>,
   i32);
 
 define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32(
     <vscale x 2 x half>* %0,
     <vscale x 2 x i32> %1,
     i32 %2)
 
   ret <vscale x 2 x half> %a
declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32(
   <vscale x 4 x half>*,
   <vscale x 4 x i32>,
   i32);
 
 define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32(
     <vscale x 4 x half>* %0,
     <vscale x 4 x i32> %1,
     i32 %2)
 
   ret <vscale x 4 x half> %a
declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32(
   <vscale x 8 x half>*,
   <vscale x 8 x i32>,
   i32);
 
 define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32(
     <vscale x 8 x half>* %0,
     <vscale x 8 x i32> %1,
     i32 %2)
 
   ret <vscale x 8 x half> %a
declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32(
   <vscale x 16 x half>*,
   <vscale x 16 x i32>,
   i32);
 
 define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32(
     <vscale x 16 x half>* %0,
     <vscale x 16 x i32> %1,
     i32 %2)
 
   ret <vscale x 16 x half> %a
declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32(
   <vscale x 1 x double>*,
   <vscale x 1 x i32>,
   i32);
 
 define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32(
     <vscale x 1 x double>* %0,
     <vscale x 1 x i32> %1,
     i32 %2)
 
   ret <vscale x 1 x double> %a
declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32(
   <vscale x 2 x double>*,
   <vscale x 2 x i32>,
   i32);
 
 define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32(
     <vscale x 2 x double>* %0,
     <vscale x 2 x i32> %1,
     i32 %2)
 
   ret <vscale x 2 x double> %a
declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32(
   <vscale x 4 x double>*,
   <vscale x 4 x i32>,
   i32);
 
 define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32(
     <vscale x 4 x double>* %0,
     <vscale x 4 x i32> %1,
     i32 %2)
 
   ret <vscale x 4 x double> %a
declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32(
   <vscale x 8 x double>*,
   <vscale x 8 x i32>,
   i32);
 
 define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32(
     <vscale x 8 x double>* %0,
     <vscale x 8 x i32> %1,
     i32 %2)
 
   ret <vscale x 8 x double> %a
declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16(
   <vscale x 1 x i8>*,
   <vscale x 1 x i16>,
   i32);
 
 define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16(
     <vscale x 1 x i8>* %0,
     <vscale x 1 x i16> %1,
     i32 %2)
 
   ret <vscale x 1 x i8> %a
declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16(
   <vscale x 2 x i8>*,
   <vscale x 2 x i16>,
   i32);
 
 define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16(
     <vscale x 2 x i8>* %0,
     <vscale x 2 x i16> %1,
     i32 %2)
 
   ret <vscale x 2 x i8> %a
declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16(
   <vscale x 4 x i8>*,
   <vscale x 4 x i16>,
   i32);
 
 define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16(
     <vscale x 4 x i8>* %0,
     <vscale x 4 x i16> %1,
     i32 %2)
 
   ret <vscale x 4 x i8> %a
declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16(
   <vscale x 8 x i8>*,
   <vscale x 8 x i16>,
   i32);
 
 define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16(
     <vscale x 8 x i8>* %0,
     <vscale x 8 x i16> %1,
     i32 %2)
 
   ret <vscale x 8 x i8> %a
declare <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16(
   <vscale x 16 x i8>*,
   <vscale x 16 x i16>,
   i32);
 
 define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16(
     <vscale x 16 x i8>* %0,
     <vscale x 16 x i16> %1,
     i32 %2)
 
   ret <vscale x 16 x i8> %a
declare <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16(
   <vscale x 32 x i8>*,
   <vscale x 32 x i16>,
   i32);
 
 define <vscale x 32 x i8> @intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8>* %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16(
     <vscale x 32 x i8>* %0,
     <vscale x 32 x i16> %1,
     i32 %2)
 
   ret <vscale x 32 x i8> %a
declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16(
   <vscale x 1 x i32>*,
   <vscale x 1 x i16>,
   i32);
 
 define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16(
     <vscale x 1 x i32>* %0,
     <vscale x 1 x i16> %1,
     i32 %2)
 
   ret <vscale x 1 x i32> %a
declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16(
   <vscale x 2 x i32>*,
   <vscale x 2 x i16>,
   i32);
 
 define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16(
     <vscale x 2 x i32>* %0,
     <vscale x 2 x i16> %1,
     i32 %2)
 
   ret <vscale x 2 x i32> %a
declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16(
   <vscale x 4 x i32>*,
   <vscale x 4 x i16>,
   i32);
 
 define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16(
     <vscale x 4 x i32>* %0,
     <vscale x 4 x i16> %1,
     i32 %2)
 
   ret <vscale x 4 x i32> %a
declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16(
   <vscale x 8 x i32>*,
   <vscale x 8 x i16>,
   i32);
 
 define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16(
     <vscale x 8 x i32>* %0,
     <vscale x 8 x i16> %1,
     i32 %2)
 
   ret <vscale x 8 x i32> %a
declare <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16(
   <vscale x 16 x i32>*,
   <vscale x 16 x i16>,
   i32);
 
 define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16(
     <vscale x 16 x i32>* %0,
     <vscale x 16 x i16> %1,
     i32 %2)
 
   ret <vscale x 16 x i32> %a
declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16(
   <vscale x 1 x float>*,
   <vscale x 1 x i16>,
   i32);
 
 define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16(
     <vscale x 1 x float>* %0,
     <vscale x 1 x i16> %1,
     i32 %2)
 
   ret <vscale x 1 x float> %a
declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16(
   <vscale x 2 x float>*,
   <vscale x 2 x i16>,
   i32);
 
 define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16(
     <vscale x 2 x float>* %0,
     <vscale x 2 x i16> %1,
     i32 %2)
 
   ret <vscale x 2 x float> %a
declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16(
   <vscale x 4 x float>*,
   <vscale x 4 x i16>,
   i32);
 
 define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16(
     <vscale x 4 x float>* %0,
     <vscale x 4 x i16> %1,
     i32 %2)
 
   ret <vscale x 4 x float> %a
declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16(
   <vscale x 8 x float>*,
   <vscale x 8 x i16>,
   i32);
 
 define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16(
     <vscale x 8 x float>* %0,
     <vscale x 8 x i16> %1,
     i32 %2)
 
   ret <vscale x 8 x float> %a
declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16(
   <vscale x 16 x float>*,
   <vscale x 16 x i16>,
   i32);
 
 define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16(
     <vscale x 16 x float>* %0,
     <vscale x 16 x i16> %1,
     i32 %2)
 
   ret <vscale x 16 x float> %a
declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16(
   <vscale x 1 x double>*,
   <vscale x 1 x i16>,
   i32);
 
 define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16(
     <vscale x 1 x double>* %0,
     <vscale x 1 x i16> %1,
     i32 %2)
 
   ret <vscale x 1 x double> %a
declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16(
   <vscale x 2 x double>*,
   <vscale x 2 x i16>,
   i32);
 
 define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16(
     <vscale x 2 x double>* %0,
     <vscale x 2 x i16> %1,
     i32 %2)
 
   ret <vscale x 2 x double> %a
declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16(
   <vscale x 4 x double>*,
   <vscale x 4 x i16>,
   i32);
 
 define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16(
     <vscale x 4 x double>* %0,
     <vscale x 4 x i16> %1,
     i32 %2)
 
   ret <vscale x 4 x double> %a
declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16(
   <vscale x 8 x double>*,
   <vscale x 8 x i16>,
   i32);
 
 define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16(
     <vscale x 8 x double>* %0,
     <vscale x 8 x i16> %1,
     i32 %2)
 
   ret <vscale x 8 x double> %a
declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8(
   <vscale x 1 x i16>*,
   <vscale x 1 x i8>,
   i32);
 
 define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8(
     <vscale x 1 x i16>* %0,
     <vscale x 1 x i8> %1,
     i32 %2)
 
   ret <vscale x 1 x i16> %a
declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8(
   <vscale x 2 x i16>*,
   <vscale x 2 x i8>,
   i32);
 
 define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8(
     <vscale x 2 x i16>* %0,
     <vscale x 2 x i8> %1,
     i32 %2)
 
   ret <vscale x 2 x i16> %a
declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8(
   <vscale x 4 x i16>*,
   <vscale x 4 x i8>,
   i32);
 
 define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8(
     <vscale x 4 x i16>* %0,
     <vscale x 4 x i8> %1,
     i32 %2)
 
   ret <vscale x 4 x i16> %a
declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8(
   <vscale x 8 x i16>*,
   <vscale x 8 x i8>,
   i32);
 
 define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8(
     <vscale x 8 x i16>* %0,
     <vscale x 8 x i8> %1,
     i32 %2)
 
   ret <vscale x 8 x i16> %a
declare <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8(
   <vscale x 16 x i16>*,
   <vscale x 16 x i8>,
   i32);
 
 define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8(
     <vscale x 16 x i16>* %0,
     <vscale x 16 x i8> %1,
     i32 %2)
 
   ret <vscale x 16 x i16> %a
declare <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8(
   <vscale x 32 x i16>*,
   <vscale x 32 x i8>,
   i32);
 
 define <vscale x 32 x i16> @intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m8,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8(
     <vscale x 32 x i16>* %0,
     <vscale x 32 x i8> %1,
     i32 %2)
 
   ret <vscale x 32 x i16> %a
declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8(
   <vscale x 1 x i32>*,
   <vscale x 1 x i8>,
   i32);
 
 define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8(
     <vscale x 1 x i32>* %0,
     <vscale x 1 x i8> %1,
     i32 %2)
 
   ret <vscale x 1 x i32> %a
declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8(
   <vscale x 2 x i32>*,
   <vscale x 2 x i8>,
   i32);
 
 define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8(
     <vscale x 2 x i32>* %0,
     <vscale x 2 x i8> %1,
     i32 %2)
 
   ret <vscale x 2 x i32> %a
declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8(
   <vscale x 4 x i32>*,
   <vscale x 4 x i8>,
   i32);
 
 define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8(
     <vscale x 4 x i32>* %0,
     <vscale x 4 x i8> %1,
     i32 %2)
 
   ret <vscale x 4 x i32> %a
declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8(
   <vscale x 8 x i32>*,
   <vscale x 8 x i8>,
   i32);
 
 define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8(
     <vscale x 8 x i32>* %0,
     <vscale x 8 x i8> %1,
     i32 %2)
 
   ret <vscale x 8 x i32> %a
declare <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8(
   <vscale x 16 x i32>*,
   <vscale x 16 x i8>,
   i32);
 
 define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8(
     <vscale x 16 x i32>* %0,
     <vscale x 16 x i8> %1,
     i32 %2)
 
   ret <vscale x 16 x i32> %a
declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8(
   <vscale x 1 x half>*,
   <vscale x 1 x i8>,
   i32);
 
 define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8(
     <vscale x 1 x half>* %0,
     <vscale x 1 x i8> %1,
     i32 %2)
 
   ret <vscale x 1 x half> %a
declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8(
   <vscale x 2 x half>*,
   <vscale x 2 x i8>,
   i32);
 
 define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8(
     <vscale x 2 x half>* %0,
     <vscale x 2 x i8> %1,
     i32 %2)
 
   ret <vscale x 2 x half> %a
declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8(
   <vscale x 4 x half>*,
   <vscale x 4 x i8>,
   i32);
 
 define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8(
     <vscale x 4 x half>* %0,
     <vscale x 4 x i8> %1,
     i32 %2)
 
   ret <vscale x 4 x half> %a
declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8(
   <vscale x 8 x half>*,
   <vscale x 8 x i8>,
   i32);
 
 define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8(
     <vscale x 8 x half>* %0,
     <vscale x 8 x i8> %1,
     i32 %2)
 
   ret <vscale x 8 x half> %a
declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8(
   <vscale x 16 x half>*,
   <vscale x 16 x i8>,
   i32);
 
 define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8(
     <vscale x 16 x half>* %0,
     <vscale x 16 x i8> %1,
     i32 %2)
 
   ret <vscale x 16 x half> %a
declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i8(
   <vscale x 32 x half>*,
   <vscale x 32 x i8>,
   i32);
 
 define <vscale x 32 x half> @intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m8,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i8(
     <vscale x 32 x half>* %0,
     <vscale x 32 x i8> %1,
     i32 %2)
 
   ret <vscale x 32 x half> %a
declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8(
   <vscale x 1 x float>*,
   <vscale x 1 x i8>,
   i32);
 
 define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8(
     <vscale x 1 x float>* %0,
     <vscale x 1 x i8> %1,
     i32 %2)
 
   ret <vscale x 1 x float> %a
declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8(
   <vscale x 2 x float>*,
   <vscale x 2 x i8>,
   i32);
 
 define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8(
     <vscale x 2 x float>* %0,
     <vscale x 2 x i8> %1,
     i32 %2)
 
   ret <vscale x 2 x float> %a
declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8(
   <vscale x 4 x float>*,
   <vscale x 4 x i8>,
   i32);
 
 define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8(
     <vscale x 4 x float>* %0,
     <vscale x 4 x i8> %1,
     i32 %2)
 
   ret <vscale x 4 x float> %a
declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8(
   <vscale x 8 x float>*,
   <vscale x 8 x i8>,
   i32);
 
 define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8(
     <vscale x 8 x float>* %0,
     <vscale x 8 x i8> %1,
     i32 %2)
 
   ret <vscale x 8 x float> %a
declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8(
   <vscale x 16 x float>*,
   <vscale x 16 x i8>,
   i32);
 
 define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8(
     <vscale x 16 x float>* %0,
     <vscale x 16 x i8> %1,
     i32 %2)
 
   ret <vscale x 16 x float> %a
declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8(
   <vscale x 1 x double>*,
   <vscale x 1 x i8>,
   i32);
 
 define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8(
     <vscale x 1 x double>* %0,
     <vscale x 1 x i8> %1,
     i32 %2)
 
   ret <vscale x 1 x double> %a
declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8(
   <vscale x 2 x double>*,
   <vscale x 2 x i8>,
   i32);
 
 define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8(
     <vscale x 2 x double>* %0,
     <vscale x 2 x i8> %1,
     i32 %2)
 
   ret <vscale x 2 x double> %a
declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8(
   <vscale x 4 x double>*,
   <vscale x 4 x i8>,
   i32);
 
 define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8(
     <vscale x 4 x double>* %0,
     <vscale x 4 x i8> %1,
     i32 %2)
 
   ret <vscale x 4 x double> %a
declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8(
   <vscale x 8 x double>*,
   <vscale x 8 x i8>,
   i32);
 
 define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8(
     <vscale x 8 x double>* %0,
     <vscale x 8 x i8> %1,
     i32 %2)
 
   ret <vscale x 8 x double> %a

llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh,+f,+d -verify-machineinstrs \
 ; RUN:   --riscv-no-aliases < %s | FileCheck %s
 declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64(
   <vscale x 1 x i8>*,
   <vscale x 1 x i64>,
   i64);
 
 define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64(
     <vscale x 1 x i8>* %0,
     <vscale x 1 x i64> %1,
     i64 %2)
 
   ret <vscale x 1 x i8> %a
declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64(
   <vscale x 2 x i8>*,
   <vscale x 2 x i64>,
   i64);
 
 define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64(
     <vscale x 2 x i8>* %0,
     <vscale x 2 x i64> %1,
     i64 %2)
 
   ret <vscale x 2 x i8> %a
declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64(
   <vscale x 4 x i8>*,
   <vscale x 4 x i64>,
   i64);
 
 define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64(
     <vscale x 4 x i8>* %0,
     <vscale x 4 x i64> %1,
     i64 %2)
 
   ret <vscale x 4 x i8> %a
declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64(
   <vscale x 8 x i8>*,
   <vscale x 8 x i64>,
   i64);
 
 define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64(
     <vscale x 8 x i8>* %0,
     <vscale x 8 x i64> %1,
     i64 %2)
 
   ret <vscale x 8 x i8> %a
declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64(
   <vscale x 1 x i16>*,
   <vscale x 1 x i64>,
   i64);
 
 define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64(
     <vscale x 1 x i16>* %0,
     <vscale x 1 x i64> %1,
     i64 %2)
 
   ret <vscale x 1 x i16> %a
declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64(
   <vscale x 2 x i16>*,
   <vscale x 2 x i64>,
   i64);
 
 define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64(
     <vscale x 2 x i16>* %0,
     <vscale x 2 x i64> %1,
     i64 %2)
 
   ret <vscale x 2 x i16> %a
declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64(
   <vscale x 4 x i16>*,
   <vscale x 4 x i64>,
   i64);
 
 define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64(
     <vscale x 4 x i16>* %0,
     <vscale x 4 x i64> %1,
     i64 %2)
 
   ret <vscale x 4 x i16> %a
declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64(
   <vscale x 8 x i16>*,
   <vscale x 8 x i64>,
   i64);
 
 define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64(
     <vscale x 8 x i16>* %0,
     <vscale x 8 x i64> %1,
     i64 %2)
 
   ret <vscale x 8 x i16> %a
declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64(
   <vscale x 1 x i32>*,
   <vscale x 1 x i64>,
   i64);
 
 define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64(
     <vscale x 1 x i32>* %0,
     <vscale x 1 x i64> %1,
     i64 %2)
 
   ret <vscale x 1 x i32> %a
declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64(
   <vscale x 2 x i32>*,
   <vscale x 2 x i64>,
   i64);
 
 define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64(
     <vscale x 2 x i32>* %0,
     <vscale x 2 x i64> %1,
     i64 %2)
 
   ret <vscale x 2 x i32> %a
declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64(
   <vscale x 4 x i32>*,
   <vscale x 4 x i64>,
   i64);
 
 define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64(
     <vscale x 4 x i32>* %0,
     <vscale x 4 x i64> %1,
     i64 %2)
 
   ret <vscale x 4 x i32> %a
declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64(
   <vscale x 8 x i32>*,
   <vscale x 8 x i64>,
   i64);
 
 define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64(
     <vscale x 8 x i32>* %0,
     <vscale x 8 x i64> %1,
     i64 %2)
 
   ret <vscale x 8 x i32> %a
declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i64(
   <vscale x 1 x half>*,
   <vscale x 1 x i64>,
   i64);
 
 define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i64(
     <vscale x 1 x half>* %0,
     <vscale x 1 x i64> %1,
     i64 %2)
 
   ret <vscale x 1 x half> %a
declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i64(
   <vscale x 2 x half>*,
   <vscale x 2 x i64>,
   i64);
 
 define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i64(
     <vscale x 2 x half>* %0,
     <vscale x 2 x i64> %1,
     i64 %2)
 
   ret <vscale x 2 x half> %a
declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i64(
   <vscale x 4 x half>*,
   <vscale x 4 x i64>,
   i64);
 
 define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i64(
     <vscale x 4 x half>* %0,
     <vscale x 4 x i64> %1,
     i64 %2)
 
   ret <vscale x 4 x half> %a
declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i64(
   <vscale x 8 x half>*,
   <vscale x 8 x i64>,
   i64);
 
 define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i64(
     <vscale x 8 x half>* %0,
     <vscale x 8 x i64> %1,
     i64 %2)
 
   ret <vscale x 8 x half> %a
declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i64(
   <vscale x 1 x float>*,
   <vscale x 1 x i64>,
   i64);
 
 define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float>* %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i64(
     <vscale x 1 x float>* %0,
     <vscale x 1 x i64> %1,
     i64 %2)
 
   ret <vscale x 1 x float> %a
declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i64(
   <vscale x 2 x float>*,
   <vscale x 2 x i64>,
   i64);
 
 define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float>* %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i64(
     <vscale x 2 x float>* %0,
     <vscale x 2 x i64> %1,
     i64 %2)
 
   ret <vscale x 2 x float> %a
declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i64(
   <vscale x 4 x float>*,
   <vscale x 4 x i64>,
   i64);
 
 define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float>* %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i64(
     <vscale x 4 x float>* %0,
     <vscale x 4 x i64> %1,
     i64 %2)
 
   ret <vscale x 4 x float> %a
declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i64(
   <vscale x 8 x float>*,
   <vscale x 8 x i64>,
   i64);
 
 define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float>* %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v8
+; CHECK-NEXT:    vluxei64.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i64(
     <vscale x 8 x float>* %0,
     <vscale x 8 x i64> %1,
     i64 %2)
 
   ret <vscale x 8 x float> %a
declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32(
   <vscale x 1 x i8>*,
   <vscale x 1 x i32>,
   i64);
 
 define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32(
     <vscale x 1 x i8>* %0,
     <vscale x 1 x i32> %1,
     i64 %2)
 
   ret <vscale x 1 x i8> %a
declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32(
   <vscale x 2 x i8>*,
   <vscale x 2 x i32>,
   i64);
 
 define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32(
     <vscale x 2 x i8>* %0,
     <vscale x 2 x i32> %1,
     i64 %2)
 
   ret <vscale x 2 x i8> %a
declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32(
   <vscale x 4 x i8>*,
   <vscale x 4 x i32>,
   i64);
 
 define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32(
     <vscale x 4 x i8>* %0,
     <vscale x 4 x i32> %1,
     i64 %2)
 
   ret <vscale x 4 x i8> %a
declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32(
   <vscale x 8 x i8>*,
   <vscale x 8 x i32>,
   i64);
 
 define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32(
     <vscale x 8 x i8>* %0,
     <vscale x 8 x i32> %1,
     i64 %2)
 
   ret <vscale x 8 x i8> %a
declare <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32(
   <vscale x 16 x i8>*,
   <vscale x 16 x i32>,
   i64);
 
 define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32(
     <vscale x 16 x i8>* %0,
     <vscale x 16 x i32> %1,
     i64 %2)
 
   ret <vscale x 16 x i8> %a
declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32(
   <vscale x 1 x i16>*,
   <vscale x 1 x i32>,
   i64);
 
 define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32(
     <vscale x 1 x i16>* %0,
     <vscale x 1 x i32> %1,
     i64 %2)
 
   ret <vscale x 1 x i16> %a
declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32(
   <vscale x 2 x i16>*,
   <vscale x 2 x i32>,
   i64);
 
 define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32(
     <vscale x 2 x i16>* %0,
     <vscale x 2 x i32> %1,
     i64 %2)
 
   ret <vscale x 2 x i16> %a
declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32(
   <vscale x 4 x i16>*,
   <vscale x 4 x i32>,
   i64);
 
 define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32(
     <vscale x 4 x i16>* %0,
     <vscale x 4 x i32> %1,
     i64 %2)
 
   ret <vscale x 4 x i16> %a
declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32(
   <vscale x 8 x i16>*,
   <vscale x 8 x i32>,
   i64);
 
 define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32(
     <vscale x 8 x i16>* %0,
     <vscale x 8 x i32> %1,
     i64 %2)
 
   ret <vscale x 8 x i16> %a
declare <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32(
   <vscale x 16 x i16>*,
   <vscale x 16 x i32>,
   i64);
 
 define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32(
     <vscale x 16 x i16>* %0,
     <vscale x 16 x i32> %1,
     i64 %2)
 
   ret <vscale x 16 x i16> %a
declare <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32(
   <vscale x 1 x i64>*,
   <vscale x 1 x i32>,
   i64);
 
 define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32(
     <vscale x 1 x i64>* %0,
     <vscale x 1 x i32> %1,
     i64 %2)
 
   ret <vscale x 1 x i64> %a
declare <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32(
   <vscale x 2 x i64>*,
   <vscale x 2 x i32>,
   i64);
 
 define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32(
     <vscale x 2 x i64>* %0,
     <vscale x 2 x i32> %1,
     i64 %2)
 
   ret <vscale x 2 x i64> %a
declare <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32(
   <vscale x 4 x i64>*,
   <vscale x 4 x i32>,
   i64);
 
 define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32(
     <vscale x 4 x i64>* %0,
     <vscale x 4 x i32> %1,
     i64 %2)
 
   ret <vscale x 4 x i64> %a
declare <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32(
   <vscale x 8 x i64>*,
   <vscale x 8 x i32>,
   i64);
 
 define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32(
     <vscale x 8 x i64>* %0,
     <vscale x 8 x i32> %1,
     i64 %2)
 
   ret <vscale x 8 x i64> %a
declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32(
   <vscale x 1 x half>*,
   <vscale x 1 x i32>,
   i64);
 
 define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32(
     <vscale x 1 x half>* %0,
     <vscale x 1 x i32> %1,
     i64 %2)
 
   ret <vscale x 1 x half> %a
declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32(
   <vscale x 2 x half>*,
   <vscale x 2 x i32>,
   i64);
 
 define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32(
     <vscale x 2 x half>* %0,
     <vscale x 2 x i32> %1,
     i64 %2)
 
   ret <vscale x 2 x half> %a
declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32(
   <vscale x 4 x half>*,
   <vscale x 4 x i32>,
   i64);
 
 define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32(
     <vscale x 4 x half>* %0,
     <vscale x 4 x i32> %1,
     i64 %2)
 
   ret <vscale x 4 x half> %a
declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32(
   <vscale x 8 x half>*,
   <vscale x 8 x i32>,
   i64);
 
 define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32(
     <vscale x 8 x half>* %0,
     <vscale x 8 x i32> %1,
     i64 %2)
 
   ret <vscale x 8 x half> %a
declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32(
   <vscale x 16 x half>*,
   <vscale x 16 x i32>,
   i64);
 
 define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half>* %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32(
     <vscale x 16 x half>* %0,
     <vscale x 16 x i32> %1,
     i64 %2)
 
   ret <vscale x 16 x half> %a
declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32(
   <vscale x 1 x double>*,
   <vscale x 1 x i32>,
   i64);
 
 define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double>* %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32(
     <vscale x 1 x double>* %0,
     <vscale x 1 x i32> %1,
     i64 %2)
 
   ret <vscale x 1 x double> %a
declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32(
   <vscale x 2 x double>*,
   <vscale x 2 x i32>,
   i64);
 
 define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double>* %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32(
     <vscale x 2 x double>* %0,
     <vscale x 2 x i32> %1,
     i64 %2)
 
   ret <vscale x 2 x double> %a
declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32(
   <vscale x 4 x double>*,
   <vscale x 4 x i32>,
   i64);
 
 define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double>* %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32(
     <vscale x 4 x double>* %0,
     <vscale x 4 x i32> %1,
     i64 %2)
 
   ret <vscale x 4 x double> %a
declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32(
   <vscale x 8 x double>*,
   <vscale x 8 x i32>,
   i64);
 
 define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double>* %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v8
+; CHECK-NEXT:    vluxei32.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32(
     <vscale x 8 x double>* %0,
     <vscale x 8 x i32> %1,
     i64 %2)
 
   ret <vscale x 8 x double> %a
declare <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16(
   <vscale x 1 x i8>*,
   <vscale x 1 x i16>,
   i64);
 
 define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16(
     <vscale x 1 x i8>* %0,
     <vscale x 1 x i16> %1,
     i64 %2)
 
   ret <vscale x 1 x i8> %a
declare <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16(
   <vscale x 2 x i8>*,
   <vscale x 2 x i16>,
   i64);
 
 define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16(
     <vscale x 2 x i8>* %0,
     <vscale x 2 x i16> %1,
     i64 %2)
 
   ret <vscale x 2 x i8> %a
declare <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16(
   <vscale x 4 x i8>*,
   <vscale x 4 x i16>,
   i64);
 
 define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16(
     <vscale x 4 x i8>* %0,
     <vscale x 4 x i16> %1,
     i64 %2)
 
   ret <vscale x 4 x i8> %a
declare <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16(
   <vscale x 8 x i8>*,
   <vscale x 8 x i16>,
   i64);
 
 define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16(
     <vscale x 8 x i8>* %0,
     <vscale x 8 x i16> %1,
     i64 %2)
 
   ret <vscale x 8 x i8> %a
declare <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16(
   <vscale x 16 x i8>*,
   <vscale x 16 x i16>,
   i64);
 
 define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16(
     <vscale x 16 x i8>* %0,
     <vscale x 16 x i16> %1,
     i64 %2)
 
   ret <vscale x 16 x i8> %a
declare <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16(
   <vscale x 32 x i8>*,
   <vscale x 32 x i16>,
   i64);
 
 define <vscale x 32 x i8> @intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8>* %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16(
     <vscale x 32 x i8>* %0,
     <vscale x 32 x i16> %1,
     i64 %2)
 
   ret <vscale x 32 x i8> %a
declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16(
   <vscale x 1 x i32>*,
   <vscale x 1 x i16>,
   i64);
 
 define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16(
     <vscale x 1 x i32>* %0,
     <vscale x 1 x i16> %1,
     i64 %2)
 
   ret <vscale x 1 x i32> %a
declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16(
   <vscale x 2 x i32>*,
   <vscale x 2 x i16>,
   i64);
 
 define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16(
     <vscale x 2 x i32>* %0,
     <vscale x 2 x i16> %1,
     i64 %2)
 
   ret <vscale x 2 x i32> %a
declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16(
   <vscale x 4 x i32>*,
   <vscale x 4 x i16>,
   i64);
 
 define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16(
     <vscale x 4 x i32>* %0,
     <vscale x 4 x i16> %1,
     i64 %2)
 
   ret <vscale x 4 x i32> %a
declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16(
   <vscale x 8 x i32>*,
   <vscale x 8 x i16>,
   i64);
 
 define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16(
     <vscale x 8 x i32>* %0,
     <vscale x 8 x i16> %1,
     i64 %2)
 
   ret <vscale x 8 x i32> %a
declare <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16(
   <vscale x 16 x i32>*,
   <vscale x 16 x i16>,
   i64);
 
 define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16(
     <vscale x 16 x i32>* %0,
     <vscale x 16 x i16> %1,
     i64 %2)
 
   ret <vscale x 16 x i32> %a
declare <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16(
   <vscale x 1 x i64>*,
   <vscale x 1 x i16>,
   i64);
 
 define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16(
     <vscale x 1 x i64>* %0,
     <vscale x 1 x i16> %1,
     i64 %2)
 
   ret <vscale x 1 x i64> %a
declare <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16(
   <vscale x 2 x i64>*,
   <vscale x 2 x i16>,
   i64);
 
 define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16(
     <vscale x 2 x i64>* %0,
     <vscale x 2 x i16> %1,
     i64 %2)
 
   ret <vscale x 2 x i64> %a
declare <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16(
   <vscale x 4 x i64>*,
   <vscale x 4 x i16>,
   i64);
 
 define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16(
     <vscale x 4 x i64>* %0,
     <vscale x 4 x i16> %1,
     i64 %2)
 
   ret <vscale x 4 x i64> %a
declare <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16(
   <vscale x 8 x i64>*,
   <vscale x 8 x i16>,
   i64);
 
 define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16(
     <vscale x 8 x i64>* %0,
     <vscale x 8 x i16> %1,
     i64 %2)
 
   ret <vscale x 8 x i64> %a
declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16(
   <vscale x 1 x float>*,
   <vscale x 1 x i16>,
   i64);
 
 define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16(
     <vscale x 1 x float>* %0,
     <vscale x 1 x i16> %1,
     i64 %2)
 
   ret <vscale x 1 x float> %a
declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16(
   <vscale x 2 x float>*,
   <vscale x 2 x i16>,
   i64);
 
 define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16(
     <vscale x 2 x float>* %0,
     <vscale x 2 x i16> %1,
     i64 %2)
 
   ret <vscale x 2 x float> %a
declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16(
   <vscale x 4 x float>*,
   <vscale x 4 x i16>,
   i64);
 
 define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16(
     <vscale x 4 x float>* %0,
     <vscale x 4 x i16> %1,
     i64 %2)
 
   ret <vscale x 4 x float> %a
declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16(
   <vscale x 8 x float>*,
   <vscale x 8 x i16>,
   i64);
 
 define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16(
     <vscale x 8 x float>* %0,
     <vscale x 8 x i16> %1,
     i64 %2)
 
   ret <vscale x 8 x float> %a
declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16(
   <vscale x 16 x float>*,
   <vscale x 16 x i16>,
   i64);
 
 define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float>* %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16(
     <vscale x 16 x float>* %0,
     <vscale x 16 x i16> %1,
     i64 %2)
 
   ret <vscale x 16 x float> %a
declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16(
   <vscale x 1 x double>*,
   <vscale x 1 x i16>,
   i64);
 
 define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double>* %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16(
     <vscale x 1 x double>* %0,
     <vscale x 1 x i16> %1,
     i64 %2)
 
   ret <vscale x 1 x double> %a
declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16(
   <vscale x 2 x double>*,
   <vscale x 2 x i16>,
   i64);
 
 define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double>* %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16(
     <vscale x 2 x double>* %0,
     <vscale x 2 x i16> %1,
     i64 %2)
 
   ret <vscale x 2 x double> %a
declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16(
   <vscale x 4 x double>*,
   <vscale x 4 x i16>,
   i64);
 
 define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double>* %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16(
     <vscale x 4 x double>* %0,
     <vscale x 4 x i16> %1,
     i64 %2)
 
   ret <vscale x 4 x double> %a
declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16(
   <vscale x 8 x double>*,
   <vscale x 8 x i16>,
   i64);
 
 define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double>* %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
-; CHECK-NEXT:    vluxei16.v v8, (a0), v8
+; CHECK-NEXT:    vluxei16.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16(
     <vscale x 8 x double>* %0,
     <vscale x 8 x i16> %1,
     i64 %2)
 
   ret <vscale x 8 x double> %a
declare <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8(
   <vscale x 1 x i16>*,
   <vscale x 1 x i8>,
   i64);
 
 define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8(
     <vscale x 1 x i16>* %0,
     <vscale x 1 x i8> %1,
     i64 %2)
 
   ret <vscale x 1 x i16> %a
declare <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8(
   <vscale x 2 x i16>*,
   <vscale x 2 x i8>,
   i64);
 
 define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8(
     <vscale x 2 x i16>* %0,
     <vscale x 2 x i8> %1,
     i64 %2)
 
   ret <vscale x 2 x i16> %a
declare <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8(
   <vscale x 4 x i16>*,
   <vscale x 4 x i8>,
   i64);
 
 define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8(
     <vscale x 4 x i16>* %0,
     <vscale x 4 x i8> %1,
     i64 %2)
 
   ret <vscale x 4 x i16> %a
declare <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8(
   <vscale x 8 x i16>*,
   <vscale x 8 x i8>,
   i64);
 
 define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8(
     <vscale x 8 x i16>* %0,
     <vscale x 8 x i8> %1,
     i64 %2)
 
   ret <vscale x 8 x i16> %a
declare <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8(
   <vscale x 16 x i16>*,
   <vscale x 16 x i8>,
   i64);
 
 define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8(
     <vscale x 16 x i16>* %0,
     <vscale x 16 x i8> %1,
     i64 %2)
 
   ret <vscale x 16 x i16> %a
declare <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8(
   <vscale x 32 x i16>*,
   <vscale x 32 x i8>,
   i64);
 
 define <vscale x 32 x i16> @intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16>* %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m8,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8(
     <vscale x 32 x i16>* %0,
     <vscale x 32 x i8> %1,
     i64 %2)
 
   ret <vscale x 32 x i16> %a
declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8(
   <vscale x 1 x i32>*,
   <vscale x 1 x i8>,
   i64);
 
 define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8(
     <vscale x 1 x i32>* %0,
     <vscale x 1 x i8> %1,
     i64 %2)
 
   ret <vscale x 1 x i32> %a
declare <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8(
   <vscale x 2 x i32>*,
   <vscale x 2 x i8>,
   i64);
 
 define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8(
     <vscale x 2 x i32>* %0,
     <vscale x 2 x i8> %1,
     i64 %2)
 
   ret <vscale x 2 x i32> %a
declare <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8(
   <vscale x 4 x i32>*,
   <vscale x 4 x i8>,
   i64);
 
 define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8(
     <vscale x 4 x i32>* %0,
     <vscale x 4 x i8> %1,
     i64 %2)
 
   ret <vscale x 4 x i32> %a
declare <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8(
   <vscale x 8 x i32>*,
   <vscale x 8 x i8>,
   i64);
 
 define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8(
     <vscale x 8 x i32>* %0,
     <vscale x 8 x i8> %1,
     i64 %2)
 
   ret <vscale x 8 x i32> %a
declare <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8(
   <vscale x 16 x i32>*,
   <vscale x 16 x i8>,
   i64);
 
 define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8(
     <vscale x 16 x i32>* %0,
     <vscale x 16 x i8> %1,
     i64 %2)
 
   ret <vscale x 16 x i32> %a
declare <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8(
   <vscale x 1 x i64>*,
   <vscale x 1 x i8>,
   i64);
 
 define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8(
     <vscale x 1 x i64>* %0,
     <vscale x 1 x i8> %1,
     i64 %2)
 
   ret <vscale x 1 x i64> %a
declare <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8(
   <vscale x 2 x i64>*,
   <vscale x 2 x i8>,
   i64);
 
 define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8(
     <vscale x 2 x i64>* %0,
     <vscale x 2 x i8> %1,
     i64 %2)
 
   ret <vscale x 2 x i64> %a
declare <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8(
   <vscale x 4 x i64>*,
   <vscale x 4 x i8>,
   i64);
 
 define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8(
     <vscale x 4 x i64>* %0,
     <vscale x 4 x i8> %1,
     i64 %2)
 
   ret <vscale x 4 x i64> %a
declare <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8(
   <vscale x 8 x i64>*,
   <vscale x 8 x i8>,
   i64);
 
 define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8(
     <vscale x 8 x i64>* %0,
     <vscale x 8 x i8> %1,
     i64 %2)
 
   ret <vscale x 8 x i64> %a
declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8(
   <vscale x 1 x half>*,
   <vscale x 1 x i8>,
   i64);
 
 define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8(
     <vscale x 1 x half>* %0,
     <vscale x 1 x i8> %1,
     i64 %2)
 
   ret <vscale x 1 x half> %a
declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8(
   <vscale x 2 x half>*,
   <vscale x 2 x i8>,
   i64);
 
 define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8(
     <vscale x 2 x half>* %0,
     <vscale x 2 x i8> %1,
     i64 %2)
 
   ret <vscale x 2 x half> %a
declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8(
   <vscale x 4 x half>*,
   <vscale x 4 x i8>,
   i64);
 
 define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8(
     <vscale x 4 x half>* %0,
     <vscale x 4 x i8> %1,
     i64 %2)
 
   ret <vscale x 4 x half> %a
declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8(
   <vscale x 8 x half>*,
   <vscale x 8 x i8>,
   i64);
 
 define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8(
     <vscale x 8 x half>* %0,
     <vscale x 8 x i8> %1,
     i64 %2)
 
   ret <vscale x 8 x half> %a
declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8(
   <vscale x 16 x half>*,
   <vscale x 16 x i8>,
   i64);
 
 define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8(
     <vscale x 16 x half>* %0,
     <vscale x 16 x i8> %1,
     i64 %2)
 
   ret <vscale x 16 x half> %a
declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i8(
   <vscale x 32 x half>*,
   <vscale x 32 x i8>,
   i64);
 
 define <vscale x 32 x half> @intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half>* %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m8,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i8(
     <vscale x 32 x half>* %0,
     <vscale x 32 x i8> %1,
     i64 %2)
 
   ret <vscale x 32 x half> %a
declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8(
   <vscale x 1 x float>*,
   <vscale x 1 x i8>,
   i64);
 
 define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8(
     <vscale x 1 x float>* %0,
     <vscale x 1 x i8> %1,
     i64 %2)
 
   ret <vscale x 1 x float> %a
declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8(
   <vscale x 2 x float>*,
   <vscale x 2 x i8>,
   i64);
 
 define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8(
     <vscale x 2 x float>* %0,
     <vscale x 2 x i8> %1,
     i64 %2)
 
   ret <vscale x 2 x float> %a
declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8(
   <vscale x 4 x float>*,
   <vscale x 4 x i8>,
   i64);
 
 define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8(
     <vscale x 4 x float>* %0,
     <vscale x 4 x i8> %1,
     i64 %2)
 
   ret <vscale x 4 x float> %a
declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8(
   <vscale x 8 x float>*,
   <vscale x 8 x i8>,
   i64);
 
 define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8(
     <vscale x 8 x float>* %0,
     <vscale x 8 x i8> %1,
     i64 %2)
 
   ret <vscale x 8 x float> %a
declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8(
   <vscale x 16 x float>*,
   <vscale x 16 x i8>,
   i64);
 
 define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float>* %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8(
     <vscale x 16 x float>* %0,
     <vscale x 16 x i8> %1,
     i64 %2)
 
   ret <vscale x 16 x float> %a
declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8(
   <vscale x 1 x double>*,
   <vscale x 1 x i8>,
   i64);
 
 define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v25, (a0), v8
+; CHECK-NEXT:    vmv1r.v v8, v25
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8(
     <vscale x 1 x double>* %0,
     <vscale x 1 x i8> %1,
     i64 %2)
 
   ret <vscale x 1 x double> %a
declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8(
   <vscale x 2 x double>*,
   <vscale x 2 x i8>,
   i64);
 
 define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double>* %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v26, (a0), v8
+; CHECK-NEXT:    vmv2r.v v8, v26
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8(
     <vscale x 2 x double>* %0,
     <vscale x 2 x i8> %1,
     i64 %2)
 
   ret <vscale x 2 x double> %a
declare <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8(
   <vscale x 4 x double>*,
   <vscale x 4 x i8>,
   i64);
 
 define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double>* %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v28, (a0), v8
+; CHECK-NEXT:    vmv4r.v v8, v28
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8(
     <vscale x 4 x double>* %0,
     <vscale x 4 x i8> %1,
     i64 %2)
 
   ret <vscale x 4 x double> %a
declare <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8(
   <vscale x 8 x double>*,
   <vscale x 8 x i8>,
   i64);
 
 define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double>* %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
-; CHECK-NEXT:    vluxei8.v v8, (a0), v8
+; CHECK-NEXT:    vluxei8.v v16, (a0), v8
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    jalr zero, 0(ra)
 entry:
   %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8(
     <vscale x 8 x double>* %0,
     <vscale x 8 x i8> %1,
     i64 %2)
 
   ret <vscale x 8 x double> %a