[AArch64][GlobalISel] Fall back if disabling neon/fp in the translator.

[aemerson]

Summary

The previous technique relied on early-exiting the legalizer predicate initialization, leaving an empty rule table. That causes a fallback for most instructions, but some have legacy rules defined like G_ZEXT which can try continue, but then crash.

We should fall back earlier, in the translator, to avoid this issue.

[paquette]

LGTM

llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h

411–413

Would it make sense for this hook to just only take in the MF, and then try to call getFunction or whatever to (try to) get at the Function?

[aemerson]

llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h

411–413

Yeah, will do.

[aemerson]

Didn't mean to update this diff, ignore.

llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H
 #define LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H
 
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/TargetCallingConv.h"
 #include "llvm/IR/Attributes.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/IR/Type.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MachineValueType.h"
 #include <cstdint>
public:
   /// This hook behaves as the extended lowerReturn function, but for targets
   /// that do not support swifterror value promotion.
   virtual bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
                            ArrayRef<Register> VRegs,
                            FunctionLoweringInfo &FLI) const {
     return false;
   }
 
-  virtual bool fallBackToDAGISel(const Function &F) const { return false; }
+  virtual bool fallBackToDAGISel(const MachineFunction &MF) const {
+    return false;
+  }
 
   /// This hook must be implemented to lower the incoming (formal)
   /// arguments, described by \p VRegs, for GlobalISel. Each argument
   /// must end up in the related virtual registers described by \p VRegs.
   /// In other words, the first argument should end up in \c VRegs[0],
   /// the second in \c VRegs[1], and so on. For each argument, there will be one
   /// register for each non-aggregate type, as returned by \c computeValueLLTs.
   /// \p MIRBuilder is set to the proper insertion for the argument

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

if (!HasMustTailInVarArgFn)
       HasMustTailInVarArgFn = checkForMustTailInVarArgFn(IsVarArg, BB);
   }
 
   MF->getFrameInfo().setHasMustTailInVarArgFunc(HasMustTailInVarArgFn);
 
   // Make our arguments/constants entry block fallthrough to the IR entry block.
   EntryBB->addSuccessor(&getMBB(F.front()));
 
-  if (CLI->fallBackToDAGISel(F)) {
+  if (CLI->fallBackToDAGISel(*MF)) {
     OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
                                F.getSubprogram(), &F.getEntryBlock());
     R << "unable to lower function: " << ore::NV("Prototype", F.getType());
     reportTranslationError(*MF, *TPC, *ORE, R);
     return false;
   }
 
   // Lower the actual args into this basic block.

llvm/lib/Target/AArch64/GISel/AArch64CallLowering.h

 class AArch64CallLowering: public CallLowering {
 public:
   AArch64CallLowering(const AArch64TargetLowering &TLI);
 
   bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
                    ArrayRef<Register> VRegs, FunctionLoweringInfo &FLI,
                    Register SwiftErrorVReg) const override;
 
-  bool fallBackToDAGISel(const Function &F) const override;
+  bool fallBackToDAGISel(const MachineFunction &MF) const override;
 
   bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
                             ArrayRef<ArrayRef<Register>> VRegs,
                             FunctionLoweringInfo &FLI) const override;
 
   bool lowerCall(MachineIRBuilder &MIRBuilder,
                  CallLoweringInfo &Info) const override;
 

llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp

static void handleMustTailForwardedRegisters(MachineIRBuilder &MIRBuilder,
 
   // Add the forwards to the MachineBasicBlock and MachineFunction.
   for (const auto &F : Forwards) {
     MBB.addLiveIn(F.PReg);
     MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg));
   }
 }
 
-bool AArch64CallLowering::fallBackToDAGISel(const Function &F) const {
+bool AArch64CallLowering::fallBackToDAGISel(const MachineFunction &MF) const {
+  auto &F = MF.getFunction();
   if (isa<ScalableVectorType>(F.getReturnType()))
     return true;
-  return llvm::any_of(F.args(), [](const Argument &A) {
+  if (llvm::any_of(F.args(), [](const Argument &A) {
         return isa<ScalableVectorType>(A.getType());
-  });
+      }))
+    return true;
+  const auto &ST = MF.getSubtarget<AArch64Subtarget>();
+  LLVM_DEBUG(dbgs() << "Falling back to SDAG because we don't support no-NEON");
+  if (!ST.hasNEON() || !ST.hasFPARMv8())
+    return true;
+  return false;
 }
 
 bool AArch64CallLowering::lowerFormalArguments(
     MachineIRBuilder &MIRBuilder, const Function &F,
     ArrayRef<ArrayRef<Register>> VRegs, FunctionLoweringInfo &FLI) const {
   MachineFunction &MF = MIRBuilder.getMF();
   MachineBasicBlock &MBB = MIRBuilder.getMBB();
   MachineRegisterInfo &MRI = MF.getRegInfo();

llvm/test/CodeGen/AArch64/GlobalISel/no-neon-no-fp.ll

-; RUN: not --crash llc -o - -verify-machineinstrs -global-isel -global-isel-abort=1 -stop-after=legalizer %s 2>&1 | FileCheck %s
+; RUN: llc -o - -verify-machineinstrs -global-isel -global-isel-abort=2 %s 2>&1 | FileCheck %s
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-unknown-unknown"
 
-; CHECK: unable to legalize instruction: G_STORE %1:_(s128), %0:_(p0) :: (store 16 into %ir.ptr) (in function: foo)
+; We should fall back in the translator if we don't have no-neon/no-fp support.
+; CHECK: Instruction selection used fallback path for foo
 define void @foo(i128 *%ptr) #0 align 2 {
 entry:
   store i128 0, i128* %ptr, align 16
   ret void
 }
 
+; This test below will crash the legalizer due to trying to use legacy rules,
+; if we don't fall back in the translator.
+declare i1 @zoo()
+; CHECK: Instruction selection used fallback path for bar
+define i32 @bar() #0 {
+  %1 = call zeroext i1 @zoo()
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
 attributes #0 = { "use-soft-float"="false" "target-features"="-fp-armv8,-neon" }