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Differential D98185

[RISCV][MC] Fix nf encoding for vector ld/st whole register
ClosedPublic

Authored by arcbbb on Mar 8 2021, 8:24 AM.

Details

Reviewers
HsiangKai
craig.topper
frasercrmck
Commits
rG5cdb2e98608b: [RISCV][MC] Fix nf encoding for vector ld/st whole register
Summary

The three bit nf is one less than the number of NFIELDS,
so we manually decrement 1 for VS1/2/4/8R & VL1/2/4/8R.

Diff Detail

Event Timeline

arcbbb created this revision.Mar 8 2021, 8:24 AM
Herald added subscribers: vkmr, evandro, luismarques and 24 others. · View Herald TranscriptMar 8 2021, 8:24 AM
arcbbb requested review of this revision.Mar 8 2021, 8:24 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 8 2021, 8:24 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
frasercrmck added a comment.Mar 8 2021, 8:38 AM

Heh, coincidentally, I created D98180 an hour or so ago. Looks like I might have read the spec incorrectly. The wording's a little odd to me.

arcbbb added a comment.Mar 8 2021, 8:54 AM

Oops, sorry I didn't notice your patch, otherwise I would reply in yours instead. I just happened to encounter this runtime bug today.

frasercrmck added a comment.Mar 8 2021, 8:55 AM
In D98185#2611483, @arcbbb wrote:

Oops, sorry I didn't notice your patch, otherwise I would reply in yours instead. I just happened to encounter this runtime bug today.

No worries, it's my fault for not including you (I usually do). I think you're right, anyway: I only tested cases 1 and 2 before submitting my patch. Shame on me.

frasercrmck mentioned this in D98180: [RISCV] Fix vector load/store whole register inst encoding.Mar 8 2021, 8:56 AM
Harbormaster completed remote builds in B92671: Diff 329025.Mar 8 2021, 11:38 AM
craig.topper accepted this revision.Mar 8 2021, 3:24 PM
craig.topper added a subscriber: Paul-C-Anagnostopoulos.

LGTM. Does this need to be merged to LLVM 12? If so please file a bugzilla.

llvm/lib/Target/RISCV/RISCVInstrInfoV.td
514

Feels like tablegen should have maybe warned about the int being truncated to 3 bits. @Paul-C-Anagnostopoulos?

This revision is now accepted and ready to land.Mar 8 2021, 3:24 PM
arcbbb added a comment.Mar 8 2021, 7:20 PM

Thanks for the reminder, I'll file it once my bugzilla account is set up.

This revision was landed with ongoing or failed builds.Mar 8 2021, 7:31 PM
Closed by commit rG5cdb2e98608b: [RISCV][MC] Fix nf encoding for vector ld/st whole register (authored by arcbbb). · Explain Why
This revision was automatically updated to reflect the committed changes.
arcbbb added a commit: rG5cdb2e98608b: [RISCV][MC] Fix nf encoding for vector ld/st whole register.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
16 lines
test/
MC/
RISCV/
rvv/
16 lines
64 lines
16 lines

Diff 329192

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

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def VSUXEI32_V : VIndexedStore<MOPSTIndexedUnord, LSWidth32, "vsuxei32.v">; def VSUXEI32_V : VIndexedStore<MOPSTIndexedUnord, LSWidth32, "vsuxei32.v">;
def VSUXEI64_V : VIndexedStore<MOPSTIndexedUnord, LSWidth64, "vsuxei64.v">; def VSUXEI64_V : VIndexedStore<MOPSTIndexedUnord, LSWidth64, "vsuxei64.v">;
def VSOXEI8_V : VIndexedStore<MOPSTIndexedOrder, LSWidth8, "vsoxei8.v">; def VSOXEI8_V : VIndexedStore<MOPSTIndexedOrder, LSWidth8, "vsoxei8.v">;
def VSOXEI16_V : VIndexedStore<MOPSTIndexedOrder, LSWidth16, "vsoxei16.v">; def VSOXEI16_V : VIndexedStore<MOPSTIndexedOrder, LSWidth16, "vsoxei16.v">;
def VSOXEI32_V : VIndexedStore<MOPSTIndexedOrder, LSWidth32, "vsoxei32.v">; def VSOXEI32_V : VIndexedStore<MOPSTIndexedOrder, LSWidth32, "vsoxei32.v">;
def VSOXEI64_V : VIndexedStore<MOPSTIndexedOrder, LSWidth64, "vsoxei64.v">; def VSOXEI64_V : VIndexedStore<MOPSTIndexedOrder, LSWidth64, "vsoxei64.v">;
defm VL1R : VWholeLoad<1, "vl1r", VR>; defm VL1R : VWholeLoad<0, "vl1r", VR>;
defm VL2R : VWholeLoad<2, "vl2r", VRM2>; defm VL2R : VWholeLoad<1, "vl2r", VRM2>;
defm VL4R : VWholeLoad<4, "vl4r", VRM4>; defm VL4R : VWholeLoad<3, "vl4r", VRM4>;
defm VL8R : VWholeLoad<8, "vl8r", VRM8>; defm VL8R : VWholeLoad<7, "vl8r", VRM8>;
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Feels like tablegen should have maybe warned about the int being truncated to 3 bits. @Paul-C-Anagnostopoulos?

craig.topper: Feels like tablegen should have maybe warned about the int being truncated to 3 bits. @Paul-C…
def : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>; def : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>;
def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VRM2:$vd, GPR:$rs1)>; def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VRM2:$vd, GPR:$rs1)>;
def : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VRM4:$vd, GPR:$rs1)>; def : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VRM4:$vd, GPR:$rs1)>;
def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VRM8:$vd, GPR:$rs1)>; def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VRM8:$vd, GPR:$rs1)>;
def VS1R_V : VWholeStore<1, "vs1r.v", VR>; def VS1R_V : VWholeStore<0, "vs1r.v", VR>;
def VS2R_V : VWholeStore<2, "vs2r.v", VRM2>; def VS2R_V : VWholeStore<1, "vs2r.v", VRM2>;
def VS4R_V : VWholeStore<4, "vs4r.v", VRM4>; def VS4R_V : VWholeStore<3, "vs4r.v", VRM4>;
def VS8R_V : VWholeStore<8, "vs8r.v", VRM8>; def VS8R_V : VWholeStore<7, "vs8r.v", VRM8>;
// Vector Single-Width Integer Add and Subtract // Vector Single-Width Integer Add and Subtract
defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>; defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>;
defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>; defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>;
defm VRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>; defm VRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>;
def : InstAlias<"vneg.v $vd, $vs$vm", (VRSUB_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>; def : InstAlias<"vneg.v $vd, $vs$vm", (VRSUB_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
▲ Show 20 Lines • Show All 639 Lines • Show Last 20 Lines

llvm/test/MC/RISCV/rvv/aliases.s

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# NO-ALIAS: vmxor.mm v0, v0, v0 # encoding: [0x57,0x20,0x00,0x6e] # NO-ALIAS: vmxor.mm v0, v0, v0 # encoding: [0x57,0x20,0x00,0x6e]
vmclr.m v0 vmclr.m v0
# ALIAS: vmset.m v0 # encoding: [0x57,0x20,0x00,0x7e] # ALIAS: vmset.m v0 # encoding: [0x57,0x20,0x00,0x7e]
# NO-ALIAS: vmxnor.mm v0, v0, v0 # encoding: [0x57,0x20,0x00,0x7e] # NO-ALIAS: vmxnor.mm v0, v0, v0 # encoding: [0x57,0x20,0x00,0x7e]
vmset.m v0 vmset.m v0
# ALIAS: vmnot.m v0, v1 # encoding: [0x57,0xa0,0x10,0x76] # ALIAS: vmnot.m v0, v1 # encoding: [0x57,0xa0,0x10,0x76]
# NO-ALIAS: vmnand.mm v0, v1, v1 # encoding: [0x57,0xa0,0x10,0x76] # NO-ALIAS: vmnand.mm v0, v1, v1 # encoding: [0x57,0xa0,0x10,0x76]
vmnot.m v0, v1 vmnot.m v0, v1
# ALIAS: vl1r.v v0, (a0) # encoding: [0x07,0x00,0x85,0x22] # ALIAS: vl1r.v v0, (a0) # encoding: [0x07,0x00,0x85,0x02]
# NO-ALIAS: vl1re8.v v0, (a0) # encoding: [0x07,0x00,0x85,0x22] # NO-ALIAS: vl1re8.v v0, (a0) # encoding: [0x07,0x00,0x85,0x02]
vl1r.v v0, (a0) vl1r.v v0, (a0)
# ALIAS: vl2r.v v0, (a0) # encoding: [0x07,0x00,0x85,0x42] # ALIAS: vl2r.v v0, (a0) # encoding: [0x07,0x00,0x85,0x22]
# NO-ALIAS: vl2re8.v v0, (a0) # encoding: [0x07,0x00,0x85,0x42] # NO-ALIAS: vl2re8.v v0, (a0) # encoding: [0x07,0x00,0x85,0x22]
vl2r.v v0, (a0) vl2r.v v0, (a0)
# ALIAS: vl4r.v v0, (a0) # encoding: [0x07,0x00,0x85,0x82] # ALIAS: vl4r.v v0, (a0) # encoding: [0x07,0x00,0x85,0x62]
# NO-ALIAS: vl4re8.v v0, (a0) # encoding: [0x07,0x00,0x85,0x82] # NO-ALIAS: vl4re8.v v0, (a0) # encoding: [0x07,0x00,0x85,0x62]
vl4r.v v0, (a0) vl4r.v v0, (a0)
# ALIAS: vl8r.v v0, (a0) # encoding: [0x07,0x00,0x85,0x02] # ALIAS: vl8r.v v0, (a0) # encoding: [0x07,0x00,0x85,0xe2]
# NO-ALIAS: vl8re8.v v0, (a0) # encoding: [0x07,0x00,0x85,0x02] # NO-ALIAS: vl8re8.v v0, (a0) # encoding: [0x07,0x00,0x85,0xe2]
vl8r.v v0, (a0) vl8r.v v0, (a0)
# ALIAS: vneg.v v2, v1, v0.t # encoding: [0x57,0x41,0x10,0x0c] # ALIAS: vneg.v v2, v1, v0.t # encoding: [0x57,0x41,0x10,0x0c]
# NO-ALIAS: vrsub.vx v2, v1, zero, v0.t # encoding: [0x57,0x41,0x10,0x0c] # NO-ALIAS: vrsub.vx v2, v1, zero, v0.t # encoding: [0x57,0x41,0x10,0x0c]
vneg.v v2, v1, v0.t vneg.v v2, v1, v0.t
# ALIAS: vncvt.x.x.w v2, v1, v0.t # encoding: [0x57,0x41,0x10,0xb0] # ALIAS: vncvt.x.x.w v2, v1, v0.t # encoding: [0x57,0x41,0x10,0xb0]
# NO-ALIAS: vnsrl.wx v2, v1, zero, v0.t # encoding: [0x57,0x41,0x10,0xb0] # NO-ALIAS: vnsrl.wx v2, v1, zero, v0.t # encoding: [0x57,0x41,0x10,0xb0]
vncvt.x.x.w v2, v1, v0.t vncvt.x.x.w v2, v1, v0.t
# ALIAS: vfneg.v v2, v1, v0.t # encoding: [0x57,0x91,0x10,0x24] # ALIAS: vfneg.v v2, v1, v0.t # encoding: [0x57,0x91,0x10,0x24]
# NO-ALIAS: vfsgnjn.vv v2, v1, v1, v0.t # encoding: [0x57,0x91,0x10,0x24] # NO-ALIAS: vfsgnjn.vv v2, v1, v1, v0.t # encoding: [0x57,0x91,0x10,0x24]
vfneg.v v2, v1, v0.t vfneg.v v2, v1, v0.t

llvm/test/MC/RISCV/rvv/load.s

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vloxei64.v v8, (a0), v4 vloxei64.v v8, (a0), v4
# CHECK-INST: vloxei64.v v8, (a0), v4 # CHECK-INST: vloxei64.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x74,0x45,0x0e] # CHECK-ENCODING: [0x07,0x74,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 74 45 0e <unknown> # CHECK-UNKNOWN: 07 74 45 0e <unknown>
vl1re8.v v8, (a0) vl1re8.v v8, (a0)
# CHECK-INST: vl1re8.v v8, (a0) # CHECK-INST: vl1re8.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x85,0x22] # CHECK-ENCODING: [0x07,0x04,0x85,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 85 22 <unknown> # CHECK-UNKNOWN: 07 04 85 02 <unknown>
vl1re16.v v8, (a0) vl1re16.v v8, (a0)
# CHECK-INST: vl1re16.v v8, (a0) # CHECK-INST: vl1re16.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x85,0x22] # CHECK-ENCODING: [0x07,0x54,0x85,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 85 22 <unknown> # CHECK-UNKNOWN: 07 54 85 02 <unknown>
vl1re32.v v8, (a0) vl1re32.v v8, (a0)
# CHECK-INST: vl1re32.v v8, (a0) # CHECK-INST: vl1re32.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x85,0x22] # CHECK-ENCODING: [0x07,0x64,0x85,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 85 22 <unknown> # CHECK-UNKNOWN: 07 64 85 02 <unknown>
vl1re64.v v8, (a0) vl1re64.v v8, (a0)
# CHECK-INST: vl1re64.v v8, (a0) # CHECK-INST: vl1re64.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x85,0x22] # CHECK-ENCODING: [0x07,0x74,0x85,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 74 85 22 <unknown> # CHECK-UNKNOWN: 07 74 85 02 <unknown>
vl2re8.v v8, (a0) vl2re8.v v8, (a0)
# CHECK-INST: vl2re8.v v8, (a0) # CHECK-INST: vl2re8.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x85,0x42] # CHECK-ENCODING: [0x07,0x04,0x85,0x22]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 85 42 <unknown> # CHECK-UNKNOWN: 07 04 85 22 <unknown>
vl2re16.v v8, (a0) vl2re16.v v8, (a0)
# CHECK-INST: vl2re16.v v8, (a0) # CHECK-INST: vl2re16.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x85,0x42] # CHECK-ENCODING: [0x07,0x54,0x85,0x22]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 85 42 <unknown> # CHECK-UNKNOWN: 07 54 85 22 <unknown>
vl2re32.v v8, (a0) vl2re32.v v8, (a0)
# CHECK-INST: vl2re32.v v8, (a0) # CHECK-INST: vl2re32.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x85,0x42] # CHECK-ENCODING: [0x07,0x64,0x85,0x22]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 85 42 <unknown> # CHECK-UNKNOWN: 07 64 85 22 <unknown>
vl2re64.v v8, (a0) vl2re64.v v8, (a0)
# CHECK-INST: vl2re64.v v8, (a0) # CHECK-INST: vl2re64.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x85,0x42] # CHECK-ENCODING: [0x07,0x74,0x85,0x22]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 74 85 42 <unknown> # CHECK-UNKNOWN: 07 74 85 22 <unknown>
vl4re8.v v8, (a0) vl4re8.v v8, (a0)
# CHECK-INST: vl4re8.v v8, (a0) # CHECK-INST: vl4re8.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x85,0x82] # CHECK-ENCODING: [0x07,0x04,0x85,0x62]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 85 82 <unknown> # CHECK-UNKNOWN: 07 04 85 62 <unknown>
vl4re16.v v8, (a0) vl4re16.v v8, (a0)
# CHECK-INST: vl4re16.v v8, (a0) # CHECK-INST: vl4re16.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x85,0x82] # CHECK-ENCODING: [0x07,0x54,0x85,0x62]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 85 82 <unknown> # CHECK-UNKNOWN: 07 54 85 62 <unknown>
vl4re32.v v8, (a0) vl4re32.v v8, (a0)
# CHECK-INST: vl4re32.v v8, (a0) # CHECK-INST: vl4re32.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x85,0x82] # CHECK-ENCODING: [0x07,0x64,0x85,0x62]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 85 82 <unknown> # CHECK-UNKNOWN: 07 64 85 62 <unknown>
vl4re64.v v8, (a0) vl4re64.v v8, (a0)
# CHECK-INST: vl4re64.v v8, (a0) # CHECK-INST: vl4re64.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x85,0x82] # CHECK-ENCODING: [0x07,0x74,0x85,0x62]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 74 85 82 <unknown> # CHECK-UNKNOWN: 07 74 85 62 <unknown>
vl8re8.v v8, (a0) vl8re8.v v8, (a0)
# CHECK-INST: vl8re8.v v8, (a0) # CHECK-INST: vl8re8.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x85,0x02] # CHECK-ENCODING: [0x07,0x04,0x85,0xe2]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 85 02 <unknown> # CHECK-UNKNOWN: 07 04 85 e2 <unknown>
vl8re16.v v8, (a0) vl8re16.v v8, (a0)
# CHECK-INST: vl8re16.v v8, (a0) # CHECK-INST: vl8re16.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x85,0x02] # CHECK-ENCODING: [0x07,0x54,0x85,0xe2]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 85 02 <unknown> # CHECK-UNKNOWN: 07 54 85 e2 <unknown>
vl8re32.v v8, (a0) vl8re32.v v8, (a0)
# CHECK-INST: vl8re32.v v8, (a0) # CHECK-INST: vl8re32.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x85,0x02] # CHECK-ENCODING: [0x07,0x64,0x85,0xe2]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 85 02 <unknown> # CHECK-UNKNOWN: 07 64 85 e2 <unknown>
vl8re64.v v8, (a0) vl8re64.v v8, (a0)
# CHECK-INST: vl8re64.v v8, (a0) # CHECK-INST: vl8re64.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x85,0x02] # CHECK-ENCODING: [0x07,0x74,0x85,0xe2]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 74 85 02 <unknown> # CHECK-UNKNOWN: 07 74 85 e2 <unknown>

llvm/test/MC/RISCV/rvv/store.s

Show First 20 Lines • Show All 202 Lines • ▼ Show 20 Lines
vsoxei64.v v24, (a0), v4 vsoxei64.v v24, (a0), v4
# CHECK-INST: vsoxei64.v v24, (a0), v4 # CHECK-INST: vsoxei64.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0x0e] # CHECK-ENCODING: [0x27,0x7c,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 7c 45 0e <unknown> # CHECK-UNKNOWN: 27 7c 45 0e <unknown>
vs1r.v v24, (a0) vs1r.v v24, (a0)
# CHECK-INST: vs1r.v v24, (a0) # CHECK-INST: vs1r.v v24, (a0)
# CHECK-ENCODING: [0x27,0x0c,0x85,0x22] # CHECK-ENCODING: [0x27,0x0c,0x85,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c 85 22 <unknown> # CHECK-UNKNOWN: 27 0c 85 02 <unknown>
vs2r.v v24, (a0) vs2r.v v24, (a0)
# CHECK-INST: vs2r.v v24, (a0) # CHECK-INST: vs2r.v v24, (a0)
# CHECK-ENCODING: [0x27,0x0c,0x85,0x42] # CHECK-ENCODING: [0x27,0x0c,0x85,0x22]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c 85 42 <unknown> # CHECK-UNKNOWN: 27 0c 85 22 <unknown>
vs4r.v v24, (a0) vs4r.v v24, (a0)
# CHECK-INST: vs4r.v v24, (a0) # CHECK-INST: vs4r.v v24, (a0)
# CHECK-ENCODING: [0x27,0x0c,0x85,0x82] # CHECK-ENCODING: [0x27,0x0c,0x85,0x62]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c 85 82 <unknown> # CHECK-UNKNOWN: 27 0c 85 62 <unknown>
vs8r.v v24, (a0) vs8r.v v24, (a0)
# CHECK-INST: vs8r.v v24, (a0) # CHECK-INST: vs8r.v v24, (a0)
# CHECK-ENCODING: [0x27,0x0c,0x85,0x02] # CHECK-ENCODING: [0x27,0x0c,0x85,0xe2]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c 85 02 <unknown> # CHECK-UNKNOWN: 27 0c 85 e2 <unknown>