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[RISCV][MC] Fix nf encoding for vector ld/st whole register
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Authored by arcbbb on Mar 8 2021, 8:24 AM.

Details

Summary

The three bit nf is one less than the number of NFIELDS,
so we manually decrement 1 for VS1/2/4/8R & VL1/2/4/8R.

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Event Timeline

arcbbb created this revision.Mar 8 2021, 8:24 AM
arcbbb requested review of this revision.Mar 8 2021, 8:24 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 8 2021, 8:24 AM

Heh, coincidentally, I created D98180 an hour or so ago. Looks like I might have read the spec incorrectly. The wording's a little odd to me.

arcbbb added a comment.Mar 8 2021, 8:54 AM

Oops, sorry I didn't notice your patch, otherwise I would reply in yours instead. I just happened to encounter this runtime bug today.

Oops, sorry I didn't notice your patch, otherwise I would reply in yours instead. I just happened to encounter this runtime bug today.

No worries, it's my fault for not including you (I usually do). I think you're right, anyway: I only tested cases 1 and 2 before submitting my patch. Shame on me.

craig.topper accepted this revision.Mar 8 2021, 3:24 PM

LGTM. Does this need to be merged to LLVM 12? If so please file a bugzilla.

llvm/lib/Target/RISCV/RISCVInstrInfoV.td
514

Feels like tablegen should have maybe warned about the int being truncated to 3 bits. @Paul-C-Anagnostopoulos?

This revision is now accepted and ready to land.Mar 8 2021, 3:24 PM
arcbbb added a comment.Mar 8 2021, 7:20 PM

Thanks for the reminder, I'll file it once my bugzilla account is set up.

This revision was landed with ongoing or failed builds.Mar 8 2021, 7:31 PM
This revision was automatically updated to reflect the committed changes.