[PowerPC] Removing _massv place holder

[masoud.ataei]

Summary

Since P8 is the oldest machine supported by MASSV pass, _massv place holder
is removed and the oldest version of MASSV functions is assumed. If the P9 vector
specific is detected in the compilation process, the P8 prefix will be updated to P9.

[rzurob]

LGTM

llvm/include/llvm/Analysis/VecFuncs.def

 
 TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVbN4v_logf", FIXED(4))
 TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVdN8v_logf", FIXED(8))
 
 #elif defined(TLI_DEFINE_MASSV_VECFUNCS)
 // IBM MASS library's vector Functions
 
 // Floating-Point Arithmetic and Auxiliary Functions
-TLI_DEFINE_VECFUNC("cbrt", "__cbrtd2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("cbrtf", "__cbrtf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("pow", "__powd2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("llvm.pow.f64", "__powd2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("powf", "__powf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("llvm.pow.f32", "__powf4_massv", FIXED(4))
+TLI_DEFINE_VECFUNC("cbrt", "__cbrtd2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("cbrtf", "__cbrtf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("pow", "__powd2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("llvm.pow.f64", "__powd2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("powf", "__powf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("llvm.pow.f32", "__powf4_P8", FIXED(4))
 
 // Exponential and Logarithmic Functions
-TLI_DEFINE_VECFUNC("exp", "__expd2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("llvm.exp.f64", "__expd2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("expf", "__expf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("llvm.exp.f32", "__expf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("exp2", "__exp2d2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("llvm.exp2.f64", "__exp2d2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("exp2f", "__exp2f4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("llvm.exp2.f32", "__exp2f4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("expm1", "__expm1d2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("expm1f", "__expm1f4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("log", "__logd2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("llvm.log.f64", "__logd2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("logf", "__logf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("llvm.log.f32", "__logf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("log1p", "__log1pd2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("log1pf", "__log1pf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("log10", "__log10d2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("llvm.log10.f64", "__log10d2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("log10f", "__log10f4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("llvm.log10.f32", "__log10f4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("log2", "__log2d2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("llvm.log2.f64", "__log2d2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("log2f", "__log2f4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("llvm.log2.f32", "__log2f4_massv", FIXED(4))
+TLI_DEFINE_VECFUNC("exp", "__expd2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("llvm.exp.f64", "__expd2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("expf", "__expf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("llvm.exp.f32", "__expf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("exp2", "__exp2d2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("llvm.exp2.f64", "__exp2d2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("exp2f", "__exp2f4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("llvm.exp2.f32", "__exp2f4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("expm1", "__expm1d2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("expm1f", "__expm1f4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("log", "__logd2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("llvm.log.f64", "__logd2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("logf", "__logf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("llvm.log.f32", "__logf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("log1p", "__log1pd2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("log1pf", "__log1pf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("log10", "__log10d2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("llvm.log10.f64", "__log10d2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("log10f", "__log10f4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("llvm.log10.f32", "__log10f4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("log2", "__log2d2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("llvm.log2.f64", "__log2d2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("log2f", "__log2f4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("llvm.log2.f32", "__log2f4_P8", FIXED(4))
 
 // Trigonometric Functions
-TLI_DEFINE_VECFUNC("sin", "__sind2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("llvm.sin.f64", "__sind2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("sinf", "__sinf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("llvm.sin.f32", "__sinf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("cos", "__cosd2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("llvm.cos.f64", "__cosd2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("cosf", "__cosf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("llvm.cos.f32", "__cosf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("tan", "__tand2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("tanf", "__tanf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("asin", "__asind2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("asinf", "__asinf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("acos", "__acosd2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("acosf", "__acosf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("atan", "__atand2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("atanf", "__atanf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("atan2", "__atan2d2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("atan2f", "__atan2f4_massv", FIXED(4))
+TLI_DEFINE_VECFUNC("sin", "__sind2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("llvm.sin.f64", "__sind2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("sinf", "__sinf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("llvm.sin.f32", "__sinf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("cos", "__cosd2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("llvm.cos.f64", "__cosd2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("cosf", "__cosf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("llvm.cos.f32", "__cosf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("tan", "__tand2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("tanf", "__tanf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("asin", "__asind2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("asinf", "__asinf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("acos", "__acosd2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("acosf", "__acosf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("atan", "__atand2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("atanf", "__atanf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("atan2", "__atan2d2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("atan2f", "__atan2f4_P8", FIXED(4))
 
 // Hyperbolic Functions
-TLI_DEFINE_VECFUNC("sinh", "__sinhd2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("sinhf", "__sinhf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("cosh", "__coshd2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("coshf", "__coshf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("tanh", "__tanhd2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("tanhf", "__tanhf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("asinh", "__asinhd2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("asinhf", "__asinhf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("acosh", "__acoshd2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("acoshf", "__acoshf4_massv", FIXED(4))
-TLI_DEFINE_VECFUNC("atanh", "__atanhd2_massv", FIXED(2))
-TLI_DEFINE_VECFUNC("atanhf", "__atanhf4_massv", FIXED(4))
+TLI_DEFINE_VECFUNC("sinh", "__sinhd2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("sinhf", "__sinhf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("cosh", "__coshd2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("coshf", "__coshf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("tanh", "__tanhd2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("tanhf", "__tanhf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("asinh", "__asinhd2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("asinhf", "__asinhf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("acosh", "__acoshd2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("acoshf", "__acoshf4_P8", FIXED(4))
+TLI_DEFINE_VECFUNC("atanh", "__atanhd2_P8", FIXED(2))
+TLI_DEFINE_VECFUNC("atanhf", "__atanhf4_P8", FIXED(4))
 
 
 #elif defined(TLI_DEFINE_SVML_VECFUNCS)
 // Intel SVM library's Vector Functions
 
 TLI_DEFINE_VECFUNC("sin", "__svml_sin2", FIXED(2))
 TLI_DEFINE_VECFUNC("sin", "__svml_sin4", FIXED(4))
 TLI_DEFINE_VECFUNC("sin", "__svml_sin8", FIXED(8))

llvm/lib/Target/PowerPC/PPCLowerMASSVEntries.cpp

 
 #define DEBUG_TYPE "ppc-lower-massv-entries"
 
 using namespace llvm;
 
 namespace {
 
 // Length of the suffix "massv", which is specific to IBM MASSV library entries.
-const unsigned MASSVSuffixLength = 5;
+const unsigned MASSVSuffixLength = 2;
 
 static StringRef MASSVFuncs[] = {
 #define TLI_DEFINE_MASSV_VECFUNCS_NAMES
 #include "llvm/Analysis/VecFuncs.def"
 };
 
 class PPCLowerMASSVEntries : public ModulePass {
 public:
PPCLowerMASSVEntries::createMASSVFuncName(Function &Func,
   std::string MASSVEntryName = GenericName + Suffix.str();
   return MASSVEntryName;
 }
 
 /// If there are proper fast-math flags, this function creates llvm.pow
 /// intrinsics when the exponent is 0.25 or 0.75.
 bool PPCLowerMASSVEntries::handlePowSpecialCases(CallInst *CI, Function &Func,
                                                  Module &M) {
-  if (Func.getName() != "__powf4_massv" && Func.getName() != "__powd2_massv")
+  if (Func.getName() != "__powf4_P8" && Func.getName() != "__powd2_P8")
     return false;
 
   if (Constant *Exp = dyn_cast<Constant>(CI->getArgOperand(1)))
     if (ConstantFP *CFP = dyn_cast_or_null<ConstantFP>(Exp->getSplatValue())) {
       // If the argument is 0.75 or 0.25 it is cheaper to turn it into pow
       // intrinsic so that it could be optimzed as sequence of sqrt's.
       if (!CI->hasNoInfs() || !CI->hasApproxFunc())
         return false;

llvm/test/CodeGen/Generic/replace-intrinsics-with-veclib.ll

 ;
 ; LIBMVEC-X86-LABEL: define {{[^@]+}}@exp_f32
 ; LIBMVEC-X86-SAME: (<4 x float> [[IN:%.*]]) {
 ; LIBMVEC-X86-NEXT:    [[TMP1:%.*]] = call <4 x float> @_ZGVbN4v_expf(<4 x float> [[IN]])
 ; LIBMVEC-X86-NEXT:    ret <4 x float> [[TMP1]]
 ;
 ; MASSV-LABEL: define {{[^@]+}}@exp_f32
 ; MASSV-SAME: (<4 x float> [[IN:%.*]]) {
-; MASSV-NEXT:    [[TMP1:%.*]] = call <4 x float> @__expf4_massv(<4 x float> [[IN]])
+; MASSV-NEXT:    [[TMP1:%.*]] = call <4 x float> @__expf4_P8(<4 x float> [[IN]])
 ; MASSV-NEXT:    ret <4 x float> [[TMP1]]
 ;
 ; ACCELERATE-LABEL: define {{[^@]+}}@exp_f32
 ; ACCELERATE-SAME: (<4 x float> [[IN:%.*]]) {
 ; ACCELERATE-NEXT:    [[TMP1:%.*]] = call <4 x float> @vexpf(<4 x float> [[IN]])
 ; ACCELERATE-NEXT:    ret <4 x float> [[TMP1]]
 ;
   %call = call <4 x float> @llvm.exp.v4f32(<4 x float> %in)

llvm/test/CodeGen/PowerPC/lower-massv-attr.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr9  < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=-power9-vector | FileCheck -check-prefixes=CHECK-PWR8,CHECK-ALL %s 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8  < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+power9-vector | FileCheck -check-prefixes=CHECK-PWR9,CHECK-ALL %s 
 
-declare <2 x double> @__cbrtd2_massv(<2 x double>)
-declare <4 x float> @__cbrtf4_massv(<4 x float>)
+declare <2 x double> @__cbrtd2_P8(<2 x double>)
+declare <4 x float> @__cbrtf4_P8(<4 x float>)
 
 ; cbrt without the power9-vector attribute on the caller
 ; check massv calls are correctly targeted for Power8
 define <2 x double>  @cbrt_f64_massv_nopwr9(<2 x double> %opnd) #0 {
 ; CHECK-ALL-LABEL: @cbrt_f64_massv_nopwr9
 ; CHECK-PWR8: bl __cbrtd2_P8
 ; CHECK-NOT: bl __cbrtd2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__cbrtd2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__cbrtd2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 ; cbrt with the power9-vector attribute on the caller
 ; check massv calls are correctly targeted for Power9
 define <2 x double>  @cbrt_f64_massv_pwr9(<2 x double> %opnd) #1 {
 ; CHECK-ALL-LABEL: @cbrt_f64_massv_pwr9
 ; CHECK-PWR9: bl __cbrtd2_P9
 ; CHECK-NOT: bl __cbrtd2_massv
+; CHECK-NOT: bl __cbrtd2_P8
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__cbrtd2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__cbrtd2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }

llvm/test/CodeGen/PowerPC/lower-massv.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr9  < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefixes=CHECK-PWR9,CHECK-ALL %s 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8  < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefixes=CHECK-PWR8,CHECK-ALL %s 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8  < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck --check-prefix=CHECK-ALL %s 
 
-declare <2 x double> @__cbrtd2_massv(<2 x double>)
-declare <4 x float> @__cbrtf4_massv(<4 x float>)
+declare <2 x double> @__cbrtd2_P8(<2 x double>)
+declare <4 x float> @__cbrtf4_P8(<4 x float>)
 
-declare <2 x double> @__powd2_massv(<2 x double>, <2 x double>)
-declare <4 x float> @__powf4_massv(<4 x float>, <4 x float>)
+declare <2 x double> @__powd2_P8(<2 x double>, <2 x double>)
+declare <4 x float> @__powf4_P8(<4 x float>, <4 x float>)
 
-declare <2 x double> @__expd2_massv(<2 x double>)
-declare <4 x float> @__expf4_massv(<4 x float>)
+declare <2 x double> @__expd2_P8(<2 x double>)
+declare <4 x float> @__expf4_P8(<4 x float>)
 
-declare <2 x double> @__exp2d2_massv(<2 x double>)
-declare <4 x float> @__exp2f4_massv(<4 x float>)
+declare <2 x double> @__exp2d2_P8(<2 x double>)
+declare <4 x float> @__exp2f4_P8(<4 x float>)
 
-declare <2 x double> @__expm1d2_massv(<2 x double>)
-declare <4 x float> @__expm1f4_massv(<4 x float>)
+declare <2 x double> @__expm1d2_P8(<2 x double>)
+declare <4 x float> @__expm1f4_P8(<4 x float>)
 
-declare <2 x double> @__logd2_massv(<2 x double>)
-declare <4 x float> @__logf4_massv(<4 x float>)
+declare <2 x double> @__logd2_P8(<2 x double>)
+declare <4 x float> @__logf4_P8(<4 x float>)
 
-declare <2 x double> @__log1pd2_massv(<2 x double>)
-declare <4 x float> @__log1pf4_massv(<4 x float>)
+declare <2 x double> @__log1pd2_P8(<2 x double>)
+declare <4 x float> @__log1pf4_P8(<4 x float>)
 
-declare <2 x double> @__log10d2_massv(<2 x double>)
-declare <4 x float> @__log10f4_massv(<4 x float>)
+declare <2 x double> @__log10d2_P8(<2 x double>)
+declare <4 x float> @__log10f4_P8(<4 x float>)
 
-declare <2 x double> @__log2d2_massv(<2 x double>)
-declare <4 x float> @__log2f4_massv(<4 x float>)
+declare <2 x double> @__log2d2_P8(<2 x double>)
+declare <4 x float> @__log2f4_P8(<4 x float>)
 
-declare <2 x double> @__sind2_massv(<2 x double>)
-declare <4 x float> @__sinf4_massv(<4 x float>)
+declare <2 x double> @__sind2_P8(<2 x double>)
+declare <4 x float> @__sinf4_P8(<4 x float>)
 
-declare <2 x double> @__cosd2_massv(<2 x double>)
-declare <4 x float> @__cosf4_massv(<4 x float>)
+declare <2 x double> @__cosd2_P8(<2 x double>)
+declare <4 x float> @__cosf4_P8(<4 x float>)
 
-declare <2 x double> @__tand2_massv(<2 x double>)
-declare <4 x float> @__tanf4_massv(<4 x float>)
+declare <2 x double> @__tand2_P8(<2 x double>)
+declare <4 x float> @__tanf4_P8(<4 x float>)
 
-declare <2 x double> @__asind2_massv(<2 x double>)
-declare <4 x float> @__asinf4_massv(<4 x float>)
+declare <2 x double> @__asind2_P8(<2 x double>)
+declare <4 x float> @__asinf4_P8(<4 x float>)
 
-declare <2 x double> @__acosd2_massv(<2 x double>)
-declare <4 x float> @__acosf4_massv(<4 x float>)
+declare <2 x double> @__acosd2_P8(<2 x double>)
+declare <4 x float> @__acosf4_P8(<4 x float>)
 
-declare <2 x double> @__atand2_massv(<2 x double>)
-declare <4 x float> @__atanf4_massv(<4 x float>)
+declare <2 x double> @__atand2_P8(<2 x double>)
+declare <4 x float> @__atanf4_P8(<4 x float>)
 
-declare <2 x double> @__atan2d2_massv(<2 x double>)
-declare <4 x float> @__atan2f4_massv(<4 x float>)
+declare <2 x double> @__atan2d2_P8(<2 x double>)
+declare <4 x float> @__atan2f4_P8(<4 x float>)
 
-declare <2 x double> @__sinhd2_massv(<2 x double>)
-declare <4 x float> @__sinhf4_massv(<4 x float>)
+declare <2 x double> @__sinhd2_P8(<2 x double>)
+declare <4 x float> @__sinhf4_P8(<4 x float>)
 
-declare <2 x double> @__coshd2_massv(<2 x double>)
-declare <4 x float> @__coshf4_massv(<4 x float>)
+declare <2 x double> @__coshd2_P8(<2 x double>)
+declare <4 x float> @__coshf4_P8(<4 x float>)
 
-declare <2 x double> @__tanhd2_massv(<2 x double>)
-declare <4 x float> @__tanhf4_massv(<4 x float>)
+declare <2 x double> @__tanhd2_P8(<2 x double>)
+declare <4 x float> @__tanhf4_P8(<4 x float>)
 
-declare <2 x double> @__asinhd2_massv(<2 x double>)
-declare <4 x float> @__asinhf4_massv(<4 x float>)
+declare <2 x double> @__asinhd2_P8(<2 x double>)
+declare <4 x float> @__asinhf4_P8(<4 x float>)
 
-declare <2 x double> @__acoshd2_massv(<2 x double>)
-declare <4 x float> @__acoshf4_massv(<4 x float>)
+declare <2 x double> @__acoshd2_P8(<2 x double>)
+declare <4 x float> @__acoshf4_P8(<4 x float>)
 
-declare <2 x double> @__atanhd2_massv(<2 x double>)
-declare <4 x float> @__atanhf4_massv(<4 x float>)
+declare <2 x double> @__atanhd2_P8(<2 x double>)
+declare <4 x float> @__atanhf4_P8(<4 x float>)
 
 ; following tests check generation of subtarget-specific calls
 ; cbrt
 define <2 x double>  @cbrt_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @cbrt_f64_massv
 ; CHECK-PWR9: bl __cbrtd2_P9
 ; CHECK-PWR8: bl __cbrtd2_P8
 ; CHECK-NOT: bl __cbrtd2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__cbrtd2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__cbrtd2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @cbrt_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @cbrt_f32_massv
 ; CHECK-PWR9: bl __cbrtf4_P9
 ; CHECK-PWR8: bl __cbrtf4_P8
 ; CHECK-NOT: bl __cbrtf4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__cbrtf4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__cbrtf4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; pow
 define <2 x double>  @pow_f64_massv(<2 x double> %opnd1, <2 x double> %opnd2) {
 ; CHECK-ALL-LABEL: @pow_f64_massv
 ; CHECK-PWR9: bl __powd2_P9
 ; CHECK-PWR8: bl __powd2_P8
 ; CHECK-NOT: bl __powd2_massv
 ; CHECK-ALL: blr
 ;
- %1 = call <2 x double> @__powd2_massv(<2 x double> %opnd1, <2 x double> %opnd2)
+ %1 = call <2 x double> @__powd2_P8(<2 x double> %opnd1, <2 x double> %opnd2)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @pow_f32_massv(<4 x float> %opnd1, <4 x float> %opnd2) {
 ; CHECK-ALL-LABEL: @pow_f32_massv
 ; CHECK-PWR9: bl __powf4_P9
 ; CHECK-PWR8: bl __powf4_P8
 ; CHECK-NOT: bl __powf4_massv
 ; CHECK-ALL: blr
 ;
- %1 = call <4 x float> @__powf4_massv(<4 x float> %opnd1, <4 x float> %opnd2)
+ %1 = call <4 x float> @__powf4_P8(<4 x float> %opnd1, <4 x float> %opnd2)
   ret <4 x float> %1 
 }
 
 ; exp
 define <2 x double>  @exp_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @exp_f64_massv
 ; CHECK-PWR9: bl __expd2_P9
 ; CHECK-PWR8: bl __expd2_P8
 ; CHECK-NOT: bl __expd2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__expd2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__expd2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @exp_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @exp_f32_massv
 ; CHECK-PWR9: bl __expf4_P9
 ; CHECK-PWR8: bl __expf4_P8
 ; CHECK-NOT: bl __expf4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__expf4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__expf4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; exp2
 define <2 x double>  @exp2_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @exp2_f64_massv
 ; CHECK-PWR9: bl __exp2d2_P9
 ; CHECK-PWR8: bl __exp2d2_P8
 ; CHECK-NOT: bl __exp2d2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__exp2d2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__exp2d2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @exp2_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @exp2_f32_massv
 ; CHECK-PWR9: bl __exp2f4_P9
 ; CHECK-PWR8: bl __exp2f4_P8
 ; CHECK-NOT: bl __exp2f4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__exp2f4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__exp2f4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; expm1
 define <2 x double>  @expm1_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @expm1_f64_massv
 ; CHECK-PWR9: bl __expm1d2_P9
 ; CHECK-PWR8: bl __expm1d2_P8
 ; CHECK-NOT: bl __expm1d2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__expm1d2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__expm1d2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @expm1_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @expm1_f32_massv
 ; CHECK-PWR9: bl __expm1f4_P9
 ; CHECK-PWR8: bl __expm1f4_P8
 ; CHECK-NOT: bl __expm1f4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__expm1f4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__expm1f4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; log
 define <2 x double>  @log_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @log_f64_massv
 ; CHECK-PWR9: bl __logd2_P9
 ; CHECK-PWR8: bl __logd2_P8
 ; CHECK-NOT: bl __logd2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__logd2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__logd2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @log_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @log_f32_massv
 ; CHECK-PWR9: bl __logf4_P9
 ; CHECK-PWR8: bl __logf4_P8
 ; CHECK-NOT: bl __logf4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__logf4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__logf4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; log1p
 define <2 x double>  @log1p_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @log1p_f64_massv
 ; CHECK-PWR9: bl __log1pd2_P9
 ; CHECK-PWR8: bl __log1pd2_P8
 ; CHECK-NOT: bl __log1pd2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__log1pd2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__log1pd2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @log1p_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @log1p_f32_massv
 ; CHECK-PWR9: bl __log1pf4_P9
 ; CHECK-PWR8: bl __log1pf4_P8
 ; CHECK-NOT: bl __log1pf4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__log1pf4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__log1pf4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; log10
 define <2 x double>  @log10_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @log10_f64_massv
 ; CHECK-PWR9: bl __log10d2_P9
 ; CHECK-PWR8: bl __log10d2_P8
 ; CHECK-NOT: bl __log10d2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__log10d2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__log10d2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @log10_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @log10_f32_massv
 ; CHECK-PWR9: bl __log10f4_P9
 ; CHECK-PWR8: bl __log10f4_P8
 ; CHECK-NOT: bl __log10f4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__log10f4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__log10f4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; log2
 define <2 x double>  @log2_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @log2_f64_massv
 ; CHECK-PWR9: bl __log2d2_P9
 ; CHECK-PWR8: bl __log2d2_P8
 ; CHECK-NOT: bl __log2d2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__log2d2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__log2d2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @log2_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @log2_f32_massv
 ; CHECK-PWR9: bl __log2f4_P9
 ; CHECK-PWR8: bl __log2f4_P8
 ; CHECK-NOT: bl __log2f4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__log2f4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__log2f4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; sin
 define <2 x double>  @sin_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @sin_f64_massv
 ; CHECK-PWR9: bl __sind2_P9
 ; CHECK-PWR8: bl __sind2_P8
 ; CHECK-NOT: bl __sind2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__sind2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__sind2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @sin_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @sin_f32_massv
 ; CHECK-PWR9: bl __sinf4_P9
 ; CHECK-PWR8: bl __sinf4_P8
 ; CHECK-NOT: bl __sinf4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__sinf4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__sinf4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; cos
 define <2 x double>  @cos_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @cos_f64_massv
 ; CHECK-PWR9: bl __cosd2_P9
 ; CHECK-PWR8: bl __cosd2_P8
 ; CHECK-NOT: bl __cosd2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__cosd2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__cosd2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @cos_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @cos_f32_massv
 ; CHECK-PWR9: bl __cosf4_P9
 ; CHECK-PWR8: bl __cosf4_P8
 ; CHECK-NOT: bl __cosf4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__cosf4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__cosf4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; tan
 define <2 x double>  @tan_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @tan_f64_massv
 ; CHECK-PWR9: bl __tand2_P9
 ; CHECK-PWR8: bl __tand2_P8
 ; CHECK-NOT: bl __tand2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__tand2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__tand2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @tan_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @tan_f32_massv
 ; CHECK-PWR9: bl __tanf4_P9
 ; CHECK-PWR8: bl __tanf4_P8
 ; CHECK-NOT: bl __tanf4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__tanf4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__tanf4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; asin
 define <2 x double>  @asin_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @asin_f64_massv
 ; CHECK-PWR9: bl __asind2_P9
 ; CHECK-PWR8: bl __asind2_P8
 ; CHECK-NOT: bl __asind2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__asind2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__asind2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @asin_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @asin_f32_massv
 ; CHECK-PWR9: bl __asinf4_P9
 ; CHECK-PWR8: bl __asinf4_P8
 ; CHECK-NOT: bl __asinf4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__asinf4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__asinf4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; acos
 define <2 x double>  @acos_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @acos_f64_massv
 ; CHECK-PWR9: bl __acosd2_P9
 ; CHECK-PWR8: bl __acosd2_P8
 ; CHECK-NOT: bl __acosd2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__acosd2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__acosd2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @acos_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @acos_f32_massv
 ; CHECK-PWR9: bl __acosf4_P9
 ; CHECK-PWR8: bl __acosf4_P8
 ; CHECK-NOT: bl __acosf4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__acosf4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__acosf4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; atan
 define <2 x double>  @atan_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @atan_f64_massv
 ; CHECK-PWR9: bl __atand2_P9
 ; CHECK-PWR8: bl __atand2_P8
 ; CHECK-NOT: bl __atand2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__atand2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__atand2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @atan_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @atan_f32_massv
 ; CHECK-PWR9: bl __atanf4_P9
 ; CHECK-PWR8: bl __atanf4_P8
 ; CHECK-NOT: bl __atanf4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__atanf4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__atanf4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; atan2
 define <2 x double>  @atan2_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @atan2_f64_massv
 ; CHECK-PWR9: bl __atan2d2_P9
 ; CHECK-PWR8: bl __atan2d2_P8
 ; CHECK-NOT: bl __atan2d2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__atan2d2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__atan2d2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @atan2_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @atan2_f32_massv
 ; CHECK-PWR9: bl __atan2f4_P9
 ; CHECK-PWR8: bl __atan2f4_P8
 ; CHECK-NOT: bl __atan2f4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__atan2f4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__atan2f4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; sinh
 define <2 x double>  @sinh_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @sinh_f64_massv
 ; CHECK-PWR9: bl __sinhd2_P9
 ; CHECK-PWR8: bl __sinhd2_P8
 ; CHECK-NOT: bl __sinhd2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__sinhd2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__sinhd2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @sinh_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @sinh_f32_massv
 ; CHECK-PWR9: bl __sinhf4_P9
 ; CHECK-PWR8: bl __sinhf4_P8
 ; CHECK-NOT: bl __sinhf4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__sinhf4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__sinhf4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; cosh
 define <2 x double>  @cosh_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @cosh_f64_massv
 ; CHECK-PWR9: bl __coshd2_P9
 ; CHECK-PWR8: bl __coshd2_P8
 ; CHECK-NOT: bl __coshd2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__coshd2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__coshd2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @cosh_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @cosh_f32_massv
 ; CHECK-PWR9: bl __coshf4_P9
 ; CHECK-PWR8: bl __coshf4_P8
 ; CHECK-NOT: bl __coshf4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__coshf4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__coshf4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; tanh
 define <2 x double>  @tanh_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @tanh_f64_massv
 ; CHECK-PWR9: bl __tanhd2_P9
 ; CHECK-PWR8: bl __tanhd2_P8
 ; CHECK-NOT: bl __tanhd2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__tanhd2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__tanhd2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @tanh_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @tanh_f32_massv
 ; CHECK-PWR9: bl __tanhf4_P9
 ; CHECK-PWR8: bl __tanhf4_P8
 ; CHECK-NOT: bl __tanhf4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__tanhf4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__tanhf4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; asinh
 define <2 x double>  @asinh_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @asinh_f64_massv
 ; CHECK-PWR9: bl __asinhd2_P9
 ; CHECK-PWR8: bl __asinhd2_P8
 ; CHECK-NOT: bl __asinhd2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__asinhd2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__asinhd2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @asinh_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @asinh_f32_massv
 ; CHECK-PWR9: bl __asinhf4_P9
 ; CHECK-PWR8: bl __asinhf4_P8
 ; CHECK-NOT: bl __asinhf4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__asinhf4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__asinhf4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; acosh
 define <2 x double>  @acosh_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @acosh_f64_massv
 ; CHECK-PWR9: bl __acoshd2_P9
 ; CHECK-PWR8: bl __acoshd2_P8
 ; CHECK-NOT: bl __acoshd2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__acoshd2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__acoshd2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @acosh_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @acosh_f32_massv
 ; CHECK-PWR9: bl __acoshf4_P9
 ; CHECK-PWR8: bl __acoshf4_P8
 ; CHECK-NOT: bl __acoshf4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__acoshf4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__acoshf4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 
 ; atanh
 define <2 x double>  @atanh_f64_massv(<2 x double> %opnd) {
 ; CHECK-ALL-LABEL: @atanh_f64_massv
 ; CHECK-PWR9: bl __atanhd2_P9
 ; CHECK-PWR8: bl __atanhd2_P8
 ; CHECK-NOT: bl __atanhd2_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <2 x double> @__atanhd2_massv(<2 x double> %opnd)
+  %1 = call <2 x double> @__atanhd2_P8(<2 x double> %opnd)
   ret <2 x double> %1 
 }
 
 define <4 x float>  @atanh_f32_massv(<4 x float> %opnd) {
 ; CHECK-ALL-LABEL: @atanh_f32_massv
 ; CHECK-PWR9: bl __atanhf4_P9
 ; CHECK-PWR8: bl __atanhf4_P8
 ; CHECK-NOT: bl __atanhf4_massv
 ; CHECK-ALL: blr
 ;
-  %1 = call <4 x float> @__atanhf4_massv(<4 x float> %opnd)
+  %1 = call <4 x float> @__atanhf4_P8(<4 x float> %opnd)
   ret <4 x float> %1 
 }
 

llvm/test/CodeGen/PowerPC/pow_massv_075_025exp.ll

vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
   %next.gep = getelementptr double, double* %z, i64 %index
   %next.gep31 = getelementptr double, double* %y, i64 %index
   %next.gep32 = getelementptr double, double* %x, i64 %index
   %0 = bitcast double* %next.gep32 to <2 x double>*
   %wide.load = load <2 x double>, <2 x double>* %0, align 8
   %1 = bitcast double* %next.gep31 to <2 x double>*
   %wide.load33 = load <2 x double>, <2 x double>* %1, align 8
-  %2 = call ninf afn nsz <2 x double> @__powd2_massv(<2 x double> %wide.load, <2 x double> %wide.load33)
+  %2 = call ninf afn nsz <2 x double> @__powd2_P8(<2 x double> %wide.load, <2 x double> %wide.load33)
   %3 = bitcast double* %next.gep to <2 x double>*
   store <2 x double> %2, <2 x double>* %3, align 8
   %index.next = add i64 %index, 2
   %4 = icmp eq i64 %index.next, 1024
   br i1 %4, label %for.end, label %vector.body
 
 for.end:
   ret void
entry:
   br label %vector.body
 
 vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
   %next.gep = getelementptr double, double* %y, i64 %index
   %next.gep19 = getelementptr double, double* %x, i64 %index
   %0 = bitcast double* %next.gep19 to <2 x double>*
   %wide.load = load <2 x double>, <2 x double>* %0, align 8
-  %1 = call ninf afn nsz <2 x double> @__powd2_massv(<2 x double> %wide.load, <2 x double> <double 7.600000e-01, double 7.600000e-01>)
+  %1 = call ninf afn nsz <2 x double> @__powd2_P8(<2 x double> %wide.load, <2 x double> <double 7.600000e-01, double 7.600000e-01>)
   %2 = bitcast double* %next.gep to <2 x double>*
   store <2 x double> %1, <2 x double>* %2, align 8
   %index.next = add i64 %index, 2
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
entry:
   br label %vector.body
 
 vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
   %next.gep = getelementptr double, double* %y, i64 %index
   %next.gep19 = getelementptr double, double* %x, i64 %index
   %0 = bitcast double* %next.gep19 to <2 x double>*
   %wide.load = load <2 x double>, <2 x double>* %0, align 8
-  %1 = call ninf afn nsz <2 x double> @__powd2_massv(<2 x double> %wide.load, <2 x double> <double 7.700000e-01, double 7.600000e-01>)
+  %1 = call ninf afn nsz <2 x double> @__powd2_P8(<2 x double> %wide.load, <2 x double> <double 7.700000e-01, double 7.600000e-01>)
   %2 = bitcast double* %next.gep to <2 x double>*
   store <2 x double> %1, <2 x double>* %2, align 8
   %index.next = add i64 %index, 2
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
entry:
   br label %vector.body
 
 vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
   %next.gep = getelementptr double, double* %y, i64 %index
   %next.gep19 = getelementptr double, double* %x, i64 %index
   %0 = bitcast double* %next.gep19 to <2 x double>*
   %wide.load = load <2 x double>, <2 x double>* %0, align 8
-  %1 = call ninf afn nsz <2 x double> @__powd2_massv(<2 x double> %wide.load, <2 x double> <double 7.700000e-01, double 7.500000e-01>)
+  %1 = call ninf afn nsz <2 x double> @__powd2_P8(<2 x double> %wide.load, <2 x double> <double 7.700000e-01, double 7.500000e-01>)
   %2 = bitcast double* %next.gep to <2 x double>*
   store <2 x double> %1, <2 x double>* %2, align 8
   %index.next = add i64 %index, 2
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
entry:
   br label %vector.body
 
 vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
   %next.gep = getelementptr double, double* %y, i64 %index
   %next.gep19 = getelementptr double, double* %x, i64 %index
   %0 = bitcast double* %next.gep19 to <2 x double>*
   %wide.load = load <2 x double>, <2 x double>* %0, align 8
-  %1 = call ninf afn nsz <2 x double> @__powd2_massv(<2 x double> %wide.load, <2 x double> <double 7.700000e-01, double 2.500000e-01>)
+  %1 = call ninf afn nsz <2 x double> @__powd2_P8(<2 x double> %wide.load, <2 x double> <double 7.700000e-01, double 2.500000e-01>)
   %2 = bitcast double* %next.gep to <2 x double>*
   store <2 x double> %1, <2 x double>* %2, align 8
   %index.next = add i64 %index, 2
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
entry:
   br label %vector.body
 
 vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
   %next.gep = getelementptr double, double* %y, i64 %index
   %next.gep19 = getelementptr double, double* %x, i64 %index
   %0 = bitcast double* %next.gep19 to <2 x double>*
   %wide.load = load <2 x double>, <2 x double>* %0, align 8
-  %1 = call ninf afn <2 x double> @__powd2_massv(<2 x double> %wide.load, <2 x double> <double 7.500000e-01, double 7.500000e-01>)
+  %1 = call ninf afn <2 x double> @__powd2_P8(<2 x double> %wide.load, <2 x double> <double 7.500000e-01, double 7.500000e-01>)
   %2 = bitcast double* %next.gep to <2 x double>*
   store <2 x double> %1, <2 x double>* %2, align 8
   %index.next = add i64 %index, 2
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
entry:
   br label %vector.body
 
 vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
   %next.gep = getelementptr double, double* %y, i64 %index
   %next.gep19 = getelementptr double, double* %x, i64 %index
   %0 = bitcast double* %next.gep19 to <2 x double>*
   %wide.load = load <2 x double>, <2 x double>* %0, align 8
-  %1 = call ninf afn nsz <2 x double> @__powd2_massv(<2 x double> %wide.load, <2 x double> <double 2.500000e-01, double 2.500000e-01>)
+  %1 = call ninf afn nsz <2 x double> @__powd2_P8(<2 x double> %wide.load, <2 x double> <double 2.500000e-01, double 2.500000e-01>)
   %2 = bitcast double* %next.gep to <2 x double>*
   store <2 x double> %1, <2 x double>* %2, align 8
   %index.next = add i64 %index, 2
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
entry:
   br label %vector.body
 
 vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
   %next.gep = getelementptr double, double* %y, i64 %index
   %next.gep19 = getelementptr double, double* %x, i64 %index
   %0 = bitcast double* %next.gep19 to <2 x double>*
   %wide.load = load <2 x double>, <2 x double>* %0, align 8
-  %1 = call <2 x double> @__powd2_massv(<2 x double> %wide.load, <2 x double> <double 7.500000e-01, double 7.500000e-01>)
+  %1 = call <2 x double> @__powd2_P8(<2 x double> %wide.load, <2 x double> <double 7.500000e-01, double 7.500000e-01>)
   %2 = bitcast double* %next.gep to <2 x double>*
   store <2 x double> %1, <2 x double>* %2, align 8
   %index.next = add i64 %index, 2
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
entry:
   br label %vector.body
 
 vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
   %next.gep = getelementptr double, double* %y, i64 %index
   %next.gep19 = getelementptr double, double* %x, i64 %index
   %0 = bitcast double* %next.gep19 to <2 x double>*
   %wide.load = load <2 x double>, <2 x double>* %0, align 8
-  %1 = call <2 x double> @__powd2_massv(<2 x double> %wide.load, <2 x double> <double 2.500000e-01, double 2.500000e-01>)
+  %1 = call <2 x double> @__powd2_P8(<2 x double> %wide.load, <2 x double> <double 2.500000e-01, double 2.500000e-01>)
   %2 = bitcast double* %next.gep to <2 x double>*
   store <2 x double> %1, <2 x double>* %2, align 8
   %index.next = add i64 %index, 2
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
 }
 
 ; Function Attrs: nounwind readnone speculatable willreturn
-declare <2 x double> @__powd2_massv(<2 x double>, <2 x double>) #1
+declare <2 x double> @__powd2_P8(<2 x double>, <2 x double>) #1

llvm/test/CodeGen/PowerPC/powf_massv_075_025exp.ll

vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
   %next.gep = getelementptr float, float* %z, i64 %index
   %next.gep31 = getelementptr float, float* %y, i64 %index
   %next.gep32 = getelementptr float, float* %x, i64 %index
   %0 = bitcast float* %next.gep32 to <4 x float>*
   %wide.load = load <4 x float>, <4 x float>* %0, align 4
   %1 = bitcast float* %next.gep31 to <4 x float>*
   %wide.load33 = load <4 x float>, <4 x float>* %1, align 4
-  %2 = call ninf afn nsz <4 x float> @__powf4_massv(<4 x float> %wide.load, <4 x float> %wide.load33)
+  %2 = call ninf afn nsz <4 x float> @__powf4_P8(<4 x float> %wide.load, <4 x float> %wide.load33)
   %3 = bitcast float* %next.gep to <4 x float>*
   store <4 x float> %2, <4 x float>* %3, align 4
   %index.next = add i64 %index, 4
   %4 = icmp eq i64 %index.next, 1024
   br i1 %4, label %for.end, label %vector.body
 
 for.end:
   ret void
entry:
   br label %vector.body
 
 vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
   %next.gep = getelementptr float, float* %y, i64 %index
   %next.gep19 = getelementptr float, float* %x, i64 %index
   %0 = bitcast float* %next.gep19 to <4 x float>*
   %wide.load = load <4 x float>, <4 x float>* %0, align 4
-  %1 = call ninf afn nsz <4 x float> @__powf4_massv(<4 x float> %wide.load, <4 x float> <float 0x3FE851EB80000000, float 0x3FE851EB80000000, float 0x3FE851EB80000000, float 0x3FE851EB80000000>)
+  %1 = call ninf afn nsz <4 x float> @__powf4_P8(<4 x float> %wide.load, <4 x float> <float 0x3FE851EB80000000, float 0x3FE851EB80000000, float 0x3FE851EB80000000, float 0x3FE851EB80000000>)
   %2 = bitcast float* %next.gep to <4 x float>*
   store <4 x float> %1, <4 x float>* %2, align 4
   %index.next = add i64 %index, 4
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
entry:
   br label %vector.body
 
 vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
   %next.gep = getelementptr float, float* %y, i64 %index
   %next.gep19 = getelementptr float, float* %x, i64 %index
   %0 = bitcast float* %next.gep19 to <4 x float>*
   %wide.load = load <4 x float>, <4 x float>* %0, align 4
-  %1 = call ninf afn nsz <4 x float> @__powf4_massv(<4 x float> %wide.load, <4 x float> <float 0x3FE861EB80000000, float 0x3FE871EB80000000, float 0x3FE851EB80000000, float 0x3FE851EB80000000>)
+  %1 = call ninf afn nsz <4 x float> @__powf4_P8(<4 x float> %wide.load, <4 x float> <float 0x3FE861EB80000000, float 0x3FE871EB80000000, float 0x3FE851EB80000000, float 0x3FE851EB80000000>)
   %2 = bitcast float* %next.gep to <4 x float>*
   store <4 x float> %1, <4 x float>* %2, align 4
   %index.next = add i64 %index, 4
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
entry:
   br label %vector.body
 
 vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
   %next.gep = getelementptr float, float* %y, i64 %index
   %next.gep19 = getelementptr float, float* %x, i64 %index
   %0 = bitcast float* %next.gep19 to <4 x float>*
   %wide.load = load <4 x float>, <4 x float>* %0, align 4
-  %1 = call ninf afn nsz <4 x float> @__powf4_massv(<4 x float> %wide.load, <4 x float> <float 7.500000e-01, float 7.500000e-01, float 7.500000e-01, float 0x3FE851EB80000000>)
+  %1 = call ninf afn nsz <4 x float> @__powf4_P8(<4 x float> %wide.load, <4 x float> <float 7.500000e-01, float 7.500000e-01, float 7.500000e-01, float 0x3FE851EB80000000>)
   %2 = bitcast float* %next.gep to <4 x float>*
   store <4 x float> %1, <4 x float>* %2, align 4
   %index.next = add i64 %index, 4
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
entry:
   br label %vector.body
 
 vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
   %next.gep = getelementptr float, float* %y, i64 %index
   %next.gep19 = getelementptr float, float* %x, i64 %index
   %0 = bitcast float* %next.gep19 to <4 x float>*
   %wide.load = load <4 x float>, <4 x float>* %0, align 4
-  %1 = call ninf afn nsz <4 x float> @__powf4_massv(<4 x float> %wide.load, <4 x float> <float 0x3FE851EB80000000, float 2.500000e-01, float 0x3FE851EB80000000, float 2.500000e-01>)
+  %1 = call ninf afn nsz <4 x float> @__powf4_P8(<4 x float> %wide.load, <4 x float> <float 0x3FE851EB80000000, float 2.500000e-01, float 0x3FE851EB80000000, float 2.500000e-01>)
   %2 = bitcast float* %next.gep to <4 x float>*
   store <4 x float> %1, <4 x float>* %2, align 4
   %index.next = add i64 %index, 4
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
entry:
   br label %vector.body
 
 vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
   %next.gep = getelementptr float, float* %y, i64 %index
   %next.gep19 = getelementptr float, float* %x, i64 %index
   %0 = bitcast float* %next.gep19 to <4 x float>*
   %wide.load = load <4 x float>, <4 x float>* %0, align 4
-  %1 = call ninf afn <4 x float> @__powf4_massv(<4 x float> %wide.load, <4 x float> <float 7.500000e-01, float 7.500000e-01, float 7.500000e-01, float 7.500000e-01>)
+  %1 = call ninf afn <4 x float> @__powf4_P8(<4 x float> %wide.load, <4 x float> <float 7.500000e-01, float 7.500000e-01, float 7.500000e-01, float 7.500000e-01>)
   %2 = bitcast float* %next.gep to <4 x float>*
   store <4 x float> %1, <4 x float>* %2, align 4
   %index.next = add i64 %index, 4
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
entry:
   br label %vector.body
 
 vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
   %next.gep = getelementptr float, float* %y, i64 %index
   %next.gep19 = getelementptr float, float* %x, i64 %index
   %0 = bitcast float* %next.gep19 to <4 x float>*
   %wide.load = load <4 x float>, <4 x float>* %0, align 4
-  %1 = call ninf afn nsz <4 x float> @__powf4_massv(<4 x float> %wide.load, <4 x float> <float 2.500000e-01, float 2.500000e-01, float 2.500000e-01, float 2.500000e-01>)
+  %1 = call ninf afn nsz <4 x float> @__powf4_P8(<4 x float> %wide.load, <4 x float> <float 2.500000e-01, float 2.500000e-01, float 2.500000e-01, float 2.500000e-01>)
   %2 = bitcast float* %next.gep to <4 x float>*
   store <4 x float> %1, <4 x float>* %2, align 4
   %index.next = add i64 %index, 4
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
entry:
   br label %vector.body
 
 vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
   %next.gep = getelementptr float, float* %y, i64 %index
   %next.gep19 = getelementptr float, float* %x, i64 %index
   %0 = bitcast float* %next.gep19 to <4 x float>*
   %wide.load = load <4 x float>, <4 x float>* %0, align 4
-  %1 = call <4 x float> @__powf4_massv(<4 x float> %wide.load, <4 x float> <float 7.500000e-01, float 7.500000e-01, float 7.500000e-01, float 7.500000e-01>)
+  %1 = call <4 x float> @__powf4_P8(<4 x float> %wide.load, <4 x float> <float 7.500000e-01, float 7.500000e-01, float 7.500000e-01, float 7.500000e-01>)
   %2 = bitcast float* %next.gep to <4 x float>*
   store <4 x float> %1, <4 x float>* %2, align 4
   %index.next = add i64 %index, 4
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
entry:
   br label %vector.body
 
 vector.body:
   %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
   %next.gep = getelementptr float, float* %y, i64 %index
   %next.gep19 = getelementptr float, float* %x, i64 %index
   %0 = bitcast float* %next.gep19 to <4 x float>*
   %wide.load = load <4 x float>, <4 x float>* %0, align 4
-  %1 = call <4 x float> @__powf4_massv(<4 x float> %wide.load, <4 x float> <float 2.500000e-01, float 2.500000e-01, float 2.500000e-01, float 2.500000e-01>)
+  %1 = call <4 x float> @__powf4_P8(<4 x float> %wide.load, <4 x float> <float 2.500000e-01, float 2.500000e-01, float 2.500000e-01, float 2.500000e-01>)
   %2 = bitcast float* %next.gep to <4 x float>*
   store <4 x float> %1, <4 x float>* %2, align 4
   %index.next = add i64 %index, 4
   %3 = icmp eq i64 %index.next, 1024
   br i1 %3, label %for.end, label %vector.body
 
 for.end:
   ret void
 }
 
 ; Function Attrs: nounwind readnone speculatable willreturn
-declare <4 x float> @__powf4_massv(<4 x float>, <4 x float>)
+declare <4 x float> @__powf4_P8(<4 x float>, <4 x float>)

llvm/test/Transforms/LoopVectorize/PowerPC/massv-altivec.ll

 ; RUN: opt -vector-library=MASSV -inject-tli-mappings -loop-vectorize -force-vector-interleave=1 -mattr=-altivec -S < %s | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-n32:64" 
 target triple = "powerpc64le-unknown-linux-gnu"
 
 declare double @cbrt(double) #0
 declare float @cbrtf(float) #0
 
 declare double @atanh(double) #0
 declare float @atanhf(float) #0
 
 ; MASSV is unsupported for AltiVec.
 ; Check that massv entries are not generated.
 define void @cbrt_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @cbrt_f64(
-; CHECK-NOT: __cbrtd2_massv{{.*}}<2 x double>
+; CHECK-NOT: __cbrtd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @cbrt(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @cbrt_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @cbrt_f32(
-; CHECK-NOT: __cbrtf4_massv{{.*}}<4 x float>
+; CHECK-NOT: __cbrtf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @cbrtf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @atanh_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @atanh_f64(
-; CHECK-NOT: __atanhd2_massv{{.*}}<2 x double>
+; CHECK-NOT: __atanhd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @atanh(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @atanh_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @atanh_f32(
-; CHECK-NOT: __atanhf4_massv{{.*}}<2 x double>
+; CHECK-NOT: __atanhf4_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32

llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll

 declare double @acosh(double) #0
 declare float @acoshf(float) #0
 
 declare double @atanh(double) #0
 declare float @atanhf(float) #0
 
 define void @cbrt_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @cbrt_f64(
-; CHECK: __cbrtd2_massv{{.*}}<2 x double>
+; CHECK: __cbrtd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @cbrt(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @cbrt_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @cbrt_f32(
-; CHECK: __cbrtf4_massv{{.*}}<4 x float>
+; CHECK: __cbrtf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @cbrtf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @pow_f64(double* nocapture %varray, double* nocapture readonly %exp) {
 ; CHECK-LABEL: @pow_f64(
-; CHECK:  __powd2_massv{{.*}}<2 x double>
+; CHECK:  __powd2_P8{{.*}}<2 x double>
 ; CHECK:  ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %arrayidx = getelementptr inbounds double, double* %exp, i64 %iv
   %tmp1 = load double, double* %arrayidx, align 4
   %tmp2 = tail call double @pow(double %conv, double %tmp1)
   %arrayidx2 = getelementptr inbounds double, double* %varray, i64 %iv
   store double %tmp2, double* %arrayidx2, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @pow_f64_intrinsic(double* nocapture %varray, double* nocapture readonly %exp) {
 ; CHECK-LABEL: @pow_f64_intrinsic(
-; CHECK: __powd2_massv{{.*}}<2 x double>
+; CHECK: __powd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %arrayidx = getelementptr inbounds double, double* %exp, i64 %iv
   %tmp1 = load double, double* %arrayidx, align 4
   %tmp2 = tail call double @llvm.pow.f64(double %conv, double %tmp1)
   %arrayidx2 = getelementptr inbounds double, double* %varray, i64 %iv
   store double %tmp2, double* %arrayidx2, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @pow_f32(float* nocapture %varray, float* nocapture readonly %exp) {
 ; CHECK-LABEL: @pow_f32(
-; CHECK: __powf4_massv{{.*}}<4 x float>
+; CHECK: __powf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %arrayidx = getelementptr inbounds float, float* %exp, i64 %iv
   %tmp1 = load float, float* %arrayidx, align 4
   %tmp2 = tail call float @powf(float %conv, float %tmp1)
   %arrayidx2 = getelementptr inbounds float, float* %varray, i64 %iv
   store float %tmp2, float* %arrayidx2, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @pow_f32_intrinsic(float* nocapture %varray, float* nocapture readonly %exp) {
 ; CHECK-LABEL: @pow_f32_intrinsic(
-; CHECK: __powf4_massv{{.*}}<4 x float>
+; CHECK: __powf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %arrayidx = getelementptr inbounds float, float* %exp, i64 %iv
   %tmp1 = load float, float* %arrayidx, align 4
   %tmp2 = tail call float @llvm.pow.f32(float %conv, float %tmp1)
   %arrayidx2 = getelementptr inbounds float, float* %varray, i64 %iv
   store float %tmp2, float* %arrayidx2, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @sqrt_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @sqrt_f64(
-; CHECK-NOT: __sqrtd2_massv{{.*}}<2 x double>
+; CHECK-NOT: __sqrtd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @sqrt(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @sqrt_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @sqrt_f32(
-; CHECK-NOT: __sqrtf4_massv{{.*}}<4 x float>
+; CHECK-NOT: __sqrtf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @sqrtf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @exp_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @exp_f64(
-; CHECK: __expd2_massv{{.*}}<2 x double>
+; CHECK: __expd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @exp(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @exp_f64_intrinsic(double* nocapture %varray) {
 ; CHECK-LABEL: @exp_f64_intrinsic(
-; CHECK: __expd2_massv{{.*}}<2 x double>
+; CHECK: __expd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @llvm.exp.f64(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @exp_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @exp_f32(
-; CHECK: __expf4_massv{{.*}}<4 x float>
+; CHECK: __expf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @expf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @exp_f32_intrinsic(float* nocapture %varray) {
 ; CHECK-LABEL: @exp_f32_intrinsic(
-; CHECK: __expf4_massv{{.*}}<4 x float>
+; CHECK: __expf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @llvm.exp.f32(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @exp2_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @exp2_f64(
-; CHECK: __exp2d2_massv{{.*}}<2 x double>
+; CHECK: __exp2d2_P8{{.*}}<2 x double>
 ; CHECK:  ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @exp2(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @exp2_f64_intrinsic(double* nocapture %varray) {
 ; CHECK-LABEL: @exp2_f64_intrinsic(
-; CHECK: __exp2d2_massv{{.*}}<2 x double>
+; CHECK: __exp2d2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @llvm.exp2.f64(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @exp2_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @exp2_f32(
-; CHECK: __exp2f4_massv{{.*}}<4 x float>
+; CHECK: __exp2f4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @exp2f(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @exp2_f32_intrinsic(float* nocapture %varray) {
 ; CHECK-LABEL: @exp2_f32_intrinsic(
-; CHECK: __exp2f4_massv{{.*}}<4 x float>
+; CHECK: __exp2f4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @llvm.exp2.f32(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @expm1_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @expm1_f64(
-; CHECK: __expm1d2_massv{{.*}}<2 x double>
+; CHECK: __expm1d2_P8{{.*}}<2 x double>
 ; CHECK:  ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @expm1(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @expm1_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @expm1_f32(
-; CHECK: __expm1f4_massv{{.*}}<4 x float>
+; CHECK: __expm1f4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @expm1f(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @log_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @log_f64(
-; CHECK: __logd2_massv{{.*}}<2 x double>
+; CHECK: __logd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @log(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @log_f64_intrinsic(double* nocapture %varray) {
 ; CHECK-LABEL: @log_f64_intrinsic(
-; CHECK: __logd2_massv{{.*}}<2 x double>
+; CHECK: __logd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @llvm.log.f64(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @log_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @log_f32(
-; CHECK: __logf4_massv{{.*}}<4 x float>
+; CHECK: __logf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @logf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @log_f32_intrinsic(float* nocapture %varray) {
 ; CHECK-LABEL: @log_f32_intrinsic(
-; CHECK: __logf4_massv{{.*}}<4 x float>
+; CHECK: __logf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @llvm.log.f32(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @log1p_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @log1p_f64(
-; CHECK: __log1pd2_massv{{.*}}<2 x double>
+; CHECK: __log1pd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @log1p(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @log1p_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @log1p_f32(
-; CHECK: __log1pf4_massv{{.*}}<4 x float>
+; CHECK: __log1pf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @log1pf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @log10_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @log10_f64(
-; CHECK: __log10d2_massv(<2 x double>
+; CHECK: __log10d2_P8(<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @log10(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @log10_f64_intrinsic(double* nocapture %varray) {
 ; CHECK-LABEL: @log10_f64_intrinsic(
-; CHECK: __log10d2_massv{{.*}}<2 x double>
+; CHECK: __log10d2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @llvm.log10.f64(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @log10_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @log10_f32(
-; CHECK: __log10f4_massv{{.*}}<4 x float>
+; CHECK: __log10f4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @log10f(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @log10_f32_intrinsic(float* nocapture %varray) {
 ; CHECK-LABEL: @log10_f32_intrinsic(
-; CHECK: __log10f4_massv{{.*}}<4 x float>
+; CHECK: __log10f4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @llvm.log10.f32(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @log2_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @log2_f64(
-; CHECK: __log2d2_massv(<2 x double>
+; CHECK: __log2d2_P8(<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @log2(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @log2_f64_intrinsic(double* nocapture %varray) {
 ; CHECK-LABEL: @log2_f64_intrinsic(
-; CHECK: __log2d2_massv{{.*}}<2 x double>
+; CHECK: __log2d2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @llvm.log2.f64(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @log2_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @log2_f32(
-; CHECK: __log2f4_massv{{.*}}<4 x float>
+; CHECK: __log2f4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @log2f(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @log2_f32_intrinsic(float* nocapture %varray) {
 ; CHECK-LABEL: @log2_f32_intrinsic(
-; CHECK: __log2f4_massv{{.*}}<4 x float>
+; CHECK: __log2f4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @llvm.log2.f32(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @sin_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @sin_f64(
-; CHECK: __sind2_massv{{.*}}<2 x double>
+; CHECK: __sind2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @sin(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @sin_f64_intrinsic(double* nocapture %varray) {
 ; CHECK-LABEL: @sin_f64_intrinsic(
-; CHECK: __sind2_massv{{.*}}<2 x double>
+; CHECK: __sind2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @llvm.sin.f64(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @sin_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @sin_f32(
-; CHECK: __sinf4_massv{{.*}}<4 x float>
+; CHECK: __sinf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @sinf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @sin_f32_intrinsic(float* nocapture %varray) {
 ; CHECK-LABEL: @sin_f32_intrinsic(
-; CHECK: __sinf4_massv{{.*}}<4 x float>
+; CHECK: __sinf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @llvm.sin.f32(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @cos_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @cos_f64(
-; CHECK: __cosd2_massv{{.*}}<2 x double>
+; CHECK: __cosd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @cos(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @cos_f64_intrinsic(double* nocapture %varray) {
 ; CHECK-LABEL: @cos_f64_intrinsic(
-; CHECK:    [[TMP5:%.*]] = call <2 x double> @__cosd2_massv(<2 x double> [[TMP4:%.*]])
+; CHECK:    [[TMP5:%.*]] = call <2 x double> @__cosd2_P8(<2 x double> [[TMP4:%.*]])
 ; CHECK:    ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @llvm.cos.f64(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @cos_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @cos_f32(
-; CHECK: __cosf4_massv{{.*}}<4 x float>
+; CHECK: __cosf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @cosf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @cos_f32_intrinsic(float* nocapture %varray) {
 ; CHECK-LABEL: @cos_f32_intrinsic(
-; CHECK: __cosf4_massv{{.*}}<4 x float>
+; CHECK: __cosf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @llvm.cos.f32(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @tan_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @tan_f64(
-; CHECK: __tand2_massv{{.*}}<2 x double>
+; CHECK: __tand2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @tan(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @tan_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @tan_f32(
-; CHECK: __tanf4_massv{{.*}}<4 x float>
+; CHECK: __tanf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @tanf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @asin_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @asin_f64(
-; CHECK: __asind2_massv{{.*}}<2 x double>
+; CHECK: __asind2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @asin(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @asin_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @asin_f32(
-; CHECK: __asinf4_massv{{.*}}<4 x float>
+; CHECK: __asinf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @asinf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @acos_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @acos_f64(
-; CHECK: __acosd2_massv{{.*}}<2 x double>
+; CHECK: __acosd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @acos(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @acos_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @acos_f32(
-; CHECK: __acosf4_massv{{.*}}<4 x float>
+; CHECK: __acosf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @acosf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @atan_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @atan_f64(
-; CHECK: __atand2_massv{{.*}}<2 x double>
+; CHECK: __atand2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @atan(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @atan_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @atan_f32(
-; CHECK: __atanf4_massv{{.*}}<4 x float>
+; CHECK: __atanf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @atanf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @atan2_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @atan2_f64(
-; CHECK: __atan2d2_massv{{.*}}<2 x double>
+; CHECK: __atan2d2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @atan2(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @atan2_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @atan2_f32(
-; CHECK: __atan2f4_massv{{.*}}<4 x float>
+; CHECK: __atan2f4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @atan2f(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @sinh_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @sinh_f64(
-; CHECK: __sinhd2_massv{{.*}}<2 x double>
+; CHECK: __sinhd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @sinh(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @sinh_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @sinh_f32(
-; CHECK: __sinhf4_massv{{.*}}<4 x float>
+; CHECK: __sinhf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @sinhf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @cosh_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @cosh_f64(
-; CHECK: __coshd2_massv{{.*}}<2 x double>
+; CHECK: __coshd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @cosh(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @cosh_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @cosh_f32(
-; CHECK: __coshf4_massv{{.*}}<4 x float>
+; CHECK: __coshf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @coshf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @tanh_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @tanh_f64(
-; CHECK: __tanhd2_massv{{.*}}<2 x double>
+; CHECK: __tanhd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @tanh(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @tanh_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @tanh_f32(
-; CHECK: __tanhf4_massv{{.*}}<4 x float>
+; CHECK: __tanhf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @tanhf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @asinh_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @asinh_f64(
-; CHECK: __asinhd2_massv{{.*}}<2 x double>
+; CHECK: __asinhd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @asinh(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @asinh_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @asinh_f32(
-; CHECK: __asinhf4_massv{{.*}}<4 x float>
+; CHECK: __asinhf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @asinhf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @acosh_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @acosh_f64(
-; CHECK: __acoshd2_massv{{.*}}<2 x double>
+; CHECK: __acoshd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @acosh(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @acosh_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @acosh_f32(
-; CHECK: __acoshf4_massv{{.*}}<4 x float>
+; CHECK: __acoshf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to float
   %call = tail call float @acoshf(float %conv)
   %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
   store float %call, float* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @atanh_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @atanh_f64(
-; CHECK: __atanhd2_massv{{.*}}<2 x double>
+; CHECK: __atanhd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @atanh(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @atanh_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @atanh_f32(
-; CHECK: __atanhf4_massv{{.*}}<4 x float>
+; CHECK: __atanhf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32

llvm/test/Transforms/LoopVectorize/PowerPC/massv-nobuiltin.ll

 ; RUN: opt -vector-library=MASSV -inject-tli-mappings -loop-vectorize -force-vector-interleave=1 -S < %s | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-n32:64" 
 target triple = "powerpc64le-unknown-linux-gnu"
 
 declare double @atanh(double) #1
 declare float @atanhf(float) #1
 
 ; Check that functions marked as nobuiltin are not lowered to massv entries.
 define void @atanh_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @atanh_f64(
-; CHECK-NOT: __atanhd2_massv{{.*}}<2 x double>
+; CHECK-NOT: __atanhd2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @atanh(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 define void @atanh_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @atanh_f32(
-; CHECK-NOT: __atanhf4_massv{{.*}}<2 x double>
+; CHECK-NOT: __atanhf4_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32

llvm/test/Transforms/LoopVectorize/PowerPC/massv-unsupported.ll

 ; RUN: opt -vector-library=MASSV -inject-tli-mappings -loop-vectorize -force-vector-interleave=1 -S < %s | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-n32:64" 
 target triple = "powerpc64le-unknown-linux-gnu"
 
 declare double @ceil(double) #0
 declare float @fabsf(float) #0
 
 declare double @llvm.sqrt.f64(double) #0
 declare float @llvm.sqrt.f32(float) #0
 
 ; Vector counterpart of ceil is unsupported in MASSV library.
 define void @ceil_f64(double* nocapture %varray) {
 ; CHECK-LABEL: @ceil_f64(
 ; CHECK-NOT: __ceild2_massv{{.*}}<2 x double>
+; CHECK-NOT: __ceild2_P8{{.*}}<2 x double>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32
   %conv = sitofp i32 %tmp to double
   %call = tail call double @ceil(double %conv)
   %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
   store double %call, double* %arrayidx, align 4
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 1000
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 ; Vector counterpart of fabs is unsupported in MASSV library.
 define void @fabs_f32(float* nocapture %varray) {
 ; CHECK-LABEL: @fabs_f32(
 ; CHECK-NOT: __fabsf4_massv{{.*}}<4 x float>
+; CHECK-NOT: __fabsf4_P8{{.*}}<4 x float>
 ; CHECK: ret void
 ;
 entry:
   br label %for.body
 
 for.body:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
   %tmp = trunc i64 %iv to i32

llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll

 ; CHECK:       vector.body:
 ; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
 ; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi <2 x double> [ zeroinitializer, [[ENTRY]] ], [ [[TMP5:%.*]], [[VECTOR_BODY]] ]
 ; CHECK-NEXT:    [[TMP0:%.*]] = zext i32 [[INDEX]] to i64
 ; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds float, float* [[ARR:%.*]], i64 [[TMP0]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = bitcast float* [[TMP1]] to <2 x float>*
 ; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <2 x float>, <2 x float>* [[TMP2]], align 4
 ; CHECK-NEXT:    [[TMP3:%.*]] = fpext <2 x float> [[WIDE_LOAD]] to <2 x double>
-; CHECK-NEXT:    [[TMP4:%.*]] = call fast <2 x double> @__sind2_massv(<2 x double> [[TMP3]])
+; CHECK-NEXT:    [[TMP4:%.*]] = call fast <2 x double> @__sind2_P8(<2 x double> [[TMP3]])
 ; CHECK-NEXT:    [[TMP5]] = fadd fast <2 x double> [[TMP4]], [[VEC_PHI]]
 ; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 2
 ; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
 ; CHECK-NEXT:    br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP0:!llvm.loop !.*]]
 ; CHECK:       middle.block:
 ; CHECK-NEXT:    [[DOTLCSSA:%.*]] = phi <2 x double> [ [[TMP5]], [[VECTOR_BODY]] ]
 ; CHECK-NEXT:    [[TMP7:%.*]] = call fast double @llvm.vector.reduce.fadd.v2f64(double -0.000000e+00, <2 x double> [[DOTLCSSA]])
 ; CHECK-NEXT:    ret double [[TMP7]]

llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-vfabi-attr.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -vectorizer-maximize-bandwidth -mtriple=powerpc64le-- -S \
 ; RUN:   -targetlibinfo -loop-simplify -loop-rotate -loop-vectorize \
 ; RUN:   -instcombine -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -force-vector-interleave=1 < %s | FileCheck %s
 define dso_local double @test(float* %Arr) {
 ; CHECK-LABEL: @test(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
 ; CHECK:       vector.body:
 ; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
 ; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi <2 x double> [ zeroinitializer, [[ENTRY]] ], [ [[TMP5:%.*]], [[VECTOR_BODY]] ]
 ; CHECK-NEXT:    [[TMP0:%.*]] = sext i32 [[INDEX]] to i64
 ; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds float, float* [[ARR:%.*]], i64 [[TMP0]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = bitcast float* [[TMP1]] to <2 x float>*
 ; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <2 x float>, <2 x float>* [[TMP2]], align 4
 ; CHECK-NEXT:    [[TMP3:%.*]] = fpext <2 x float> [[WIDE_LOAD]] to <2 x double>
-; CHECK-NEXT:    [[TMP4:%.*]] = call fast <2 x double> @__sind2_massv(<2 x double> [[TMP3]])
+; CHECK-NEXT:    [[TMP4:%.*]] = call fast <2 x double> @__sind2_P8(<2 x double> [[TMP3]])
 ; CHECK-NEXT:    [[TMP5]] = fadd fast <2 x double> [[VEC_PHI]], [[TMP4]]
 ; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 2
 ; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
 ; CHECK-NEXT:    br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP0:!llvm.loop !.*]]
 ; CHECK:       middle.block:
 ; CHECK-NEXT:    [[TMP7:%.*]] = call fast double @llvm.vector.reduce.fadd.v2f64(double -0.000000e+00, <2 x double> [[TMP5]])
 ; CHECK-NEXT:    ret double [[TMP7]]
 ;
for.inc:
   %inc = add nsw i32 %i.0, 1
   br label %for.cond
 
 for.end:
   ret double %Sum.0
 }
 
 declare double @llvm.sin.f64(double) #0
-declare <2 x double> @__sind2_massv(<2 x double>) #0
+declare <2 x double> @__sind2_P8(<2 x double>) #0
 attributes #0 = { nounwind readnone speculatable willreturn }
-attributes #1 = { "vector-function-abi-variant"="_ZGV_LLVM_N2v_llvm.sin.f64(__sind2_massv)" }
+attributes #1 = { "vector-function-abi-variant"="_ZGV_LLVM_N2v_llvm.sin.f64(__sind2_P8)" }

llvm/test/Transforms/Util/add-TLI-mappings.ll

 ; SVML-SAME:        [6 x i8*] [
 ; SVML-SAME:          i8* bitcast (<2 x double> (<2 x double>)* @__svml_sin2 to i8*),
 ; SVML-SAME:          i8* bitcast (<4 x double> (<4 x double>)* @__svml_sin4 to i8*),
 ; SVML-SAME:          i8* bitcast (<8 x double> (<8 x double>)* @__svml_sin8 to i8*),
 ; SVML-SAME:          i8* bitcast (<4 x float> (<4 x float>)* @__svml_log10f4 to i8*),
 ; SVML-SAME:          i8* bitcast (<8 x float> (<8 x float>)* @__svml_log10f8 to i8*),
 ; SVML-SAME:          i8* bitcast (<16 x float> (<16 x float>)* @__svml_log10f16 to i8*)
 ; MASSV-SAME:       [2 x i8*] [
-; MASSV-SAME:         i8* bitcast (<2 x double> (<2 x double>)* @__sind2_massv to i8*),
-; MASSV-SAME:         i8* bitcast (<4 x float> (<4 x float>)* @__log10f4_massv to i8*)
+; MASSV-SAME:         i8* bitcast (<2 x double> (<2 x double>)* @__sind2_P8 to i8*),
+; MASSV-SAME:         i8* bitcast (<4 x float> (<4 x float>)* @__log10f4_P8 to i8*)
 ; ACCELERATE-SAME:  [1 x i8*] [
 ; ACCELERATE-SAME:    i8* bitcast (<4 x float> (<4 x float>)* @vlog10f to i8*)
 ; LIBMVEC-X86-SAME: [2 x i8*] [
 ; LIBMVEC-X86-SAME:   i8* bitcast (<2 x double> (<2 x double>)* @_ZGVbN2v_sin to i8*),
 ; LIBMVEC-X86-SAME:   i8* bitcast (<4 x double> (<4 x double>)* @_ZGVdN4v_sin to i8*)
 ; COMMON-SAME:      ], section "llvm.metadata"
 
 define double @sin_f64(double %in) {

 attributes #0 = { nounwind readnone }
 
 ; SVML:      attributes #[[SIN]] = { "vector-function-abi-variant"=
 ; SVML-SAME:   "_ZGV_LLVM_N2v_sin(__svml_sin2),
 ; SVML-SAME:   _ZGV_LLVM_N4v_sin(__svml_sin4),
 ; SVML-SAME:   _ZGV_LLVM_N8v_sin(__svml_sin8)" }
 
 ; MASSV:      attributes #[[SIN]] = { "vector-function-abi-variant"=
-; MASSV-SAME:   "_ZGV_LLVM_N2v_sin(__sind2_massv)" }
+; MASSV-SAME:   "_ZGV_LLVM_N2v_sin(__sind2_P8)" }
 ; MASSV:      attributes #[[LOG10]] = { "vector-function-abi-variant"=
-; MASSV-SAME:   "_ZGV_LLVM_N4v_llvm.log10.f32(__log10f4_massv)" }
+; MASSV-SAME:   "_ZGV_LLVM_N4v_llvm.log10.f32(__log10f4_P8)" }
 
 ; ACCELERATE:      attributes #[[LOG10]] = { "vector-function-abi-variant"=
 ; ACCELERATE-SAME:   "_ZGV_LLVM_N4v_llvm.log10.f32(vlog10f)" }
 
 ; LIBMVEC-X86:      attributes #[[SIN]] = { "vector-function-abi-variant"=
 ; LIBMVEC-X86-SAME:   "_ZGV_LLVM_N2v_sin(_ZGVbN2v_sin),
 ; LIBMVEC-X86-SAME:   _ZGV_LLVM_N4v_sin(_ZGVdN4v_sin)" }