[AArch64] Add patterns for add(udot(0, x, y), z) -> udot(z, x, y).

[dmgreen]

Summary

Given a zero input for a udot, an add can be folded in to take the place of the input.

[SjoerdMeijer]

llvm/lib/Target/AArch64/AArch64InstrFormats.td

5626 ↗

(On Diff #325419)

As you know I don't mind nice and concise little patterns, but was wondering if we don't expect this simplification to happen earlier?

[fhahn]

llvm/lib/Target/AArch64/AArch64InstrFormats.td

5626 ↗

(On Diff #325419)

Not sure what the exact policy is, but InstCombinerImpl::visitCallInst( does optimize some target specific intrinsics. But I think this would be good to have for instruction selection in any case

[dmgreen]

llvm/lib/Target/AArch64/AArch64InstrFormats.td

5626 ↗

(On Diff #325419)

Oh, you mean pre-ISel? We lower a vecreduce.add(v16i8 x) to a vecreduce(udot(zero, one, x)), so this needs to be done sometime during ISel lowering at least. I'll add some tests for it.

I can make it into a DAG combine. That should capture more cases without extra patterns, and should be simple enough I think.

[dmgreen]

Convert to a DAGCombine, with some vecreduce tests.

[fhahn]

LGTM, thanks

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

static SDValue performUADDVCombine(SDNode *N, SelectionDAG &DAG) {
   EVT ValVT = Val1->getValueType(0);
   SDLoc DL(N);
   SDValue AddVal = DAG.getNode(ISD::ADD, DL, ValVT, Val1, Val2);
   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
                      DAG.getNode(AArch64ISD::UADDV, DL, ValVT, AddVal),
                      DAG.getConstant(0, DL, MVT::i64));
 }
 
+// ADD(UDOT(zero, x, y), A) -->  UDOT(A, x, y)
+static SDValue performAddDotCombine(SDNode *N, SelectionDAG &DAG) {
+  EVT VT = N->getValueType(0);
+  if (N->getOpcode() != ISD::ADD)
+    return SDValue();
+
+  SDValue Dot = N->getOperand(0);
+  SDValue A = N->getOperand(1);
+  // Handle commutivity
+  auto isZeroDot = [](SDValue Dot) {
+    return (Dot.getOpcode() == AArch64ISD::UDOT ||
+            Dot.getOpcode() == AArch64ISD::SDOT) &&
+           ISD::isBuildVectorAllZeros(Dot.getOperand(0).getNode());
+  };
+  if (!isZeroDot(Dot))
+    std::swap(Dot, A);
+  if (!isZeroDot(Dot))
+    return SDValue();
+
+  return DAG.getNode(Dot.getOpcode(), SDLoc(N), VT, A, Dot.getOperand(1),
+                     Dot.getOperand(2));
+}
+
 // The basic add/sub long vector instructions have variants with "2" on the end
 // which act on the high-half of their inputs. They are normally matched by
 // patterns like:
 //
 // (add (zeroext (extract_high LHS)),
 //      (zeroext (extract_high RHS)))
 // -> uaddl2 vD, vN, vM
 //

 }
 
 static SDValue performAddSubCombine(SDNode *N,
                                     TargetLowering::DAGCombinerInfo &DCI,
                                     SelectionDAG &DAG) {
   // Try to change sum of two reductions.
   if (SDValue Val = performUADDVCombine(N, DAG))
     return Val;
+  if (SDValue Val = performAddDotCombine(N, DAG))
+    return Val;
 
   return performAddSubLongCombine(N, DCI, DAG);
 }
 
 // Massage DAGs which we can use the high-half "long" operations on into
 // something isel will recognize better. E.g.
 //
 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->

llvm/test/CodeGen/AArch64/neon-dot-product.ll

entry:
   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #2
   ret <4 x i32> %vdot1.i
 }
 
 
 define <2 x i32> @test_vdot_u32_zero(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #0 {
 ; CHECK-LABEL: test_vdot_u32_zero:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    movi v3.2d, #0000000000000000
-; CHECK-NEXT:    udot v3.2s, v1.8b, v2.8b
-; CHECK-NEXT:    add v0.2s, v3.2s, v0.2s
+; CHECK-NEXT:    udot v0.2s, v1.8b, v2.8b
 ; CHECK-NEXT:    ret
 entry:
   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> zeroinitializer, <8 x i8> %b, <8 x i8> %c) #2
   %ret = add <2 x i32> %vdot1.i, %a
   ret <2 x i32> %ret
 }
 
 define <4 x i32> @test_vdotq_u32_zero(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #0 {
 ; CHECK-LABEL: test_vdotq_u32_zero:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    movi v3.2d, #0000000000000000
-; CHECK-NEXT:    udot v3.4s, v1.16b, v2.16b
-; CHECK-NEXT:    add v0.4s, v3.4s, v0.4s
+; CHECK-NEXT:    udot v0.4s, v1.16b, v2.16b
 ; CHECK-NEXT:    ret
 entry:
   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> zeroinitializer, <16 x i8> %b, <16 x i8> %c) #2
   %ret = add <4 x i32> %vdot1.i, %a
   ret <4 x i32> %ret
 }
 
 define <2 x i32> @test_vdot_s32_zero(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #0 {
 ; CHECK-LABEL: test_vdot_s32_zero:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    movi v3.2d, #0000000000000000
-; CHECK-NEXT:    sdot v3.2s, v1.8b, v2.8b
-; CHECK-NEXT:    add v0.2s, v3.2s, v0.2s
+; CHECK-NEXT:    sdot v0.2s, v1.8b, v2.8b
 ; CHECK-NEXT:    ret
 entry:
   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> zeroinitializer, <8 x i8> %b, <8 x i8> %c) #2
   %ret = add <2 x i32> %vdot1.i, %a
   ret <2 x i32> %ret
 }
 
 define <4 x i32> @test_vdotq_s32_zero(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #0 {
 ; CHECK-LABEL: test_vdotq_s32_zero:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    movi v3.2d, #0000000000000000
-; CHECK-NEXT:    sdot v3.4s, v1.16b, v2.16b
-; CHECK-NEXT:    add v0.4s, v3.4s, v0.4s
+; CHECK-NEXT:    sdot v0.4s, v1.16b, v2.16b
 ; CHECK-NEXT:    ret
 entry:
   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> zeroinitializer, <16 x i8> %b, <16 x i8> %c) #2
   %ret = add <4 x i32> %vdot1.i, %a
   ret <4 x i32> %ret
 }
 
 
entry:
   %shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
   ret <4 x i32> %vdot1.i
 }
 
 
 define <2 x i32> @test_vdot_lane_u32_zero(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) {
+; CHECK-LABEL: test_vdot_lane_u32_zero:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT:    udot v0.2s, v1.8b, v2.4b[1]
+; CHECK-NEXT:    ret
 entry:
   %.cast = bitcast <8 x i8> %c to <2 x i32>
   %shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
   %.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> zeroinitializer, <8 x i8> %b, <8 x i8> %.cast5) #2
   %ret = add <2 x i32> %vdot1.i, %a
   ret <2 x i32> %ret
 }
 
 define <4 x i32> @test_vdotq_lane_u32_zero(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) {
+; CHECK-LABEL: test_vdotq_lane_u32_zero:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT:    udot v0.4s, v1.16b, v2.4b[1]
+; CHECK-NEXT:    ret
 entry:
   %.cast = bitcast <8 x i8> %c to <2 x i32>
   %shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> zeroinitializer, <16 x i8> %b, <16 x i8> %.cast3) #2
   %ret = add <4 x i32> %vdot1.i, %a
   ret <4 x i32> %ret
 }
 
 define <2 x i32> @test_vdot_laneq_u32_zero(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c) {
 ; CHECK-LABEL: test_vdot_laneq_u32_zero:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    movi v3.2d, #0000000000000000
-; CHECK-NEXT:    udot v3.2s, v1.8b, v2.4b[1]
-; CHECK-NEXT:    add v0.2s, v3.2s, v0.2s
+; CHECK-NEXT:    udot v0.2s, v1.8b, v2.4b[1]
 ; CHECK-NEXT:    ret
 entry:
   %.cast = bitcast <16 x i8> %c to <4 x i32>
   %shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
   %.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> zeroinitializer, <8 x i8> %b, <8 x i8> %.cast5) #2
   %ret = add <2 x i32> %vdot1.i, %a
   ret <2 x i32> %ret
 }
 
 define <4 x i32> @test_vdotq_laneq_u32_zero(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) {
 ; CHECK-LABEL: test_vdotq_laneq_u32_zero:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    movi v3.2d, #0000000000000000
-; CHECK-NEXT:    udot v3.4s, v1.16b, v2.4b[1]
-; CHECK-NEXT:    add v0.4s, v3.4s, v0.4s
+; CHECK-NEXT:    udot v0.4s, v1.16b, v2.4b[1]
 ; CHECK-NEXT:    ret
 entry:
   %.cast = bitcast <16 x i8> %c to <4 x i32>
   %shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> zeroinitializer, <16 x i8> %b, <16 x i8> %.cast3) #2
   %ret = add <4 x i32> %vdot1.i, %a
   ret <4 x i32> %ret
entry:
   %shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
   ret <4 x i32> %vdot1.i
 }
 
 
 define <2 x i32> @test_vdot_lane_s32_zero(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) {
+; CHECK-LABEL: test_vdot_lane_s32_zero:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT:    sdot v0.2s, v1.8b, v2.4b[1]
+; CHECK-NEXT:    ret
 entry:
   %.cast = bitcast <8 x i8> %c to <2 x i32>
   %shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
   %.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> zeroinitializer, <8 x i8> %b, <8 x i8> %.cast5) #2
   %ret = add <2 x i32> %vdot1.i, %a
   ret <2 x i32> %ret
 }
 
 define <4 x i32> @test_vdotq_lane_s32_zero(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) {
+; CHECK-LABEL: test_vdotq_lane_s32_zero:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT:    sdot v0.4s, v1.16b, v2.4b[1]
+; CHECK-NEXT:    ret
 entry:
   %.cast = bitcast <8 x i8> %c to <2 x i32>
   %shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> zeroinitializer, <16 x i8> %b, <16 x i8> %.cast3) #2
   %ret = add <4 x i32> %vdot1.i, %a
   ret <4 x i32> %ret
 }
 
 define <2 x i32> @test_vdot_laneq_s32_zero(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c) {
 ; CHECK-LABEL: test_vdot_laneq_s32_zero:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    movi v3.2d, #0000000000000000
-; CHECK-NEXT:    sdot v3.2s, v1.8b, v2.4b[1]
-; CHECK-NEXT:    add v0.2s, v3.2s, v0.2s
+; CHECK-NEXT:    sdot v0.2s, v1.8b, v2.4b[1]
 ; CHECK-NEXT:    ret
 entry:
   %.cast = bitcast <16 x i8> %c to <4 x i32>
   %shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
   %.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> zeroinitializer, <8 x i8> %b, <8 x i8> %.cast5) #2
   %ret = add <2 x i32> %vdot1.i, %a
   ret <2 x i32> %ret
 }
 
 define <4 x i32> @test_vdotq_laneq_s32_zero(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) {
 ; CHECK-LABEL: test_vdotq_laneq_s32_zero:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    movi v3.2d, #0000000000000000
-; CHECK-NEXT:    sdot v3.4s, v1.16b, v2.4b[1]
-; CHECK-NEXT:    add v0.4s, v3.4s, v0.4s
+; CHECK-NEXT:    sdot v0.4s, v1.16b, v2.4b[1]
 ; CHECK-NEXT:    ret
 entry:
   %.cast = bitcast <16 x i8> %c to <4 x i32>
   %shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> zeroinitializer, <16 x i8> %b, <16 x i8> %.cast3) #2
   %ret = add <4 x i32> %vdot1.i, %a
   ret <4 x i32> %ret
 }

llvm/test/CodeGen/AArch64/neon-dotreduce.ll

entry:
   ret i32 %x
 }
 
 define i32 @test_udot_v16i8_double_nomla(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
 ; CHECK-LABEL: test_udot_v16i8_double_nomla:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    movi v1.16b, #1
 ; CHECK-NEXT:    movi v3.2d, #0000000000000000
-; CHECK-NEXT:    movi v4.2d, #0000000000000000
-; CHECK-NEXT:    udot v4.4s, v1.16b, v0.16b
 ; CHECK-NEXT:    udot v3.4s, v1.16b, v2.16b
-; CHECK-NEXT:    add v0.4s, v4.4s, v3.4s
-; CHECK-NEXT:    addv s0, v0.4s
+; CHECK-NEXT:    udot v3.4s, v1.16b, v0.16b
+; CHECK-NEXT:    addv s0, v3.4s
 ; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
 entry:
   %az = zext <16 x i8> %a to <16 x i32>
   %r1 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %az)
   %cz = zext <16 x i8> %c to <16 x i32>
   %r2 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %cz)
   %x = add i32 %r1, %r2
entry:
   ret i32 %x
 }
 
 define i32 @test_sdot_v16i8_double_nomla(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
 ; CHECK-LABEL: test_sdot_v16i8_double_nomla:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    movi v1.16b, #1
 ; CHECK-NEXT:    movi v3.2d, #0000000000000000
-; CHECK-NEXT:    movi v4.2d, #0000000000000000
-; CHECK-NEXT:    sdot v4.4s, v1.16b, v0.16b
 ; CHECK-NEXT:    sdot v3.4s, v1.16b, v2.16b
-; CHECK-NEXT:    add v0.4s, v4.4s, v3.4s
-; CHECK-NEXT:    addv s0, v0.4s
+; CHECK-NEXT:    sdot v3.4s, v1.16b, v0.16b
+; CHECK-NEXT:    addv s0, v3.4s
 ; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
 entry:
   %az = sext <16 x i8> %a to <16 x i32>
   %r1 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %az)
   %cz = sext <16 x i8> %c to <16 x i32>
   %r2 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %cz)
   %x = add i32 %r1, %r2
   ret i32 %x
 }